Array substrate and preparation method therefor, and flexible electronic paper display panel

Abstract

Disclosed in the present application are an array substrate (30) and a preparation method therefor, and a flexible electronic paper display panel (10). A first active switch (310) and a second active switch (320) in each pixel unit (710) are respectively arranged on a front surface (41) and a back surface (42) of a flexible base (40), and pixel electrodes (170) are arranged on the flexible base (40) and are located in the pixel units (710); and first sub-data lines (511), the first active switches (310), the second active switches (320), and the pixel electrodes (170) are connected in sequence. By means of the design, the problem of grayscale reduction when the flexible electronic paper display panel (10) is bent is avoided, such that a display effect is improved.

Description

Array substrate and its fabrication method and flexible electronic paper display panel

[0001] This application claims priority to Chinese Patent Application No. 2024115168901, filed on October 29, 2024, entitled “Array Substrate and Method for Preparing the Same and Flexible Electronic Paper Display Panel”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of display technology, and in particular to an array substrate, a method for fabricating the same, and a flexible electronic paper display panel. Background Technology

[0003] With the development of digital technology, more and more display devices are entering people's lives, such as electronic paper (EP) display panels. Because electronic paper display panels can maintain display for a long time when the power is off, and have advantages such as being lightweight, thin, having low power consumption, and being simple to manufacture, they are becoming increasingly popular.

[0004] Current flexible electronic paper display panels can be rolled up and folded arbitrarily by using flexible substrates made of polyimide film. However, when in use, pixel units at the corresponding bending and folding positions will exhibit display abnormalities such as reduced grayscale. Summary of the Invention

[0005] The purpose of this application is to provide an array substrate and its preparation method, as well as a flexible electronic paper display panel, to avoid the problem of grayscale reduction when the flexible electronic paper display panel is bent, and to improve the display effect of the flexible electronic paper display panel.

[0006] This application discloses an array substrate for use in a flexible electronic paper display panel. The array substrate includes a flexible substrate, a first active switch, a second active switch, a first sub-data line, a first sub-scan line, and pixel electrodes.

[0007] The first sub-data line and the first sub-scan line are disposed on the flexible substrate, and the first sub-data line and the first sub-scan line are arranged in a longitudinal and transverse manner, dividing the substrate into multiple pixel units;

[0008] The first active switch and the second active switch in each pixel unit are respectively disposed on the front and back sides of the flexible substrate, and the pixel electrode is disposed on the flexible substrate and located in the pixel unit; the first sub-data line, the first active switch, the second active switch and the pixel electrode are connected in sequence.

[0009] Optionally, the array substrate includes a first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, a second insulating layer, a passivation layer, a pixel electrode, a third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer.

[0010] The first active switch includes a first gate, a first sub-semiconductor, a first source, and a first drain; the second active switch includes a second gate, a second sub-semiconductor, a second source, and a second drain.

[0011] The flexible substrate has the third metal layer, the third insulating layer, the second semiconductor layer, the fourth metal layer, the fourth insulating layer, the passivation layer, and the pixel electrode stacked sequentially on its front side; the third metal layer contains the second gate, the second semiconductor layer contains the second sub-semiconductor, and the fourth metal layer contains the second source and the second drain.

[0012] The flexible substrate has a first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, and a second insulating layer stacked sequentially on its back side; the first metal layer contains the first gate, the first semiconductor layer contains the first sub-semiconductor, and the second metal layer contains the first source and the first drain.

[0013] The first sub-data line is connected to the first source, the first drain is connected to the second source, the second drain is connected to the pixel electrode, and the first sub-scan line is connected to both the first gate and the second gate.

[0014] Optionally, the array substrate includes a first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, a second insulating layer, a passivation layer, a pixel electrode, a third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer.

[0015] The first active switch includes a first gate, a first sub-semiconductor, a first source, and a first drain; the second active switch includes a second gate, a second sub-semiconductor, a second source, and a second drain.

[0016] The flexible substrate has a first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, a second insulating layer, a passivation layer, and a pixel electrode stacked sequentially on its front side; the first metal layer contains a first gate, the first semiconductor layer contains a first sub-semiconductor, and the second metal layer contains a first source and a first drain.

[0017] The back side of the flexible substrate is provided with the third metal layer, the third insulating layer, the second semiconductor layer, the fourth metal layer, and the fourth insulating layer stacked sequentially; the third metal layer contains the second gate, the second semiconductor layer contains the second sub-semiconductor, and the fourth metal layer contains the second source and the second drain.

[0018] The first sub-data line is connected to the first source, the first drain is connected to the second source, the second drain is connected to the pixel electrode, and the first sub-scan line is connected to the first gate and the second gate.

[0019] Optionally, the first channel formed between the first source and the first drain, and the second channel formed between the second source and the second drain, are located on the same straight line along their length directions.

[0020] Optionally, the array substrate further includes a third active switch and a fourth active switch; the third active switch includes a third gate, a third sub-semiconductor, a third source, and a third drain; the fourth active switch includes a fourth gate, a fourth sub-semiconductor, a fourth source, and a fourth drain.

[0021] The third metal layer also contains the third gate, the second semiconductor layer also contains the third sub-semiconductor, and the fourth metal layer also contains the third source and the third drain.

[0022] The first metal layer also contains the fourth gate, the first semiconductor layer also contains the fourth sub-semiconductor, and the second metal layer also contains the fourth source and the fourth drain.

[0023] The array substrate further includes a second sub-data line and a second sub-scan line;

[0024] The first sub-data line is connected to the first source, the first drain is connected to the second source, the second drain is connected to the pixel electrode, and the first sub-scan line is connected to both the first gate and the second gate.

[0025] The second sub-data line is connected to the third source, the third drain is connected to the fourth source, the fourth drain is connected to the pixel electrode, and the second sub-scan line is connected to both the third gate and the fourth gate.

[0026] Optionally, the first sub-scan line is located within the first metal layer, and the first sub-data line is located within the second metal layer;

[0027] The second sub-scan line is located within the third metal layer, and the second sub-data line is located within the fourth metal layer; the third channel formed between the third source and the third drain, and the fourth channel formed between the fourth source and the fourth drain, are located on the same straight line along their length directions.

[0028] This application also discloses a method for fabricating an array substrate, the method being used to fabricate the array substrate described above, the steps of which include:

[0029] A first sub-data line, a first sub-scan line, a first active switch, and a second active switch are formed on a flexible substrate;

[0030] A passivation layer is formed on the first active switch or the second active switch;

[0031] The pixel electrode is formed on the passivation layer;

[0032] The first sub-data line and the first sub-scan line are arranged in a vertical and horizontal pattern and divided into multiple pixel units. The first active switch and the second active switch in each pixel unit are respectively disposed on the front and back sides of the flexible substrate. The first sub-data line, the first active switch, the second active switch and the pixel electrode are connected in sequence. The first sub-data line is connected to the first active switch and the second active switch at the same time.

[0033] Optionally, the step of forming the first sub-data line, the first sub-scan line, the first active switch, and the second active switch on the flexible substrate includes:

[0034] A third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer are sequentially stacked on the front side of the flexible substrate; a second gate is disposed in the third metal layer, a second sub-semiconductor is disposed in the second semiconductor layer, and a second source and a second drain are disposed in the fourth metal layer; the second gate, the second sub-semiconductor, the second source, and the second drain form the second active switch.

[0035] A first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, and a second insulating layer are sequentially stacked on the back side of the flexible substrate; a first gate is disposed in the first metal layer, a first sub-semiconductor is disposed in the first semiconductor layer, and a first source and a first drain are disposed in the second metal layer; the first gate, the first sub-semiconductor, the first source, and the first drain form the first active switch.

[0036] The step of forming a passivation layer on the first active switch or the second active switch includes:

[0037] The passivation layer is formed on the fourth insulating layer.

[0038] Optionally, the step of forming the first sub-data line, the first sub-scan line, the first active switch, and the second active switch on the flexible substrate includes:

[0039] A first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, and a second insulating layer are sequentially stacked on the front side of the flexible substrate; a first gate is disposed in the first metal layer, a first sub-semiconductor is disposed in the first semiconductor layer, and a first source and a first drain are disposed in the second metal layer; the first gate, the first sub-semiconductor, the first source, and the first drain form the first active switch.

[0040] A third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer are sequentially stacked on the back side of the flexible substrate; a second gate is disposed in the third metal layer, a second sub-semiconductor is disposed in the second semiconductor layer, and a second source and a second drain are disposed in the fourth metal layer; the second gate, the second sub-semiconductor, the second source, and the second drain form the second active switch.

[0041] The step of forming a passivation layer on the first active switch or the second active switch includes:

[0042] The passivation layer is formed on the second insulating layer.

[0043] This application also discloses a flexible electronic paper display panel, which includes an electronic paper film and an array substrate. The electronic paper film is attached to the array substrate and is located on the side of the pixel electrode opposite to the flexible substrate.

[0044] Compared to existing array substrates where the first and second active switches are located on the same side of the flexible substrate, this application places the first and second active switches on the front and back sides of the flexible substrate, respectively. This means that when the flexible electronic paper display panel is bent, the width of the first channel within the first active switch widens while the width of the second channel within the second active switch narrows; conversely, the narrowing of the first channel and the widening of the second channel achieve mutual compensation between the changes in the first and second active switches. This avoids grayscale reduction during bending of the flexible electronic paper display panel and improves its display performance. Attached Figure Description

[0045] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0046] Figure 1 is a schematic diagram of a flexible electronic paper display panel according to an embodiment of this application;

[0047] Figure 2 is a schematic diagram of an array substrate according to the first embodiment of this application;

[0048] Figure 3 is a schematic diagram of a pixel unit plane according to the first embodiment of this application;

[0049] Figure 4 is a schematic diagram of a flexible substrate with scan lines on both the front and back sides according to the first embodiment of this application;

[0050] Figure 5 is a plan view of a flexible substrate with scan lines on both the front and back sides according to the first embodiment of this application;

[0051] Figure 6 is a cross-sectional schematic diagram of a first channel and a second channel according to the first embodiment of this application;

[0052] Figure 7 is a plan view of a first channel and a second channel according to the first embodiment of this application;

[0053] Figure 8 is a schematic diagram of an array substrate according to a second embodiment of this application;

[0054] Figure 9 is a cross-sectional schematic diagram of an array substrate according to a third embodiment of this application;

[0055] Figure 10 is a cross-sectional schematic diagram of a third active switch and a fourth active switch according to a third embodiment of this application;

[0056] Figure 11 is a schematic diagram of a pixel unit according to a third embodiment of this application;

[0057] Figure 12 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of this application;

[0058] Figures 13a-13b are schematic diagrams of a fabrication method for an array substrate according to an embodiment of this application.

[0059] Figure 14 is a schematic flowchart of a method for fabricating an array substrate according to an embodiment of this application;

[0060] Figures 15a-15b are schematic diagrams illustrating the fabrication process of an array substrate according to an embodiment of this application. Detailed Implementation

[0061] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0062] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0063] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0064] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0065] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0066] Figure 1 is a schematic diagram of a flexible electronic paper display panel according to an embodiment of this application. As shown in Figure 1, this application discloses a flexible electronic paper display panel 10, which includes an electronic paper film 20 and an array substrate 30. The electronic paper film 20 is attached to the array substrate 30 and is located on the side of the pixel electrode 170 away from the flexible substrate 40.

[0067] The flexible electronic paper display panel 10 can be rolled into a tube or folded during use.

[0068] The electronic paper film 20 includes a particle layer 21 and a common electrode layer 22. Electrophoretic particles are disposed in the particle layer 21. The electrophoretic particles include black electrophoretic particles, white electrophoretic particles, and can also include colored electrophoretic particles, such as red electrophoretic particles, blue electrophoretic particles, and green electrophoretic particles. The common electrode layer 22 is located on the side of the particle layer 21 away from the array substrate 30. An electric field is formed between the common electrode layer 22 and the pixel electrode 170 on the array substrate 30, driving the electrophoretic particles to move and realize the display of the image.

[0069] This application also discloses an array substrate 30, which can be used in the flexible electronic paper display panel 10 described above. Regarding the array substrate 30, this application provides the following design, which is specifically described through several embodiments:

[0070] Example 1:

[0071] Figure 2 is a schematic diagram of an array substrate according to the first embodiment of this application, and Figure 3 is a schematic diagram of a pixel unit plane according to the first embodiment of this application. As shown in Figures 2 and 3, this application discloses an array substrate 30 for use in a flexible electronic paper display panel 10. The array substrate 30 includes a flexible substrate 40, a first active switch 310, a second active switch 320, a first sub-data line 511, a first sub-scan line 521, and a pixel electrode 170.

[0072] The first sub-data line 511 and the first sub-scan line 521 are disposed on the flexible substrate 40, and the first sub-data line 511 and the first sub-scan line 521 are arranged in a longitudinal and transverse manner, dividing into multiple pixel units 710.

[0073] The first active switch 310 and the second active switch 320 in each pixel unit 710 are respectively disposed on the front side 41 and the back side 42 of the flexible substrate 40. The pixel electrode 170 is disposed on the flexible substrate 40 and located in the pixel unit 710. The first sub-data line 511, the first active switch 310, the second active switch 320 and the pixel electrode 170 are connected in sequence.

[0074] For example, the first sub-scan line 521 can be connected to both the first active switch 310 and the second active switch 320 simultaneously.

[0075] In simple terms, each pixel unit 710 is provided with a first active switch 310, a second active switch 320 and a pixel electrode 170, and the first active switch 310, the second active switch 320 and the pixel electrode 170 are connected in series.

[0076] Furthermore, the first active switch 310 may be on the front side 41 of the flexible substrate 40 and the second active switch 320 may be on the back side 42 of the flexible substrate 40; alternatively, the first active switch 310 may be on the back side 42 of the flexible substrate 40 and the second active switch 320 may be on the front side 41 of the flexible substrate 40. Then, the first active switch 310 and the second active switch 320 may be connected through a via, and the second active switch 320 and the pixel electrode 170 may also be connected through a via.

[0077] Furthermore, the first sub-data line 511 and the first sub-scan line 521 can be simultaneously disposed on the front side 41 of the flexible substrate 40, or simultaneously disposed on the back side 42 of the flexible substrate 40. Alternatively, the first sub-data line 511 can be disposed on the front side 41 of the flexible substrate 40, and the first sub-scan line 521 can be disposed on the back side 42 of the flexible substrate 40, or the first sub-data line 511 can be disposed on the back side 42 of the flexible substrate 40, and the first sub-scan line 521 can be disposed on the front side 41 of the flexible substrate 40.

[0078] When existing flexible electronic paper display panels are bent, a fold line is formed in the middle area of ​​the bend. This defines the first channel 315 formed by the source and drain in the first active switch 310, and the second channel 325 formed by the source and drain in the second active switch 320. Since the first active switch 310 and the second active switch 320 are both located on the same side of the flexible substrate 40, when the existing flexible electronic paper display panels are folded, the first channel 315 and the second channel 325 at the position corresponding to the fold line on the array substrate 30 will either widen or narrow simultaneously.

[0079] That is, when both the first active switch 310 and the second active switch 320 are disposed on the front side 41 of the flexible substrate 40.

[0080] When the flexible electronic paper display panel 10 is bent upward, the width of the first channel 315 in the first active switch 310 and the second channel 325 in the second active switch 320 will narrow simultaneously, resulting in increased leakage current in the off state and a decrease in grayscale at the position of the corresponding pixel unit 710 of the flexible electronic paper display panel 10.

[0081] When the flexible electronic paper display panel 10 is bent downwards, the width of the first channel 315 in the first active switch 310 and the second channel 325 in the second active switch 320 will widen simultaneously, resulting in a decrease in the charging performance of the pixel electrode 170. This leads to a decrease in grayscale at the position of the corresponding pixel unit 710 of the flexible electronic paper display panel 10, especially when the length direction of the first channel 315, the length direction of the second channel 325, and the length direction of the fold line are all consistent, the change is most obvious.

[0082] Compared to the existing method where the first active switch 310 and the second active switch 320 are disposed on the same side of the flexible substrate 40 on the array substrate, this application disposes the first active switch 310 and the second active switch 320 on the front side 41 and the back side 42 of the flexible substrate 40, respectively. This means that when the flexible electronic paper display panel 10 is bent, the width of the first channel 315 in the first active switch 310 widens while the width of the second channel 325 in the second active switch 320 narrows; conversely, the narrowing of the first channel 315 in the first active switch 310 and the widening of the second channel 325 in the second active switch 320 achieve mutual compensation of the changes in the first and second active switches 320, thus avoiding grayscale reduction during bending of the flexible electronic paper display panel 10 and improving the display effect of the flexible electronic paper display panel 10.

[0083] In this embodiment, the first active switch 310 is disposed on the back side 42 of the flexible substrate 40, and the second active switch 320 is disposed on the front side 41 of the flexible substrate 40.

[0084] Specifically, the array substrate 30 includes a first metal layer 110, a first insulating layer 120, a first semiconductor layer 130, a second metal layer 140, a second insulating layer 150, a passivation layer 160, a pixel electrode 170, a third metal layer 210, a third insulating layer 220, a second semiconductor layer 230, a fourth metal layer 240, and a fourth insulating layer 250.

[0085] The first active switch 310 includes a first gate 311, a first sub-semiconductor 312, a first source 313, and a first drain 314; the second active switch 320 includes a second gate 321, a second sub-semiconductor 322, a second source 323, and a second drain 324.

[0086] The flexible substrate 40 has the third metal layer 210, the third insulating layer 220, the second semiconductor layer 230, the fourth metal layer 240, the fourth insulating layer 250, the passivation layer 160 and the pixel electrode 170 stacked sequentially on its front side 41. The third metal layer 210 contains the second gate 321, the second semiconductor layer 230 contains the second sub-semiconductor 322, and the fourth metal layer 240 contains the second source 323 and the second drain 324.

[0087] The flexible substrate 40 has a first metal layer 110, a first insulating layer 120, a first semiconductor layer 130, a second metal layer 140, and a second insulating layer 150 stacked sequentially on its back side 42. The first metal layer 110 contains the first gate 311, the first semiconductor layer 130 contains the first sub-semiconductor 312, and the second metal layer 140 contains the first source 313 and the first drain 314.

[0088] The first sub-data line 511 is connected to the first source 313, the first drain 314 is connected to the second source 323, the second drain 324 is connected to the pixel electrode 170, and the first sub-scan line 521 is connected to both the first gate 311 and the second gate 321. In simpler terms, the first active switch 310 is disposed on the back side 42 of the flexible substrate 40, the second active switch 320 is disposed on the front side 41 of the flexible substrate 40, and the pixel electrode 170 is also disposed on the front side 41 of the flexible substrate 40. This reduces the via length connecting the second active switch 320 and the pixel electrode 170, thereby reducing manufacturing complexity and improving signal transmission stability.

[0089] Furthermore, the first sub-data line 511 is disposed on the back side 42 of the flexible substrate 40 and in the second metal layer 140. Thus, the connection between the first sub-data line 511 and the first source 313 of the first active switch 310 does not require via connection, reducing process difficulty, improving fabrication yield, and improving the transmission stability of data signals. The first sub-scan line 521 is disposed on the back side 42 of the flexible substrate 40 and in the first metal layer.

[0090] Figure 4 is a schematic diagram of a flexible substrate with scan lines on both the front and back sides according to the first embodiment of this application. Figure 5 is a planar schematic diagram of a flexible substrate with scan lines on both the front and back sides according to the first embodiment of this application. As shown in Figures 4 and 5, scan lines are provided on both the front side 41 and the back side 42 of the flexible substrate 40. Specifically, the array substrate 30 also includes a third sub-scan line 523. The first sub-scan line 521 is disposed on the back side 42 of the flexible substrate 40 and located in the first metal layer 110. The third sub-scan line 523 is disposed on the front side 41 of the flexible substrate 40 and located in the third metal layer 210.

[0091] Furthermore, the first sub-scan line 521 and the third sub-scan line 523 are connected to the same driving signal. The first sub-scan line 521 is connected to the first gate 311 of the first active switch 310, and the third sub-scan line 523 is connected to the second gate 321 of the second active switch 320. The first sub-scan line 521 and the third sub-scan line 523 correspond one-to-one, simultaneously turning on the first active switch 310 and the second active switch 320 within a pixel unit 710. This eliminates the need for openings to connect the second gate 321 of the second active switch 320 and the first sub-scan line 521 for each pixel unit 710, thereby reducing manufacturing complexity and improving the yield of the flexible electronic paper display panel 10.

[0092] Figure 6 is a cross-sectional schematic diagram of a first channel and a second channel according to the first embodiment of this application, and Figure 7 is a planar schematic diagram of a first channel and a second channel according to the first embodiment of this application. As shown in Figures 6 and 7, in order to avoid the inability of the width change of the first channel 315 and the width change of the second channel 325 to compensate for each other well, such as the first channel 315 having a large width change and the second channel 325 having a small width change, this application also adjusts the position of the first channel 315 and the second channel 325.

[0093] A first channel 315 is formed between the first source 313 and the first drain 314, and a second channel 325 is formed between the second source 323 and the second drain 324. The length directions of the first channel 315 and the second channel 325 are on the same straight line.

[0094] For example, taking the length direction of the first sub-data line 511 as the first direction 610, the length directions of the first channel 315 and the second channel 325 are the same as the first direction 610, and the orthographic projection of the first active switch 310 on the flexible substrate 40 and the orthographic projection of the second active switch 320 on the flexible substrate 40 do not overlap. In simple terms, the orthographic projection of the second channel 325 on the substrate is located on the extension line of the length of the orthographic projection of the first channel 315 on the flexible substrate 40.

[0095] In this way, when the flexible electronic paper display panel 10 is bent and folded, the width change of the first channel 315 of the first active switch 310 and the width change of the second channel 325 of the second active switch 320 can be well compensated for each other. This avoids a situation where the width change of the first channel 315 of the first active switch 310 is large, while the width change of the second channel 325 of the second active switch 320 is small.

[0096] The array substrate 30 further includes a first electrode plate 421, a second electrode plate 422, a first common electrode sheet 411, and a second common electrode sheet 412. The first common electrode sheet 411 is disposed in the first metal layer 110, the first electrode plate 421 is disposed in the second metal layer 140, the second common electrode sheet 412 is disposed in the third metal layer 210, and the second electrode plate 422 is disposed in the fourth metal layer 240.

[0097] Both the first common electrode plate 411 and the second common electrode plate 412 are connected to the common electrode layer 22, and both the first electrode plate 421 and the second electrode plate 422 are connected to the pixel electrode 170. A first storage capacitor is formed between the first electrode plate 421 and the first common electrode plate 411, and a second storage capacitor is formed between the second electrode plate 422 and the second common electrode plate 412. The areas of the first electrode plate 421, the second electrode plate 422, the first common electrode plate 411, and the second common electrode plate 412 are all equal.

[0098] During use, repeated folding causes the first electrode plate 421, the second electrode plate 422, the first common electrode sheet 411, and the second common electrode sheet 412 to shift in position. The further away the first electrode plate 421 and the second electrode plate 422 are from the flexible substrate 40, the greater the degree of positional shift. Therefore, this application also misaligns the first electrode plate 421 and the first common electrode sheet 411, and misaligns the second electrode plate 422 and the second common electrode sheet 412. The misalignment direction of the first electrode plate 421 and the first common electrode sheet 411 and the misalignment direction of the second electrode plate 422 and the second common electrode sheet 412 are opposite.

[0099] For example, the orthographic projection of the first common electrode 411 on the flexible substrate 40 overlaps with the orthographic projection of the second common electrode 412 on the flexible substrate 40; the second electrode plate 422 covers the left portion of the second common electrode 412 and the first electrode plate 421 covers the right portion of the first common electrode 411, or the second electrode plate 422 covers the right portion of the second common electrode 412 and the first electrode plate 421 covers the left portion of the first common electrode 411.

[0100] In this way, when the second electrode plate 422 and the first electrode plate 421 are simultaneously offset in one direction, the changes in the first storage capacitor and the second storage capacitor will cancel each other out, thereby ensuring that the charging capability of the pixel unit 710 is not changed, avoiding display abnormalities, and improving the display effect.

[0101] Example 2:

[0102] Figure 8 is a schematic diagram of an array substrate according to a second embodiment of this application. As shown in Figure 8, the difference from the first embodiment is that the first active switch 310 is disposed on the front side 41 of the flexible substrate 40, and the second active switch 320 is disposed on the back side 42 of the flexible substrate 40.

[0103] The array substrate 30 includes a first metal layer 110, a first insulating layer 120, a first semiconductor layer 130, a second metal layer 140, a second insulating layer 150, a passivation layer 160, a pixel electrode 170, a third metal layer 210, a third insulating layer 220, a second semiconductor layer 230, a fourth metal layer 240, and a fourth insulating layer 250.

[0104] The first active switch 310 includes a first gate 311, a first sub-semiconductor 312, a first source 313, and a first drain 314; the second active switch 320 includes a second gate 321, a second sub-semiconductor 322, a second source 323, and a second drain 324.

[0105] The flexible substrate 40 has the first metal layer 110, the first insulating layer 120, the first semiconductor layer 130, the second metal layer 140, the second insulating layer 150, the passivation layer 160, and the pixel electrode 170 stacked sequentially on its front side 41. The first metal layer 110 contains the first gate 311, the first semiconductor layer 130 contains the first sub-semiconductor 312, and the second metal layer 140 contains the first source 313 and the first drain 314.

[0106] The back side 42 of the flexible substrate 40 is provided with the third metal layer 210, the third insulating layer 220, the second semiconductor layer 230, the fourth metal layer 240 and the fourth insulating layer 250 stacked sequentially; the third metal layer 210 is provided with the second gate 321, the second semiconductor layer 230 is provided with the second sub-semiconductor 322, and the fourth metal layer 240 is provided with the second source 323 and the second drain 324.

[0107] The first sub-data line 511 is connected to the first source 313, the first drain 314 is connected to the second source 323, the second drain 324 is connected to the pixel electrode 170, and the first sub-scan line 521 is connected to the first gate 311 and the second gate 321.

[0108] Compared to the first embodiment, in this embodiment, the first active switch 310 is disposed on the front side 41 of the flexible substrate 40, and the second active switch 320 is disposed on the back side 42 of the flexible substrate 40. The second active switch 320 is directly connected to the pixel electrode 170. The parasitic capacitance of the second active switch 320 disposed on the back side 42 of the flexible substrate 40 is smaller, and its impact on the voltage of the pixel electrode 170 is also smaller.

[0109] Furthermore, when the array substrate 30 only includes the first sub-data line 511 and the first sub-scan line 521, both the first sub-data line 511 and the first sub-scan line 521 are disposed on the front side 41 of the flexible substrate 40. The first sub-scan line 521 is located in the first metal layer 110 and is connected to the first gate 311 of the first active switch 310 and the second gate 321 of the second active switch 320. The first sub-data line 511 is located in the second metal layer 140 and is connected to the first source 313 of the first active switch 310.

[0110] When the array substrate 30 includes a first sub-data line 511, a first sub-scan line 521, and a third sub-scan line 523, the first sub-data line 511 and the first sub-scan line 521 are both disposed on the front side 41 of the flexible substrate 40, and the third sub-scan line 523 is disposed on the back side 42 of the flexible substrate 40. The first sub-scan line 521 is located in the first metal layer 110 and is connected to the first gate 311 of the first active switch 310. The first sub-data line 511 is located in the second metal layer 140 and is connected to the first source 313 of the first active switch 310. The third sub-scan line 523 is located in the third metal layer 210 and is connected to the second gate 321 of the second active switch 320.

[0111] Example 3:

[0112] Figure 9 is a cross-sectional schematic diagram of an array substrate according to the third embodiment of this application. As shown in Figure 9, the difference from the first embodiment is that each pixel unit 710 in this embodiment is provided with two sets of active switches, wherein the first set of active switches is the first active switch 310 and the second active switch 320, and the second set of active switches is the third active switch 330 and the fourth active switch 340.

[0113] The first active switch 310 is disposed on the back side 42 of the flexible substrate 40, the second active switch 320 is disposed on the front side 41 of the flexible substrate 40, the third active switch 330 is disposed on the front side 41 of the flexible substrate 40, and the fourth active switch 340 is disposed on the back side 42 of the flexible substrate 40.

[0114] Furthermore, the first active switch 310, the second active switch 320 and the pixel electrode 170 are connected in series, the third active switch 330 and the fourth active switch 340 and the pixel electrode 170 are connected in series, and the first group of active switches and the second group of active switches are connected in parallel.

[0115] The array substrate 30 further includes a third active switch 330 and a fourth active switch 340; the third active switch 330 includes a third gate 331, a third sub-semiconductor 332, a third source 333, and a third drain 334; the fourth active switch 340 includes a fourth gate 341, a fourth sub-semiconductor 342, a fourth source 343, and a fourth drain 344.

[0116] The third metal layer 210 also contains the third gate 331, the second semiconductor layer 230 also contains the third sub-semiconductor 332, and the fourth metal layer 240 also contains the third source 333 and the third drain 334.

[0117] The first metal layer 110 is further provided with the fourth gate 341, the first semiconductor layer 130 is further provided with the fourth sub-semiconductor 342, and the second metal layer 140 is further provided with the fourth source 343 and the fourth drain 344.

[0118] The array substrate 30 further includes a second sub-data line 512 and a second sub-scan line 522. The first sub-data line 511 is connected to the first source 313, the first drain 314 is connected to the second source 323, the second drain 324 is connected to the pixel electrode 170, and the first sub-scan line 521 is connected to both the first gate 311 and the second gate 321; and the first sub-data line 511 is disposed in the second metal layer 140, and the first sub-scan line 521 is disposed in the first metal layer 110.

[0119] The second sub-data line 512 is connected to the third source 333, the third drain 334 is connected to the fourth source 343, the fourth drain 344 is connected to the pixel electrode 170, and the second sub-scan line 522 is connected to both the third gate 331 and the fourth gate 341. Furthermore, the second sub-data line 512 is located in the fourth metal layer 240, and the second sub-scan line 522 is located in the third metal layer 210.

[0120] The first sub-data line 511 and the second sub-data line 512 are both connected to the same driving signal. When the flexible electronic paper display panel 10 is working, since the two active switches in each group of active switches are connected in series, when one group of active switches is damaged, since the first group of active switches and the second group of active switches are independently connected to the same pixel electrode 170, the other group of active switches can be selected to work.

[0121] For example, when the first active switch 310 is damaged, it is not necessary to input signals to the first sub-scan line 521 and the first sub-data line 511. Instead, the second set of active switches, namely the third active switch 330 and the fourth active switch 340, can be selected to work, and drive signals can be supplied to the second sub-scan line 522 and the second sub-data line 512.

[0122] Figure 10 is a cross-sectional schematic diagram of a third active switch and a fourth active switch according to a third embodiment of this application. As shown in Figure 10, to avoid the inability of the width variation of the third channel 335 and the width variation of the fourth channel 345 to compensate for each other, i.e., to avoid situations where the width variation of the third channel 335 is large and the width variation of the fourth channel 345 is small, this application also adjusts the positions of the third channel 335 and the fourth channel 345. That is, the third channel 335 formed between the third source 333 and the third drain 334, and the fourth channel 345 formed between the fourth source 343 and the fourth drain 344, are located on the same straight line along their length directions.

[0123] At this time, the first sub-scan line 521 is located within the first metal layer 110, and the first sub-data line 511 is located within the second metal layer 140; the second sub-scan line 522 is located within the third metal layer 210, and the second data line 512 is located within the fourth metal layer 240.

[0124] Of course, as shown in FIG10, the third active switch 330 can also be disposed on the back side 42 of the flexible substrate 40, and the fourth active switch 340 is disposed on the front side 41 of the flexible substrate 40. In this case, the third gate 331 is located in the first metal layer 110, the third sub-semiconductor 332 is located in the first semiconductor layer 130, and the third source 333 and the third drain 334 are located in the second metal layer 140; the fourth gate 341 is located in the third metal layer 210, the fourth sub-semiconductor 342 is located in the second semiconductor layer 230, and the fourth source 343 and the fourth drain 344 are located in the fourth metal layer 240.

[0125] The first sub-scan line 521 is located within the first metal layer 110, and the first sub-data line 511 is located within the second metal layer 140; the second sub-scan line 522 is also located within the first metal layer 110, and the second sub-data line 512 is also located within the second metal layer 140.

[0126] In this way, when the flexible electronic paper display panel 10 is bent and folded, the width change of the third channel 335 of the third active switch 330 and the width change of the fourth channel 345 of the fourth active switch 340 can be well compensated for each other. This avoids a situation where the width change of the third channel 335 of the third active switch 330 is large, while the width change of the fourth channel 345 of the fourth active switch 340 is small.

[0127] Figure 11 is a schematic diagram of a pixel unit according to the third embodiment of this application. As shown in Figure 11, during the use of the flexible electronic paper display panel 10, it is frequently bent and folded according to the user's usage habits. A fold line will be formed at the fold position of the flexible electronic paper display panel 10. When the channel length direction of the active switch located on the fold line is the same as the length direction of the fold line, the channel width of the active switch is greatly affected and is more prone to damage.

[0128] Therefore, this application also adjusts the positions of the two sets of active switches, that is, the length direction of the first channel 315 and the length direction of the second channel 325 are the first direction 610, the length direction of the third channel 335 and the length direction of the fourth channel 345 are the second direction 620, and the first direction 610 and the second direction 620 are perpendicular.

[0129] For example, the length direction of the first sub-data line 511 is taken as the first direction 610, the length direction of the first sub-scan line 521 is taken as the second direction 620, the first direction 610 is perpendicular to the second direction 620, the length direction of the first channel 315 is the same as the length direction of the second channel 325, and the length directions of the first channel 315 and the second channel 325 are parallel to the first direction 610, the length direction of the third channel 335 is the same as the length direction of the fourth channel 345, and the length directions of the third channel 335 and the fourth channel 345 are parallel to the second direction 620.

[0130] Thus, in the first active switch 310 and the second active switch 320 in the first group of active switches, and in the third active switch 330 and the fourth active switch 340 in the second group of active switches, the length direction of the channel of one of the active switches will not be parallel to the length direction of the fold line.

[0131] For example, when the length direction of the fold line is horizontal to the length direction of the first sub-data line 511, the first active switch 310 and the second active switch 320 of the first group are prone to damage. After the first active switch 310 and the second active switch 320 of the first group are damaged, they are replaced with the third active switch 330 and the fourth active switch 340 of the second group. Since the length direction of the third channel 335 in the third active switch 330 of the second group is perpendicular to the fold line, and the length direction of the fourth channel 345 in the fourth active switch 340 of the second group is perpendicular to the fold line, the third active switch 330 and the fourth active switch 340 of the second group are less affected, thereby improving the lifespan of the flexible electronic paper display panel 10.

[0132] Furthermore, the array substrate 30 also includes a third sub-scan line 523 and a fourth sub-scan line 524; the first sub-scan line 521 is disposed on the back side 42 of the flexible substrate 40 and located in the first metal layer 110, and the third sub-scan line 523 is disposed on the front side 41 of the flexible substrate 40 and located in the third metal layer 210.

[0133] Furthermore, the first sub-scan line 521 and the third sub-scan line 523 are connected to the same driving signal. The first sub-scan line 521 is connected to the first gate 311 of the first active switch 310, and the third sub-scan line 523 is connected to the second gate 321 of the second active switch 320. The first sub-scan line 521 and the third sub-scan line 523 correspond one-to-one, simultaneously turning on the first active switch 310 and the second active switch 320 within a pixel unit 710. This eliminates the need for openings to connect the second gate 321 of the second active switch 320 and the first sub-scan line 521 for each pixel unit 710, thereby reducing process complexity and improving product yield.

[0134] The second sub-scan line 522 is disposed on the front side 41 of the flexible substrate 40 and located in the third metal layer 210, and the fourth sub-scan line 524 is disposed on the back side 42 of the flexible substrate 40 and located in the first metal layer 110.

[0135] Furthermore, the second sub-scan line 522 and the fourth sub-scan line 524 are connected to the same driving signal. The second sub-scan line 522 is connected to the third gate 331 of the third active switch 330, and the fourth sub-scan line 524 is connected to the fourth gate 341 of the fourth active switch 340. The second sub-scan line 522 and the fourth sub-scan line 524 correspond one-to-one, simultaneously turning on the third active switch 330 and the fourth active switch 340 within a pixel unit 710.

[0136] This eliminates the need for openings in the fourth gate 341 and second sub-scan line 522 of the fourth active switch 340 for each pixel unit 710, thereby reducing process difficulty and improving product yield.

[0137] Figure 12 is a flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application. Figures 13a and 13b are process diagrams illustrating a method for fabricating an array substrate according to an embodiment of this application. In conjunction with Figures 12 and 13b, this application also discloses a method for fabricating an array substrate 30. This method for fabricating the array substrate 30 is used to fabricate the aforementioned array substrate 30, and includes the following steps:

[0138] S1: Form a first sub-data line, a first sub-scan line, a first active switch, and a second active switch on a flexible substrate;

[0139] S2: A passivation layer is formed on the first active switch or the second active switch;

[0140] S3: The pixel electrode is formed on the passivation layer;

[0141] The first sub-data line 511 and the first sub-scan line 521 are arranged in a vertical and horizontal pattern and divided into multiple pixel units. The first active switch 310 and the second active switch 320 in each pixel unit are respectively disposed on the front side 41 and the back side 42 of the flexible substrate 40. The first sub-data line 511, the first active switch 310, the second active switch 320 and the pixel electrode 170 are connected in sequence. The first sub-data line 511 is connected to the first active switch 310 and the second active switch 320 at the same time.

[0142] Compared to the existing method where the first active switch 310 and the second active switch 320 on the array substrate 30 are disposed on the same side of the flexible substrate 40, this application disposes the first active switch 310 and the second active switch 320 on the front side 41 and the back side 42 of the flexible substrate 40, respectively. This means that when the flexible electronic paper display panel 10 is bent, the width of the first channel 315 in the first active switch 310 widens while the width of the second channel 325 in the second active switch 320 narrows; conversely, the narrowing of the first channel 315 in the first active switch 310 and the widening of the second channel 325 in the second active switch 320 achieve mutual compensation between the changes in the first active switch 310 and the second active switch 320, thus avoiding grayscale reduction during bending of the flexible electronic paper display panel 10 and improving the display effect of the flexible electronic paper display panel 10.

[0143] Wherein, S1: the step of forming the first sub-data line, the first sub-scan line, the first active switch, and the second active switch on the flexible substrate includes:

[0144] S111: A third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer are stacked sequentially on the front side of the flexible substrate; a second gate is disposed in the third metal layer, a second sub-semiconductor is disposed in the second semiconductor layer, and a second source and a second drain are disposed in the fourth metal layer; the second gate, the second sub-semiconductor, the second source, and the second drain form the second active switch.

[0145] S112: A first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, and a second insulating layer are sequentially stacked on the back side of the flexible substrate; a first gate is disposed in the first metal layer, a first sub-semiconductor is disposed in the first semiconductor layer, and a first source and a first drain are disposed in the second metal layer; the first gate, the first sub-semiconductor, the first source, and the first drain form the first active switch.

[0146] S2: The step of forming a passivation layer on the first active switch or the second active switch includes:

[0147] S211: The passivation layer is formed on the fourth insulating layer.

[0148] This reduces the via length connecting the second active switch 320 and the pixel electrode 170, thereby reducing manufacturing complexity and improving signal transmission stability.

[0149] Figure 14 is a flowchart illustrating a method for fabricating an array substrate according to an embodiment of this application. Figures 15a and 15b are process diagrams illustrating a method for fabricating an array substrate according to an embodiment of this application. Referring to Figures 14-15b, step S1: forming a first sub-data line, a first sub-scan line, a first active switch, and a second active switch on a flexible substrate includes:

[0150] S121: A first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, and a second insulating layer are sequentially stacked on the front side of the flexible substrate; a first gate is disposed in the first metal layer, a first sub-semiconductor is disposed in the first semiconductor layer, and a first source and a first drain are disposed in the second metal layer; the first gate, the first sub-semiconductor, the first source, and the first drain form the first active switch.

[0151] S122: A third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer are sequentially stacked on the back side of the flexible substrate; a second gate is disposed in the third metal layer, a second sub-semiconductor is disposed in the second semiconductor layer, and a second source and a second drain are disposed in the fourth metal layer; the second gate, the second sub-semiconductor, the second source, and the second drain form the second active switch.

[0152] S2: The step of forming a passivation layer on the first active switch or the second active switch includes:

[0153] S221: The passivation layer is formed on the second insulating layer.

[0154] It should be noted that the limitations on each step involved in this solution are not considered as limiting the order of steps, provided that they do not affect the implementation of the specific solution. The steps listed first can be executed first, later, or even simultaneously. As long as this solution can be implemented, it should be considered to fall within the scope of protection of this application.

[0155] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0156] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. An array substrate for use in a flexible electronic paper display panel, wherein, The array substrate includes a flexible substrate, a first active switch, a second active switch, a first sub-data line, a first sub-scan line, and a pixel electrode; The first sub-data line and the first sub-scan line are disposed on the flexible substrate, and the first sub-data line and the first sub-scan line are arranged in a longitudinal and transverse manner, dividing the substrate into multiple pixel units; The first active switch and the second active switch in each pixel unit are respectively disposed on the front and back sides of the flexible substrate, and the pixel electrode is disposed on the flexible substrate and located in the pixel unit; the first sub-data line, the first active switch, the second active switch and the pixel electrode are connected in sequence.

2. The array substrate according to claim 1, wherein, The array substrate includes a first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, a second insulating layer, a passivation layer, a pixel electrode, a third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer. The first active switch includes a first gate, a first sub-semiconductor, a first source, and a first drain; the second active switch includes a second gate, a second sub-semiconductor, a second source, and a second drain. The flexible substrate has the third metal layer, the third insulating layer, the second semiconductor layer, the fourth metal layer, the fourth insulating layer, the passivation layer, and the pixel electrode stacked sequentially on its front side; the third metal layer contains the second gate, the second semiconductor layer contains the second sub-semiconductor, and the fourth metal layer contains the second source and the second drain. The flexible substrate has a first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, and a second insulating layer stacked sequentially on its back side; the first metal layer contains the first gate, the first semiconductor layer contains the first sub-semiconductor, and the second metal layer contains the first source and the first drain. The first sub-data line is connected to the first source, the first drain is connected to the second source, the second drain is connected to the pixel electrode, and the first sub-scan line is connected to both the first gate and the second gate.

3. The array substrate according to claim 2, wherein, The first sub-data line is disposed on the back side of the flexible substrate and is disposed in the second metal layer.

4. The array substrate according to claim 2, wherein, The array substrate further includes a third sub-scan line. The first sub-scan line is disposed on the back side of the flexible substrate and located in the first metal layer. The third sub-scan line is disposed on the front side of the flexible substrate and located in the third metal layer. Furthermore, the first sub-scan line and the third sub-scan line are used to connect to the same driving signal. The first sub-scan line is connected to the first gate of the first active switch, and the third sub-scan line is connected to the second gate of the second active switch. The first sub-scan line and the third sub-scan line correspond one-to-one, and simultaneously turn on the first active switch and the second active switch within a pixel unit.

5. The array substrate according to claim 1, wherein, The array substrate includes a first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, a second insulating layer, a passivation layer, a pixel electrode, a third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer. The first active switch includes a first gate, a first sub-semiconductor, a first source, and a first drain; the second active switch includes a second gate, a second sub-semiconductor, a second source, and a second drain. The flexible substrate has a first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, a second insulating layer, a passivation layer, and a pixel electrode stacked sequentially on its front side; the first metal layer contains a first gate, the first semiconductor layer contains a first sub-semiconductor, and the second metal layer contains a first source and a first drain. The back side of the flexible substrate is sequentially stacked with the third metal layer, the third insulating layer, the second semiconductor layer, the fourth metal layer, and the fourth insulating layer; the third metal layer contains the second gate, the second semiconductor layer contains the second sub-semiconductor, and the fourth metal layer contains the second source and the second drain. The first sub-data line is connected to the first source, the first drain is connected to the second source, the second drain is connected to the pixel electrode, and the first sub-scan line is connected to the first gate and the second gate.

6. The array substrate according to claim 5, wherein, Both the first sub-data line and the first sub-scan line are disposed on the front side of the flexible substrate. The first sub-scan line is located in the first metal layer and is connected to the first gate of the first active switch and the second gate of the second active switch. The first sub-data line is located in the second metal layer and is connected to the first source of the first active switch.

7. The array substrate according to claim 5, wherein, The array substrate further includes a third sub-scan line. The first sub-data line and the first sub-scan line are both disposed on the front side of the flexible substrate, and the third sub-scan line is disposed on the back side of the flexible substrate. The first sub-scan line is located in the first metal layer and is connected to the first gate of the first active switch. The first sub-data line is located in the second metal layer and is connected to the first source of the first active switch. The third sub-scan line is located in the third metal layer and is connected to the second gate of the second active switch.

8. The array substrate according to claim 2, wherein, A first channel is formed between the first source and the first drain, and a second channel is formed between the second source and the second drain. The length directions of the first channel and the second channel are on the same straight line.

9. The array substrate according to claim 2, wherein, The array substrate further includes a third active switch and a fourth active switch; the third active switch includes a third gate, a third sub-semiconductor, a third source, and a third drain; the fourth active switch includes a fourth gate, a fourth sub-semiconductor, a fourth source, and a fourth drain; The third metal layer also contains the third gate, the second semiconductor layer also contains the third sub-semiconductor, and the fourth metal layer also contains the third source and the third drain. The first metal layer also contains the fourth gate, the first semiconductor layer also contains the fourth sub-semiconductor, and the second metal layer also contains the fourth source and the fourth drain. The array substrate further includes a second sub-data line and a second sub-scan line; The first sub-data line is connected to the first source, the first drain is connected to the second source, the second drain is connected to the pixel electrode, and the first sub-scan line is connected to both the first gate and the second gate. The second sub-data line is connected to the third source, the third drain is connected to the fourth source, the fourth drain is connected to the pixel electrode, and the second sub-scan line is connected to both the third gate and the fourth gate.

10. The array substrate according to claim 9, wherein, The first sub-scan line is located within the first metal layer, and the first sub-data line is located within the second metal layer; The second sub-scan line is located within the third metal layer, and the second sub-data line is located within the fourth metal layer; the third channel formed between the third source and the third drain, and the fourth channel formed between the fourth source and the fourth drain, are located on the same straight line along their length directions.

11. The array substrate according to claim 10, wherein, A first channel is formed between the first source and the first drain, and a second channel is formed between the second source and the second drain, wherein the length direction of the first channel and the length direction of the second channel are on the same straight line; The length direction of the first channel and the length direction of the second channel are the first direction, and the length direction of the third channel and the length direction of the fourth channel are the second direction, with the first direction and the second direction being perpendicular.

12. The array substrate according to claim 2, wherein, The array substrate further includes a first electrode plate, a second electrode plate, a first common electrode sheet, and a second common electrode sheet. The first common electrode sheet is disposed within the first metal layer, the first electrode plate is disposed within the second metal layer, the second common electrode sheet is disposed within the third metal layer, and the second electrode plate is disposed within the fourth metal layer. Both the first common electrode sheet and the second common electrode sheet are used to connect to the common electrode layer, and both the first electrode plate and the second electrode plate are connected to the pixel electrode; a first storage capacitor is formed between the first electrode plate and the first common electrode sheet, and a second storage capacitor is formed between the second electrode plate and the second common electrode sheet.

13. The array substrate according to claim 12, wherein, The areas of the first electrode plate, the second electrode plate, the first common electrode sheet, and the second common electrode sheet are all equal.

14. The array substrate according to claim 12, wherein, The orthographic projection of the first common electrode sheet on the flexible substrate overlaps with the orthographic projection of the second common electrode sheet on the flexible substrate; the second electrode plate covers the left portion of the second common electrode sheet, and the first electrode plate covers the right portion of the first common electrode sheet.

15. The array substrate according to claim 12, wherein, The orthographic projection of the first common electrode sheet on the flexible substrate overlaps with the orthographic projection of the second common electrode sheet on the flexible substrate; the second electrode plate covers the right side of the second common electrode sheet, and the first electrode plate covers the left side of the first common electrode sheet.

16. A method for fabricating an array substrate, wherein, The method for preparing the array substrate is used to prepare the array substrate according to any one of claims 1-15, and the steps include: A first sub-data line, a first sub-scan line, a first active switch, and a second active switch are formed on a flexible substrate; A passivation layer is formed on the first active switch or the second active switch; The pixel electrode is formed on the passivation layer; The first sub-data line and the first sub-scan line are arranged in a vertical and horizontal pattern and divided into multiple pixel units. The first active switch and the second active switch in each pixel unit are respectively disposed on the front and back sides of the flexible substrate. The first sub-data line, the first active switch, the second active switch and the pixel electrode are connected in sequence. The first sub-data line is connected to the first active switch and the second active switch at the same time.

17. The method for fabricating an array substrate according to claim 16, wherein, The step of forming the first sub-data line, the first sub-scan line, the first active switch, and the second active switch on the flexible substrate includes: A third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer are sequentially stacked on the front side of the flexible substrate; a second gate is disposed in the third metal layer, a second sub-semiconductor is disposed in the second semiconductor layer, and a second source and a second drain are disposed in the fourth metal layer; the second gate, the second sub-semiconductor, the second source, and the second drain form the second active switch. A first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, and a second insulating layer are sequentially stacked on the back side of the flexible substrate; a first gate is disposed in the first metal layer, a first sub-semiconductor is disposed in the first semiconductor layer, and a first source and a first drain are disposed in the second metal layer; the first gate, the first sub-semiconductor, the first source, and the first drain form the first active switch. The step of forming a passivation layer on the first active switch or the second active switch includes: The passivation layer is formed on the fourth insulating layer.

18. The method for fabricating an array substrate according to claim 16, wherein, The step of forming the first sub-data line, the first sub-scan line, the first active switch, and the second active switch on the flexible substrate includes: A first metal layer, a first insulating layer, a first semiconductor layer, a second metal layer, and a second insulating layer are sequentially stacked on the front side of the flexible substrate; a first gate is disposed in the first metal layer, a first sub-semiconductor is disposed in the first semiconductor layer, and a first source and a first drain are disposed in the second metal layer; the first gate, the first sub-semiconductor, the first source, and the first drain form the first active switch. A third metal layer, a third insulating layer, a second semiconductor layer, a fourth metal layer, and a fourth insulating layer are sequentially stacked on the back side of the flexible substrate; a second gate is disposed in the third metal layer, a second sub-semiconductor is disposed in the second semiconductor layer, and a second source and a second drain are disposed in the fourth metal layer; the second gate, the second sub-semiconductor, the second source, and the second drain form the second active switch. The step of forming a passivation layer on the first active switch or the second active switch includes: The passivation layer is formed on the second insulating layer.

19. A flexible electronic paper display panel, wherein, The flexible electronic paper display panel includes an electronic paper film and an array substrate as described in any one of claims 1-15, wherein the electronic paper film is attached to the array substrate and is located on the side of the pixel electrode opposite to the flexible substrate.

20. The flexible electronic paper display panel according to claim 19, wherein, The electronic paper film includes a particle layer and a common electrode layer. The common electrode layer is located on the side of the particle layer away from the array substrate, and an electric field is formed between the common electrode layer and the pixel electrode on the array substrate.

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