In-plane 2d telluride hetero-phase structures and methods for fabrication

Abstract

A device includes a substrate, an insulator, a first semimetallic 1T' phase telluride portion, a semiconducting 2H phase telluride portion, and a second semimetallic 1T' phase telluride portion. The insulator is on the substrate. The first semimetallic 1T' phase telluride portion is on the insulator. The semiconducting 2H phase telluride portion is on the insulator and seamlessly connected at the atomic level to the first semimetallic 1T' phase telluride portion. The second semimetallic 1T' phase telluride portion is on the insulator and spaced apart from the first semimetallic 1T' phase telluride portion and seamlessly connected at the atomic level to the semiconducting 2HI phase telluride portion.

Description

IN-PLANE 2D TELLURIDE HETERO PHASE STRUCTURES AND METHODS FOR FABRICATIONCross-reference to Related Application

[0001] This application claims the benefit of and priority to United States Provisional Application No. 63 / 713,821 filed on October 30, 2024, the contents of which are incorporated herein by reference in their entirety for all purposes.Field

[0002] The present disclosure relates generally to in-plane 2D telluride hetero-phase structures and methods for fabrication. In particular, the present disclosure relates to in-plane 2D telluride hetero-phase structures fabricated by simultaneously forming a semimetallic IT' phase telluride portion seamlessly connected at the atomic level to a semiconducting 211 phase telluride portion.Background

[0003] Typical transistors with 2D material channels are Schottky barrier transistors, which have large contact resistance due to high Schottky barrier, atomically thin body, and Fermi level pinning. This high contact resistance significantly limits current injection efficiency and overall device performance, especially at low operating voltages. Moreover, the lack of robust doping strategies and the sensitivity of 2D materials to interface states further exacerbate the challenge of achieving low-resistance contacts.Summary

[0004] It has been demonstrated that employing a 1T' / 2H phase heterojunction may significantly reduce contact resistance in MoTe2 2D transistors. One suggested fabrication method for MoTe2 2D transistors involves using a laser to induce phase change in specific areas of the 2H MoTe2 flake, thereby creating a 1T' / 2H MoTe2 heterojunction. This method, however, fails to ensure good crystallinity in the IT' MoTe2 contact region and does not support large-scale fabrication. Alternatively, some studies have shown that a 1T' / 2H MoTe2 heterojunction may be formed during a chemical vapor deposition (CVD) process bycontrolling reaction parameters such as duration and temperature, which results in low contact resistance. However, the random determination of the position and dimensions of the IT' and 2H phase MoTe2 regions during the synthesis makes these approaches impractical for very large scale integrated (VLSI) device fabrication. Other approaches include multi-step processes such as transferring IT’ contacts onto the 2H phase M0TC2 or using CVD twice to fomi the 2H and IT’ phase MoTe2 regions, both of which complicate the fabrication process.

[0005] The in-plane 2D telluride hetero-phase structures disclosed herein effectively reduce the contact resistance while maintaining a high on / off ratio by taking advantage of the semiconducting nature of the 2H phase and the semimetallic properties of the IT’ phase. The hetero-phase structures may be used for high performance logic transistors, memories, photo detectors, etc., where the IT’ phase transition metal dichalcogenide (TMD) serves as the source and drain contacts, while the 2H phase TMD serves as the channel. The methods disclosed herein simplify the fabrication process for in-plane 2D telluride hetero-phase structures, allow for large-scale production, and provide precise control over the position and dimensions of the devices, facilitating a scaling down of the device size. By addressing the issue of large contact resistance, the current disclosure enhances the commercial viability of 2D transistors and resolves a significant challenge in 2D transistor technology.

[0006] Some examples of the present disclosure relate to a device. The device includes a substrate, an insulator, a first semimetallic IT’ phase telluride portion, a semiconducting 2H phase telluride portion, and a second semimetallic IT’ phase telluride portion. The insulator is on the substrate. The first semimetallic IT’ phase telluride portion is on the insulator. The semiconducting 2H phase telluride portion is on the insulator and seamlessly connected at the atomic level to the first semimetallic IT’ phase telluride portion. The second semimetallic IT' phase telluride portion is on the insulator and spaced apart from the first semimetallic IT' phase telluride portion and seamlessly connected at the atomic level to the semiconducting 2H phase telluride portion.

[0007] Other examples of the present disclosure relate to a method for fabricating an in-plane 2D telluride hetero-phase structure. The method includes forming an insulating layer on a substrate. The method includes forming a first metal portion and a second metal portion spaced apart from the first metal portion on the insulating layer such that a portion of the insulating layer is exposed directly between the first metal portion and the second metal portion. The method includes simultaneously converting the first metal portion and the second metal portion to a semimetallic IT' phase telluride while forming a semiconducting2H phase telluride on the exposed portion of the insulating layer between the first metal portion and the second metal portion.

[0008] Additional features and advantages will be set forth in the detailed description which follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the embodiments as described herein, including the detailed description which follows, the claims, as well as the appended drawings.Brief Description of the Drawings

[0009] The disclosure may be more completely understood in consideration of the following description of various illustrative embodiments in connection with the accompanying drawings in which:

[0010] FIG. 1 is a top view illustrating an exemplary in-plane 2D telluride hetero-phase structure;

[0011] FIG. 2 is a cross-sectional view illustrating an exemplary back-gated hetero-phase telluride transistor;

[0012] FIG. 3 is a cross-sectional view illustrating an exemplary top-gated hetero-phase telluride transistor;

[0013] FIG. 4 is a cross-sectional view illustrating an exemplary PN diode based on heterophase telluride;

[0014] FIG. 5 is a cross-sectional view illustrating an exemplary flash memory cell based on hetero-phase telluride;

[0015] FIG. 6A is a cross-sectional view and FIG. 6B is a top view illustrating an exemplary radio frequency (RF) transistor based on hetero-phase telluride;

[0016] FIGS. 7A-7E are cross-sectional views illustrating an exemplary method for fabricating an in-plane 2D telluride hetero-phase structure;

[0017] FIGS. 8A-8C are top views illustrating an exemplary method for fabricating an array of in-plane 2D telluride hetero-phase structures; and

[0018] FIGS. 9A-9D are flow diagrams illustrating an exemplary method for fabricating an in-plane 2D telluride hetero-phase structure.Detailed Description

[0019] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific examples inwhich the disclosure may be practiced. It is to be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims. It is to be understood that features of the various examples described herein may be combined, in part or whole, with each other, unless specifically noted otherwise.

[0020] As used herein, directional terms such as "up," "down," "left," "right," "front," "back," "top," "bottom," "vertical," and "horizontal" refer solely to the orientation depicted in the accompanying figures. These terms are intended to aid in understanding the illustrations and do not indicate fixed or absolute spatial directions in any real-world context.

[0021] FIG. 1 is a top view illustrating an exemplary in-plane 2D telluride hetero-phase structure 100. The in-plane 2D telluride hetero-phase structure 100 includes a first semimetallic IT' phase telluride portion 110a, a semiconducting 2H phase telluride portion 120, and a second semimetallic IT' phase telluride portion 110b. The first semimetallic IT' phase telluride portion 110a is spaced apart from the second semimetallic IT' phase telluride portion 110b, such that the semiconducting 2H phase telluride portion 120 extends between the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b. The semiconducting 2H phase telluride portion 120 is seamlessly connected at the atomic level to the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b, such that the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b are connected through covalent bonds to the semiconducting 2H phase telluride portion 120. The first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b may form source and drain contacts of a device, while the semiconducting 2H phase telluride portion 120 may form a channel region of the device.

[0022] In some examples, the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b may include molybdenum ditelluride (MoTe2), tungsten telluride (WTe2), molybdenum tungsten telluride (MoxW1−xTe2), tungsten selenium telluride (WSe2x−2xTe2x), tungsten sulfur telluride (WSe2x−2xTe2x), or another suitable telluride. In some examples, the semiconducting 2H phase telluride 120 may include molybdenum ditelluride (MoTe2), molybdenum tungsten telluride (MoxW1−xTe2), molybdenum selenium telluride (MoSe2X-2XTe2X), molybdenum sulfur telluride(MoSe2x−2xTe2x), tungsten selenium telluride (WSe2x−2xTe2x), tungsten sulfur telluride (WSe2x−2xTe2x), or another suitable telluride.

[0023] By seamlessly connecting the semiconducting 2H phase telluride portion 120 at the atomic level through covalent bonds to the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b, device quality is enhanced. For a telluride including MoTe2, which has a bandgap of about 1 eV, the in-plane 2D telluride hetero-phase structure 100 is suitable for both n-type and p-type channel devices. For example, the in-plane 2D telluride hetero-phase structure 100 may be used for ultra-scaled and energy efficient logic, memory, and optoelectronic devices for advanced computing and optical communication applications. Example devices including an in-plane 2D telluride hetero-phase structure 100 are described below with reference to FIGS. 2-6B.

[0024] FIG. 2 is a cross-sectional view illustrating an exemplary back-gated hetero-phase telluride transistor 200. The transistor 200 includes a first semimetallic IT’ phase telluride portion 110a, a semiconducting 2H phase telluride portion 120, and a second semimetallic IT' phase telluride portion 110b as previously described and illustrated with reference to FIG.1. In addition, the transistor 200 includes a substrate 210a, an insulator 220, a first metal electrode 230a, and a second metal electrode 230b. The insulator 220 is on (e.g., directly on) the substrate 210a, such that the bottom surface of the insulator 220 contacts (e.g., directly contacts) the top surface of the substrate 210a. The first semimetallic IT' phase telluride portion 110a is on (e.g., directly on) the insulator 220, such that the bottom surface of the first semimetallic IT' phase telluride portion 110a contacts (e.g., directly contacts) the top surface of the insulator 220. The semiconducting 2H phase telluride portion 120 is on (e.g., directly on) the insulator 220, such that the bottom surface of the semiconducting 2H phase telluride portion 120 contacts (e.g., directly contacts) the top surface of the insulator 220. The second semimetallic IT' phase telluride portion 110b is on (e.g., directly on) the insulator 220, such that the bottom surface of the second semimetallic IT' phase telluride portion 410b contacts (e.g., directly contacts) the top surface of the insulator 220.

[0025] As previously described and illustrated with reference to FIG. 1, the semiconducting 2H phase telluride portion 120 is between and seamlessly connected at the atomic level to the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b. A thickness (between the bottom surface and the top surface) of the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b may be greater than a thickness (between the bottom surface and thetop surface) of the semiconducting 2H phase telluride portion 120. In some examples, the thickness of the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT' phase telluride portion 110b may be greater than the thickness of the semiconducting 2H phase telluride portion 120 due to the fabrication process described below with reference to FIGS. 7A-9D.

[0026] The first metal electrode 230a is on (e.g., directly on) the first semimetallic IT' phase telluride portion 110a, such that the bottom surface of the first metal electrode 230a contacts (e.g., directly contacts) the top surface of the first semimetallic IT' phase telluride portion 110a. The second metal electrode 230b is on (e.g., directly on) the second semimetallic IT' phase telluride portion 110b, such that the bottom surface of the second metal electrode 230b contacts (e.g., directly contacts) the top surface of the second semimetallic IT' phase telluride portion 110b. In some examples, the metal electrodes 230a and 230b can be omitted, as the IT' phase telluride portions 110a and 110b are conductive, which can serve as the source / drain electrodes.

[0027] In back-gated transistor 200, the substrate 210a may include silicon, germanium, silicon germanium, a group III-V material, a group II- VI material, a metal, or other conducting or semiconducting materials. In this case, the substrate can serve as the back-gate for the transistor 200. In some examples, the insulator 220 may include silicon dioxide (SiO2), silicon nitride (Si3N4), boron nitride (BN), aluminum oxide (AbOs), hafnium oxide (HfCh), zirconium oxide (ZrCb), titanium dioxide (TiCb), tantalum pentoxide (Ta2C>5), lanthanum oxide (La Ch), yttrium oxide (Y2O3), and / or another suitable dielectric material (e.g., high-k material) or a combination thereof. In some examples, the first metal electrode 230a and the second metal electrode 230b may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), cobalt (Co), platinum (Pt), or another suitable metal.

[0028] In this example, the first semimetallic IT' phase telluride portion 110a forms a first source / drain region (e.g., source region) of the transistor 200, the second semimetallic IT' phase telluride portion 110b forms a second source / drain region (e.g., drain region) of the transistor 200, and the semiconducting 2H phase telluride portion 120 forms a channel region of the transistor 200. The first metal electrode 230a forms a first source / drain contact (e.g., source contact) for the transistor 200, the second metal electrode 230b forms a second source / drain contact (e.g., drain contact) for the transistor 200, the substrate 210a can serve as the back gate for the transistor 200, and the insulator 220 can serve as the back gate insulator for the transistor 200.

[0029] FIG. 3 is a cross-sectional view illustrating an exemplary top-gated hetero-phase telluride transistor 300. The transistor 300 includes a first semimetallic IT' phase telluride portion 110a, a semiconducting 2H phase telluride portion 120, and a second semimetallic IT' phase telluride portion 110b as previously described and illustrated with reference to FIG.1. The transistor 300 also includes a substrate 210b, which may include silicon, germanium, silicon germanium, a group III-V material, a group II- VI material, sapphire, quartz, polyethylene terephthalate (PET), polyimide, or poly(dimethyl siloxane) (PDMS). The transistor 300 also includes an insulator 220, a first metal electrode 230a, and a second metal electrode 230b as previously described and illustrated with reference to FIG. 2. In some examples, the insulator 220 can be omitted if the substrate 210b is non-conductive. In addition, the transistor 300 includes a gate insulator 310 and a gate electrode 320. The gate insulator 310 is on (e.g., directly on) the semiconducting 2H phase telluride portion 120, such that the bottom surface of the gate insulator 310 contacts (e.g., directly contacts) the top surface of the semiconducting 2H phase telluride portion 120. In some examples, the gate insulator 310 may also contact (e.g., directly contact) a portion of the top surface of the first semimetallic IT' phase telluride portion 110a (which is not covered by the first metal electrode 230a) and a portion of the top surface of the second semimetallic IT' phase telluride portion 110b (which is not covered by the second metal electrode 230b). The gate electrode 320 is on (e.g., directly on) the gate insulator 310, such that the bottom surface of the gate electrode 320 contacts (e.g., directly contacts) the top surface of the gate insulator 310.

[0030] In some examples, the gate insulator 310 may include silicon dioxide (SiCE), silicon nitride (Si3N4), boron nitride (BN), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), and / or another suitable dielectric material (e.g., high-k material) or combination thereof. In some examples, the gate electrode 320 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), cobalt (Co), platinum (Pt), or another suitable metal.

[0031] In this example, the first semimetallic IT' phase telluride portion 110a forms a first source / drain region (e.g., source region) of the transistor 300, the second semimetallic IT' phase telluride portion 110b forms a second source / drain region (e.g., drain region) of the transistor 300, and the semiconducting 2H phase telluride portion 120 forms a channel region of the transistor 300. The first metal electrode 230a forms a first source / drain contact (e.g.,source contact) for the transistor 300 and the second metal electrode 230b forms a second source / drain contact (e.g., drain contact) for the transistor 300.

[0032] FIG. 4 is a cross-sectional view illustrating an exemplary PN diode 400 based on hetero-phase telluride. The PN diode 400 includes a substrate 210b, an insulator 220, a first metal electrode 230a, and a second metal electrode 230b as previously described and illustrated with reference to FIG. 2. In addition, the PN diode 400 includes a first semimetallic IT' phase telluride portion 410a, a second semimetallic IT' phase telluride portion 410b, a first semiconducting 2H phase telluride portion 420a, and a second semiconducting 2H phase telluride portion 420b.

[0033] The first semimetallic IT' phase telluride portion 410a is on (e.g., directly on) the insulator 220, such that the bottom surface of the first semimetallic IT' phase telluride portion 41 a contacts (e.g., directly contacts) the top surface of the insulator 220. The first semiconducting 2H phase telluride portion 420a is on (e.g., directly on) the insulator 220, such that the bottom surface of the first semiconducting 2H phase telluride portion 420a contacts (e.g., directly contacts) the top surface of the insulator 220. The second semiconducting 2H phase telluride portion 420b is on (e.g., directly on) the insulator 220, such that the bottom surface of the second semiconducting 2H phase telluride portion 420b contacts (e.g., directly contacts) the top surface of the insulator 220. The second semimetallic IT' phase telluride portion 410b is on (e.g., directly on) the insulator 220, such that the bottom surface of the second semimetallic IT' phase telluride portion 410b contacts (e.g., directly contacts) the top surface of the insulator 220.

[0034] The first semiconducting 2H phase telluride portion 420a is seamlessly connected at the atomic level to the second semiconducting 2H phase telluride portion 420b. The first semiconducting 2H phase telluride portion 420a and the second semiconducting 2H phase telluride portion 420b are between the first semimetallic IT phase telluride portion 410a and the second semimetallic I phase telluride portion 410b. The first IT' phase telluride portion 410a is seamlessly connected at the atomic level to the first semiconducting 211 phase telluride portion 420a, and the second IT' phase telluride portion 410b is seamlessly connected at the atomic level to the second semiconducting 2H phase telluride portion 420b. A thickness (between the bottom surface and the top surface) of the first semimetallic IT' phase telluride portion 410a and the second semimetallic IT' phase telluride portion 410b may be greater than a thickness (between the bottom surface and the top surface) of the first semiconducting 2H phase telluride portion 420a and the second semiconducting 2H phasetelluride portion 420b. In some examples, the thickness of the first semimetallic IT’ phase telluride portion 410a and the second semimetallic IT' phase telluride portion 410b may be greater than the thickness of the first semiconducting 2H phase telluride portion 420a and the second semiconducting 2H phase telluride portion 420b due to the fabrication process described below with reference to FIGS. 7A-9D.

[0035] The first metal electrode 230a is on (e.g., directly on) the first semimetallic IT' phase telluride portion 410a, such that the bottom surface of the first metal electrode 230a contacts (e.g., directly contacts) the top surface of the first semimetallic IT' phase telluride portion 410a. The second metal electrode 230b is on (e.g., directly on) the second semimetallic IT' phase telluride portion 410b, such that the bottom surface of the second metal electrode 230b contacts (e.g., directly contacts) the top surface of the second semimetallic IT' phase telluride portion 410b.

[0036] The first semiconducting 2H phase telluride portion 420a forms an n-type doped region and the second semiconducting 2H phase telluride portion 420b forms a p-type doped region thereby forming a p-n junction. In some examples, the n-type doped region 420a and the p-type doped region 420b may be formed by selectively diffusing or implanting dopants into a semiconducting 2H phase telluride portion (e.g., 120 of FIG. 1 or 2) to form the first semiconducting 2H phase telluride portion 420a and the second semiconducting 2H phase telluride portion 420b. The first semimetallic IT' phase telluride portion 410a contacts (e.g., is seamlessly connected at the atomic level) the first semiconducting 2H phase telluride portion 420a (e.g., n-type region) and includes a first (e.g., low) work function. The second semimetallic IT' phase telluride portion 410b contacts (e.g., is seamlessly connected at the atomic level) the second semiconducting 2H phase telluride portion 420b (e.g., p-type region) and includes a second (e.g., high) work function. In some examples, the first work function of the first semimetallic IT' phase telluride portion 410a and the second work function of the second semimetallic IT' phase telluride portion 410b may be set by selectively depositing different metals at these regions before tellurization will form the first semimetallic IT' phase telluride portion 410a and the second semimetallic IT' phase telluride portion 410b having the desired work functions, respectively. For example, yttrium (Y) and molybdenum (Mo) can be co-deposited in region 1, while rhodium (Rh) and molybdenum (Mo) can be codeposited in region 2. After tellurization, Y-doped IT' MoTe2 will provide low work function, while Rh-doped IT' MoTe2 will provide high work function.

[0037] In this example, the first metal electrode 230a forms a first contact for the PN diode 400, and the second metal electrode 230b forms a second contact for the PN diode 400. In some examples, the PN diode 400 may form a solar cell, a photodetector, a laser, or another suitable device.

[0038] FIG. 5 is a cross-sectional view illustrating an exemplary flash memory cell 500 based on hetero-phase telluride. The flash memory cell 500 includes a first semimetallic IT' phase telluride portion 110a, a semiconducting 2H phase telluride portion 120, and a second semimetallic IT' phase telluride portion 110b as previously described and illustrated with reference to FIG. 1. The flash memory cell 500 also includes a substrate 210b, an insulator 220, a first metal electrode 230a, and a second metal electrode 230b as previously described and illustrated with reference to FIG. 2. In addition, the flash memory cell 500 includes a tunnel insulator 510, a floating gate or charge trapping layer 520, a gate insulator 530, and a gate electrode 540.

[0039] The tunnel insulator 510 is on (e.g., directly on) the semiconducting 2H phase telluride portion 120, such that the bottom surface of the tunnel insulator 510 contacts (e.g., directly contacts) the top surface of the semiconducting 2H phase telluride portion 120. In some examples, the tunnel insulator 510 may also contact (e.g., directly contact) a portion of the top surface of the first semimetallic IT' phase telluride portion 110a (which is not covered by the first metal electrode 230a) and a portion of the top surface of the second semimetallic IT' phase telluride portion 110b (which is not covered by the second metal electrode 230b). The floating gate or charge trapping layer 520 is on (e.g., directly on) the tunnel insulator 510, such that the bottom surface of the floating gate or charge trapping layer 520 contacts (e.g., directly contacts) the top surface of the tunnel insulator 510. The gate insulator 530 is on (e.g., directly on) the floating gate or charge trapping layer 520, such that the bottom surface of the gate insulator 530 contacts (e.g., directly contacts) the top surface of the floating gate or charge trapping layer 520. The gate electrode 540 is on (e.g., directly on) the gate insulator 530, such that the bottom surface of the gate electrode 540 contacts (e.g., directly contacts) the top surface of the gate insulator 530.

[0040] In some examples, where the floating gate or charge trapping layer 520 is a floating gate, the floating gate may include polysilicon, graphene, titanium (Ti), gold (Au), titanium nitride (TiN), lead (Pd), nickel (Ni), tungsten (W), and / or another suitable material or combination thereof. In some examples, where the floating gate or charge trapping layer 520 is a charge trapping layer, the charge trapping layer may include silicon nitride (Si3N4),oxynitride, aluminum oxide (AI2O3), hafnium oxide (HfCh), zirconium oxide (ZrCh), titanium dioxide (TiCh), tantalum pentoxide (d h), lanthanum oxideyttrium oxide (Y2O3), and / or another suitable material or combination thereof. In some examples, the tunnel insulator 510 and / or the gate insulator 530 may include silicon dioxide (SiO2), silicon nitride (SisN4), boron nitride (BN), aluminum oxide (AI2O3), hafnium oxide (HfCF), zirconium oxide (ZrCh), titanium dioxide (TiCF), tantalum pentoxide (Ta2C>5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), and / or another suitable dielectric material (e.g., high-k material) or combination thereof.

[0041] In this example, the first semimetallic IT' phase telluride portion 110a forms a first source / drain region (e.g., source region) of the flash memory cell 500, the second semimetallic IT' phase telluride portion 110b forms a second source / drain region (e.g., drain region) of the flash memory cell 500, and the semiconducting 2H phase telluride portion 120 forms a channel region of the flash memory cell 500. The first metal electrode 230a forms a first source / drain contact (e.g., source contact) for the flash memory cell 500, and the second metal electrode 230b forms a second source / drain contact (e.g., drain contact) for the flash memory cell 500.

[0042] FIG. 6A is a cross-sectional view (e.g., along A- A' of FIG. 6B) and FIG. 6B is a top view illustrating an exemplary RF transistor 600 based on hctcro-phasc telluride. The RF transistor 600 includes a first semimetallic IT' phase telluride portion 110a, a (e.g., first) semiconducting 2H phase telluride portion 120a, a second semimetallic IT' phase telluride portion 110b, a further (e.g., second) semiconducting 2H phase telluride portion 120b, and a third semimetallic IT' phase telluride portion 110c. The first semimetallic IT' phase telluride portion 110a, the second semimetallic IT’ phase telluride portion 110b, and the third semimetallic IT' phase telluride portion 110c are similar to the semimetallic IT' phase telluride portions 110a and 110b of FIG. 1. The first semiconducting 2H phase telluride portion 120a and the second semiconducting 2H phase telluride portion 120b are similar to the semiconducting 211 phase telluride portion 120 of FIG. 1. The RF transistor 600 also includes a substrate 210b, an insulator 220, a first metal electrode 230a, and a second metal electrode 230b as previously described and illustrated with reference to FIG. 2. In addition, the RF transistor 600 includes a gate insulator 610a and 610b, a gate electrode 620 including two fingers 620a and 620b, and a third (e.g., center) metal electrode 630.

[0043] The first semimetallic IT' phase telluride portion 110a is on (e.g., directly on) the insulator 220, such that the bottom surface of the first semimetallic IT' phase telluride portion110a contacts (e.g., directly contacts) the top surface of the insulator 220. The first semiconducting 2H phase telluride portion 120a is on (e.g., directly on) the insulator 220, such that the bottom surface of the first semiconducting 2H phase telluride portion 120a contacts (e.g., directly contacts) the top surface of the insulator 220. The second semimetallic IT' phase telluride portion 110b is on (e.g., directly on) the insulator 220, such that the bottom surface of the second semimetallic IT' phase telluride portion 410b contacts (e.g., directly contacts) the top surface of the insulator 220. Similarly, as described and illustrated with reference to FIG. 1, the first semiconducting 2H phase telluride portion 120a is between and seamlessly connected at the atomic level to the first semimetallic IT' phase telluride portion 110a and the second semimetallic IT’ phase telluride portion 110b. The second semiconducting 2H phase telluride portion 120b is on (e.g., directly on) the insulator 220, such that the bottom surface of the second semiconducting 2H phase telluride portion 120b contacts (e.g., directly contacts) the top surface of the insulator 220. The third semimetallic IT’ phase telluride portion 110c is on (e.g., directly on) the insulator 220, such that the bottom surface of the third semimetallic IT' phase telluride portion 110c contacts (e.g., directly contacts) the top surface of the insulator 220. Similarly, as described and illustrated with reference to FIG. 1, the second semiconducting 2H phase telluride portion 120b is between and seamlessly connected at the atomic level to the second semimetallic IT' phase telluride portion 110b and the third semimetallic IT' phase telluride portion 110c.

[0044] The first metal electrode 230a is on (e.g., directly on) the first semimetallic IT' phase telluride portion 110a, such that the bottom surface of the first metal electrode 230a contacts (e.g., directly contacts) the top surface of the first semimetallic IT' phase telluride portion 110a. The second metal electrode 230b is on (e.g., directly on) the third semimetallic IT' phase telluride portion 110c, such that the bottom surface of the second metal electrode 230b contacts (e.g., directly contacts) the top surface of the third semimetallic IT' phase telluride portion 110c. The third metal electrode 630 is on (e.g., directly on) the second semimetallic IT’ phase telluride portion 110b, such that the bottom surface of the third metal electrode 630 contacts (e.g., directly contacts) the top surface of the second semimetallic IT' phase telluride portion 110b.

[0045] The gate insulator 610a is on (e.g., directly on) the first semiconducting 2H phase telluride portion 120a, such that the bottom surface of the gate insulator 610a contacts (e.g., directly contacts) the top surface of the first semiconducting 2H phase telluride portion 120a. In some examples, the gate insulator 610a may also contact (e.g., directly contact) a portionof the top surface of the first semimetallic IT’ phase telluride portion 110a (which is not covered by the first metal electrode 230a) and a portion of the top surface of the second semimetallic IT' phase telluride portion 110b (which is not covered by the third metal electrode 630). The gate insulator 610b is on (e.g., directly on) the second semiconducting 2H phase telluride portion 120b, such that the bottom surface of the gate insulator 610b contacts (e.g., directly contacts) the top surface of the second semiconducting 2H phase telluride portion 120b. In some examples, the gate insulator 610b may also contact (e.g., directly contact) a portion of the top surface of the second semimetallic IT’ phase telluride portion 110b (which is not covered by the third metal electrode 630) and a portion of the top surface of the third semimetallic IT' phase telluride portion 110c (which is not covered by the second metal electrode 230b).

[0046] The gate electrode finger 620a of gate electrode 620 is on (e.g., directly on) the gate insulator 610a, such that the bottom surface of the gate electrode finger 620a contacts (e.g., directly contacts) the top surface of the gate insulator 610a. The gate electrode finger 620b of gate electrode 620 is on (e.g., directly on) the gate insulator 610b, such that the bottom surface of the gate electrode finger 620b contacts (e.g., directly contacts) the top surface of the gate insulator 610b.

[0047] In some examples, the gate insulator 610a and 610b includes silicon dioxide (SiCL), silicon nitride (Si3N4), boron nitride (BN), aluminum oxide (AI2O3), hafnium oxide (HfCh), zirconium oxide (ZrCF), titanium dioxide (TiCF), tantalum pentoxide (Ta2Os), lanthanum oxide (La2Ch), yttrium oxide (Y2O3) and / or another suitable dielectric material (e.g., high-k material) or combination thereof. In some examples, the gate electrode 620 and / or the third metal electrode 630 may include copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), cobalt (Co), platinum (Pt), or another suitable metal.

[0048] In this example, the first semimetallic IT' phase telluride portion 110a forms a first source / drain region (e.g., source region) of the RF transistor 600, the third semimetallic IT' phase telluride portion 110c forms a second source / drain region (e.g., drain region) of the RF transistor 600, and the first semiconducting 2H phase telluride portion 120a, the second semimetallic IT' phase telluride portion 110b, and the second semiconducting 2H phase telluride portion 120b form a channel region of the RF transistor 600. The first metal electrode 230a forms a first source / drain contact (e.g., source contact) for the RF transistor 600, the second metal electrode 230b forms a second source / drain contact (e.g., drain contact) for the RF transistor 600, and the third metal electrode 630 forms a center contact for the RFtransistor 600. The third metal electrode 630 and the second semimetallic IT’ phase telluride portion 110b extend between the two fingers 620a and 620b of the gate electrode 620.

[0049] FIGS. 7A-7E are cross-sectional views illustrating an exemplary method for fabricating an in-plane 2D telluride hetero-phase structure, such as used within back-gated hctcro-phasc telluride transistor 200 of FIG. 2, top-gated hetero-phase telluride transistor 300 of FIG. 3, PN diode 400 of FIG. 4, flash memory cell 500 of FIG. 5, RF transistor 600 of FIGS. 6A and 6B, and / or other devices. As illustrated in FIG. 7A at 700a, the method includes providing a substrate 210 (e.g., 210a or 210b). In some examples, the substrate 210 may include silicon, germanium, silicon germanium, a group III-V material, a group II- VI material, sapphire, quartz, polyethylene terephthalate (PET), polyimide, poly(dimethyl siloxane) (PDMS), or other suitable metal material depending on the gating variant of the device.

[0050] As illustrated in FIG. 7B at 700b, the method includes forming an insulating layer 220 on the substrate 210. In some examples, the insulating layer 220 may include silicon dioxide (SiO2), silicon nitride (Si3N4), boron nitride (BN), aluminum oxide (Al2O3), hafnium oxide (HfCh), zirconium oxide (ZrO2). titanium dioxide (TiCF), tantalum pentoxide (Ta2C>5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), and / or another suitable dielectric material or combination thereof. Insulating layer 220 may be formed on substrate 210 via spin coating, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable process.

[0051] As illustrated in FIG. 7C at 700c, the method includes forming a first metal portion 710a and a second metal portion 710b spaced apart from the first metal portion 710a on the insulating layer 220, such that a portion of the insulating layer 220 is exposed directly between the first metal portion 710a and the second metal portion 710b. In some examples, the first metal portion 710a and the second metal portion 710b may include molybdenum (Mo), tungsten (W), yttrium (Y), rhodium (Rh), and / or another suitable metal or combination thereof. First metal portion 710a and second metal portion 710b may be formed on insulating layer 220 using photolithography and etching processes, E-beam lithography, sputtering, inkjet printing, or another suitable process.

[0052] As illustrated in FIG. 7D at 700d, the structure at 700c of FIG. 7C is placed into a deposition chamber 720 (e.g., a chemical vapor deposition (CVD) chamber or a metal organic chemical vapor deposition (MOCVD) chamber) and subjected to a CVD or MOCVD process using precursors 730a and 730b. The CVD or MOCVD process simultaneously converts thefirst metal portion 710a and the second metal portion 710b to a semimetallic IT' phase telluride 110a and 110b, respectively, while forming a semiconducting 2H phase telluride 120 on the exposed portion of the insulating layer 220 between the first metal portion 710a and the second metal portion 710b as illustrated in FIG. 7E at 700e. In some examples, the thickness of the semiconducting 2H phase telluride 120 is less than the thickness of the semimetallic IT' phase telluride 110a and 110b after the CVD or MOCVD process. The thickness of the semimetallic IT phase telluride 110a and 110b may be determined by the thickness of the first metal portion 710a and the second metal portion 710b deposited before CVD or MOCVD as illustrated in FIG 7C. The thickness of the semiconducting 2H phase telluride 120 may be determined by the growth temperature and time of the CVD or MOCVD process. In other examples, the thickness of the semiconducting 2H phase telluride 120 may equal the thickness of the semimetallic IT phase telluride 110a and 110b.

[0053] The CVD or MOCVD process may include a first precursor 730a and a second precursor 730b. In some examples, the first precursor 730a may include a tellurium precursor flux, and the second precursor 730b may include a molybdenum precursor flux. The semimetallic IT' phase telluride 110a and 110b may include, for example, molybdenum ditelluride (MoTe2), tungsten telluride (WTe?), molybdenum tungsten telluride (MoxW1−xTe2), tungsten selenium telluride (WSc2X-2XTc2X), or tungsten sulfur telluride (WSc2X-2XTc2X). The semiconducting 2H phase telluride 120 may include, for example, molybdenum ditelluride (MoTe2), molybdenum tungsten telluride (MoxW1−xTe2), molybdenum selenium telluride (MoSe2X-2XTe2X), molybdenum sulfur telluride (MoSe2X-2XTe2X), tungsten selenium telluride (WSe2X-2XTe2X), or tungsten sulfur telluride (WSe2X-2XTe2X).

[0054] In some examples, simultaneously converting the first metal portion 710a and the second metal portion 710b to the semimetallic IT' phase telluride 110a and 110b, respectively, while forming the semiconducting 2H phase telluride 120 on the exposed portion of the insulating layer 220 between the first metal portion 710a and the second metal portion 710b includes a single-step chemical vapor deposition (CVD) process. The CVD process may include a precursor 730a or 730b including molybdenum oxide (MoOs), molybdenum (Mo), molybdenum pentachloride (MoCb), molybdenum tetrachloride oxide (MoOCl4), molybdenum dioxo-dichloride (MOO2CI2), tellurium (Te), tellurium tetrachloride (TeCh), dimethyl selenide ((CFL^Se), selenium (Se), hydrogen selenide (H2Se), sulfur (S), hydrogen sulfide (H2S), and / or another suitable precursor.

[0055] In other examples, simultaneously converting the first metal portion 710a and the second metal portion 710b to the semimetallic IT' phase telluride 110a and 110b, respectively, while forming the semiconducting 2H phase telluride 120 on the exposed portion of the insulating layer 220 between the first metal portion 710a and the second metal portion 710b includes a single-step metal-organic chemical vapor deposition (MOCVD) process. The MOCVD process may include a precursor 730a or 730b including molybdenum hexacarbonyl (Mo(CO)e), molybdenum (Mo), bis(diethyldithiocarbamato) dioxomolybdenum (Mo(Et2NCS2)2O2), tetrakis(dimethylamido)molybdenum (Mo(NMe2)4), molybdenum acetylacetonate (Mo(acac)3), diethyl telluride ((C2H5)2Te), dimethyl telluride ((CH3)2Te), di-tert-butyl telluride ((C4H9)2Te), tellurium tetrachloride (TeCh), tris(isopropyl) telluride ((CH3)2CH)3Te), selenium (Se), dimethyl selenide ((CH3)2Se), hydrogen selenide (H2Se), diethyl selenide ((C2H5)2Se), selenourea (H2NC(Se)NH2), diisopropyl selenide((CH3)2CH)2Se), triethyl phosphine selenide ((C2H5)3PSe), sulfur (S), diethyl sulfide ((C2H5)2S), hydrogen sulfide (H2S), carbon disulfide (CS2), dimethyl sulfide ((CH3)2S), bis(trimethylsilyl)sulfide ((CH3)3Si)2S), tert-butyl thiol (C4H9SH), diisopropyl sulfide ((CH3)2CH)2S, and / or another suitable precursor.

[0056] With the semimetallic IT’ phase telluride 110a and 110b and the semiconducting 2H phase telluride 120 formed on the insulating layer 220, further processing may be used to form the back-gated hetero-phase telluride transistor 200 of FIG. 2, the top-gated heterophase telluride transistor 300 of FIG. 3, the PN diode 400 of FIG. 4, the flash memory cell 500 of FIG. 5, the RF transistor 600 of FIGS. 6A and 6B, and / or another device.

[0057] FIGS. 8A-8C are top views illustrating an exemplary method for fabricating an array of in-plane 2D telluride hetero-phase structures, such as used within back-gated hetero-phase telluride transistor 200 of FIG. 2, top-gated hetero-phase telluride transistor 300 of FIG. 3, PN diode 400 of FIG. 4, flash memory cell 500 of FIG. 5, RF transistor 600 of FIGS. 6A and 6B, and / or other devices. As illustrated in FIG. 8 A at 800a, the method includes forming a plurality of metal portions 710 on (e.g., directly on) an insulating layer 220 similarly as described and illustrated with reference to FIG. 7C. Each metal portion 710 may be spaced apart from adjacent metal portions 710 such that a portion of insulating layer 220 is exposed between adjacent metal portions 710.

[0058] As illustrated in FIG. 8B at 800b, the structure 800a of FIG. 8A is subjected to a CVD or MOCVD process similarly as described and illustrated with reference to FIG. 7D to form aplurality of semimetallic IT' phase telluride portions 110 from the plurality of metal portions 710 and 2H phase telluride 120 on the exposed portions of the insulating layer 220.

[0059] As illustrated in FIG. 8C at 800c, the method may include etching (e.g., dry etching) the semiconducting 2H phase telluride 120 to define a plurality of in-plane 2D telluride hctcro-phasc structures 810 each including a channel region from the semiconducting 2H phase telluride 120, a first contact region 110a from the semimetallic IT' phase telluride corresponding to a first metal portion 710, and a second contact region 110b from the semimetallic IT' phase telluride corresponding to a second metal portion 710. While 12 inplane 2D telluride hetero-phase structures 810 arranged in four rows and three columns are illustrated in FIG. 8C, in some examples, any suitable number (e.g., 100, 1000, 5000, or more) of in-plane 2D telluride hetero-phase structures 810 may be formed, and the structures 810 may be arranged in any suitable number of rows and / or columns and / or in other suitable configurations. With in-plane 2D telluride hetero-phase structures 810 formed on the insulating layer 220, further processing may be used to form a plurality of back-gated heterophase telluride transistors 200 of FIG. 2, a plurality of top-gated hetero-phase telluride transistors 300 of FIG. 3, a plurality of PN diodes 400 of FIG. 4, a plurality of flash memory cells 500 of FIG. 5, and / or a plurality of other devices. A similar process as described with reference to FIGS. 8A-8C may be used to form a plurality of RF transistors 600 of FIGS. 6A and 6B.

[0060] FIGS. 9A-9D are flow diagrams illustrating an exemplary method 900 for fabricating an in-plane 2D telluride hetero-phase structure, such as used within back-gated hetero-phase telluride transistor 200 of FIG. 2, top-gated hetero-phase telluride transistor 300 of FIG. 3, PN diode 400 of FIG. 4, flash memory cell 500 of FIG. 5, RF transistor 600 of FIGS. 6A and 6B, and / or other devices. As illustrated in FIG. 9 A at 902, method 900 includes forming an insulating layer (e.g., 220) on a substrate (e.g., 210). The substrate includes, for example, silicon, germanium, silicon germanium, a group III-V material, a group II- VI material, or other semiconductor; an insulator, such as sapphire, quartz, polyethylene terephthalate (PET), polyimide, or poly(dimethyl siloxane) (PDMS); or a suitable metal depending on the gate configuration. The insulator layer includes, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), boron nitride (BN), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), lanthanum oxide (La2O3), and / or yttrium oxide (Y2O3).

[0061] At 904, method 900 includes forming a first metal portion (e.g., 710a) and a second metal portion (e.g., 710b) spaced apart from the first metal portion on the insulating layer such that a portion of the insulating layer is exposed directly between the first metal portion and the second metal portion. The metal may include, for example, molybdenum (Mo), tungsten (W), yttrium (Y), and / or rhodium (Rh).

[0062] At 906, method 900 includes simultaneously converting the first metal portion and the second metal portion to a semimetallic IT' phase telluride (e.g., 110) while forming a semiconducting 2H phase telluride (e.g., 120) on the exposed portion of the insulating layer between the first metal portion and the second metal portion. The semimetallic IT' phase telluride includes, for example, molybdenum ditelluride (MoTe?), tungsten telluride (WTe2), molybdenum tungsten telluride (MoxW1−xTe2), tungsten selenium telluride (WSe2X-2XTe2X), or tungsten sulfur telluride (WSe2X-2XTe2X). The semiconducting 2H phase telluride includes, for example, molybdenum ditelluride (MoTe2), molybdenum tungsten telluride (MoxWixTe2), molybdenum selenium telluride (MoSe2X-2XTe2X), molybdenum sulfur telluride(MoSe2X-2XTe2X), tungsten selenium telluride (WSe2X-2XTe2X), or tungsten sulfur telluride (WSe2x-2XTe2x).

[0063] In some examples, simultaneously converting the first metal portion and the second metal portion to the semimetallic IT' phase telluride while forming the semiconducting 2H phase telluride on the exposed portion of the insulating layer between the first metal portion and the second metal portion comprises a single-step chemical vapor deposition (CVD) process. The CVD process may include a precursor (e.g., 730a, 730b) including, for example, molybdenum oxide (MoO3), molybdenum (Mo), molybdenum pentachloride (MoCl5), molybdenum tetrachloride oxide (MoOCl4), molybdenum dioxo-dichloride (MOO2CI2), tellurium (Te), tellurium tetrachloride (TeCh), dimethyl selenide ((CH3)2Se), selenium (Se), hydrogen selenide (H2Se), sulfur (S), or hydrogen sulfide (H2S).

[0064] In other examples, simultaneously converting the first metal portion and the second metal portion to the semimetallic IT' phase telluride while forming the semiconducting 211 phase telluride on the exposed portion of the insulating layer between the first metal portion and the second metal portion comprises a single-step metal-organic chemical vapor deposition (MOCVD) process. The MOCVD process may include a precursor (e.g., 730a, 730b) including, for example, molybdenum hexacarbonyl (Mo(CO)e), molybdenum (Mo), bis(diethyldithiocarbamato) dioxomolybdenum (Mo(Et2NCS2)2O2), tetrakis(dimethylamido)molybdenum (Mo(NMe2)4), molybdenum acetylacetonate(Mo(acac)3), diethyl telluride ((C2H5)2Te), dimethyl telluride ((CH3)2Te), di-tert-butyl telluride ((C4H9)2Te), tellurium tetrachloride (TeCh), tris(isopropyl) telluride ((CH3)2CH)2Te), selenium (Se), dimethyl selenide ((CH3)2Se), hydrogen selenide (H2Se), diethyl selenide ((C2H5)2Se), selenourea (H2NC(Se)NH2), diisopropyl selenide ((CH3)2CH)2SC), triethyl phosphine selenide ((C2H5)3PSe), sulfur (S), diethyl sulfide ((C2H5)2S), hydrogen sulfide (H2S), carbon disulfide (CS2), dimethyl sulfide ((CH3)2S). bis(trimethylsilyl)sulfide ((CH3)3Si)2S), tert-butyl thiol (C4H9SH), or diisopropyl sulfide ((CH3)2CH)2S.

[0065] As illustrated in FIG. 9B at 908, method 900 may further include etching (e.g., dry etching) the semiconducting 2H phase telluride to define a transistor (e.g., 200, 810) comprising a channel region (e.g., 120) from the semiconducting 2H phase telluride, a first contact region (e.g., 110a) from the semimetallic IT' phase telluride corresponding to the first metal portion, and a second contact region (e.g., 110b) from the semimetallic IT' phase telluride corresponding to the second metal portion.

[0066] As illustrated in FIG. 9C at 910, method 900 may further include forming a metal source electrode (e.g., 230a) on the first contact region. At 912, method 900 may further include forming a metal drain electrode (e.g., 230b) on the second contact region.

[0067] As illustrated in FIG. 9D at 914, method 900 may further include forming a gate insulator (e.g., 310) on the semiconducting 2H phase telluride. At 916, method 900 may further include forming a gate electrode (e.g., 320) on the gate insulator.

[0068] It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.

[0069] Although specific examples have been illustrated and described herein, a variety of alternate and / or equivalent implementations may be substituted for the specific examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific examples discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and the equivalents thereof.

Claims

What is claimed is:

1. A device comprising:a substrate;an insulator on the substrate;a first semimetallic IT' phase telluride portion on the insulator;a semiconducting 2H phase telluride portion on the insulator and seamlessly connected at the atomic level to the first semimetallic IT' phase telluride portion, and a second semimetallic IT' phase telluride portion on the insulator and spaced apart from the first semimetallic IT' phase telluride portion and seamlessly connected at the atomic level to the semiconducting 2H phase telluride portion.

2. The device of claim 1, wherein the semimetallic IT' phase telluride comprises molybdenum ditelluride (MoTe2), tungsten telluride (WTe?), molybdenum tungsten telluride (MoxW1−xTe2), tungsten selenium telluride (WSe2X-2XTe2X), or tungsten sulfur telluride (WSe2X-2XTe2X).

3. The device of claim 1, wherein the semiconducting 2H phase telluride comprises molybdenum ditelluride (MoTe2), molybdenum tungsten telluride (MoxW1−xTe2), molybdenum selenium telluride (MoSe2X-2XTe2X), molybdenum sulfur telluride (MoSe2X-2XTe2x), tungsten selenium telluride (WSe2X-2XTe2X), or tungsten sulfur telluride (WSe2X-2xTe2x).

4. The device of claim 1, further comprising:a first metal electrode contacting the first semimetallic IT' phase telluride portion; anda second metal electrode contacting the second semimetallic IT' phase telluride portion.

5. The device of claim 1, further comprising:a gate insulator on the semiconducting 2H phase telluride portion; and a gate electrode on the gate insulator.

6. The device of claim 1, wherein the semiconducting 2H phase telluride portion comprises an n-type doped region and a p-type doped region forming a p-n junction.

7. The device of claim 6, wherein the first semimetallic IT' phase telluride portion contacts the n-type region and comprises a first work function, andwherein the second semimetallic IT' phase telluride portion contacts the p-type region and comprises a second work function.

8. The device of claim 1, further comprising:a tunnel insulator on the semiconducting 2H phase telluride portion;a floating gate or charge trapping layer on the tunnel insulator;a gate insulator on the floating gate or charge trapping layer;a gate electrode on the gate insulator;a metal source contact contacting the first semimetallic IT' phase telluride portion; anda metal drain contact contacting the second semimetallic IT' phase telluride portion.

9. The device of claim 8, wherein the floating gate comprises polysilicon, graphene, titanium (Ti), gold (Au), titanium nitride (TiN), lead (Pd), nickel (Ni), or tungsten (W).

10. The device of claim 8, wherein the charge trapping layer comprises silicon nitride (Si3N4), oxynitride, aluminum oxide (AI2O3), hafnium oxide (HfO2). zirconium oxide (ZrCh), titanium dioxide (TiCT), tantalum pentoxide (Ta2O5), lanthanum oxide (LajCh), and / or yttrium oxide (Y2O3).

11. The device of claim 1, further comprising:a further semiconducting 2H phase telluride portion on the insulator and seamlessly connected at the atomic level to the second semimetallic IT phase telluride portion;a third semimetallic IT' phase telluride portion on the insulator and spaced apart from the second semimetallic IT' phase telluride portion and seamlessly connected at the atomic level to the further semiconducting 2H phase telluride portion;a metal source contact contacting the first semimetallic IT' phase telluride portion;a metal drain contact contacting the third semimetallic IT' phase telluride portion;a gate insulator on the semiconducting 2H phase telluride portion and the further semiconducting 2H phase telluride portion; anda gate electrode comprising two fingers on the gate insulator.

12. The device of claim 1, wherein the substrate comprises silicon, germanium, silicon germanium, a group III-V material, a group II-VI material, a metal, sapphire, quartz, polyethylene terephthalate (PET), polyimide, or poly(dimethyl siloxane) (PDMS).

13. The device of claim 1, wherein the insulator comprises silicon dioxide (SiO2), silicon nitride (Si3N4), boron nitride (BN), aluminum oxide (AI2O3), hafnium oxide (HfO2), zirconium oxide (ZrCh), titanium dioxide (TiCh), tantalum pentoxide (Ta2O5), lanthanum oxide (La2Os), and / or yttrium oxide (Y2O3).

14. A method for fabricating an in-plane 2D telluride hetero-phase structure, the method comprising:forming an insulating layer on a substrate;forming a first metal portion and a second metal portion spaced apart from the first metal portion on the insulating layer such that a portion of the insulating layer is exposed directly between the first metal portion and the second metal portion; and simultaneously converting the first metal portion and the second metal portion to a semimetallic IT' phase telluride while forming a semiconducting 2H phase telluride on the exposed portion of the insulating layer between the first metal portion and the second metal portion.

15. The method of claim 14, further comprising:etching the semiconducting 2H phase telluride to define a transistor comprising a channel region from the semiconducting 2H phase telluride, a first contact region from the semimetallic IT' phase telluride corresponding to the first metal portion, and a second contact region from the semimetallic IT' phase telluride corresponding to the second metal portion.

16. The method of claim 15, further comprising:forming a metal source electrode on the first contact region; andforming a metal drain electrode on the second contact region.

17. The method of claim 16, further comprising:forming a gate insulator on the semiconducting 2H phase telluride; and forming a gate electrode on the gate insulator.

18. The method of claim 14, wherein simultaneously converting the first metal portion and the second metal portion to the semimetallic IT' phase telluride while forming the semiconducting 2H phase telluride on the exposed portion of the insulating layer between the first metal portion and the second metal portion comprises a single-step chemical vapor deposition (CVD) process.

19. The method of claim 18, wherein the CVD process comprises a precursor comprising molybdenum oxide (MoO3), molybdenum (Mo), molybdenum pentachloride (MoCl5), molybdenum tetrachloride oxide (MoOCl4), molybdenum dioxo-dichloride (MoO2Cl2), tellurium ( Te), tellurium tetrachloride (TeCl4), dimethyl selenide ((CH3)2Se), selenium (Se), hydrogen selenide (H2Se), sulfur (S), or hydrogen sulfide (H2S).

20. The method of claim 14, wherein simultaneously converting the first metal portion and the second metal portion to the semimetallic IT' phase telluride while forming the semiconducting 2H phase telluride on the exposed portion of the insulatinglayer between the first metal portion and the second metal portion comprises a single-step metal-organic chemical vapor deposition (MOCVD) process.

21. The method of claim 20, wherein the MOCVD process comprises a precursor comprising molybdenum hexacarbonyl (Mo(CO)e), molybdenum (Mo), bis(diethyldithiocarbamato) dioxomolybdenum (Mo(Et2NCS2)2O2), tetrakis(dimethylamido)molybdenum (Mo(NMe2)4), molybdenum acetylacetonate (Mo(acac)3), diethyl telluride ((C2H5)2Te), dimethyl telluride ((CH3)2Te), di-tert-butyl telluride ((C4H9)2Te), tellurium tetrachloride (TeCl4), tris(isopropyl) telluride ((CH3)2CH)3Te), selenium (Se), dimethyl selenide ((CH3)2Se), hydrogen selenide (H2Se), diethyl selenide ((C2H5)2Se), selenourea (H2NC(Se)NH2), diisopropyl selenide ((CH3)2CH)2Se), triethyl phosphine selenide ((C^HsbPSe), sulfur (S), diethyl sulfide ((C2HS)2S), hydrogen sulfide (H2S), carbon disulfide (CS2), dimethyl sulfide ((CH3)2S), bis(trimethylsilyl)sulfide ((CH3)3Si)2S), tert-butyl thiol (C4H9SH), or diisopropyl sulfide ((CH3)2CH)2S.

22. The method of claim 14, wherein the metal comprises molybdenum (Mo), tungsten (W), yttrium (Y), and / or rhodium (Rh).

23. The method of claim 14, wherein the semimetallic IT' phase telluride comprises molybdenum ditelluride (MoTe2), tungsten telluride (WTe2), molybdenum tungsten telluride (MoxW1−xTe2), tungsten selenium telluride (WSe2X-2XTe2X), or tungsten sulfur telluride (WSe2X-2XTc2X).

24. The method of claim 14, wherein the semiconducting 2H phase telluride comprises molybdenum ditelluride (MoTe2), molybdenum tungsten telluride (MoxW1−xTe2), molybdenum selenium telluride (MoSe2X-2XTe2X), molybdenum sulfur telluride (MoSe2X-2XTe2X), tungsten selenium telluride (WSe2X-2XTe2X), or tungsten sulfur telluride (WSe2X-2XTe2X).

25. The method of claim 14, wherein the substrate comprises silicon, germanium, silicon germanium, a group III-V material, a group II- VI material, a metal, sapphire,quartz, polyethylene terephthalate (PET), polyimide, or poly(dimethyl siloxane) (PDMS).

Images