LDPC-code-based communication method and communication apparatus

Abstract

An LDPC-code-based communication method and communication apparatus. A device can perform encoding and decoding on the basis of an LDPC matrix. The LDPC matrix is determined on the basis of an LDPC code shift value matrix and a lifting value, and the LDPC code shift value matrix comprises a portion or all of a first shift value matrix. The first shift value matrix comprises a second shift value matrix and a third shift value matrix, wherein the second shift value matrix comprises a first region, the third shift value matrix comprises a second region, the shift value of the second region in the third shift value matrix is determined on the basis of the shift value of the first region in the second shift value matrix and a first sequence, and the first sequence corresponds to the rows of the LDPC code shift value matrix. In the method, a shift value matrix (e.g., a third shift value matrix) is added to an existing shift value matrix (e.g., a second shift value matrix), thereby improving the performance of an LDPC code in the case of a small number of iterations.

Description

Communication methods and devices based on LDPC codes

[0001] This application claims priority to Chinese Patent Application No. 202411603176.6, filed on November 11, 2024, entitled "Communication Method and Communication Device Based on LDPC Code", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of coding, and more specifically, to a communication method and communication apparatus based on low-density parity check (LDPC) codes. Background Technology

[0003] In the field of channel coding, LDPC codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using a simple feedback shift register, reducing the coding complexity of LDPC codes.

[0004] Currently, LDPC codes have a slow convergence speed in high-throughput scenarios, and their performance is poor with a low number of iterations. Summary of the Invention

[0005] The embodiments of this application provide a communication method and communication device based on LDPC codes, which improves the performance of LDPC codes under low iteration counts while ensuring the stability of LDPC codes.

[0006] In the first aspect, a communication method based on LDPC code is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0007] The method includes: acquiring an information bit sequence; determining an LDPC matrix, the LDPC matrix being determined based on an LDPC code shift matrix and a boost value Zc, the LDPC code shift matrix including part or all of a first shift matrix, the first shift matrix including a second shift matrix and a third shift matrix, the second shift matrix including a first region, the third shift matrix including a second region, wherein the second shift matrix is ​​obtained by replacing 1 elements in part or all regions of the LDPC code base matrix with the shift values ​​corresponding to the 1 elements, the shift values ​​corresponding to the 1 elements in the LDPC base matrix being determined based on the Zc, the shift values ​​in the second region being determined based on the shift values ​​in the first region and a first sequence, the first sequence corresponding to the rows of the LDPC code shift matrix; performing LDPC encoding on the information bit sequence according to the LDPC matrix to obtain a codeword sequence; and sending the codeword sequence.

[0008] For example, the first region belongs to the second translation value matrix, which is a matrix obtained by replacing some or all of the 1 elements in the LDPC code base matrix with the translation values ​​corresponding to the 1 elements. It can be seen that the translation values ​​included in the second translation value matrix are the translation values ​​corresponding to the 1 elements in the existing LDPC code base matrix. These translation values ​​can be predefined or pre-configured; that is, the translation values ​​included in the first region can be predefined or pre-configured.

[0009] For example, the first sequence may be predefined, preconfigured, or indicated by instruction information.

[0010] For example, part or all of the first translation value matrix is ​​an LDPC code translation value matrix used to determine the LDPC matrix. The first translation value matrix includes a second translation value matrix and a third translation value matrix. The second translation value matrix can be understood to include part or all of the translation value matrix corresponding to the existing LDPC code base matrix, and the third translation value matrix can be understood to be a newly added translation value matrix based on the existing translation value matrix.

[0011] For example, the first and second translation value matrices have the same number of rows, but the number of columns can be the same or different.

[0012] It should be understood that the second translation value matrix is ​​the translation value matrix corresponding to a certain region in the first translation matrix, and the third translation value matrix is ​​the translation value matrix corresponding to other regions in the first translation value matrix besides the region corresponding to the second translation value matrix.

[0013] According to the method provided in this application, the translation value of the second region is determined based on the translation value of the first region and the first sequence. The first region can be regarded as a translation value matrix obtained based on the LDPC code basis matrix, and the second region can be regarded as a translation value matrix obtained based on the first region. In order to improve the performance of LDPC codes at low iteration counts, it is necessary to increase the number of columns of the translation value matrix. Therefore, the second region in this application can achieve the effect of increasing the number of columns of the translation value matrix. At the same time, this application provides that the translation value in the newly added translation value matrix (e.g., the second region) can be determined by the translation value of the existing translation value matrix (e.g., the first region) and the first sequence. This method determines the translation value in the newly added translation value matrix in a concise way, simplifying the complexity of LDPC code encoding and decoding.

[0014] Secondly, a communication method based on LDPC code is provided. This method can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0015] The method includes: acquiring a symbol sequence; determining an LDPC matrix, wherein the LDPC matrix is ​​determined based on an LDPC code shift matrix and a boost value Zc, the LDPC code shift matrix including part or all of a first shift matrix, the first shift matrix including a second shift matrix and a third shift matrix, the second shift matrix including a first region, the third shift matrix including a second region, wherein the second shift matrix is ​​obtained by replacing 1 elements in part or all regions of the LDPC code base matrix with the shift values ​​corresponding to the 1 elements, the shift values ​​corresponding to the 1 elements in the LDPC base matrix are determined based on the Zc, the shift values ​​in the second region are determined based on the shift values ​​in the first region and a first sequence, the first sequence corresponding to the rows of the LDPC code shift matrix; and performing LDPC decoding on the symbol sequence according to the LDPC matrix to obtain an information bit sequence.

[0016] For the beneficial effects of the second aspect, please refer to the description of the first aspect, which will not be repeated here.

[0017] In some implementations of the first or second aspect, the first translation value matrix includes a first matrix, which is a matrix corresponding to multiple rows and all columns of the first translation value matrix, wherein...

[0018] The first region is the region consisting of at least one column of the first matrix.

[0019] The second region is a region consisting of at least one column from the remaining regions of the first matrix excluding the first region.

[0020] For example, multiple lines in this application can be understood as two or more lines.

[0021] For example, the first matrix is ​​a matrix consisting of multiple rows and all columns in the first translation value matrix. The multiple rows of the first matrix can be multiple rows with consecutive row numbers in the first translation value matrix, or multiple rows with non-consecutive row numbers, or multiple rows in which some rows have consecutive row numbers and some rows have non-consecutive row numbers.

[0022] Based on the above technical solution, the first region and the second region are defined as belonging to a matrix (e.g., the first matrix) of the first translation value matrix. The first region can be a region composed of at least one column of the first matrix, and the second region is a region composed of at least one column of the remaining columns of the first matrix excluding the first region. The first region and the second region have the same number of rows and do not overlap.

[0023] In some implementations of the first or second aspect, the first translation value matrix corresponds to the second matrix, which is a matrix obtained by replacing the values ​​at the positions containing translation values ​​in the first translation value matrix with 1 elements and replacing the values ​​at the remaining positions with 0 elements. The first translation value matrix includes X′ rows and Y′ columns, wherein the matrix corresponding to the region formed by the x1′+1 to X′ rows and the y2′+1 to Y′ columns of the second matrix is ​​an identity matrix, the matrix corresponding to the region formed by the 1 to x1′ rows and the y2′+1 to Y′ columns of the second matrix is ​​an all-zero matrix, and the matrix corresponding to the region formed by the 1 to x1′ rows and the y1′+1 to y2′ columns of the second matrix is ​​a square matrix, wherein 1 < x1′ < X′, 1 < y1′ < y2′ < Y′, and x1′, X′, y1′, y2′, and Y′ are all integers.

[0024] It can be understood that the matrix corresponding to the first region can be a matrix obtained by truncating the base matrix based on the code rate. For example, the matrix corresponding to the first region can be a matrix obtained by truncating the first 22 rows and the first 44 columns of the base matrix. This matrix corresponding to the first region is located in the second matrix.

[0025] It can also be understood that rows 1 to x1′ of the second matrix are the core rows of the base matrix, columns 1 to y1′ are the core columns of the base matrix, columns y1′+1 to y2′ are the core check columns of the base matrix, and columns y2′+1 to Y′ are all or some of the extended check columns of the base matrix.

[0026] In some implementations of the first or second aspect, the first translation value matrix further includes a third matrix, which is the matrix corresponding to the x1′+1 to X′ rows and the 1 to y2′ columns of the first translation value matrix, wherein the first region is the region composed of at least one column of the third matrix, and the second region is the region composed of at least one column of the remaining regions of the third matrix excluding the column containing the first region.

[0027] It can be understood that the first region and the second region belong to the third matrix in the first translation value matrix. This third matrix can be the matrix corresponding to the x′+1 to X′ rows and the 1 to y2′ columns in the first translation value matrix.

[0028] In some implementations of the first or second aspect, the LDPC code shift value matrix further includes a fourth matrix, which is the matrix corresponding to rows 1 to x1′ and columns 1 to y1′ in the first shift value matrix, and the matrix corresponding to rows x1′+1 to X′ and columns 1 to y1′ in the first shift value matrix, wherein the first region is the region composed of at least one column of the fourth matrix, and the second region is the region composed of at least one column of the remaining regions of the fourth matrix excluding the column containing the first region.

[0029] It can be understood that the first region and the second region belong to the fourth matrix in the first translation value matrix. This fourth matrix can be the matrix corresponding to the first to x1′ rows and the first to y1′ columns in the first translation value matrix, as well as the matrix corresponding to the x1′+1 to X′ rows and the first to y1′ columns.

[0030] In some implementations of the first or second aspect, the first translation value matrix further includes a third matrix, which is the matrix corresponding to the x1′+1 to X′ rows and the 1 to y2′ columns of the first translation value matrix, wherein the first region is the region composed of at least one column of the odd-numbered columns of the third matrix, and the second region is the region composed of at least one column of the even-numbered columns of the third matrix.

[0031] It can be understood that the first region and the second region belong to the third matrix in the first translation value matrix. The first region belongs to the region composed of at least one column in the odd-numbered columns of the third matrix, and the second region belongs to the region composed of at least one column in the even-numbered columns of the third matrix.

[0032] For example, the first region is the region consisting of at least one column of the even-numbered columns in the third matrix, and the second region is the region consisting of at least one column of the odd-numbered columns in the third matrix.

[0033] In some implementations of the first or second aspect, the second translation value matrix includes a fourth translation value matrix and a fifth translation value matrix, the first translation value matrix includes the fourth translation value matrix, the third translation value matrix and the fifth translation value matrix, the fourth translation value matrix includes the first region, the third translation value matrix includes the second region, wherein the fourth translation value matrix is ​​a matrix obtained by replacing the 1 elements in the X′ row and information column of the LDPC base matrix with the corresponding translation values, and the fifth translation value matrix is ​​a matrix obtained by replacing the 1 elements in the X′ row and Y′ column of the LDPC base matrix (excluding the information column) with the corresponding translation values.

[0034] In some implementations of the first or second aspect, the last column of the fourth translation value matrix is ​​adjacent to the first column of the third translation value matrix, and the last column of the third translation value matrix is ​​adjacent to the first column of the fifth translation value matrix.

[0035] In some implementations of the first or second aspect, the LDPC basis matrix is ​​a base graph BG1, where X′ equals 46, Y′ equals 66, x1′ equals 4, y1′ equals 44, and y2′ equals 48.

[0036] In some implementations of the first or second aspect, the number of rows in the first region and the number of columns in the second region are both greater than or equal to 4.

[0037] In some implementations of the first or second aspect, the presence or absence of translation values ​​at N positions between the first and second regions is the opposite, while the presence or absence of translation values ​​at other positions between the first and second regions besides the N positions is the same, where N is a non-negative integer less than or equal to 5.

[0038] It is understandable that the first and second regions differ in the presence or absence of translation values ​​at N positions, while the presence or absence of translation values ​​at other positions is the same. Specifically, the first and second regions differ in the presence or absence of translation values ​​at N positions: a position in a row and column of the first region does not contain a translation value, while the corresponding positions in the second region (row and column positions in the same location as in the first region) do contain a translation value, and vice versa.

[0039] In some implementations of the first or second aspect, the first sequence includes a second sequence and / or a third sequence, wherein the number of elements in each of the first sequences is the same as the number of rows X′ of the first translation value matrix.

[0040] In some implementations of the first or second aspect, the first sequence includes a second sequence and / or a third sequence, wherein the number of elements in each of the second and third sequences is equal to the number of rows in the third matrix of the first translation value matrix, wherein the third matrix is ​​the matrix corresponding to the x1′+1 to X′ rows and the 1 to y2′ columns of the first translation value matrix.

[0041] In some implementations of the first or second aspect, the first sequence includes a second sequence and / or a third sequence, wherein at least one element in the second sequence corresponds to at least one row of the third matrix in the first translation value matrix, and / or, at least one element in the third sequence corresponds to at least one row of the third matrix, wherein the third matrix is ​​the matrix corresponding to the x1′+1 to X′ rows and the 1 to y2′ columns of the first translation value matrix.

[0042] In some implementations of the first or second aspect, where the positions of translation values ​​are the same in both the first and second regions, and the first sequence includes a second and a third sequence, the translation values ​​corresponding to the other positions in the second region that have translation values ​​besides the n positions with translation values ​​are determined in one of the following ways: b i,j =x i *p i,j +y i Or, b i,j =f(x) i ,y i ,p i,j ); where p i,j b represents the translation value of row i and column j in the first region. i,j This represents the translation value of row i and column j in the second region, where x i It is the element in the second sequence corresponding to row i, and y i is the element in the third sequence corresponding to row i, f is a non-linear function, and n is a non-negative integer less than or equal to 5.

[0043] Based on the above scheme, this application provides a method for determining the translation value in the second region when the first sequence includes two sequences.

[0044] In some implementations of the first or second aspect, the positions where the translation values ​​exist in the first region and the second region are the same. When the first sequence includes a second sequence or a third sequence, the translation values ​​corresponding to the other positions in the second region that have translation values, excluding the n positions, are determined in one of the following ways: b i,j =x i *pi,j Or, b i,j =p i,j +y i ; where p i,j b represents the translation value of row i and column j in the first region. i,j This represents the translation value of row i and column j in the second region, where x i It is the element in the second sequence corresponding to row i, and y i is the element in the third sequence corresponding to row i, where n is a non-negative integer less than or equal to 5.

[0045] Based on the above scheme, this application provides a method for determining the translation value in the second region when the first sequence includes a sequence.

[0046] In some implementations of the first or second aspect, the x i It is the i-th element in the second sequence corresponding to row i.

[0047] In some implementations of the first or second aspect, the y i It is the i-th element in the third sequence corresponding to row i.

[0048] In some implementations of the first or second aspect, the translation value in the first region is less than a first value, where the first value is... Or, the first value is the stated Round up or down, where c is a positive integer.

[0049] Thirdly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0050] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0051] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0052] Fourthly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0053] In one implementation, the device is either a transmitting device or a receiving device.

[0054] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0055] Fifthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0056] In one implementation, the device further includes the memory.

[0057] Sixthly, a processor is provided for executing the methods provided in the above aspects.

[0058] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0059] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0060] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0061] Ninthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0062] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0063] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0064] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0065] Eleventhly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0066] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0067] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0068] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0069] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0070] Figure 5 is a schematic diagram of the information transmission process.

[0071] Figure 6 is a schematic flowchart of a communication method 600 provided in this application.

[0072] Figure 7 is a schematic diagram of a translation value matrix provided in an embodiment of this application.

[0073] Figure 8 is a schematic diagram of another translation value matrix provided in an embodiment of this application.

[0074] Figure 9 is a schematic diagram of another translation value matrix provided in an embodiment of this application.

[0075] Figure 10 is a simulation comparison diagram provided by an embodiment of this application.

[0076] Figure 11 is a schematic block diagram of a communication device 1100 provided in an embodiment of this application.

[0077] Figure 12 is a schematic block diagram of the communication device 1200 provided in an embodiment of this application. Detailed Implementation

[0078] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0079] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when," "under the circumstances," "if," and "if" indicate that the device will take corresponding action under certain objective conditions, not that there is a time limit, nor do they require the device to perform a judgment action during implementation, nor do they imply any other limitations.

[0080] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0081] The following describes a communication system to which embodiments of this application can be applied.

[0082] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0083] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0084] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0085] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0086] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, or RAN equipment including CU and DU nodes, or RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes. Alternatively, network equipment may also be a radio controller, relay station, vehicle-mounted equipment, or wearable device in a cloud radio access network (CRAN) scenario. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station may support networks with the same or different access technologies, without limitation.

[0087] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0088] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0089] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, ultra-reliable low-latency communication (URLLC) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0090] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0091] 1. LDPC code

[0092] LDPC codes are a type of linear block code. Linear block codes divide the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0093] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit sequence length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0094] In 1981, Tanner represented the parity-check matrix H graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint, which will be explained below with reference to Figures 2 and 3.

[0095] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0096] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0097] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0098] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. A cycle in the Tanner graph consists of interconnected vertices. The cycle starts and ends at one vertex in this group of vertices and passes through each node only once. The length of a cycle is defined as the number of edges it contains, and the perimeter of the graph, also known as the graph's circumference, is defined as the minimum cycle length in the graph. In Figure 3, the perimeter is 4, as shown by the bolded lines. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to the parity bits in the LDPC. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, then the element (i, j) in the H matrix has a value of 1; if there is no connection, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as: there is a connection or an edge between the check node and the variable node. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge. Furthermore, in a Tanner graph, a cycle is a closed loop formed by connecting variable nodes, check nodes, and edges end-to-end.

[0099] 2. QC-LDPC code

[0100] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BGAn element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0101] Based on the basis matrix and the boosting value Z c (Lifting size) allows the basis matrix to be expanded into a complete parity-check matrix for encoding or decoding. In this application, Z... c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements in the basis matrix to a Z-shape. c ×Z c A square matrix, in which 0 is promoted to Z. c ×Z c The zero matrix is ​​promoted to an identity matrix, and then cyclically shifted based on the shifting value (SV) corresponding to the 1. This cyclic shift can be to the left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, 2, and 3, the cyclically shifted matrix after shifting to the right is as follows:

[0102] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0103] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0104] (3) When the translation value is 2, the corresponding cyclically shifted matrix is:

[0105] (4) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0106] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the array corresponds to a Z. c ×Z c The submatrix is ​​represented by an exponential matrix H, where each element indicates the number of times the corresponding submatrix has been cyclically shifted by the identity matrix. This significantly reduces the storage space required for the complete parity check matrix H. bThe elements in it can also be called QC blocks.

[0107] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0108] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the array represents a Z. c Square matrix of order Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0109] For example, As shown below:

[0110] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0111] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the base matrix. The 1s in the base matrix are then expanded into a cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a 0 matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained.

[0112] 3. Increase value Z c (Lifting Size) and (Shifting Value)

[0113] The storage content of the 5G LDPC code regarding shifting values ​​includes: (1) a list of lifting sizes; and (2) a list of shifting values ​​that correspond one-to-one with the rows of the lifting size list.

[0114] For example, the list of Lifting Sizes is shown in Table 1.

[0115] Table 1

[0116] The j-th row of the Lifting Size list includes Where a j ∈{2,3,5,7,9,11,13,15}, max(kj )∈{7,7,6,5,5,5,4,4}; The row index of Lifting Size corresponds one-to-one with the column index of Shifting Value, that is, the lifting size in each row of the Lifting Size list corresponds to a set of Shifting Values.

[0117] For example, the list of Shifting Values ​​is shown in Table 2.

[0118] Table 2

[0119] It is understandable that the basis matrix H BG The elements in the matrix include 0 and 1, meaning all elements are either 0 or 1. Table 2 stores all rows of the base matrix and the associated columns for each row. If an associated column exists, it indicates that the value at that position in the base matrix is ​​1; otherwise, it is 0.

[0120] For a fixed lift index, a non-zero position in the base matrix corresponds to one translation value. For example, H... BG The shift value corresponding to row 0, column 0 when the promotion index is 0 is 211, H BG The shift value corresponding to the 6th column of the 1st row in the middle when the lifting index = 3 is 66, H BG The shift value corresponding to the second row and ninth column of the middle column when the promotion index is 7 is 206.

[0121] It's understandable that LDPC encoding requires first determining the lift value, and then constructing a parity check matrix based on the corresponding shift value. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0122] 4. Column weight and row weight

[0123] For a given column of a matrix, column weight refers to the number of non-zero elements contained in that column. For a given row of a matrix, row weight refers to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the descriptions of row and column weights is the parity check matrix H.

[0124] 5. Structure of the basis matrix

[0125] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0126] As shown in Figure 4(1), the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(2). Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or a parity with a degree greater than or equal to 2, or a parity node corresponding to the set of rows with the highest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 4(2) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(2). The raptor-like region can correspond to part E in Figure 4(2) and can be an identity matrix corresponding to the parity bits of the low-rate extension.

[0127] The parity check matrix of the LDPC code shown in Figure 4 adopts a "raptor-like" structure, which can be gradually extended to low code rates through a high code rate core matrix. In actual use, as shown in (1) of Figure 4, the first X rows and the first Y columns of the parity check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0128] It should be noted that the parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0129] 6. Information column and validation column

[0130] The columns of the LDPC base matrix consist of information columns and check columns.

[0131] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0132] Check columns: Corresponding to check bits (or check digits, etc.), these can include core check columns and extended check columns. The core check columns are the columns corresponding to part B, and the extended check columns are the columns corresponding to part C or part E. Extended check columns can also be called raptor-like columns.

[0133] 7. Core rows, core columns, core matrix, and core check columns

[0134] Core rows: The core rows of the LDPC base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0135] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0136] The kernel matrix is ​​a matrix region consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the part consisting of part A and part B.

[0137] Core check columns: N columns following the information columns in the LDPC base matrix, where N equals the number of rows corresponding to the core rows. For example, the information columns are 1 to K. b If the column is K, then the core verification column is K. b +1 to K b +N columns. This core verification column corresponds to the verification region where both the lower and upper triangular areas have non-zero positions.

[0138] 8. Message length, code length, and code rate

[0139] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0140] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0141] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0142] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, media access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0143] 9. Information Transmission Process

[0144] Figure 5 is a schematic diagram of the information transmission process applicable to this application. As shown in Figure 5, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the transmitting end device, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the receiving end device. The embodiments of this application mainly involve the source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0145] Currently, LDPC codes suffer from slow convergence speed and poor performance at low iteration counts in high-throughput scenarios. This application addresses these issues by providing a communication method based on LDPC codes. This method aims to improve the overall performance of LDPC codes by resolving the poor performance at low iteration counts.

[0146] Figure 6 is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application. The method includes the following steps.

[0147] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0148] S610, the transmitting device obtains the information bit sequence.

[0149] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0150] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0151] S620, the transmitting device determines the LDPC matrix.

[0152] It should be understood that the LDPC matrix can be the generator matrix of an LDPC code, the parity check matrix of an LDPC code, or a matrix of other LDPC codes, and this application does not limit it.

[0153] The LDPC matrix is ​​determined based on the LDPC code shift matrix and the boost value Zc. The LDPC code shift matrix includes part or all of the first shift matrix. The first shift matrix includes a second shift matrix and a third shift matrix.

[0154] 1) The second and third translation value matrices in the first translation value matrix will be introduced below.

[0155] In one possible implementation, the second translation value matrix is ​​a matrix obtained by replacing some or all of the 1 elements in the LDPC code base matrix with the corresponding translation values. For example, the second translation value can be understood as the translation value matrix corresponding to the existing LDPC base matrix, as shown in Figure 4. The second translation value matrix includes some or all of the existing LDPC base matrix. The third translation value matrix can be understood as a matrix obtained by adding multiple columns based on the number of rows in the second translation value matrix. The specific size of the number of newly added columns is not limited in this application. For example, the number of columns in the third translation value matrix can be less than or equal to the number of columns in the second translation value matrix, or the number of columns in the third translation value matrix can be greater than the number of columns in the second translation value matrix.

[0156] For example, the first column of the third translation value matrix may be adjacent to the last column of the second translation value matrix, or the last column of the third translation value matrix may be adjacent to the first column of the second translation value matrix, or the first column of the third translation value matrix may be adjacent to any column of the second translation value matrix that is not the first column, and the last column of the third translation value matrix may be adjacent to any column of the second translation value matrix that is not the last column.

[0157] It is understandable that if the region corresponding to the second shift value matrix is ​​obtained based on the actual bit rate, then the LDPC matrix is ​​the first shift value matrix. If the second shift value matrix is ​​obtained based on a relatively low bit rate, then the LDPC matrix includes part or all of the region of the first shift value matrix, that is, it can be obtained by truncating the first shift value matrix based on the actual bit rate.

[0158] It can also be understood that if a zero element in the base matrix has no corresponding translation value, then the region corresponding to the second translation value matrix does not contain a translation value at the position corresponding to a zero element in the base matrix. For example, the region corresponding to the second translation value matrix is ​​a matrix obtained by replacing some or all of the 1 elements in the base matrix with their translation values ​​and replacing the zero elements with -1, where -1 indicates that no translation value exists. Alternatively, -1 can be replaced with other non-negative integer characters (e.g., null), which is not limited in this application.

[0159] 2) The first and second regions will be introduced below.

[0160] It should be understood that the first translation value matrix includes a first region and a second region. The first region is located within the region corresponding to the second translation value matrix, and the second region is located within the region corresponding to the third translation value matrix. Specifically, the first column in the first region and the second column in the second region correspond to the same row in the first translation value matrix. The second column is any column in the second region, and the first column is the column in the first region corresponding to the second column. The first and second columns satisfy the following characteristics: the remainder of the difference between the translation value of the i-th row in the first column and the translation value of the i-th row in the second column divided by a first value is the second value. The first value is a positive integer, is related to Zc, and the second value is a non-negative integer.

[0161] For example, the first value is Zc / c, or the first value is Zc / c rounded up or down, where c is a positive integer. For instance, the first value equals... Indicates rounding down. This indicates rounding up to the nearest integer.

[0162] For example, the translation value of the first region is less than the first value.

[0163] Based on the above description, it can be understood that the rows containing translation values ​​are the same in the first and second columns. The first and second columns correspond to the same rows in the first translation value matrix; if there is a translation value in the i-th row of the first column, there is also a translation value in the i-th row of the second column.

[0164] For example, the first column corresponds to a row number greater than or equal to 4 in the first translation value matrix.

[0165] For example, there is column #1 in the first region and column #2 in the second region, where column #1 and column #2 (an example of the first and second columns) are corresponding rows. Column #1 and column #2 correspond to the same row k1 in the first translation value matrix, and column #1 and column #2 satisfy the above characteristics. As another example, there is column #3 in the first region and column #4 in the second region, where column #3 and column #4 (another example of the first and second columns) are corresponding rows. Column #3 and column #4 correspond to the same row k2 in the first translation value matrix, and column #3 and column #4 satisfy the above characteristics.

[0166] For example, k1 and k2 can be the same or different. For instance, k1 = k2 = 4.

[0167] For example, column #1 and column #3 can be the same column or different columns. For instance, if k1 = k2, column #3 and column #1 can be the same column.

[0168] For example, if k1 equals 4, Zc = 64, c = 8, the first, second, and third rows of column #1 have the shifted value {2,7,1}, and the corresponding first, second, and third rows of column #2 have the shifted value {2,15,17}. The difference between the shifted value in column #2 and the corresponding shifted value in column #1 is {0,8,16}. It can be seen that the remainder of any element in {0,8,16} divided by Zc / c (i.e., the first value is 8) is the same, that is, the second value is 0.

[0169] For example, if k2 equals 4, Zc = 64, c = 8, the first, second, and fourth rows of column #3 contain the shifted value {7, 5, 4}, and the corresponding first, second, and fourth rows of column #4 contain the shifted value {7, 13, 36}. The difference between the shifted value in column #4 and the corresponding shifted value in column #3 is {0, 8, 32}. It can be seen that the remainder of any element in {0, 8, 32} divided by Zc / c (i.e., the first value is 8) is the same, meaning the second value is 0.

[0170] It is understandable that there may be other columns besides column #2 and column #4 in the second region, and a corresponding column in the first region can also be found that satisfies the characteristics between the first and second columns mentioned above.

[0171] For example, each column in the first and second regions corresponds to the same row in the first translation value matrix.

[0172] For example, rows in the first and second regions can be consecutive or non-consecutive. For example, rows with lower row weight in the region corresponding to the first translation value matrix may not be included in the first region.

[0173] For example, the first region and the second region include the same number of columns m, and the translation value of the j-th column in the second region and the translation value of the j-th column in the first region satisfy the characteristic between the first column and the second column, 1≤j≤m.

[0174] Based on the characteristics satisfied between the first and second columns described above, in one possible implementation, the translation values ​​in the first column and the translation values ​​in the second column satisfy the formula... Where, p 1,i,j Let q be the shift value of the i-th row in the first column. 1,i,j Let γ be the shift value of the i-th row in the second column, where c is a positive integer and γ is a positive integer. i / c is a constant corresponding to the i-th row of the first column, and γ i It is a non-negative integer less than c.

[0175] For example, based on the above formula, the first value is The second value is 0.

[0176] For example, in the first region, each row i corresponds to a γ. i .

[0177] For example, the first region corresponds to 4 rows, c=4, and the first to fourth rows in the third region correspond to {γ1,γ2,γ3,γ4}={0,1,2,3} respectively.

[0178] For example, the protocol can store the γ corresponding to all rows in the third region. i / c.

[0179] The following examples will illustrate the specific positions of the first and second regions within the first translation value matrix.

[0180] In one possible implementation, the first translation value matrix includes a first matrix that is a matrix corresponding to multiple rows and all columns of the first translation value matrix. The first region is a region consisting of at least one column of the first matrix; the second region is a region consisting of at least one column of the remaining regions of the first matrix excluding the first region.

[0181] As an example, suppose the LDPC code shift value matrix consists of X′ rows and Y′ columns. The first matrix is ​​a matrix consisting of G rows and Y′ columns of the LDPC code shift value matrix, where G is a positive integer less than X′.

[0182] The first matrix includes G rows that can be either continuous or non-continuous rows in the LDPC code shift value matrix.

[0183] For example, assuming that the first region and the second region both contain 4 or more rows, then the first matrix contains G rows, where G is a positive integer greater than or equal to 8.

[0184] For example, assume that the number of rows and columns of the first region and the second region are equal. The first region and the second region are regions composed of M columns in the first matrix, where M is a positive integer less than Y′ / 2. The M columns in the first region can be consecutive M columns or non-consecutive M columns in the first matrix. The M columns in the second region can be consecutive M columns or non-consecutive M columns in the first matrix.

[0185] In another possible implementation, the first translation value matrix corresponds to the second matrix. The second matrix is ​​obtained by replacing the values ​​at the positions containing translation values ​​in the first translation value matrix with 1 elements and replacing the values ​​at the remaining positions with 0 elements. The first translation value matrix includes X′ rows and Y′ columns. The matrix corresponding to the region formed by the x1′+1 to X′ rows and the y2′+1 to Y′ columns of the second matrix is ​​the identity matrix. The matrix corresponding to the region formed by the 1 to x1′ rows and the y2′+1 to Y′ columns of the second matrix is ​​an all-zero matrix. The matrix corresponding to the region formed by the 1 to x1′ rows and the y1′+1 to y2′ columns of the second matrix is ​​a square matrix. In this matrix, 1 < x1′ < X′, 1 < y1′ < y2′ < Y′, and x1′, X′, y1′, y2′, and Y′ are all integers.

[0186] It should be understood that the matrix corresponding to the region formed by rows x1′+1 to X′ and columns y2′+1 to Y′ of the second matrix is ​​the identity matrix, which can be understood as part E of the second matrix; the matrix corresponding to the region formed by rows 1 to x1′ and columns y2′+1 to Y′ of the second matrix is ​​a matrix of all zeros, which can be understood as part C of the second region; and the matrix corresponding to the region formed by rows 1 to x1′ and columns y1′+1 to y2′ of the second matrix is ​​a square matrix, which can be understood as part B of the second region.

[0187] As an example, the first translation value matrix also includes a third matrix, which is the matrix corresponding to the x1′+1 to X′ rows and the 1 to y2′ columns in the first translation value matrix. The first region is the region consisting of at least one column of the third matrix, and the second region is the region consisting of at least one column of the remaining regions in the third matrix excluding the column containing the first region, as shown in (1) of Figure 7.

[0188] As another example, the first translation value matrix also includes a fourth matrix, which is the matrix corresponding to the first translation value matrix in rows 1 to x1′ and columns 1 to y1′, and the matrix corresponding to the first translation value matrix in rows x1′+1 to X′ and columns 1 to y1′. The first region is the region composed of at least one column of the fourth matrix, and the second region is the region composed of at least one column of the remaining regions of the fourth matrix excluding the column of the first region, as shown in (2) of Figure 7.

[0189] As another example, the first translation value matrix also includes a third matrix, which is the matrix corresponding to the x1′+1~X′ rows and the 1~y2′ columns in the translation value matrix. The first region is the region composed of at least one column in the odd-numbered columns of the third matrix, and the second region is the region composed of at least one column in the even-numbered columns of the third matrix, as shown in (3) of Figure 7.

[0190] Based on the above example, the second translation value matrix is ​​composed of the fourth translation value matrix and the fifth translation value matrix, and the first translation value matrix is ​​composed of the fourth translation value matrix, the third translation value matrix, and the fifth translation value matrix. The fourth translation value matrix includes the first region, and the third translation value matrix includes the second region. The fourth translation value matrix is ​​obtained by replacing the 1 element in the X′ row and information column of the LDPC base matrix with the corresponding translation value, and the fifth translation value matrix is ​​obtained by replacing the 1 element in the X′ row and Y column of the LDPC base matrix (excluding the information column) with the corresponding translation value.

[0191] For example, the third translation value matrix is ​​the same size as the fourth translation value matrix.

[0192] For example, the second region is the same size as the first region.

[0193] For example, the second region is positioned in the third translation value matrix in the same way that the first region is positioned in the fourth translation value matrix.

[0194] For example, the last column of the fourth translation value matrix is ​​adjacent to the first column of the third translation value matrix, and the last column of the third translation value matrix is ​​adjacent to the first column of the fifth translation value matrix, as shown in Figure 8.

[0195] It should be understood that Figure 8 is merely an example, and this application does not limit the specific position of the third translation value matrix. For example, the first column of the third translation value matrix may be adjacent to the last column of the fifth translation value matrix, or the third translation value matrix may be located in the middle of the fourth or fifth translation value matrix.

[0196] As an example, suppose the LDPC basis matrix is ​​the basis graph BG1, where X′ can be 46 and Y′ can be 66, where x1′ equals 4, y1′ equals 44 and y2′ equals 48.

[0197] For example, the first translation value matrix includes a second translation value matrix and a third translation value matrix, where the second translation value matrix includes a fourth translation value matrix and a fifth translation value matrix. The matrix corresponding to the second translation value matrix is ​​obtained by truncating the first 22 rows and the first 44 columns of the base matrix. For example, the specific values ​​of the parameters for the number of rows in the second translation value matrix are as follows:

[0198] X″=22、Y″=44、x1″=4、y1″=22、y2″=26、X″、Y″、x1″、y1″、y2″ have similar meanings and relationships between parameters as X′、Y′、x1′、y1′、y2′ in the first translation value matrix.

[0199] For example, if the third translation value matrix has 22 columns, then the values ​​of the parameters of the first and second translation value matrices can be: X′=22, Y″=66, x1″=4, y1″=44, y2″=48.

[0200] The characteristics of the translation values ​​between the first and second regions are described below.

[0201] In one possible implementation, the presence or absence of translation values ​​at N positions between the first and second regions is the opposite of the presence or absence of translation values ​​at other positions between the first and second regions besides the N positions, where N is a non-negative integer less than or equal to 5.

[0202] It should be understood that the existence of translation values ​​at N positions in the first and second regions is the opposite of the case where translation values ​​exist. That is, there are N positions in the basis matrix corresponding to the first region that are different from the non-zero positions in the basis matrix corresponding to the second region. The specific magnitude of the translation values ​​in the first and second regions is not limited in this application.

[0203] As an example, assuming N=3, there are three positions in the first and second regions where the presence or absence of translation values ​​differs, meaning that the values ​​at three positions in the corresponding basis matrices of the first and second regions are different. For example, the first region has no translation value at the 1st row and 3rd column position, while the second region does; similarly, the first region has a translation value at the 2nd row and 1st column, while the second region does not; and so on. Conversely, the first region has a translation value at the 3rd row and 2nd column, while the second region does not; and so on. However, assuming N=0, the presence or absence of translation values ​​at all positions in the first and second regions is the same.

[0204] The following will provide an example of how to determine the translation values ​​corresponding to non-zero positions in the first and second regions.

[0205] It should be understood that the translation values ​​in the second region are determined based on the translation values ​​in the first region and a first sequence, which corresponds to the rows of the LDPC code translation value matrix. For example, the translation value at row i, column j in the second region is determined based on the translation value at row i, column j in the first region and the first sequence corresponding to row i.

[0206] In one possible implementation, the first sequence may include one or two sequences, such as a second sequence and / or a third sequence, wherein the number of elements in each sequence of the first sequence is the same as the number of rows X′ of the first translation value matrix. Each sequence in the first sequence corresponds to a row in the first translation value matrix.

[0207] Suppose that in the first or second region, there exists at least one row located in the third matrix within the first shift value matrix, and the elements of the second and / or third sequences correspond to at least one row in the third matrix. The third matrix is ​​the matrix corresponding to rows x1′+1 to X′ and columns 1 to y2′ in the LDPC code shift value matrix, as shown in Figure 7(1) and Figure 7(3).

[0208] In another possible implementation, the first sequence may include one or two sequences, such as a second sequence and / or a third sequence, where the number of elements in each sequence of the first sequence is the same as the number of rows in the third matrix of the first translation value matrix. Each sequence in the first sequence corresponds to a row in the third matrix of the first translation value matrix.

[0209] As an example, if the positions with translation values ​​are the same in both the first and second regions, and the first sequence includes two sequences (e.g., the first sequence includes a second sequence and a third sequence), the translation values ​​corresponding to the other positions with translation values ​​in the second region besides the n positions with translation values ​​can be determined by either method one or method two as follows:

[0210] Method 1: b i,j =x i *p i,j +y i

[0211] Where, p i,j b represents the shift value of row i and column j in the first region. i,j x represents the shift value of row i and column j in the second region. i It is the element in the second sequence corresponding to row i, y i It is the element in the third sequence corresponding to row i.

[0212] Method 2: b i,j =f(x) i ,y i ,p i,j )

[0213] Here, f is a nonlinear function. For example, f can be a polynomial function or other nonlinear functions.

[0214] It should be understood that the position of row i, column j in the first region corresponds to the position of row i, column j in the second region, and both have a translation value. Specifically, the translation value in row i, column j of the second region is determined based on the predefined translation value in row i, column j of the first region, the elements in the second sequence corresponding to row i, and the elements in the third sequence corresponding to row i.

[0215] Optional, the x i It can also be the i-th element in the second sequence corresponding to row i, y i It can also be the i-th element in the third sequence corresponding to row i.

[0216] It should also be understood that n is a non-negative integer less than or equal to 5, meaning that there may be at most 5 positions in the second region whose translation values ​​are not determined based on Method 1 or Method 2, or that the translation values ​​in the second region can all be determined based on Method 1 and Method 2.

[0217] As another example, when the positions where translation values ​​exist are the same in both the first and second regions, and the first sequence includes a sequence (e.g., the first sequence includes a second or third sequence), the translation values ​​corresponding to the other positions where translation values ​​exist in the second region besides the n positions where translation values ​​exist can be determined using either method three or method four below:

[0218] Method 3: b i,j =x i *p i,j

[0219] Where, p i,j b represents the shift value of row i and column j in the first region. i,j x represents the shift value of row i and column j in the second region. i It is an element in the second sequence corresponding to row i.

[0220] Method 4: b i,j =p i,j +y i

[0221] Among them, y i It is the element in the third sequence corresponding to row i.

[0222] Optional, the x i It can also be the i-th element in the second sequence corresponding to row i, y i It can also be the i-th element in the third sequence corresponding to row i.

[0223] The determination of translation values ​​in the first and second regions has been described in detail above. The translation value characteristics of the remaining regions in the first translation value matrix (excluding the first region) and the remaining regions in the second translation value matrix (excluding the second region) are described below.

[0224] Below is a specific example of the first translation value matrix. The base matrix is ​​BG1. The second translation value matrix is ​​obtained by replacing the 1 elements in the first 22 rows and first 44 columns of the base matrix with their corresponding translation values, and replacing the 0 elements with -1. The second translation value matrix consists of a fourth translation value matrix and a fifth translation value matrix. The region corresponding to the fourth translation value matrix is ​​the region consisting of the first 22 columns of the second translation value matrix (i.e., the information columns corresponding to the base matrix). The region corresponding to the fifth translation value matrix is ​​the remaining region in the second translation value matrix excluding the region corresponding to the fourth translation value matrix. The region corresponding to the third translation value matrix is ​​the same size as the region corresponding to the fourth translation value matrix (i.e., both are 22 rows and 22 columns). The position and size of the second region in the third translation value matrix are the same as the position and size of the first region in the fourth translation value matrix. The translation values ​​in the third translation value matrix are determined based on the translation values ​​in the fourth translation value matrix, as shown in Figure 9. The first row of the third translation value matrix is ​​the same as the first row of the fourth translation value matrix. The translation value corresponding to the i-th element in the second row of the third translation value matrix is ​​determined based on the translation value corresponding to the i-th element in the second row of the fourth translation value matrix. For example, if the translation value of the i-th element in the second row of the fourth translation value matrix is ​​'a', then the translation value of the i-th element in the second row of the third translation value matrix is ​​'b' = (a + 384 * 1 / 4) mod 384. The translation values ​​in the third row of the fourth translation value matrix are... The translation value of the i-th element in the third row of the third translation matrix is ​​a, and the translation value of the i-th element in the third row of the third translation matrix is ​​b = (a + 384 * 1 / 2) mod 384; the translation value of the i-th element in the fourth row of the fourth translation matrix is ​​a, and the translation value of the i-th element in the fourth row of the third translation matrix is ​​b = (a + 384 * 3 / 4) mod 384; the translation value of the i-th element in the k-th row of the fourth translation matrix is ​​a, and the translation value of the i-th element in the k-th row of the third translation matrix is ​​b = (a + k) mod 384, where k is an integer greater than 4.

[0225] It should also be understood that other forms of LDPC code shift value matrices can be obtained by simultaneously adding or subtracting the same value from the corresponding shift values ​​of several rows or columns in the LDPC code shift value matrix, and then performing row or column permutations. The resulting LDPC codes are related to the characteristics of the LDPC code shift value matrix provided in this application, and can be regarded as being within the protection scope of this application.

[0226] S630: The transmitting device encodes the information bit sequence according to the LDPC parity check matrix to obtain the codeword sequence.

[0227] S640, the transmitting device sends a codeword sequence to the receiving device. Correspondingly, the receiving device receives a symbol sequence from the transmitting device.

[0228] It should be noted that, since channel noise signals may be introduced during the transmission of the codeword sequence, the LDPC codeword sequence output or transmitted by the transmitting device may be different from the sequence received by the receiving device. That is, the transmitting device transmits a codeword sequence, while the receiving device receives a symbol sequence.

[0229] In S650, the receiving device decodes the symbol sequence according to the LDPC parity check matrix to obtain the information bit sequence.

[0230] The LDC parity check matrix used for decoding by the receiving device is the same as the LDPC parity check matrix used for encoding by the sending device. The specific method by which the receiving device determines the LDPC matrix can be found in the description on the sending device side, and will not be detailed here.

[0231] The scheme shown in Figure 6 above improves the performance of LDPC codes with a low number of iterations by adding new translation value matrices (e.g., adding columns) to the existing translation value matrix. Furthermore, this method provides that the translation values ​​in the newly added translation value matrix (e.g., the second region) can be determined using the translation values ​​of the existing translation value matrix (e.g., the first region) and the first sequence. This simplifies the complexity of LDPC code encoding and decoding by providing a concise way to determine the translation values ​​in the newly added translation value matrix.

[0232] Based on the method shown in Figure 6, Figure 10 illustrates a simulation diagram of an SC-LDPC code under different code rates. The simulation in Figure 10 uses a min-sum decoding algorithm with 5 iteration rounds to compare the performance of LDPC codes. In Figure 10, the horizontal axis represents the information length, and the vertical axis represents the block error rate (BLER) reaching 1. e-2 The corresponding signal-to-noise ratio, therefore, the lower the bit error rate of this block, the better the performance.

[0233] As shown in Figure 10, at a code rate of 11 / 12, the block error rate (BER) of existing 5G LDPC codes is higher than that of the LDPC codes provided in this application; at a code rate of 11 / 14, the BER of existing 5G LDPC codes is higher than that of the LDPC codes provided in this application; and at a code rate of 2 / 3, the BER of existing 5G LDPC codes is higher than that of the LDPC codes provided in this application. Based on the simulation numerical comparison shown in Figure 10, it can be seen that the method provided in this application has better performance gains at various code rates and code lengths.

[0234] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0235] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0236] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0237] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 10. The apparatus embodiments of this application will now be described with reference to Figures 10 and 12. It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 10 and 12 include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0238] Figures 11 and 12 are schematic diagrams of possible apparatus structures provided in embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0239] Figure 11 is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. As shown in Figure 11, the device 1100 may include a communication unit 1110 and a processing unit 1120. The communication unit 1110 can communicate with the outside world, and the processing unit 1120 is used for data processing. The communication unit 1110 may also be referred to as a communication interface or a transceiver unit.

[0240] In one possible design, the device 1100 can implement the steps or processes corresponding to those executed by the transmitting device in the above method embodiments, wherein the processing unit 1120 is used to execute processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1110 is used to execute transmission-related operations of the transmitting device in the above method embodiments.

[0241] In another possible design, the device 1100 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1110 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1120 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0242] It is understood that the device 1100 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, combined logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1100 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1100 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0243] The apparatus 1100 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1100 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0244] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In the embodiments of this application, the device in FIG11 can be the receiving end device or transmitting end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitation is made here.

[0245] Figure 12 is a schematic block diagram of a communication device 1200 provided in an embodiment of this application. The device 1200 includes a processor 1210 and a transceiver 1220. The processor 1210 and the transceiver 1220 communicate with each other through an internal connection path. The processor 1210 is used to execute instructions to control the transceiver 1220 to send and / or receive signals.

[0246] Optionally, the device 1200 may further include a memory 1230, which communicates with the processor 1210 and the transceiver 1220 via an internal connection path. The memory 1230 stores instructions, and the processor 1210 can execute the instructions stored in the memory 1230. In one possible implementation, the device 1200 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1200 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0247] Optionally, the memory 1230 may be integrated into the processor 1210.

[0248] In one possible scenario, the device 1200 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0249] It is understood that the device 1200 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1220 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1200 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0250] Optionally, the memory 1230 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1210 may be used to execute instructions stored in the memory, and when the processor 1210 executes instructions stored in the memory, the processor 1210 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0251] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0252] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0253] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0254] Optionally, the memory (e.g., 1230) in this embodiment may be integrated into the processor (e.g., 1210).

[0255] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0256] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0257] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0258] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0259] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0260] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0261] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0262] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0263] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0264] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0265] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the information bit sequence; The LDPC matrix is ​​determined based on the LDPC code shift matrix and the boost value Zc. The LDPC code shift matrix includes part or all of the first shift matrix, which in turn includes a second and a third shift matrix. The second shift matrix includes a first region, and the third shift matrix includes a second region. The second shift value matrix is ​​a matrix obtained by replacing some or all of the 1 elements in the LDPC code base matrix with the shift values ​​corresponding to the 1 elements. The shift values ​​corresponding to the 1 elements in the LDPC base matrix are determined based on the ZC. The shift values ​​in the second region are determined based on the shift values ​​in the first region and the first sequence. The first sequence corresponds to the rows of the LDPC code shift value matrix. Based on the LDPC matrix, the information bit sequence is LDPC encoded to obtain a codeword sequence; Send the codeword sequence.

2. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the symbol sequence; The LDPC matrix is ​​determined based on the LDPC code shift matrix and the boost value Zc. The LDPC code shift matrix includes part or all of the first shift matrix, which in turn includes a second and a third shift matrix. The second shift matrix includes a first region, and the third shift matrix includes a second region. The second shift value matrix is ​​a matrix obtained by replacing some or all of the 1 elements in the LDPC code base matrix with the shift values ​​corresponding to the 1 elements. The shift values ​​corresponding to the 1 elements in the LDPC base matrix are determined based on the ZC. The shift values ​​in the second region are determined based on the shift values ​​in the first region and the first sequence. The first sequence corresponds to the rows of the LDPC code shift value matrix. The symbol sequence is LDPC decoded according to the LDPC matrix to obtain the information bit sequence.

3. The method according to claim 1 or 2, characterized in that, The first translation value matrix includes a first matrix, which is a matrix consisting of multiple rows and all columns of the first translation value matrix. The first region is the region consisting of at least one column of the first matrix. The second region is a region consisting of at least one column from the remaining regions of the first matrix excluding the first region.

4. The method according to claim 3, characterized in that, The rows included in the first matrix have consecutive row numbers in the first translation value matrix.

5. The method according to any one of claims 1 to 4, characterized in that, The first translation value matrix corresponds to the second matrix, which is obtained by replacing the values ​​at the positions containing translation values ​​in the first translation value matrix with 1 elements and replacing the values ​​at the remaining positions with 0 elements. The first translation value matrix includes X′ rows and Y′ columns, where... The matrix corresponding to the region formed by rows x1′+1 to X′ and columns y2′+1 to Y′ of the second matrix is ​​the identity matrix. The matrix corresponding to the region formed by rows 1 to x1′ and columns y2′+1 to Y′ of the second matrix is ​​a matrix of all zeros. The matrix corresponding to the region formed by rows 1 to x1′ and columns y1′+1 to y2′ of the second matrix is ​​a square matrix. Where 1 < x1′ < X′, 1 < y1′ < y2′ < Y′, and x1′, X′, y1′, y2′, and Y′ are all integers.

6. The method according to claim 5, characterized in that, The first translation value matrix also includes a third matrix, which is the matrix corresponding to rows x1′+1 to x′ and columns 1 to y2′ in the first translation value matrix. in, The first region is a region consisting of at least one column of the third matrix, and the second region is a region consisting of at least one column of the remaining regions of the third matrix excluding the column containing the first region.

7. The method according to claim 5, characterized in that, The first translation value matrix further includes a fourth matrix, which is the matrix corresponding to rows 1 to x1′ and columns 1 to y1′ in the first translation value matrix, and the matrix corresponding to rows x1′+1 to X′ and columns 1 to y1′ in the first translation value matrix. in, The first region is a region consisting of at least one column of the fourth matrix, and the second region is a region consisting of at least one column of the remaining regions of the fourth matrix excluding the column containing the first region.

8. The method according to claim 5, characterized in that, The first translation value matrix also includes a third matrix, which is the matrix corresponding to rows x1′+1 to x′ and columns 1 to y2′ in the first translation value matrix. in, The first region is the region consisting of at least one column of the odd-numbered columns of the third matrix, and the second region is the region consisting of at least one column of the even-numbered columns of the third matrix.

9. The method according to any one of claims 5 to 8, characterized in that, The second translation value matrix includes a fourth translation value matrix and a fifth translation value matrix, the first translation value matrix includes the fourth translation value matrix, the third translation value matrix and the fifth translation value matrix, the fourth translation value matrix includes the first region, the third translation value matrix includes the second region, wherein, The fourth translation value matrix is ​​obtained by replacing the 1 elements in the X′ row and information column of the LDPC base matrix with the corresponding translation values. The fifth translation value matrix is ​​obtained by replacing the 1 elements in the X′ row and Y′ column of the LDPC base matrix (excluding the information column) with the corresponding translation values.

10. The method according to claim 9, characterized in that, The last column of the fourth translation value matrix is ​​adjacent to the first column of the third translation value matrix, and the last column of the third translation value matrix is ​​adjacent to the first column of the fifth translation value matrix.

11. The method according to claim 9 or 10, characterized in that, The LDPC basis matrix is ​​the base graph BG1, where X′ equals 46, Y′ equals 66, x1′ equals 4, y1′ equals 44, and y2′ equals 48.

12. The method according to any one of claims 1 to 11, characterized in that, The number of rows in both the first region and the second region is greater than or equal to 4, and the number of columns in both regions is greater than or equal to 4.

13. The method according to any one of claims 1 to 12, characterized in that, The cases where there are translation values ​​at N positions between the first region and the second region are opposite, while the cases where there are translation values ​​at other positions besides the N positions between the first region and the second region are the same, where N is a non-negative integer less than or equal to 5.

14. The method according to any one of claims 1 to 13, characterized in that, The first sequence includes a second sequence and / or a third sequence, wherein the number of elements in each sequence of the first sequence is the same as the number of rows X of the first translation value matrix.

15. The method according to any one of claims 5 to 13, characterized in that, The first sequence includes a second sequence and / or a third sequence, wherein the number of elements in each of the second and third sequences is equal to the number of rows in the third matrix of the first translation value matrix. The third matrix is ​​the matrix corresponding to the x1′+1 to X′ rows and the 1 to y2′ columns in the first translation value matrix.

16. The method according to any one of claims 5 to 13, characterized in that, The first sequence includes a second sequence and / or a third sequence, wherein at least one element in the second sequence corresponds to at least one row of the third matrix in the first translation value matrix, and / or, at least one element in the third sequence corresponds to at least one row of the third matrix. The third matrix is ​​the matrix corresponding to the x1′+1 to X′ rows and the 1 to y2′ columns in the first translation value matrix.

17. The method according to any one of claims 1 to 16, characterized in that, In the case where the positions of the translation values ​​are the same in both the first and second regions, and the first sequence includes both the second and third sequences. The translation values ​​for the other positions in the second region that have translation values, excluding the n positions, can be determined using one of the following methods: b i,j =x i *p i,j +y i Or, b i,j =f(x) i ,y i ,p i,j ) Where, p i,j b represents the translation value of row i and column j in the first region. i,j This represents the translation value of row i and column j in the second region, where x i It is the element in the second sequence corresponding to row i, and y i is the element in the third sequence corresponding to row i, f is a non-linear function, and n is a non-negative integer less than or equal to 5.

18. The method according to any one of claims 1 to 16, characterized in that, The positions where the translation values ​​are in the first region and the second region are the same, and the first sequence includes either the second sequence or the third sequence. The translation values ​​for the other positions in the second region that have translation values, excluding the n positions, can be determined using one of the following methods: b i,j =x i *p i,j Or, b i,j =p i,j +y i Where, p i,j b represents the translation value of row i and column j in the first region. i,j This represents the translation value of row i and column j in the second region, where x i It is the element in the second sequence corresponding to row i, and y i is the element in the third sequence corresponding to row i, where n is a non-negative integer less than or equal to 5.

19. The method according to claim 17 or 18, characterized in that, The x i It is the i-th element in the second sequence corresponding to row i.

20. The method according to any one of claims 17 to 19, characterized in that, The y i It is the i-th element in the third sequence corresponding to row i.

21. The method according to any one of claims 1 to 20, characterized in that, The translation value in the first region is less than the first value, where the first value is... Or, the first value is the stated Round up or down, where c is a positive integer.

22. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 21 to be implemented via logic circuits or executing code instructions.

23. The communication device according to claim 22, characterized in that, The communication device is a chip or chip system.

24. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 21 to be implemented.

25. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 21 to be implemented.

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