Communication method and communication apparatus based on LDPC codes

Abstract

A communication method and communication apparatus based on LDPC codes. In the method, a device performs encoding or decoding on the basis of an LDPC matrix, wherein the LDPC matrix is determined on the basis of an LDPC code shift value matrix and a lifting value Zc, and the LDPC code shift value matrix comprises some or all of the regions of a first shift value matrix. The first shift value matrix consists of a first region and a second region, wherein the first region is a matrix obtained by means of replacing 1-elements in a base matrix with shift values of the 1 elements; the first region comprises a third region, and the second region comprises a fourth region; a first column of the third region and a second column of the fourth region correspond to the same row in the first shift value matrix; and the first column and the second column satisfy the following characteristics: the difference between the shift value at an ith row in the first column and the shift value of an ith row at the second column, modulo a first value, is equal to a second value, and the first value is related to Zc. The method can improve the performance of LDPC codes in high-throughput scenarios.

Description

Communication methods and devices based on LDPC codes

[0001] This application claims priority to Chinese Patent Application No. 202411604349.6, filed on November 11, 2024, entitled "Communication Method and Communication Device Based on LDPC Code", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of coding, and more specifically, to a communication method and communication device based on LDPC codes. Background Technology

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, they can be encoded using simple feedback shift registers, reducing the coding complexity of LDPC codes.

[0004] In modern communications, efficient and reliable channel coding schemes are crucial for ensuring the performance and efficiency of information transmission. Existing LDPC codes exhibit slow convergence speeds in high-throughput scenarios and poor performance with low iteration counts. Therefore, improving the performance of LDPC codes with low iteration counts has become an urgent problem to be solved. Summary of the Invention

[0005] The embodiments of this application provide a communication method and communication device based on LDPC codes, which can improve the performance of LDPC codes in high-throughput scenarios.

[0006] In the first aspect, a communication method based on LDPC code is provided. This method can be executed by a transmitting device. Unless otherwise specified, the term "transmitting device" in this application can refer to the transmitting device itself (e.g., a network device, a terminal device), a component in the transmitting device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the transmitting device.

[0007] The method includes: acquiring an information bit sequence; encoding the information bit sequence according to an LDPC matrix to obtain a codeword sequence, wherein the LDPC matrix is ​​determined based on an LDPC code shift matrix and a boost value Zc, the LDPC code shift matrix includes part or all of a first shift matrix, the first shift matrix includes a first region and a second region, wherein the first region is the entire region of the matrix obtained by replacing the 1 element in part or all of the regions of the LDPC base matrix with the shift value of the 1 element, the shift value corresponding to the 1 element in the LDPC base matrix is ​​determined based on Zc, the first region includes a third region, the second region includes a fourth region, the first column in the third region and the second column in the fourth region correspond to the same row in the first shift matrix, the second column is any column in the fourth region, the first column is the column in the third region corresponding to the second column, the first column and the second column satisfy the following characteristics: the difference between the shift value of the i-th row in the first column and the shift value of the i-th row in the second column modulo the first value is the second value, the first value is a positive integer, the first value is related to Zc, and the second value is a non-negative integer.

[0008] Based on the above description, it can be understood that the rows containing translation values ​​are the same in the first and second columns. The first and second columns correspond to the same rows in the first translation value matrix; if there is a translation value in the i-th row of the first column, there is also a translation value in the i-th row of the second column.

[0009] For example, the first column corresponds to a row number greater than or equal to 4 in the first translation value matrix.

[0010] For example, there is column #1 in the third region and column #2 in the fourth region, where column #1 and column #2 (an example of the first and second columns) are corresponding columns. Column #1 and column #2 correspond to the same row k1 in the first translation value matrix, and column #1 and column #2 satisfy the above characteristics.

[0011] For example, there is column #3 in the third region and column #4 in the fourth region, where column #3 and column #4 (another example of the first and second columns) are corresponding columns. Column #3 and column #4 correspond to the same row k2 in the first translation value matrix, and they satisfy the above characteristics. For example, k1 and k2 can be the same or different.

[0012] For example, column #1 and column #3 can be the same column or different columns.

[0013] In the above technical solution, the first region can be regarded as a translation value matrix obtained based on the basis matrix, and the second region can be regarded as a translation value matrix obtained based on the first region. In order to improve the performance of LDPC codes at low iteration counts, it is necessary to increase the number of columns of the translation value matrix. Therefore, the second region in this application can achieve the effect of increasing the number of columns of the translation value matrix. In addition, the characteristics satisfied by the translation values ​​in the first column and the translation values ​​in the second column can guarantee the cyclic property of the LDPC code. For example, if the first region has no short cycles (e.g., 4 cycles or 6 cycles), the second region also has no short cycles.

[0014] Secondly, a communication method is provided, which can be executed by a receiving device. Unless otherwise specified, the term "receiving device" in this application can refer to the receiving device itself (e.g., a network device, a terminal device), a component in the receiving device (e.g., a processor, a chip, or a chip system), or a logic module or software that can implement all or part of the functions of the receiving device.

[0015] The method includes: acquiring a symbol sequence; decoding the symbol sequence according to an LDPC matrix to obtain an information bit sequence, wherein the LDPC matrix is ​​determined based on an LDPC code shift matrix and a boost value Zc, the LDPC code shift matrix includes part or all of a first shift matrix, the first shift matrix includes a first region and a second region, wherein the first region is the entire region of the matrix obtained by replacing the 1 elements in part or all of the regions of the LDPC base matrix with the shift values ​​of the 1 elements, the shift values ​​corresponding to the 1 elements in the LDPC base matrix are determined based on Zc, and the first region... The domain includes a third region, the second region includes a fourth region, the first column of the third region and the second column of the fourth region correspond to the same row in the first translation value matrix, the second column is any column in the fourth region, and the first column is the column in the third region corresponding to the second column. The first column and the second column satisfy the following characteristics: the difference between the translation value of the i-th row in the first column and the translation value of the i-th row in the second column modulo the first value is the second value, the first value is a positive integer, the first value is related to Zc, and the second value is a non-negative integer; according to the LDPC matrix, the symbol sequence is decoded to obtain the information bit sequence.

[0016] For the beneficial effects of the second aspect, please refer to the description of the first aspect, which will not be repeated here.

[0017] In some implementations of the first or second aspect, the first value is Or, the first value is Round up or down, where c is a positive integer.

[0018] In some implementations of the first or second aspect, the first value is The second value is 0, and the translation value of the i-th row in the first column is p. 1,i,j The translation value of the i-th row in the second column is q. 1,i,j ,in, Where c is a positive integer, γ i / c is the value corresponding to the i-th row of the first column, and γi is a non-negative integer less than c.

[0019] The above technical solution provides a specific feature that the translation values ​​in the first column and the translation values ​​in the second column satisfy, which can guarantee the guaranteed loop property of the LDPC code.

[0020] In some implementations of the first or second aspect, the first column corresponds to 4 rows, c = 4, and the first to fourth rows in the first column correspond to {γ1, γ2, γ3, γ4} = {0, 1, 2, 3} respectively.

[0021] In some implementations of the first or second aspect, the first region corresponds to the first matrix, which is a matrix obtained by replacing the values ​​at positions in the first region with 1 elements and replacing the values ​​at the remaining positions with 0 elements. The first region includes X′ rows and Y′ columns. The matrix formed by the x1+1 to X′ rows and the y2+1 to Y′ columns of the first matrix is ​​an identity matrix. The matrix formed by the 1 to x1 rows and the y2+1 to Y′ columns of the first matrix is ​​an all-zero matrix. The matrix formed by the 1 to x1 rows and the y1+1 to y2 columns of the first matrix is ​​a square matrix. In this matrix, 1 < x1 < X′, 1 < y1 < y2 < Y′, and x1, X, y1, y2, and Y′ are all integers.

[0022] It is understandable that the first matrix can be obtained by truncating the base matrix. For example, the first matrix can be obtained by truncating the first 22 rows and the first 44 columns of the base matrix.

[0023] It can also be understood that rows 1 to x1′ of the first matrix are the core rows of the base matrix, columns 1 to y1′ are the core columns of the base matrix, columns y1′+1 to y2′ are the core check columns of the base matrix, and columns y2′+1 to Y′ are all or some of the extended check columns of the base matrix.

[0024] In some implementations of the first or second aspect, the first region is composed of a fifth region and a sixth region, the sixth region being a region composed of at least one column of the first region, and the third region being a region composed of at least one row of the fifth region.

[0025] In some implementations of the first or second aspect, the fifth region is the region consisting of columns 1 to y1 of the first region.

[0026] In some implementations of the first or second aspect, the first region is composed of a fifth region and a sixth region, the sixth region being a region composed of at least one column and at least one row in the first region, and the third region being a region composed of at least one row in the fifth region.

[0027] In some implementations of the first or second aspect, the fifth region is the region consisting of rows 1 to x1 and columns 1 to y1 of the first region.

[0028] In some implementations of the first or second aspect, the first translation value matrix consists of a fifth region, a second region, and a sixth region, wherein the fifth region and the second region have the same number of rows, the last column of the fifth region is adjacent to the first column of the second region, and the last column of the second region is adjacent to the first column of the sixth region.

[0029] In some implementations of the first or second aspect, the fifth region and the second region have the same number of columns.

[0030] In some implementations of the first or second aspect, the third and fourth regions are the same size.

[0031] In some implementations of the first or second aspect, the third region is located in the fifth region in the same position as the fourth region is located in the second region.

[0032] In some implementations of the first or second aspect, the first region further includes a seventh region, and the second region further includes an eighth region. The third column of the seventh region and the fourth column of the eighth region correspond to the same row in the first translation value matrix. The fourth column is any column in the eighth region, and the third column is the column in the seventh region corresponding to the fourth column. The translation value in the third column of the seventh region and the translation value in the fourth column of the eighth region satisfy the formula q. t,i,j =α t,i *p t,i,j +β t,i , or q 2,i,j =β i *p 2,i,j , where p 1,i,j q is the shift value of the i-th row in the third column. 1,i,j α is the shift value of the i-th row in the fourth column. t,i βi and α are constants corresponding to the i-th row of the third column. t,i and β i It is a non-negative integer.

[0033] In some implementations of the first or second aspect, the translation value in the third column of the seventh region and the translation value in the fourth column of the eighth region satisfy the formula: q t,i,j =f t,i (pt,i,j ), where p 1,i,j q is the shift value of the i-th row in the third column. 1,i,j f is the shift value of the i-th row in the fourth column. t,i Let be a nonlinear function, and the nonlinear function corresponds to at least one constant used for the nonlinear transformation. The at least one constant used for the nonlinear transformation is the constant corresponding to the i-th row of the third column.

[0034] In one possible scenario, if the row weight in the region corresponding to the first region in the basis matrix is ​​low, then the row corresponding to that low-weight row in the first region is included in the seventh region. When the translation values ​​in the seventh and eighth regions satisfy the above characteristics, their corresponding LDPC performance is relatively better.

[0035] In some implementations of the first or second aspect, Zc is greater than or equal to 64.

[0036] The proposed scheme exhibits better LDPC code performance when the boost value Zc is greater than or equal to 64. For example, when Zc is greater than or equal to 64, there are no short cycles in the first region.

[0037] In some implementations of the first or second aspect, the translation value of the third region is less than the first value.

[0038] Thirdly, a communication apparatus is provided for performing the method provided by any of the above aspects or their implementations. Specifically, the apparatus may include units and / or modules for performing the method provided by any of the above aspects or their implementations, such as processing units and / or transceiver units.

[0039] In one implementation, the device is either a transmitting device or a receiving device. When the device is a transmitting device or a receiving device, the transceiver unit can be a transceiver, an input / output interface, or a communication interface; the processing unit can be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0040] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device. When the device is a chip, chip system, or circuit used in a transmitting or receiving device, the transceiver unit can be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; the processing unit can be at least one processor, processing circuit, or logic circuit.

[0041] Fourthly, a communication device is provided, comprising: a memory for storing a program; and at least one processor for executing the computer program or instructions stored in the memory to perform the method provided in any of the foregoing aspects or their implementations.

[0042] In one implementation, the device is either a transmitting device or a receiving device.

[0043] In another implementation, the device is a chip, chip system, or circuit used in a transmitting or receiving device.

[0044] Fifthly, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to obtain a computer program or instructions stored in a memory via the communication interface to execute the method provided in any of the foregoing aspects or their implementations. The communication interface may be implemented in hardware or software.

[0045] In one implementation, the device further includes the memory.

[0046] Sixthly, a processor is provided for executing the methods provided in the above aspects.

[0047] Unless otherwise specified, or if it does not contradict its actual function or internal logic in the relevant description, the transmission and acquisition / reception operations involved in the processor can be understood as processor output and reception, input and other operations, or as transmission and reception operations performed by radio frequency circuits and antennas. This application does not limit them in this regard.

[0048] In a seventh aspect, a computer-readable storage medium is provided that stores program code for execution by a device, the program code including methods for performing any of the foregoing aspects or their implementations.

[0049] Eighthly, a computer program product containing instructions is provided, which, when run on a computer, causes the computer to perform the method provided in any of the foregoing aspects or their implementations.

[0050] Ninthly, a chip is provided, comprising a processor and a communication interface. The processor reads instructions stored in a memory through the communication interface and executes the methods provided in any of the above aspects or their implementations. The communication interface can be implemented in hardware or software.

[0051] Optionally, as one implementation, the chip also includes a memory that stores computer programs or instructions. The processor is used to execute the computer programs or instructions stored in the memory. When the computer programs or instructions are executed, the processor is used to perform the methods provided by any of the above aspects or their implementations.

[0052] When the method provided in this application is executed by a chip, this application does not limit the specific number of chips implementing the method. For example, it can be executed by one chip, or by two or more chips. Furthermore, when the number of chips implementing the method is two or more, the chip manufacturers are not limited; they can be from the same manufacturer or different manufacturers.

[0053] In a tenth aspect, a computer program is provided that, when run on a computer, causes the methods provided by any of the foregoing aspects or their implementations to be executed.

[0054] Eleventhly, a communication system is provided, including at least one of the transmitting end device or receiving end device described above. Attached Figure Description

[0055] Figure 1 is a schematic diagram of a network architecture to which embodiments of this application can be applied.

[0056] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0057] Figure 3 shows the Tanner plot of the parity-check matrix H of an LDPC.

[0058] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0059] Figure 5 is a schematic diagram of the information transmission process.

[0060] Figure 6 is a schematic flowchart of a communication method 600 based on LDPC code provided in this application.

[0061] Figure 7 is a schematic diagram of the region contained in the first translation value matrix.

[0062] Figure 8 is a schematic diagram of the five regions A to E in the first translation value matrix proposed in this application.

[0063] Figure 9 is a comparison diagram of the five parts A to E of the first translation value matrix and the division diagram of each region contained in the first translation value matrix.

[0064] Figure 10 is a schematic diagram of the translation values ​​in the second and fifth regions.

[0065] Figure 11 is a schematic diagram of the simulation performance of the LDPC matrix proposed in this application and the LDPC matrix used in 5G.

[0066] Figure 12 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application.

[0067] Figure 13 is a schematic block diagram of the communication device 1100 provided in an embodiment of this application. Detailed Implementation

[0068] To facilitate understanding of the embodiments of this application, the following points will be explained before introducing the embodiments of this application.

[0069] The terms "for indicating" or "instruction" can include both direct and indirect indication, or they can be explicit and / or implicit. The various numerical designations such as "first," "second," etc., are merely for descriptive convenience and are not intended to limit the scope of the embodiments of this application, such as distinguishing different messages or different information. "Predefined" can be implemented by pre-storing corresponding codes, tables, or other methods that can be used to indicate relevant information in the device; this application does not limit the specific implementation method. The "protocol" involved can refer to standard protocols in the field of communication, such as the Long Term Evolution (LTE) protocol, the New Radio (NR) protocol, and related protocols applied to future communication systems; this application does not limit this. The words "exemplary," "for example," "exemplary," "as another example," etc., are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or designs. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized. "At least one" means one or more, while "more" means two or more. "At most one" means one or zero. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, and c can mean: a, or, b, or, c, or, a and b, or, a and c, or, b and c, or, a, b, and c. Here, a, b, and c can be single or multiple. Descriptions relating to network element A sending messages, information, or data to network element B, and network element B receiving messages, information, or data from network element A, aim to specify which network element the message, information, or data is intended for, without specifying whether the transmission is direct or indirect via other network elements. Descriptions such as "when…", "in the case of…", "if", and "if" indicate that the device will take corresponding action under certain objective circumstances, not a time limit, nor requiring the device to perform a judgment action during implementation, nor implying any other limitations. Phrases such as "corresponding to…", "correspondingly", and equivalent expressions indicate a correspondence between the preceding and following elements, which may include indirect correspondence. For example, corresponding to a certain objective situation, the device will directly or indirectly take corresponding action, without requiring the corresponding action to immediately follow that objective situation.

[0070] Furthermore, the network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0071] The following describes a communication system to which embodiments of this application can be applied.

[0072] The embodiments of this application can be applied to various communication systems, including but not limited to: 5th generation (5G) systems, LTE systems, Long Term Evolution-Advanced (LTE-A) systems, LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, etc. They can also be applied to future communication systems, such as 6th generation mobile communication systems. Furthermore, they can be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, or other communication systems. Furthermore, it can be extended to similar wireless communication systems, such as Wireless-Fidelity (WiFi), Worldwide Interoperability for Microwave Access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0073] The communication system applicable to embodiments of this application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0074] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of this application. As shown in Figure 1, the embodiments of this application can be applied to both uplink and downlink data transmission. Figure 1 only uses uplink or downlink data transmission between one network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the sending device is the terminal device and the receiving device is the network device; conversely, in downlink data transmission, the sending device is the network device and the receiving device is the terminal device. Furthermore, the applicability of the embodiments of this application in other communication scenarios is not limited; for example, they can also be applied to sidelink communication.

[0075] The terminal equipment in this application can also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication equipment, user agent, or user device, etc. The terminal equipment in the embodiments of this application can be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as handheld devices with wireless connectivity, vehicle-mounted devices, etc. The terminal devices in the embodiments of this application may be mobile phones, tablets, laptops, handheld computers, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, etc.

[0076] The network equipment in this application can be a device with wireless transceiver capabilities, which can be a device that provides wireless communication services. It is usually located on the network side, including but not limited to next-generation base stations (gNodeB, gNB) in 5G systems, base stations in sixth-generation mobile communication systems, base stations in future mobile communication systems, or access nodes in wireless fidelity (WiFi) systems, evolved node B (eNB), radio network controller (RNC), node B (NB), base station controller (BSC), home base station (e.g., home evolved NodeB or home Node B, HNB), base band unit (BBU), transmission reception point (TRP), transmitting point (TP), base transceiver station (BTS), satellites, drones, etc. in long term evolution (LTE) systems. In a network architecture, network equipment may include centralized unit (CU) nodes, distributed unit (DU) nodes, RAN equipment including CU and DU nodes, RAN equipment including control plane CU nodes, user plane CU nodes, and DU nodes, or, in a cloud radio access network (CRAN) scenario, radio controllers, relay stations, vehicle-mounted equipment, and wearable devices. Furthermore, a base station may be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station may also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station may also be a mobile switching center and equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in 6G networks, and equipment performing base station functions in future communication systems. A base station can support networks with the same or different access technologies, without limitation.

[0077] Unless otherwise specified, the means for implementing the functions of a terminal device or network device in this application can refer to the terminal device or network device itself, or it can refer to a means that enables the terminal device or network device to implement the functions, such as a chip system or chip, specifically a system-on-a-chip (SoC) or a modem. This means can be installed in the terminal device or network device. In the embodiments of this application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0078] It should also be noted that some embodiments in this article use a 5G system as an example to introduce specific solution details. It is understood that when this solution is used in other communication systems, such as LTE systems, or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can achieve the corresponding functions, and this application does not limit this.

[0079] Furthermore, the embodiments of this application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability low-latency scenarios, or low-power scenarios. Among them, high-throughput scenarios can be, for example, enhanced mobile broadband (eMBB) scenarios, high-reliability low-latency scenarios can be, for example, URLLC (ultra-reliable low-latency communication) scenarios, and low-power scenarios can be, for example, M2M scenarios, MTC scenarios, or IoT scenarios.

[0080] To facilitate understanding of the embodiments of this application, several concepts or terms involved in the embodiments of this application are briefly described. The concepts or terms described below are based on the concepts or terms specified in the agreement, but do not mean that the embodiments of this application can only be applied to existing systems. The concepts or terms involved in the embodiments of this application can be applied to future systems. Furthermore, the specific names of the concepts or terms (e.g., concepts or terms involving functional descriptions) can be adjusted as the system develops in the future.

[0081] 1. LDPC code.

[0082] LDPC codes are a type of linear block code. Linear block codes divide the information sequence to be encoded into groups of q bits each. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits are then combined with the m parity bits to obtain a codeword of length n = q + m. The mapping from q information bits to an n-bit codeword is typically represented by a parity check matrix H. Based on the parity check matrix H, a codeword sequence can be generated to complete the encoding process. After the codeword sequence is transmitted through the channel, the receiving equipment decodes the received signal to determine the original information bits.

[0083] The parity-check matrix H of an LDPC is a sparse matrix. The number of zero elements in the parity-check matrix H is far greater than the number of non-zero elements; in other words, the row weight (or column weight) of the parity-check matrix is ​​far less than the number of elements in each row (or column) of the LDPC matrix. Specifically, an LDPC code with an information bit sequence length of q and a code length of n can be uniquely determined by its parity-check matrix H.

[0084] In 1981, Tanner represented the parity-check matrix H graphically, and this type of graph is now called a Tanner graph. There is a one-to-one correspondence between the Tanner graph and the parity-check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits and is called variable nodes, and the other type consists of parity nodes, representing parity constraints. Each parity node represents a parity constraint, which will be explained below with reference to Figures 2 and 3.

[0085] Figure 2 is a schematic diagram of the parity check matrix H of an LDPC.

[0086] In Figure 2, {V i} represents the set of variable nodes (VN), {C i} represents the set of check nodes (CNs). Each row of the check matrix H represents a check equation, and each check equation corresponds to a check node. Each column represents a codeword bit, and each codeword bit corresponds to a variable node. In Figure 2, there are 8 variable nodes and 4 check nodes. If a codeword bit is included in the corresponding check equation, a line is used to connect the involved variable nodes and check nodes to obtain the Tanner graph.

[0087] Figure 3 is a Tanner plot of the parity-check matrix H of an LDPC.

[0088] As shown in Figure 3, the Tanner graph represents the parity-check matrix of the LDPC. For example, for a parity-check matrix H of size m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m parity nodes. The n variable nodes correspond to the n columns of the parity-check matrix H, and the m parity nodes correspond to the m rows of the parity-check matrix H. Cycles in the Tanner graph are composed of interconnected vertices, with one vertex serving as both the start and end point, and each cycle passes through each node only once. More specifically, a cycle is a closed loop formed by connecting variable nodes, parity nodes, and edges. The length of a cycle is defined as the number of edges it contains, while the perimeter of the graph, also known as the circumference, is defined as the length of the smallest cycle in the graph. In Figure 3, the perimeter is 4, as shown by the bolded lines. The variable nodes in the Tanner graph correspond to each column of the parity-check matrix H, which is equivalent to each codeword bit in the LDPC. The parity nodes in the Tanner graph correspond to each row of the parity-check matrix H, which is equivalent to each parity bit in the LDPC. The connection between the two types of nodes corresponds to the value of an element in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the element (i, j) in the H matrix has a value of 1; otherwise, the corresponding element is 0. The connection between a variable node and a check node can also be called an edge. A connection between a check node and a variable node can also be described as: the check node and the variable node have a connection or an edge. The edge relationship between a check node and a variable node can include either the presence of an edge or the absence of an edge.

[0089] 2. QC-LDPC code.

[0090] QC-LDPC codes are a type of structured LDPC codes. Due to the unique structure of their parity-check matrix, encoding can be implemented using a simple feedback shift register, reducing the encoding complexity of LDPC codes. In practice, QC-LDPC codes are represented using a base graph (BG), where elements are either 0 or 1. Expanding the 1s and 0s in the BG yields a parity-check matrix H, which can be used for encoding or decoding. In the embodiments of this application, the BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG Basis matrix H BG An element of 0 indicates that there are no edges in the base graph, while a value of 1 indicates that there are edges in the base graph (or that the corresponding check is associated with the corresponding variable). NR LDPC codes involve multiple base graph selection; currently, the standard stores two base graphs, BG1 and BG2. BG2 is used when the information length is less than or equal to 292, or when the information length is less than or equal to 3824 and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25; otherwise, BG1 is used. The expansion process of the base matrix is ​​described below.

[0091] Based on the base matrix and the lifting size Zc, the base matrix can be expanded into a complete parity-check matrix for encoding or decoding. In this application, Zc... c It can also be called the expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process involves lifting all elements of the base matrix into a Zc*Zc square matrix, where 0 is lifted into a Zc*Zc 0 matrix, 1 is lifted into an identity matrix, and the identity matrix is ​​cyclically shifted based on the shifting value (SV) corresponding to 1. This cyclic shift can be left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shifting value. Taking a 4*4 identity matrix as an example, if the shifting values ​​are 0, 1, and 3, the cyclically shifted matrix after cyclically shifting to the right is as follows:

[0092] (1) When the translation value is 0 (i.e., remains unchanged), the corresponding cyclically shifted matrix is:

[0093] (2) When the translation value is 1, the corresponding cyclically shifted matrix is:

[0094] (3) When the translation value is 3, the corresponding cyclically shifted matrix is:

[0095] Alternatively, it can be understood that the complete parity check matrix H can be derived from an exponential matrix H. b H indicates b Each element in the matrix corresponds to a Zc*Zc submatrix. Each element indicates the number of times the corresponding submatrix is ​​cyclically shifted from the Zc*Zc identity matrix. Therefore, the storage space required for the complete parity check matrix H is greatly reduced. (Exponential matrix H) b The elements in it can also be called QC blocks.

[0096] For example, the exponent matrix H of the QC-LDPC code b As shown below:

[0097] It can be seen that the exponent matrix H b The size is 4 rows and 24 columns, and the exponent matrix H b Each element i in the matrix represents a square matrix of order Zc. Let represent a cyclic shift matrix, where i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. Additionally, the exponent matrix H... b In this context, "-1" represents a zero matrix and "0" represents the identity matrix.

[0098] For example, As shown below:

[0099] Optional, exponent matrix H b In addition to "-1", zero elements in the matrix can also be represented in other ways, such as using "-" or null values ​​to represent a matrix of all zeros.

[0100] It is understandable that the above exponent matrix H b The matrix corresponding to the positions greater than or equal to 0 that are changed to 1 and the positions of -1 that are changed to 0 is the basis matrix. The 1s in the basis matrix are expanded into a Zc-order cyclic shift matrix based on the corresponding elements of the exponent matrix, and the 0s are expanded into a Zc-order all-zero matrix. After the expansion, the parity check matrix H is obtained.

[0101] Next, the information bit sequence c can be encoded based on the parity-check matrix H to obtain a codeword sequence. The codeword sequence includes (N+2*Zc-K) parity bits w, where N is the length of the codeword sequence, K = Kb*Zc, Kb is the number of columns corresponding to the information column in the base map, and Zc is the boost value. For details on Zc, please refer to the explanation in Terminology 3. Specifically, the parity bits w are determined based on the information bit sequence c and the parity-check matrix H, where the parity bits are w = [w0, w1, w2, ..., wN+2*Zc-K-1]. T c = [c0, c1, c2, ..., c K-1 ] T The encoding process is solving equations The process of obtaining w.

[0102] 3. Lifting Size (Zc) and Shifting Value.

[0103] The storage content of the 5G LDPC code regarding the translation values ​​includes: (1) a list of lifting values; and (2) a list of translation values ​​that corresponds one-to-one with the rows of the Lifting Size list.

[0104] For example, the list of promotion values ​​is shown in Table 1.

[0105] Table 1

[0106] The j-th row of the boost list includes Where aj∈{2,3,5,7,9,11,13,15}, max(kj)∈{7,7,6,5,5,5,4,4}; the index of the lifting value corresponds one-to-one with the column index of the translation value, that is, the lifting value index in each row of the lifting value list corresponds to a set of translation values.

[0107] For example, the list of translation values ​​is shown in Table 2.

[0108] Table 2

[0109] For a fixed lift index, a non-zero position in the base matrix corresponds to one translation value. For example, H... BG The shift value corresponding to row 0, column 0 when the promotion index is 0 is 211, H BG The shift value corresponding to the 6th column of the 1st row in the middle when the lifting index = 3 is 66, H BG The shift value corresponding to the second row and ninth column of the middle column when the promotion index is 7 is 206.

[0110] It's understandable that LDPC encoding requires first determining the lift value, and then constructing a parity check matrix based on the corresponding shift value. For example, if the determined lift value is 40, and the lift value index corresponding to 40 in Table 1 is 2, then the parity check matrix can be constructed based on the shift value in the column corresponding to lift value index = 2 in Table 2.

[0111] 4. The structure of the parity check matrix and the basis matrix.

[0112] Figure 4 is a schematic diagram of the structure of the parity check matrix.

[0113] As shown in Figure 4(a), the parity check matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 4(b). Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or it can be a parity with a degree greater than or equal to 2, or it can be the parity node corresponding to the row set with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 4(b) and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 4(b). The raptor-like region can correspond to part E in Figure 4(b) and can be an identity matrix corresponding to the parity bits of the low-rate extension. Part B and Part E are both verification parts. Part B is defined as the core verification region, and its features can be non-lower triangular coding parts (i.e., values ​​above the diagonal are not all 0) or coding parts with column weight greater than 1. Part E is defined as the extended verification region, and its features can be lower triangular coding parts (i.e., values ​​above the diagonal are all 0) or diagonal matrices.

[0114] The parity-check matrix of the LDPC code shown in Figure 4 adopts a "raptor-like" structure, which can be gradually extended to low code rates from a high code rate core matrix. In actual use, as shown in Figure 4(a), the first X rows and the first Y columns of the parity-check matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands.

[0115] It should be noted that the parity check matrix can be represented by the LDPC basis matrix. Therefore, the structure of the LDPC basis matrix is ​​similar to that of the parity check matrix, and will not be described in detail here.

[0116] 5. Information column and validation column.

[0117] The columns of the LDPC base matrix consist of information columns and check columns.

[0118] Information column: Corresponding to information bits (or information bits, system bits, etc.), it is the column corresponding to part A.

[0119] Check columns: Corresponding to check bits (or check digits, etc.), these are the columns corresponding to parts B and C, and can include core check columns and extended check columns. The core check columns are those corresponding to part B, while the extended check columns are those corresponding to parts C or E. Extended check columns can also be called raptor-like columns. Alternatively, the core check columns are the check columns in part B with a column weight greater than 1 (part B has 1 elements both above and below its diagonal), and the extended check columns are the remaining check columns excluding the core check columns.

[0120] 6. Core rows, core columns, and core matrix.

[0121] Core rows: The core rows of the LDPC base matrix correspond to the core parity bits. In other words, the core rows are the rows corresponding to high bitrate regions, or the rows corresponding to parts A, B, or C.

[0122] Core columns: These can include all information columns and all core check columns. In other words, core columns are the columns corresponding to high bitrate areas, or the columns corresponding to part A plus part B.

[0123] The kernel matrix is ​​a matrix consisting of all the kernel rows and columns of the LDPC base matrix. In other words, the kernel matrix is ​​the high-rate region of the LDPC base matrix, or the part consisting of part A and part B.

[0124] 7. Message length, code length, and code rate.

[0125] The information length is the length of the bit sequence of information to be sent (i.e., the number of bits contained therein). This length can be the length of the payload information bits, or the length of the payload information bits after adding cyclic redundancy check (CRC) bits. This application does not impose any specific restrictions.

[0126] Code length refers to the length of the bit sequence to be transmitted, which can be the transmitted bit sequence corresponding to the modulated symbol.

[0127] Code rate refers to the ratio of the length of the bit sequence of information to be transmitted to the code length.

[0128] Optionally, the above three values ​​can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, or they can be directly obtained and calculated by the transceiver. For example, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bit sequence; the code rate can be indicated in the above manner or given in the modulation and coding scheme (MCS).

[0129] 8. Information transmission process.

[0130] Figure 5 is a schematic diagram of the information transmission process applicable to this application. As shown in Figure 5, information is sent from the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, and finally reaches the destination, completing the transmission of information from the source to the destination. The processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation) is performed at the transmitting end device, while the processing shown in the lower layer (including demodulation, channel decoding, and source recovery) is performed at the receiving end device. The embodiments of this application mainly involve the source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0131] Based on the description in the background section, this application proposes a communication method based on LDPC codes, which can effectively solve the corresponding technical problems. The method proposed in this application is described in detail below.

[0132] Figure 6 is a schematic flowchart of a communication method 600 based on LDPC codes provided in this application. The method includes the following steps.

[0133] It is understood that method 600 can be executed by both the sending device and the receiving device. Unless otherwise specified, "sending device" or "receiving device" can refer to the sending device or receiving device itself, or it can refer to a device that enables the sending device or receiving device to implement this function. For ease of description, the following text will use "sending device" and "receiving device" to describe it. Among them, the sending device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0134] S610, the transmitting device obtains the information bit sequence.

[0135] It is understandable that if the sending device needs to communicate with the receiving device, that is, if the sending device needs to send a signal to the receiving device, then the sending device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0136] The process of the transmitting device acquiring the information bit sequence can refer to: the transmitting device performing source encoding on the source symbols to generate the information bit sequence; or, the transmitting device acquiring the information bit sequence can also refer to: the transmitting device receiving the information bit sequence from other communication devices. This application does not limit the method of acquiring the information bit sequence.

[0137] S620, the transmitting device determines the LDPC matrix. This LDPC matrix is ​​determined based on the LDPC shift value matrix and the boost value Zc. The LDPC code shift value matrix includes part or all of the region of the first shift value matrix, and the first shift value matrix includes a first region and a second region.

[0138] The first translation value matrix includes a first region and a second region, and can also be described as follows: the first translation value matrix is ​​composed of a first region and a second region. The first region and the second region are described below.

[0139] (1) The first region is the entire region of the matrix obtained by replacing the 1 element in part or all regions of the LDPC basis matrix (hereinafter referred to as the basis matrix) with the translation value of the 1 element. The translation value corresponding to the 1 element in the LDPC basis matrix is ​​determined based on Zc.

[0140] For example, the basis matrix is ​​NR, either BG1 or BG2.

[0141] For example, the boost value Zc is greater than or equal to 64.

[0142] For example, a portion of the base matrix can be determined based on the actual code rate. That is, as shown in Figure 4(a), a portion of the base matrix can be obtained by truncating the base matrix based on the actual code rate required in the current communication scenario.

[0143] For example, a portion of the base matrix can also correspond to a relatively low bitrate region within the base matrix. As shown above, the lower the bitrate, the larger the corresponding region. For instance, in high-throughput scenarios, the first region can be obtained by extracting the first 22 rows and the first 44 columns of the base matrix.

[0144] It is understandable that if the first region is obtained based on the actual bit rate, then the LDPC matrix is ​​the first shift value matrix. If the first region is obtained based on a relatively low bit rate, then the LDPC matrix includes part or all of the region of the first shift value matrix, that is, it can be obtained by truncating the first shift value matrix based on the actual bit rate.

[0145] It can also be understood that if a 0 element in the base matrix has no corresponding translation value, then the position in the first region corresponding to the 0 element in the base matrix will not have a translation value. For example, the first region is a matrix obtained by replacing some or all 1 elements in the base matrix with their translation values ​​and replacing 0 elements with -1, where -1 indicates that no translation value exists. Alternatively, -1 can be replaced with other non-negative integer characters (e.g., null), which is not limited in this application.

[0146] For example, the translation value corresponding to the element 1 in the basis matrix can be obtained by looking up Zc, Table 1 and Table 2. The specific lookup method will not be described here.

[0147] (2) The first region includes the third region, the second region includes the fourth region, the first column of the third region and the second column of the fourth region correspond to the same row in the first translation value matrix, the second column is any column in the fourth region, the first column is the column in the third region corresponding to the second column, the first column and the second column satisfy the following characteristics: the difference between the translation value of the i-th row in the first column and the translation value of the i-th row in the second column modulo the first value is the second value, the first value is a positive integer, the first value is related to Zc, and the second value is a non-negative integer.

[0148] For example, the first value is Zc / c, or the first value is Zc / c rounded up or down, where c is a positive integer. For instance, the first value equals... Indicates rounding down. This indicates rounding up to the nearest integer.

[0149] For example, the translation value of the third region is less than that of the first region.

[0150] Based on the above description, it can be understood that the rows containing translation values ​​are the same in the first and second columns. The first and second columns correspond to the same rows in the first translation value matrix; if there is a translation value in the i-th row of the first column, there is also a translation value in the i-th row of the second column.

[0151] For example, the first column corresponds to a row number greater than or equal to 4 in the first translation value matrix.

[0152] For example, there is column #1 in the third region and column #2 in the fourth region. Column #1 and column #2 (an example of the first and second columns) are corresponding columns. Column #1 and column #2 correspond to the same row k1 in the first translation value matrix, and they satisfy the above characteristics. As another example, there is column #3 in the third region and column #4 in the fourth region. Column #3 and column #4 (another example of the first and second columns) are corresponding columns. Column #3 and column #4 correspond to the same row k2 in the first translation value matrix, and they satisfy the above characteristics.

[0153] For example, k1 and k2 can be the same or different. For instance, k1 = k2 = 4.

[0154] For example, column #1 and column #3 can be the same column or different columns. For instance, if k1 = k2, column #3 and column #1 can be the same column.

[0155] It is understood that in this application, A modulo B is C, which means A mod B = C.

[0156] For example, if k1 equals 4, Zc = 64, c = 8, the first, second, and third rows of column #1 have the shifted value {2, 7, 1}, and the corresponding first, second, and third rows of column #2 have the shifted value {2, 15, 17}. The difference between the shifted value in column #1 and the corresponding shifted value in column #2 is {0, -8, -16}. It can be seen that the remainder when any element in {0, -8, -16} is modulo Zc / c (i.e., the first value is 8) is the same, that is, the second remainder value is 0.

[0157] For example, if k1 equals 4, Zc = 64, c = 8, the first, second, and third rows of column #1 have the shifted value {3, 8, 2}, and the corresponding first, second, and third rows of column #2 have the shifted value {2, 15, 17}. The difference between the shifted value in column #1 and the corresponding shifted value in column #2 is {1, -7, -15}. It can be seen that any element in {1, -7, -15} has the same remainder when modulo Zc / c (i.e., the first value is 8), that is, the second remainder value is 1. For example, if k2 equals 4, Zc = 64, c = 8, the first, second, and fourth rows of column #3 contain the shifted value {7, 5, 4}, and the corresponding first, second, and fourth rows of column #4 contain the shifted value {7, 13, 36}. The difference between the shifted values ​​in column #3 and the corresponding shifted values ​​in column #4 is {0, -8, -32}. It can be seen that the remainder when any element in {0, 8, 32} is modulo Zc / c (i.e., the first value is 8) is the same, that is, the second remainder is 0.

[0158] It is understandable that there may be other columns besides column #2 and column #4 in the fourth region, and a corresponding column in the third region can also be found that satisfies the characteristics between the first and second columns mentioned above.

[0159] For example, in the third and fourth regions, each column corresponds to the same row in the first translation value matrix.

[0160] For example, rows in the third and fourth regions can be consecutive or non-consecutive. For example, rows with low row weight in the first region may not be included in the third region.

[0161] For example, the third and fourth regions contain the same number of columns m, and the translation value of the j-th column in the fourth region and the translation value of the j-th column in the third region satisfy the characteristic between the first and second columns, 1≤j≤m.

[0162] Based on the characteristics satisfied between the first and second columns described above, in one possible implementation, the translation values ​​in the first column and the translation values ​​in the second column satisfy the formula... Where, p 1,i,j Let q be the shift value of the i-th row in the first column. 1,i,j Let γ be the shift value of the i-th row in the second column, where c is a positive integer and γ is a positive integer. i / c is a constant corresponding to the i-th row of the first column, and γ i It is a non-negative integer less than c.

[0163] For example, based on the above formula, the first value is The second value is 0.

[0164] For example, in the third region, each row i corresponds to a γ. i .

[0165] For example, the third region corresponds to 4 rows, c=4, and the first to fourth rows in the third region correspond to {γ1,γ2,γ3,γ4}={0,1,2,3} respectively.

[0166] For example, the protocol can store the γ corresponding to all rows in the third region. i / c.

[0167] The following describes the possible specific matrix forms for the first region.

[0168] The first region corresponds to the first matrix, which is obtained by replacing the values ​​at positions with translation values ​​in the first region with 1 and the values ​​at the remaining positions with 0 (i.e., the first matrix can be seen as a matrix obtained by truncating the base matrix based on the actual bitrate and a lower bitrate). The first region (or the first matrix) includes X′ rows and Y′ columns. The matrix formed by rows x1′+1 to X′ and columns y2′+1 to Y′ of the first matrix is ​​the identity matrix. The matrix formed by rows 1 to x1′ and columns y2′+1 to Y of the first matrix is ​​an all-zero matrix. The matrix formed by rows 1 to x1′ and columns y1′+1 to y2′ of the first matrix is ​​a square matrix, where 1 < x1′ < X′, 1 < y1′ < y2′ < Y′, and x1′, X′, y1′, y2′, and Y′ are all integers.

[0169] It can be understood that rows 1 to x1′ of the first matrix are the core rows of the base matrix, columns 1 to y1′ are the core columns of the base matrix, columns y1′+1 to y2′ are the core check columns of the base matrix, and columns y2′+1 to Y′ are all or some of the extended check columns of the base matrix.

[0170] The first region consists of the fifth region and the sixth region. The sixth region is a region consisting of at least one column of the first region, and the third region is a region consisting of at least one row of the fifth region.

[0171] For example, the fifth region is the region consisting of columns 1 to y2′ in the first region, and the sixth region is the region consisting of columns y2′+1 to Y′ in the first region.

[0172] For example, the fifth region is the region consisting of columns 1 to y1′ in the first region, and the sixth region is the region consisting of columns y1′+1 to Y′ in the first region.

[0173] For example, the third region is the region consisting of the first four rows of the fifth region.

[0174] It's understandable that when the third region contains more than 4 rows, the performance deteriorates with increasing row count. Generally, to ensure LDPC code performance, the third region contains n rows, where c can be any value for n. The rows 1 through n in the third region correspond to {γ1, γ2, ..., γ...} n}={0,1,…,n-1}. That is, when c=4, if n=4, the LDPC code has good performance when the first to fourth rows of the third region correspond to {γ1,γ2,γ3,γ4}={0,1,2,3} respectively. However, when the number of rows in the first region increases, the value of c needs to be increased to ensure performance. For example, when Zc / c=4, the second region can inherit the performance of the first region with a boost value of 4. When Zc / c=8, the second region can inherit the performance of the first region with a boost value of 8. Since the larger the boost value, the fewer short loops the first region has and the better the performance, the larger n is, the larger the value of c is to ensure performance, which will lead to a smaller Zc / c, and the performance inherited by the second region will deteriorate, thus causing the LDPC code performance to deteriorate.

[0175] The following example illustrates the first translation value matrix and the division of the third and fourth regions within the first translation value matrix, based on the above description.

[0176] Figure 7 is a schematic diagram of the regions contained in the first translation value matrix. As shown in Figure 7, the first translation value matrix consists of a fifth region, a second region, and a sixth region. The second region and the fifth region have the same number of rows in the first translation value matrix. The last column of the fifth region is adjacent to the first column of the second region, and the last column of the second region is adjacent to the first column of the sixth region. The third region is located within the fifth region, and the fourth region is located within the second region.

[0177] For example, the number of columns corresponding to the second and fifth regions may be the same or different; this application does not impose any restrictions on this. It is understood that when the number of columns corresponding to the second and fifth regions is the same, the second and fifth regions are of the same size.

[0178] It is understood that in this application, the fact that two matrices or two regions are the same size means that they have the same dimensions, that is, the number of rows and columns of the two matrices or two regions.

[0179] For example, the fourth region may be the same size as or different from the third region.

[0180] For example, the rows in the third and fourth regions can be consecutive or non-consecutive.

[0181] For example, the second and fifth regions have the same number of columns (i.e., the second and fifth regions are the same size), and the fourth region in the second region has the same size and position as the third region in the fifth region.

[0182] For example, if the fifth region is the region formed by columns 1 to y1' of the first region, then the first translation value matrix corresponds to the second matrix. The second matrix is ​​obtained by replacing the values ​​at the positions containing translation values ​​in the first translation value matrix with 1, and replacing the values ​​at the remaining positions with 0. The first translation value matrix (or the second matrix) includes X″ rows and Y″ columns. The matrix formed by rows x1″+1 to X″ and columns y2″+1 to Y″ of the second matrix is ​​the identity matrix. The matrix formed by the first row and columns y2″+1 to y2″ is a matrix of all zeros. The matrix formed by the first to x1″ rows and columns y1″+1 to y2′ of the second matrix is ​​a square matrix, where 1 < x1″ < X″, 1 < y1″ < y2″ < Y″, and x1″, X″, y1″, y2″, and Y″ are all integers. X″ = X′, x1″ = x1′, y1″ = y1′+s, y2″ = y2′+s, Y″ = Y′+s, where s is the column number corresponding to the second region.

[0183] For ease of description, this application refers to the region formed by rows x1″+1 to X″ and columns y2″+1 to Y″ of the first translation value matrix as region E, the region formed by rows 1 to x1″ and columns y2″+1 to Y″ of the second matrix as region C, the region formed by rows 1 to x1″ and columns y1″+1 to y2″ of the second matrix as region B, the region formed by rows 1 to x1″ and columns 1 to y1″ of the first translation value matrix as region A, and the region formed by rows x1″+1 to X″ and columns 1 to y2″ of the first translation value matrix as region D. Figure 8 is a schematic diagram of the five regions A to E in the first translation value matrix.

[0184] Figure 9 is a comparison diagram of the five parts A to E of the first translation value matrix and the fifth, sixth, and second regions in the first translation value matrix. Specifically, the regions containing rows 1 to X″ and columns 1 to y1″ of the first translation value matrix are the second and fifth regions, and the remaining regions in the first translation value matrix are the sixth region.

[0185] For example, the first matrix corresponding to the first region is the matrix obtained by cutting off the first 22 rows and the first 44 columns of the base matrix, then X′=22, Y′=44, x1′=4, y1′=22, y2′=26. For example, the second region includes 22 columns, then X″=22, Y″=66, x1″=4, y1″=44, y2″=48.

[0186] The translation values ​​of the third region in the first region and the fourth region in the second region were described in detail above. The translation value characteristics of the remaining regions in the first region (excluding the third region) and the second region (excluding the fourth region) are described below.

[0187] The first region also includes the seventh region, and the second region also includes the eighth region. The third column in the seventh region and the fourth column in the eighth region correspond to the same row in the first translation value matrix. The fourth column is any column in the eighth region, and the third column is the column in the seventh region that corresponds to the fourth column.

[0188] In one implementation, the translation value in the third column of the seventh region and the translation value in the fourth column of the eighth region satisfy the formula q. 2,i,j =p 2,i,j +β i , or q 2,i,j =β i *p 2,i,j , where p 1,i,j q is the shift value of the i-th row in the third column. 1,i,j β is the shift value of the i-th row in the fourth column. i This is the constant corresponding to the i-th row of the third column. For example, β i It is a non-negative integer.

[0189] In another implementation, the translation value in the third column of the seventh region and the translation value in the fourth column of the eighth region satisfy the formula q. t,i,j =α t,i *p t,i,j +β t,i , where p 1,i,j q is the shift value of the i-th row in the third column. 1,i,j α is the shift value of the i-th row in the fourth column. t,i and β i Let α be the constant corresponding to the i-th row of the third column. For example, α... t,i and β i It is a non-negative integer.

[0190] In another implementation, the translation value in the third column of the seventh region and the translation value in the fourth column of the eighth region satisfy the formula: q t,i,j =f t,i (p t,i,j ), where p 1,i,j q is the shift value of the i-th row in the third column. 1,i,j f is the shift value of the i-th row in the fourth column. t,i Let be a nonlinear function, and the nonlinear function corresponds to at least one constant used for the nonlinear transformation. The at least one constant used for the nonlinear transformation is the constant corresponding to the i-th row of the third column.

[0191] For example, the protocol can store the constants corresponding to all rows in the eighth region.

[0192] For example, the area remaining in the fifth region excluding the third region is the seventh region, and the area remaining in the second region excluding the fourth region is the eighth region.

[0193] Here is a concrete example of the first translation value matrix. The base matrix is ​​BG1, and the first region is the matrix obtained by replacing the 1 elements in the first 22 rows and first 44 columns of the base matrix with their corresponding translation values, and replacing the 0 elements with -1. The first region consists of the fifth and sixth regions. The fifth region comprises the first 22 columns (i.e., the information columns corresponding to the base matrix) of the first region, and the sixth region comprises the remaining regions of the first region excluding the fifth region. The second region is the same size as the fifth region (i.e., both the second and fifth regions are 22 rows and 22 columns). Therefore, X″ = 22, Y″ = 66, x1″ = 4, y1″ = 44, and y2″ = 48. The fourth region has the same position and size in the second region as the third region has in the fifth region. Furthermore, the translation value in the j-th column of the fourth region satisfies the following characteristic: the difference between the translation value in the i-th row and j-th column of the fourth region and the translation value in the i-th row and j-th column of the third region, modulo the first value, equals the second value, where 1 ≤ j ≤ 22. Figure 10 is a possible schematic diagram of the translation values ​​in the fifth and second regions. As shown in Figure 10, the region comprised of the first 22 columns is the fifth region, the region comprised of the last 22 columns is the second region, and the region comprised of the first 4 rows of the fifth region... The domain is the third region, and the region formed by the first four rows of the second region is the fourth region. Here, Zc = 384. The first row of the fifth region is the same as the first row of the second region; the translation value corresponding to the i-th element in the second row of the fifth region is determined based on the translation value corresponding to the i-th element in the second row of the second region. For example, if the translation value of the i-th element in the second row of the second region is 'a', then the translation value of the i-th element in the second row of the fifth region is 'b' = (a + 384 * 1 / 4) mod 384; the translation value of the i-th element in the third row of the second region... The translation value of the first element is 'a', and the translation value of the 'i' element in the third row of the fifth region is 'b' = (a + 384 * 1 / 2) mod 384; the translation value of the 'i' element in the fourth row of the second region is 'a', and the translation value of the 'i' element in the fourth row of the fifth region is 'b' = (a + 384 * 3 / 4) mod 384; the translation value of the 'i' element in the k-th row of the second region is 'a', and the translation value of the 'i' element in the k-th row of the fifth region is 'b' = (a + k) mod 384, where k is an integer greater than 4.

[0194] Optionally, the protocol can store Z corresponding to each set of boost values. max The corresponding first translation value matrix. At this time, Zc = Z max Therefore, the stored matrix translation values ​​are taken from [0, Z]. max / 4。

[0195] In this application, the LDPC translation value matrix includes part or all of the region of the first translation value matrix. That is, in this implementation, the LDPC translation value matrix is ​​obtained by truncating the first translation value matrix.

[0196] Optionally, a new LDPC translation value matrix can be obtained by adding or subtracting the third value modulo Zc from the translation values ​​in at least one row of the LDPC translation value matrix, and / or by adding or subtracting the fourth value modulo Zc from the translation values ​​in at least one column of the LDPC translation value matrix, and / or by performing row permutations on the LDPC translation value matrix, and / or by performing column permutations on the LDPC translation value matrix, where the third and fourth values ​​are non-negative integers. Then, this new LDPC matrix is ​​lifted and shifted to obtain the corresponding LDPC matrix.

[0197] Optionally, the LDPC translation value matrix includes part or all of the region of the second translation value matrix, wherein the second translation value matrix is ​​obtained by adding or subtracting a third value modulo Zc from the translation values ​​in at least one row of the first translation value matrix, and / or adding or subtracting a fourth value modulo Zc from the translation values ​​in at least one column of the first translation value matrix, and / or performing row permutations on the first translation value matrix, and / or performing column permutations on the first translation value matrix, wherein the third and fourth values ​​are non-negative integers. That is, in this implementation, the LDPC translation value matrix is ​​obtained by truncating the second translation value matrix.

[0198] It is understood that a few corresponding columns in the third and fourth regions of this application that do not meet the characteristics of the first and second columns are also included within the scope of protection of this application.

[0199] It can also be understood that after obtaining the LDPC shift value matrix, the corresponding LDPC matrix can be obtained by lifting and shifting the LDPC shift value matrix. In this application, the LDPC matrix can also be called the LDPC encoding matrix. For example, the LDPC matrix can be an LDPC parity check matrix or an LDPC generator matrix. The LDPC parity check matrix or the LDPC generator matrix is ​​the matrix obtained by lifting and shifting the elements in all regions of the base matrix, and there is a one-to-one correspondence between the LDPC generator matrix and the LDPC parity check matrix.

[0200] S630: The transmitting device encodes the information bit sequence according to the LDPC matrix and outputs the codeword sequence.

[0201] For ease of description, this step is briefly explained using the LDPC parity check matrix H as an example. The information bit sequence c is encoded based on the LDPC parity check matrix H to obtain a codeword sequence. This codeword sequence includes (N+2*Zc-K) parity bits w, where N is the length of the codeword sequence, and K = Kb*Zc, where Kb is the number of columns corresponding to the information column in the base map. Specifically, the parity bits w are determined based on the information bit sequence c and the parity check matrix H, where the parity bits are w = [w0, w1, w2, ..., wN+2*Zc-K-1]. T c = [c0, c1, c2, ..., c K-1 ] T The encoding process is solving equations The process of obtaining w.

[0202] S640, the transmitting device determines the symbol sequence based on the codeword sequence.

[0203] It is understandable that a symbol sequence can be a rate-matched sequence or a modulated sequence. For example, the transmitting device performs rate matching on the codeword sequence, then modulates the rate-matched sequence to obtain a symbol sequence, and then maps the modulated symbol sequence onto physical resources for transmission.

[0204] S650, the transmitting device sends a symbol sequence to the receiving device. Correspondingly, the receiving device receives the symbol sequence from the transmitting device.

[0205] It is understandable that the symbol sequence #1 sent by the transmitting device and the symbol sequence #2 received by the receiving device may be different because channel noise signals may be introduced during the transmission of the symbol sequence.

[0206] In S660, the receiving device decodes the symbol sequence according to the LDPC matrix to obtain the information bit sequence.

[0207] The LDCP matrix used for decoding by the receiving device is the same as the LDPC matrix used for encoding by the transmitting device. The specific method by which the receiving device determines the LDPC matrix can be found in the description on the transmitting device side, and will not be detailed here.

[0208] Figure 11 is a schematic diagram of the simulation performance of the LDPC matrix proposed in this application and the LDPC matrix used in 5G. The horizontal axis represents the information length, and the vertical axis represents the signal-to-noise ratio (SNR) corresponding to a block error ratio (BLER) of 1e-2. The simulation results use a Min-sum decoding algorithm with 5 iterations to compare the performance of the LDPC codes.

[0209] In this diagram, line 1 represents the simulated performance of the LDPC matrix used in 5G at a code rate of 11 / 12; line 2 represents the simulated performance of the LDPC matrix proposed in this application at a code rate of 11 / 12; line 3 represents the simulated performance of the LDPC matrix used in 5G at a code rate of 11 / 14; line 4 represents the simulated performance of the LDPC matrix proposed in this application at a code rate of 11 / 14; line 5 represents the simulated performance of the LDPC matrix used in 5G at a code rate of 11 / 12; and line 6 represents the simulated performance of the LDPC matrix proposed in this application at a code rate of 11 / 12. It can be understood that, with the same value on the horizontal axis, a lower value on the vertical axis indicates better performance. Therefore, the LDPC matrix proposed in this application has performance gains at various code rates and code lengths.

[0210] It is understood that the steps in the above figures are merely illustrative and are not intended to be strictly limited. Furthermore, the sequence numbers of the processes described above do not imply a specific order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0211] It is also understood that some optional features in the various embodiments of this application may not depend on other features in some scenarios, or may be combined with other features in some scenarios, without limitation.

[0212] It is also understood that, in the above-described method embodiments, the methods and operations implemented by the device (transmitting device or receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0213] The method embodiments provided in this application have been described in detail above with reference to Figures 1 to 11. The apparatus embodiments of this application will be described below with reference to Figures 12 and 13. It is understood that, in order to implement the functions in the above embodiments, the apparatuses in Figures 12 and 13 include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, based on the units and method steps of the various examples described in conjunction with the embodiments disclosed in this application, this application can be implemented in hardware or a combination of hardware and computer software. It is understood that the technical features described in the above method embodiments are also applicable to the following apparatus embodiments.

[0214] Figures 12 and 13 are schematic diagrams of possible apparatus structures provided in embodiments of this application. These apparatuses can be used to implement the functions of the transmitting or receiving devices in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.

[0215] Figure 12 is a schematic block diagram of a communication device 1000 provided in an embodiment of this application. As shown in Figure 12, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used for data processing. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0216] In one possible design, the device 1000 can implement the steps or processes corresponding to those performed by the transmitting device in the above method embodiments, wherein the processing unit 1020 is used to perform processing-related operations of the transmitting device in the above method embodiments, and the communication unit 1010 is used to perform transmission-related operations of the transmitting device in the above method embodiments.

[0217] In another possible design, the device 1000 can implement the steps or processes corresponding to those performed by the receiving device in the above method embodiments, wherein the communication unit 1010 is used to perform the receiving-related operations of the receiving device in the above method embodiments, and the processing unit 1020 is used to perform the processing-related operations of the receiving device in the above method embodiments.

[0218] It is understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application-specific integrated circuit (ASIC), electronic circuitry, a processor (e.g., a shared processor, a proprietary processor, or a group processor, etc.) and memory for executing one or more software or firmware programs, integrated logic circuitry, and / or other suitable components supporting the described functions. In an alternative example, those skilled in the art will understand that the device 1000 may specifically be the transmitting end device in the above embodiments, used to execute the various processes and / or steps corresponding to the transmitting end device in the above method embodiments; or, the device 1000 may specifically be the receiving end device in the above embodiments, used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiments. To avoid repetition, further details are omitted here.

[0219] The apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the transmitting device in the above-described method, or the apparatus 1000 of each of the above-described schemes has the function of implementing the corresponding steps performed by the receiving device in the above-described method. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above functions; for example, the communication unit can be replaced by a transceiver (e.g., the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as processing units, can be replaced by a processor, respectively executing the transmission and reception operations and related processing operations in each method embodiment.

[0220] Furthermore, the aforementioned communication unit can also be a transceiver circuit (e.g., it may include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In the embodiments of this application, the device in FIG12 can be the receiving end device or transmitting end device in the foregoing embodiments, or it can be a chip or a chip system, such as a system on chip (SoC). The communication unit can be an input / output circuit or a communication interface; the processing unit is a processor, microprocessor, or integrated circuit integrated on the chip. No limitation is made here.

[0221] Figure 13 is a schematic block diagram of a communication device 1100 provided in an embodiment of this application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other through an internal connection path. The processor 1110 is used to execute instructions to control the transceiver 1120 to send and / or receive signals.

[0222] Optionally, the device 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 stores instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the transmitting device in the above method embodiments. In another possible implementation, the device 1100 is used to implement the various processes and steps corresponding to the receiving device in the above method embodiments.

[0223] Optionally, the memory 1130 may be integrated into the processor 1110.

[0224] In one possible scenario, device 1100 includes at least one processor with integrated memory, and other memory besides the memory integrated on the processor.

[0225] It is understood that the device 1100 can specifically be the transmitting or receiving device in the above embodiments, or it can be a chip or a chip system. Correspondingly, the transceiver 1120 can be the transceiver circuit of the chip, which is not limited here. Specifically, the device 1100 can be used to execute the various steps and / or processes corresponding to the transmitting or receiving device in the above method embodiments.

[0226] Optionally, the memory 1130 may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may include non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be used to execute instructions stored in the memory, and when the processor 1110 executes instructions stored in the memory, the processor 1110 is used to perform the various steps and / or processes of the method embodiments corresponding to the transmitting or receiving devices described above.

[0227] In implementation, each step of the above method can be completed by integrated logic circuits in the processor's hardware or by instructions in software. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware processor, or by a combination of hardware and software modules in the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method. To avoid repetition, detailed descriptions are omitted here.

[0228] It should be noted that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuitry in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor in the embodiments of this application can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0229] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0230] Optionally, the memory (e.g., 1130) in this embodiment may be integrated into the processor (e.g., 1110).

[0231] In addition, this application also provides a computer-readable storage medium storing computer instructions, which, when executed on a computer, cause the operations and / or processes performed by the sending or receiving device in the various method embodiments of this application to be executed.

[0232] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending end device or the receiving end device in the various method embodiments of this application are executed.

[0233] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by a transmitting or receiving device in any method embodiment are performed.

[0234] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0235] In addition, this application also provides a communication system, including the transmitting end device and the receiving end device in the embodiments of this application.

[0236] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0237] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for example, the division of units is merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0238] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0239] It is understood that the term "embodiment" used throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this application. Therefore, various embodiments throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0240] It can also be understood that in this application, "when," "if," and "if" all refer to the network element making corresponding processing under certain objective circumstances, and are not time-limited, nor do they require the network element to make a judgment when it is implemented, nor do they mean that there are other limitations.

[0241] It can also be understood that in the various embodiments of this application, "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it can also be understood that determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

Claims

1. A communication method based on low-density parity-check (LDPC) codes, characterized in that, The method includes: Obtain the information bit sequence; The information bit sequence is encoded according to the LDPC matrix to obtain a codeword sequence. The LDPC matrix is ​​determined based on the LDPC code shift matrix and the boost value Zc. The LDPC code shift matrix includes part or all of a first shift matrix, which includes a first region and a second region. The first region is a matrix obtained by replacing the 1 elements in part or all of the LDPC base matrix with the shift values ​​of those 1 elements. The shift values ​​corresponding to the 1 elements in the LDPC base matrix are determined based on Zc. The first region includes a third region, and the second region includes a fourth region. The first column in the third region and the second column in the fourth region correspond to the same row in the first shift matrix. The second column is any column in the fourth region, and the first column is the column in the third region corresponding to the second column. The first column and the second column satisfy the following characteristics: the difference between the shift value of the i-th row in the first column and the shift value of the i-th row in the second column is modulo a first value to obtain a second value. The first value is a positive integer and is related to Zc. The second value is a non-negative integer.

2. A communication method based on low-density parity-check (LDPC) codes, characterized in that, Obtain the symbol sequence; The symbol sequence is decoded using the LDPC matrix to obtain the information bit sequence. The LDPC matrix is ​​determined based on the LDPC code shift matrix and the boost value Zc. The LDPC code shift matrix includes part or all of a first shift matrix, which includes a first region and a second region. The first region is a matrix obtained by replacing the 1 elements in part or all of the LDPC base matrix with the shift values ​​of those 1 elements. The shift values ​​corresponding to the 1 elements in the LDPC base matrix are determined based on Zc. The first region includes a third region, and the second region includes a fourth region. The first column in the third region and the second column in the fourth region correspond to the same row in the first shift matrix. The second column is any column in the fourth region, and the first column is the column in the third region corresponding to the second column. The first column and the second column satisfy the following characteristics: the difference between the shift value of the i-th row in the first column and the shift value of the i-th row in the second column is modulo a first value to obtain a second value. The first value is a positive integer and is related to Zc. The second value is a non-negative integer.

3. The method according to claim 1 or 2, characterized in that, The rows containing translation values ​​are the same in both the first and second columns.

4. The method according to any one of claims 1 to 3, characterized in that, The first column corresponds to a row number greater than or equal to 4 in the first translation value matrix.

5. The method according to any one of claims 1 to 4, characterized in that, The first value is Or, the first value is the stated Round up or down, where c is a positive integer.

6. The method according to claim 5, characterized in that, The first value is The second value is 0. The translation value of the i-th row in the first column is p 1,i,j The translation value of the i-th row in the second column is q. 1,i,j ,in, Where c is a positive integer, and γ i / c is the value corresponding to the i-th row of the first column, and the γ i It is a non-negative integer less than c.

7. The method according to claim 6, characterized in that, The first column corresponds to 4 rows, c = 4, and the first to fourth rows in the first column correspond to {γ1, γ2, γ3, γ4} = {0, 1, 2, 3} respectively.

8. The method according to any one of claims 1 to 7, characterized in that, The first region corresponds to a first matrix, which is obtained by replacing the values ​​at positions with translation values ​​in the first region with 1 elements and replacing the values ​​at the remaining positions with 0 elements. The first region includes X′ rows and Y′ columns, where... The matrix formed by the x1′+1 to X′ rows and the y2′+1 to Y′ columns of the first matrix is ​​the identity matrix. The matrix formed by the first matrix from row 1 to x1′ and column y2′+1 to Y′ is a matrix of all zeros. The matrix formed by the first matrix from row 1 to x1′ and column y1′+1 to y2′ is a square matrix. Where 1 < x1′ < X′, 1 < y1′ < y2′ < Y′, and x1′, X′, y1′, y2′, and Y′ are all integers.

9. The method according to claim 8, characterized in that, The first region is composed of a fifth region and a sixth region, wherein the sixth region is a region composed of at least one column of the first region, and the third region is a region composed of at least one row of the fifth region.

10. The method according to claim 9, characterized in that, The sixth region is the region formed by columns y2′+1 to Y′ in the first region. or, The sixth region is the region formed by columns y1′+1 to Y′ in the first region.

11. The method according to claim 9 or 10, characterized in that, The first translation value matrix is ​​composed of the fifth region, the second region, and the sixth region, wherein the fifth region and the second region have the same number of rows, the last column of the fifth region is adjacent to the first column of the second region, and the last column of the second region is adjacent to the first column of the sixth region.

12. The method according to claim 11, characterized in that, The fifth region has the same number of columns as the second region.

13. The method according to claim 12, characterized in that, The third region and the fourth region are the same size.

14. The method according to claim 13, characterized in that, The third region is located in the same position as the fourth region in the second region.

15. The method according to any one of claims 1 to 14, characterized in that, The first region further includes a seventh region, and the second region further includes an eighth region. The third column of the seventh region and the fourth column of the eighth region correspond to the same row in the first translation value matrix. The fourth column is any column in the eighth region, and the third column is the column in the seventh region corresponding to the fourth column. The third and fourth columns satisfy the following characteristics: q 2,i,j =p 2,i,j +β i , or q 2,i,j =β i *p 2,i,j , Wherein, the translation value of the i-th row and j-th column in the seventh region is p 2,i,j The translation value of the i-th row and j-th column in the eighth region is q. 2,i,j The β i This is the value corresponding to the i-th row of the third column.

16. The method according to any one of claims 1 to 15, characterized in that, The Zc is greater than or equal to 64.

17. The method according to any one of claims 1 to 16, characterized in that, The translation value of the third region is less than the first value.

18. A communication device, characterized in that, The device includes at least one processor and an interface circuit, the interface circuit being configured to receive signals from other communication devices besides the communication device and transmit them to the processor, or to send signals from the processor to other communication devices besides the communication device, the processor causing the method as described in any one of claims 1 to 17 to be implemented via logic circuits or executing code instructions.

19. The communication device according to claim 18, characterized in that, The communication device is a chip or chip system.

20. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions that, when executed, cause the method as described in any one of claims 1 to 17 to be implemented.

21. A computer program product, characterized in that, Includes a computer program that, when run, causes the method as described in any one of claims 1 to 17 to be implemented.

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