High resolution shadow mask gasket

The integration of a shadow mask gasket with the shadow mask and substrate addresses underspray issues, enabling precise thin film deposition with vertical edges, enhancing manufacturing precision and circuit density in integrated circuits.

WO2026112116A1PCT designated stage Publication Date: 2026-05-28BAE SYSTEMS INFORMATION ANDELECTRONIC SYSTEMS INTEGRATION INC
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Patent Information

Application Number
PCT/US2025/056063
Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-11-22
Filing Date
2025-11-19
Publication Date
2026-05-28

AI Technical Summary

Technical Problem

Existing shadow masks in vapor deposition processes suffer from underspray, leading to low resolution and inefficient use of materials due to imperfect mask engagement, resulting in blurry edges and reduced circuit density.

Method used

The use of a high resolution shadow mask gasket interposed between the shadow mask and substrate, aligning with the mask's apertures to prevent underspray and enable precise deposition of thin film features with vertical side edges.

Benefits of technology

This approach enhances manufacturing precision, reduces electrical shorts and parasitic capacitance, and allows for higher resolution features at higher densities by minimizing underspray, thereby improving the performance and reliability of integrated circuits.

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Abstract

A system, assembly and method of producing an integrated circuit is provided. A shadow mask is adhered to and aligned with a substrate. There is a shadow mask gasket interposed between the shadow mask and the substrate. A thin film material is deposited on the substrate, such as a silicon wafer, through the shadow mask and the shadow mask gasket. The thin film material that is deposited results in a thin film feature having a boundary with a vertical edge.
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