Display panel and display apparatus

Abstract

A display panel and a display apparatus. The display panel comprises a pixel driving circuit and a light-emitting unit (L), wherein the pixel driving circuit comprises a driving transistor (T3), a fourth transistor (T4), a fifth transistor (T5) and a sixth transistor (T6); a first electrode of the fourth transistor is connected to a data line (Data), and a second electrode of the fourth transistor is connected to a gate of the driving transistor; a first electrode of the fifth transistor is connected to a first power supply line (VDD), and a second electrode of the fifth transistor is connected to a first electrode of the driving transistor; a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode of the sixth transistor is connected to a first electrode of the light-emitting unit. The display panel further comprises a base substrate (100), a first active layer and a second active layer, wherein the first active layer is located on one side of the base substrate; the second active layer is located on the side of the first active layer facing away from the base substrate, and the second active layer comprises a third active portion (93), the third active portion being configured to form a channel region of the driving transistor; the channel region of one or more of the fourth transistor, the fifth transistor and the sixth transistor is located in the first active layer. The display panel has a good display effect.

Description

Display panel, display device Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] In related technologies, display panels include pixel driving circuits, which are used to drive light-emitting units to emit light. This application provides a new display panel with a new pixel driving circuit.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, wherein the display panel includes a pixel driving circuit and a light-emitting unit, the pixel driving circuit includes a driving transistor, a fourth transistor, a fifth transistor, and a sixth transistor, the first electrode of the fourth transistor is connected to a data line, the second electrode of the fourth transistor is connected to the gate of the driving transistor, the first electrode of the fifth transistor is connected to a first power line, the second electrode of the fifth transistor is connected to the first electrode of the driving transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the display panel further includes:

[0005] Substrate;

[0006] The first active layer is located on one side of the substrate.

[0007] The second active layer is located on the side of the first active layer away from the substrate. The second active layer includes a third active portion, which is used to form the channel region of the driving transistor.

[0008] The channel regions of one or more of the fourth, fifth, and sixth transistors are located in the first active layer.

[0009] In one exemplary embodiment of this disclosure, the transistor formed by the first active layer is a low-temperature polysilicon transistor, and the transistor formed by the second active layer is an oxide transistor.

[0010] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to a second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit;

[0011] The first active layer includes a fifth active portion, a sixth active portion, and a seventh active portion. The fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor.

[0012] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0013] The first capacitor has a second electrode connected to the second terminal of the driving transistor;

[0014] The second capacitor has its first electrode connected to the first electrode of the first capacitor and its second electrode connected to the gate of the driving transistor.

[0015] A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the gate of the driving transistor;

[0016] The second transistor has its first terminal connected to the first initial signal line and its second terminal connected to the first electrode of the first capacitor.

[0017] The channel regions of the first transistor, the driving transistor, and the fourth transistor are located in the second active layer.

[0018] In one exemplary embodiment of this disclosure, the display panel further includes a first gate line, the first gate line extending along a first direction by an orthographic projection on the substrate, and at least a portion of the structure of the first gate line being used to form the gate of the fourth transistor;

[0019] The second active layer includes a first main active portion, a second main active portion, and a third main active portion. The orthographic projections of the first main active portion, the second main active portion, and the third main active portion on the substrate extend along a second direction and are spaced apart along a first direction. The second direction intersects with the first direction.

[0020] The first main active portion includes a first active portion and a fourth active portion connected in the same layer. The orthographic projections of the first active portion and the fourth active portion on the substrate are distributed at intervals along the second direction. The first active portion is used to form the channel region of the first transistor, and the fourth active portion is used to form the channel region of the fourth transistor.

[0021] The second main active portion includes the third active portion, and the third main active portion includes the second active portion, which is used to form the channel region of the second transistor.

[0022] In one exemplary embodiment of this disclosure, the display panel further includes a third reset signal line, the orthographic projection of the third reset signal line on the substrate extending along a first direction, and at least a portion of the structure of the third reset signal line being used to form the gate of the seventh transistor;

[0023] The first active layer includes a fourth main active portion and a fifth main active portion, wherein the orthographic projections of the fourth main active portion and the fifth main active portion on the substrate extend along a second direction and are spaced apart along the second direction;

[0024] The fourth main active portion includes a fifth active portion, which is used to form the channel region of the fifth transistor;

[0025] The fifth main active portion includes a sixth active portion and a seventh active portion connected in the same layer. The orthographic projections of the sixth active portion and the seventh active portion on the substrate are distributed at intervals along a second direction. The sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor.

[0026] In one exemplary embodiment of this disclosure, the first active layer includes a fourth active portion, which is used to form the channel region of the fourth transistor.

[0027] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0028] The first capacitor has a second electrode connected to the second terminal of the driving transistor;

[0029] The second capacitor has its first electrode connected to the first electrode of the first capacitor and its second electrode connected to the gate of the driving transistor.

[0030] A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the gate of the driving transistor;

[0031] The second transistor has its first terminal connected to the first initial signal line and its second terminal connected to the first electrode of the first capacitor.

[0032] A seventh transistor, wherein the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit;

[0033] The channel regions of the first transistor, the driving transistor, the fifth transistor, the sixth transistor, and the seventh transistor are located in the second active layer.

[0034] In one exemplary embodiment of this disclosure, the display panel further includes a third reset signal line, the orthographic projection of the third reset signal line on the substrate extending along a first direction, and at least a portion of the structure of the third reset signal line being used to form the gate of the seventh transistor;

[0035] The second active layer includes a first main active portion, a second main active portion, and a third main active portion. The orthographic projections of the first main active portion, the second main active portion, and the third main active portion on the substrate extend along a second direction and are spaced apart along a first direction. The second direction intersects with the first direction.

[0036] The first main active portion includes a first active portion, which is used to form the channel region of the first transistor;

[0037] The second main active portion includes a fifth active portion, a third active portion, a sixth active portion, and a seventh active portion connected in the same layer. The orthographic projections of the fifth active portion, the third active portion, the sixth active portion, and the seventh active portion on the substrate are distributed sequentially along a second direction. The fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor.

[0038] The third main active portion includes a second active portion, which is used to form the channel region of the second transistor.

[0039] In one exemplary embodiment of this disclosure, the display panel further includes:

[0040] A first enable signal line extends along a first direction in its orthogonal projection onto the substrate, and at least a portion of the structure of the first enable signal line is used to form the gate of the fifth transistor.

[0041] A first gate line, whose orthogonal projection on the substrate extends along the first direction, wherein at least a portion of the structure of the first gate line is used to form the gate of the fourth transistor;

[0042] A fourth conductive portion, which is used to form the gate of the driving transistor;

[0043] In the same pixel driving circuit, the orthogonal projection of the first gate line on the substrate is located between the orthogonal projection of the first enable signal line on the substrate and the orthogonal projection of the fourth conductive part on the substrate.

[0044] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first transistor, the first terminal of which is connected to a first initial signal line, and the second terminal of which is connected to the gate of the driving transistor.

[0045] The display panel also includes:

[0046] A first gate line, whose orthogonal projection on the substrate extends along the first direction, wherein at least a portion of the structure of the first gate line is used to form the gate of the fourth transistor;

[0047] A first reset signal line extends along a first direction in the orthographic projection on the substrate, and at least a portion of the structure of the first reset signal line is used to form the gate of the first transistor.

[0048] A fourth conductive portion, which is used to form the gate of the driving transistor;

[0049] A second enable signal line extends along the first direction in its orthogonal projection onto the substrate, and at least a portion of the structure of the second enable signal line is used to form the gate of the sixth transistor.

[0050] In the same pixel driving circuit, the orthographic projection of the second enable signal line on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the fourth conductive part on the substrate, and the orthographic projection of the second enable signal line on the substrate is located on the side of the orthographic projection of the fourth conductive part on the substrate that is away from the orthographic projection of the first gate line on the substrate.

[0051] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a first capacitor, a second capacitor, a first transistor, a second transistor, and a seventh transistor. The first electrode of the first capacitor and the first electrode of the second capacitor are connected. The second electrode of the first capacitor is connected to the second electrode of the driving transistor. The second electrode of the second capacitor is connected to the gate of the driving transistor. The first electrode of the first transistor is connected to a first initial signal line. The second electrode of the first transistor is connected to the gate of the driving transistor. The first electrode of the second transistor is connected to the first initial signal line. The second electrode of the second transistor is connected to the first electrode of the first capacitor. The first electrode of the seventh transistor is connected to a second initial signal line. The second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit.

[0052] The display panel also includes:

[0053] A first reset signal line extends along a first direction in the orthographic projection on the substrate, and at least a portion of the structure of the first reset signal line is used to form the gate of the first transistor.

[0054] The second reset signal line extends along a first direction in the orthogonal projection on the substrate, and at least a portion of the structure of the second reset signal line is used to form the gate of the second transistor.

[0055] A third reset signal line, the orthogonal projection of the third reset signal line on the substrate extending along the first direction, and at least a portion of the structure of the third reset signal line being used to form the gate of the seventh transistor;

[0056] A fourth conductive portion, which is used to form the gate of the driving transistor;

[0057] In the same pixel driving circuit, the orthogonal projection of the third reset signal line on the substrate is located on the side where the orthogonal projection of the second reset signal line on the substrate is away from the orthogonal projection of the fourth conductive part on the substrate, and the orthogonal projection of the second reset signal line on the substrate is located on the side where the orthogonal projection of the first reset signal line on the substrate is away from the orthogonal projection of the fourth conductive part on the substrate.

[0058] In an exemplary embodiment of this disclosure, the pixel driving circuit further includes a first capacitor, a second capacitor, a first transistor, and a second transistor. The first electrode of the first transistor is connected to a first initial signal line, and the second electrode of the first transistor is connected to the gate of the driving transistor. The first electrode of the first capacitor and the first electrode of the second capacitor are connected. The second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The first electrode of the second transistor is connected to the first initial signal line, and the second electrode of the second transistor is connected to the first electrode of the first capacitor. The gate of the second transistor is connected to a second reset signal line, and the orthogonal projection of the second reset signal line on the substrate extends along a first direction.

[0059] In a first direction, the orthographic projections of the channel region of the fifth transistor, the sixth transistor, and the seventh transistor on the substrate are located between the orthographic projections of the channel region of the first transistor and the second transistor on the substrate.

[0060] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a first capacitor and a second capacitor, a first electrode of the first capacitor is connected to a first electrode of the second capacitor, a second electrode of the first capacitor is connected to a second electrode of the driving transistor, and a second electrode of the second capacitor is connected to the gate of the driving transistor.

[0061] The display panel also includes:

[0062] A first gate layer is located between the substrate and the second active layer. The first gate layer includes a first conductive portion. A portion of the structure of the first conductive portion is used to form a first electrode of the first capacitor, and a portion of the structure of the first conductive portion is used to form a first electrode of the second capacitor.

[0063] A second gate layer is located between the first gate layer and the second active layer. The second gate layer includes a second conductive portion and a third conductive portion. The orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The second conductive portion is used to form the second electrode of the second capacitor. The orthographic projection of the third conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The third conductive portion is used to form the second electrode of the first capacitor.

[0064] The orthographic projections of the second conductive portion and the third conductive portion on the substrate are distributed along a second direction.

[0065] In one exemplary embodiment of this disclosure, the display panel further includes:

[0066] A first enable signal line extends along a first direction in its orthographic projection on the substrate, and at least a portion of the structure of the first enable signal line is used to form the gate of the fifth transistor, wherein the first direction and the second direction intersect.

[0067] A second enable signal line extends along a first direction in its orthogonal projection on the substrate, and at least a portion of the structure of the second enable signal line is used to form the gate of the sixth transistor.

[0068] In the same pixel driving circuit, the orthographic projections of the second conductive part and the third conductive part on the substrate are located between the orthographic projections of the first enable signal line on the substrate and the orthographic projections of the second enable signal line on the substrate.

[0069] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a first capacitor and a second capacitor, a first electrode of the first capacitor is connected to a first electrode of the second capacitor, a second electrode of the first capacitor is connected to a second electrode of the driving transistor, and a second electrode of the second capacitor is connected to the gate of the driving transistor.

[0070] The display panel also includes:

[0071] A second gate layer is located between the first active layer and the second active layer. The second gate layer includes a third conductive portion, which is used to form the second electrode of the first capacitor.

[0072] Wherein, the orthographic projection of the third conductive part on the substrate and the orthographic projection of the third active part on the substrate at least partially overlap.

[0073] In one exemplary embodiment of this disclosure, the gate of the fifth transistor is connected to a first enable signal line, the gate of the sixth transistor is connected to a second enable signal line, and the gate of the fourth transistor is connected to a first gate line.

[0074] The pixel driving circuit also includes:

[0075] The first capacitor has a second electrode connected to the second terminal of the driving transistor;

[0076] The second capacitor has its first electrode connected to the first electrode of the first capacitor and its second electrode connected to the gate of the driving transistor.

[0077] A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the gate of the driving transistor, and the gate is connected to a first reset signal line;

[0078] The second transistor has its first terminal connected to the first initial signal line, its second terminal connected to the first electrode of the first capacitor, and its gate connected to the second reset signal line.

[0079] The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the third reset signal line.

[0080] The display panel also includes:

[0081] Multiple grid lines, at least some of which include grid line segments extending along a first direction and spaced apart along the first direction;

[0082] The first enable signal line, the second enable signal line, the first gate line, the first reset signal line, the second reset signal line, and the third reset signal line form the gate line.

[0083] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes:

[0084] The first capacitor has a second electrode connected to the second terminal of the driving transistor;

[0085] The second capacitor has its first electrode connected to the first electrode of the first capacitor and its second electrode connected to the gate of the driving transistor.

[0086] A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the gate of the driving transistor, and the gate is connected to a first reset signal line;

[0087] The second transistor has its first terminal connected to the first initial signal line, its second terminal connected to the first electrode of the first capacitor, and its gate connected to the second reset signal line.

[0088] The display panel further includes a first gate driving circuit, which includes multiple cascaded shift register units. The first reset signal line and the second reset signal line are connected to different shift register units in the first gate driving circuit.

[0089] In one exemplary embodiment of this disclosure, the gate of the fifth transistor is connected to a first enable signal line, and the gate of the sixth transistor is connected to a second enable signal line.

[0090] The display panel further includes a second gate driving circuit, which includes multiple cascaded shift register units. The first enable signal line and the second enable signal line are connected to different shift register units in the second gate driving circuit.

[0091] In one exemplary embodiment of this disclosure, the gate of the fourth transistor is connected to the first gate line;

[0092] The pixel driving circuit also includes:

[0093] The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the third reset signal line.

[0094] The display panel further includes a third gate driving circuit, which includes multiple cascaded shift register units. The first gate line and the third reset signal line are connected to different shift register units in the same gate driving circuit.

[0095] According to one aspect of this disclosure, a display device is provided, wherein the display device includes the display panel described above.

[0096] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0097] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0098] Figure 1 is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0099] Figure 2 is a timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 1;

[0100] Figure 3 is a timing diagram of the driving method in an exemplary embodiment of the pixel driving circuit of this disclosure;

[0101] Figure 4 is a timing diagram of the driving method in an exemplary embodiment of the pixel driving circuit of this disclosure;

[0102] Figure 5 is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure;

[0103] Figure 6 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0104] Figure 7 shows the structural layout of the first active layer in Figure 6;

[0105] Figure 8 is a structural layout of the first gate layer in Figure 6;

[0106] Figure 9 is a structural layout of the second gate layer in Figure 6;

[0107] Figure 10 shows the structural layout of the second active layer in Figure 6;

[0108] Figure 11 is a structural layout of the third gate layer in Figure 6;

[0109] Figure 12 is a structural layout of the first source / drain layer in Figure 6;

[0110] Figure 13 is a structural layout of the second source / drain layer in Figure 6;

[0111] Figure 14 is a structural layout of the first active layer and the first gate layer in Figure 6;

[0112] Figure 15 is a structural layout of the first active layer, the first gate layer, and the second gate layer in Figure 6;

[0113] Figure 16 is a structural layout of the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 6;

[0114] Figure 17 is a structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 6.

[0115] Figure 18 is a structural layout of the first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source / drain layer in Figure 6;

[0116] Figure 19 is a partial cross-sectional view of the display panel shown in Figure 5, cut along the dashed line AA;

[0117] Figure 20 is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0118] Figure 21 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure;

[0119] Figure 22 is the structural layout of the first active layer in Figure 21;

[0120] Figure 23 is a structural layout of the first gate layer in Figure 21;

[0121] Figure 24 is a structural layout of the second gate layer in Figure 21;

[0122] Figure 25 shows the structural layout of the second active layer in Figure 21;

[0123] Figure 26 is a structural layout of the third gate layer in Figure 21;

[0124] Figure 27 is a structural layout of the first source / drain layer in Figure 21;

[0125] Figure 28 is the structural layout of the second source / drain layer in Figure 21;

[0126] Figure 29 is a structural layout of the first active layer and the first gate layer in Figure 21;

[0127] Figure 30 is a structural layout of the first active layer, the first gate layer, and the second gate layer in Figure 21;

[0128] Figure 31 is a structural layout of the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 21;

[0129] Figure 32 is a structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 21;

[0130] Figure 33 is a structural layout of the first active layer, first gate layer, second gate layer, second active layer, third gate layer, and first source / drain layer in Figure 21;

[0131] Figure 34 is a partial cross-sectional view of the display panel shown in Figure 21, cut along the dashed line BB.

[0132] Figure 35 is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0133] Figure 36 is a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0134] Figure 37 is a timing diagram of a driving method for the pixel driving circuit shown in Figure 36;

[0135] Figure 38 is a schematic diagram of the structure of another exemplary embodiment of the pixel driving circuit of this disclosure;

[0136] Figure 39 is a timing diagram of one driving method for the pixel driving circuit shown in Figure 38. Detailed Implementation

[0137] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0138] The terms “a,” “one,” and “” are used to indicate the existence of one or more elements / components / etc.; the terms “include” and “have” are used to indicate an open-ended meaning of inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0139] Figure 1 shows a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure. The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2. The gate of the driving transistor T3 is connected to a first node N1, and its second terminal is connected to a third node N3. The first terminal of the first transistor T1 is connected to a first initial signal terminal Vinit1, its second terminal is connected to the first node N1, and its gate is connected to a first reset signal terminal Re1. The first terminal of the second transistor T2 is connected to the first initial signal terminal Vinit1, its second terminal is connected to the second node N2, and its gate is connected to a second reset signal terminal Re2. The first terminal of the fourth transistor T4 is connected to a data signal terminal Data, its second terminal is connected to the first node N1, and its gate is connected to a first gate driving signal terminal G1. The first terminal of the fifth transistor T5 is connected to a first power supply terminal. VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first enable signal terminal EM1; the first electrode of the sixth transistor T6 is connected to the third node N3, the second electrode is connected to the first electrode of the light-emitting unit L, and the gate is connected to the second enable signal terminal EM2; the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the first electrode of the light-emitting unit L, and the gate is connected to the third reset signal terminal Re3; the first electrode of the first capacitor C1 is connected to the second node N2, and the second electrode is connected to the third node N3; the first electrode of the second capacitor C2 is connected to the second node N2, and the second electrode is connected to the first node N1. The second electrode of the light-emitting unit L is connected to the second power supply terminal VSS.

[0140] In this exemplary embodiment, the driving transistor T3, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be oxide transistors. For example, the driving transistor T3, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be N-type metal-oxide transistors.

[0141] Figure 2 shows the timing diagram of each node in a driving method of the pixel driving circuit shown in Figure 1. G1 represents the timing diagram of the first gate driving signal terminal, Re1 represents the timing diagram of the first reset signal terminal, Re2 represents the timing diagram of the second reset signal terminal, Re3 represents the timing diagram of the third reset signal terminal, EM1 represents the timing diagram of the first enable signal terminal EM1, and EM2 represents the timing diagram of the second enable signal terminal EM2.

[0142] The driving method of the pixel driving circuit may include a first reset stage t1, a second reset stage t2, a threshold compensation stage t3, a data writing stage t4, and a light emission stage t5.

[0143] In the first reset phase t1:

[0144] The first enable signal terminal EM1 and the second enable signal terminal EM2 output low-level signals, the fifth transistor T5 and the sixth transistor T6 are turned off, the first reset signal terminal Re1 and the third reset signal terminal Re3 output high-level signals, the first transistor T1 and the seventh transistor T7 are turned on, the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1, and the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit L.

[0145] Second reset phase t2:

[0146] The first reset signal terminal Re1, the second reset signal terminal Re2, the third reset signal terminal Re3, and the second enable signal terminal EM2 output high-level signals. The first transistor T1, the second transistor T2, the seventh transistor T7, and the sixth transistor T6 are turned on. The second initial signal terminal Vinit2 inputs the second initial signal to the third node N3 through the sixth transistor T6.

[0147] In the threshold compensation phase t3:

[0148] The first enable signal terminal EM1, the first reset signal terminal Re1, and the second reset signal terminal Re2 output high level. The fifth transistor T5, the first transistor T1, and the second transistor T2 are turned on. The first initial signal terminal Vinit1 inputs the first initial signal to the first node N1 and the second node N2. The first power supply terminal VDD inputs the compensation Vdd-Vth to the third node N3 through the fifth transistor T5 and the driving transistor T3, where Vdd is the voltage of the first power supply terminal and Vth is the threshold voltage of the driving transistor.

[0149] During data writing phase t4:

[0150] The second reset signal terminal Re2 and the first gate drive signal terminal G1 output high-level signals, the second transistor T2 and the fourth transistor T4 are turned on, and the data signal terminal Data inputs the data signal Vdata to the first node N1.

[0151] During the luminescence stage t5:

[0152] The first enable signal terminal EM1 and the second enable signal terminal EM2 output high-level signals, driving transistor T3 to drive the light-emitting unit L to emit light. The formula for the output current of the driving transistor is as follows: I=(μWCox / 2L)(Vgs-Vth) 2

[0153] Where I is the output current of the driving transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; and Vgs is the gate-source voltage difference of the driving transistor. In the pixel driving circuit described above, the output current of the driving transistor is I = (μWCox / 2L)(Vdata - (Vdd - Vth) - Vth). 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0154] Figure 3 shows a timing diagram of the driving method in an exemplary embodiment of the pixel driving circuit of this disclosure. During the light-emitting stage t5, the display panel can control the brightness of the light-emitting unit by controlling the frequency and duration of the high-level signal pulses output by the first enable signal terminal EM1. Accordingly, the display panel requires the fifth transistor T5 to have a high response speed. It should be understood that in other exemplary embodiments, the display panel can also control the brightness of the light-emitting unit by controlling the frequency and duration of the high-level signal pulses output by the first enable signal terminal EM1 and / or the second enable signal terminal EM2. Accordingly, the fifth transistor T5 and the sixth transistor T6 need to have high response speeds.

[0155] Figure 4 shows a timing diagram of the driving method in an exemplary embodiment of the pixel driving circuit of this disclosure. The display panel driving method may include a scan frame Hs and a hold frame Hb. The scan frame Hs includes the first reset stage t1, the second reset stage t2, the threshold compensation stage t3, the data writing stage t4, and the light emission stage t5 shown in Figure 2. The hold frame Hb includes a black insertion stage t6 and a light emission stage t5. In the black insertion stage t6, the first enable signal terminal EM1 and the second enable signal terminal EM2 output low-level signals, and the third reset signal terminal Re3 outputs a high-level signal; the light emission unit does not emit light. Accordingly, the seventh transistor T7 in this display panel needs to have a high response speed.

[0156] Based on this, this exemplary embodiment provides a pixel driving circuit, as shown in FIG5, which is a schematic diagram of an exemplary embodiment of the pixel driving circuit of this disclosure. Compared with the pixel driving circuit shown in FIG1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor in the pixel driving circuit shown in FIG5 can be low-temperature polysilicon transistors. Low-temperature polysilicon transistors have higher carrier mobility, and correspondingly, the fifth transistor T5, the sixth transistor T6, and the seventh transistor have higher response speed. This pixel driving circuit can improve the display effect in the driving methods shown in FIG3 and FIG4. The fifth transistor T5, the sixth transistor T6, and the seventh transistor can be P-type low-temperature polysilicon transistors.

[0157] This exemplary embodiment also provides a display panel, which may include a substrate, a first active layer, a first gate layer, a second gate layer, a second active layer, a third gate layer, a first source / drain layer, and a second source / drain layer stacked sequentially, with an insulating layer disposed between the aforementioned layers.

[0158] As shown in Figures 6-18, Figure 6 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 7 is a structural layout diagram of the first active layer in Figure 6; Figure 8 is a structural layout diagram of the first gate layer in Figure 6; Figure 9 is a structural layout diagram of the second gate layer in Figure 6; Figure 10 is a structural layout diagram of the second active layer in Figure 6; Figure 11 is a structural layout diagram of the third gate layer in Figure 6; Figure 12 is a structural layout diagram of the first source / drain layer in Figure 6; Figure 13 is a structural layout diagram of the second source / drain layer in Figure 6; and Figure 14 is a structural layout diagram of the first active layer in Figure 6. The structural layout of the first gate layer is shown in Figure 15, which is the structural layout of the first active layer, the first gate layer, and the second gate layer in Figure 6. The structural layout of the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 6 is shown in Figure 16. The structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 6 is shown in Figure 17. The structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in Figure 6 is shown in Figure 18.

[0159] The display panel may include multiple pixel driving circuits as shown in Figure 5. The multiple pixel driving circuits may be distributed in an array along the first direction X and the second direction Y. The first direction X and the second direction Y may intersect, for example, the first direction X and the second direction Y may be perpendicular.

[0160] As shown in Figures 6, 7, and 14, the first active layer may include: a fourth main active portion 074 and a fifth main active portion 075. The orthographic projections of the fourth main active portion 074 and the fifth main active portion 075 onto the substrate extend along the second direction Y and are spaced apart along the second direction Y. The fourth main active portion 074 includes: a fifth active portion 75, an eleventh active portion 711, and a twelfth active portion 712. The fifth main active portion 075 includes: a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, and a tenth active portion 710. The fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 is connected to the side of the sixth active portion 76 away from the seventh active portion 77; the ninth active portion 79 is connected to the side of the seventh active portion 77 away from the sixth active portion 76; the tenth active portion 710 is connected between the sixth active portion 76 and the seventh active portion 77; the eleventh active portion 711 and the twelfth active portion 712 are connected to both ends of the fifth active portion 75. The first active layer can be formed of polycrystalline silicon material, and correspondingly, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0161] As shown in Figures 6, 8, and 14, the first gate layer may include: a first enable signal line EM1, a second enable signal line EM2, a third reset signal line Re3, and a first conductive portion 11. The orthogonal projections of the first enable signal line EM1, the second enable signal line EM2, and the third reset signal line Re3 onto the substrate may extend along a first direction X. The first enable signal line EM1 provides the first enable signal terminal in FIG5. The orthographic projection of the first enable signal line EM1 on the substrate covers the orthographic projection of the fifth active part 75 on the substrate. A portion of the structure of the first enable signal line EM1 is used to form the gate of the fifth transistor. The second enable signal line EM2 provides the second enable signal terminal in FIG5. The orthographic projection of the second enable signal line EM2 on the substrate covers the orthographic projection of the sixth active part 76 on the substrate. A portion of the structure of the second enable signal line EM2 is used to form the gate of the sixth transistor. The third reset signal line Re3 provides the third reset signal terminal in FIG5. The orthographic projection of the third reset signal line Re3 on the substrate covers the orthographic projection of the seventh active part 77 on the substrate. A portion of the structure of the third reset signal line Re3 is used to form the gate of the seventh transistor. A portion of the structure of the first conductive part 11 is used to form the first electrode of the first capacitor C1, and a portion of the structure of the first conductive part 11 is used to form the first electrode of the second capacitor C2. The display panel can use the first gate layer as a mask to conduct the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductor structure.

[0162] As shown in Figures 6, 9, and 15, the second gate layer may include: a second gate line 2G1, a fourth reset signal line 2Re1, a fifth reset signal line 2Re2, a second conductive portion 22, and a third conductive portion 23. The second gate line 2G1 provides the first gate drive signal terminal in Figure 5, the fourth reset signal line 2Re1 provides the first reset signal terminal in Figure 5, and the fifth reset signal line 2Re2 provides the second reset signal terminal in Figure 5. Specifically, the second gate line 2G1 includes second gate line segments 2G11 spaced apart and extending along the first direction X; the fourth reset signal line 2Re1 includes fourth reset signal line segments 2Re11 spaced apart and extending along the first direction X; and the fifth reset signal line 2Re2 includes fifth reset signal line segments 2Re21 spaced apart and extending along the first direction X. The orthographic projection of the second conductive portion 22 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate at least partially overlap, and the second conductive portion 22 is used to form the second electrode of the second capacitor C2; the orthographic projection of the third conductive portion 23 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate at least partially overlap, and the third conductive portion 23 is used to form the second electrode of the first capacitor C1.

[0163] As shown in Figures 6, 10, and 16, the second active layer may include a first main active portion 091, a second main active portion 092, and a third main active portion 093. The orthographic projections of the first main active portion 091, the second main active portion 092, and the third main active portion 093 onto the substrate extend along the second direction Y and are spaced apart along the first direction X. The first main active portion 091 includes: a first active portion 91, a fourth active portion 94, a fourteenth active portion 914, a fifteenth active portion 915, a sixteenth active portion 916, and a twentieth active portion 920; the second main active portion 092 includes: a third active portion 93, a seventeenth active portion 917, and an eighteenth active portion 918; the third main active portion 093 includes: a second active portion 92, a thirteenth active portion 913, and a nineteenth active portion 919. The first active portion 91 is used to form the channel region of the first transistor T1; the second active portion 92 is used to form the channel region of the second transistor T2; the third active portion 93 is used to form the channel region of the driving transistor T3; the fourth active portion 94 is used to form the channel region of the fourth transistor T4; the thirteenth active portion 913 and the nineteenth active portion 919 are connected to the two ends of the second active portion 92; the fourteenth active portion 914 is connected to the end of the first active portion 91 away from the fourth active portion 94; the fifteenth active portion 915 is connected between the first active portion 91 and the fourth active portion 94; the twentieth active portion 920 is connected between the fifteenth active portion 915 and the fourth active portion 94; the sixteenth active portion 916 is connected to the end of the fourth active portion 94 away from the first active portion 91; the seventeenth active portion 917 and the eighteenth active portion 918 are connected to the two ends of the third active portion 93. The second active layer can be formed of indium gallium zinc oxide, and correspondingly, the first transistor, the second transistor, the driving transistor, and the fourth transistor can be N-type metal oxide thin film transistors.

[0164] As shown in Figures 6, 10, and 16, the orthographic projection of the second gate segment 2G11 on the substrate covers the orthographic projection of the fourth active portion 94 on the substrate, and at least a portion of the structure of the second gate segment 2G11 is used to form the bottom gate of the fourth transistor T4; the orthographic projection of the fourth reset signal segment 2Re11 on the substrate covers the orthographic projection of the first active portion 91 on the substrate, and at least a portion of the structure of the fourth reset signal segment 2Re11 is used to form the bottom gate of the first transistor T1; the orthographic projection of the fifth reset signal segment 2Re21 on the substrate covers the orthographic projection of the second active portion 92 on the substrate, and at least a portion of the structure of the fifth reset signal segment 2Re21 is used to form the bottom gate of the second transistor T2.

[0165] As shown in Figures 6, 11, and 17, the third gate layer may include: a first gate line 3G1, a first reset signal line 3Re1, a second reset signal line 3Re2, and a fourth conductive portion 34. The first gate line 3G1 provides the first gate drive signal terminal in Figure 5, the first reset signal line 3Re1 provides the first reset signal terminal in Figure 5, and the second reset signal line 3Re2 provides the second reset signal terminal in Figure 5. Specifically, the first gate line 3G1 includes first gate line segments 3G11 spaced apart and extending along the first direction X; the first reset signal line 3Re1 includes first reset signal line segments 3Re11 spaced apart and extending along the first direction X; and the second reset signal line 3Re2 includes second reset signal line segments 3Re21 spaced apart and extending along the first direction X. The orthographic projection of the first gate segment 3G11 on the substrate covers the orthographic projection of the fourth active portion 94 on the substrate, and at least a portion of the structure of the first gate segment 3G11 is used to form the top gate of the fourth transistor T4; the orthographic projection of the first reset signal segment 3Re11 on the substrate covers the orthographic projection of the first active portion 91 on the substrate, and at least a portion of the structure of the first reset signal segment 3Re11 is used to form the top gate of the first transistor T1; the orthographic projection of the second reset signal segment 3Re21 on the substrate covers the orthographic projection of the second active portion 92 on the substrate, and at least a portion of the structure of the second reset signal segment 3Re21 is used to form the top gate of the second transistor T2. The orthographic projection of the fourth conductive portion 34 on the substrate covers the orthographic projection of the third active portion 93 on the substrate, and at least a portion of the structure of the fourth conductive portion 34 is used to form the top gate of the driving transistor T3. The display panel can use the third gate layer as a mask to conduct the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductor structure.

[0166] As shown in Figures 6, 12, and 18, the first source / drain layer may include: a first power supply line VDD, a first reset connection line 4Re1, a second reset connection line 4Re2, a first gate connection line 4G1, a first initial signal line Vinit1, a second initial signal line Vinit2, a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, and a seventh bridging portion 47. The orthogonal projections of the first power supply line VDD, the first reset connection line 4Re1, the second reset connection line 4Re2, the first gate connection line 4G1, the first initial signal line Vinit1, and the second initial signal line Vinit2 onto the substrate may extend along a first direction X.

[0167] As shown in Figures 6, 12, and 18, the first power line VDD provides the first power terminal in Figure 5. The first power line VDD can be connected to the twelfth active part 712 via vias to connect to the first terminal of the fifth transistor T5. The first reset connection line 4Re1 can be connected to multiple first reset signal segments 3Re11 in the same first reset signal line via vias. Simultaneously, the first reset connection line 4Re1 can be connected to multiple fourth reset signal segments 2Re11 in the same fourth reset signal line via vias. The second reset connection line 4Re2 can be connected to multiple second reset signal segments 3Re21 in the same second reset signal line via vias. Simultaneously, the first reset connection line 4Re1 can be connected to multiple fifth reset signal segments 2Re21 in the same fifth reset signal line via vias. The first gate connection line 4G1 can be connected to multiple first gate segments 3G11 in the same first gate line via vias. Simultaneously, the first gate connection line 4G1 can be connected to multiple second gate segments 2G11 in the same second gate line via vias. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in FIG5. The first initial signal line Vinit1 can be connected to the fourteenth active part 914 and the nineteenth active part 919 through vias, respectively, to connect the first initial signal terminal to the first terminal of the first transistor T1 and the first terminal of the second transistor T2. The second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG5. The second initial signal line Vinit2 can be connected to the ninth active part 79 through vias, to connect the second initial signal terminal to the first terminal of the seventh transistor T7.

[0168] As shown in Figures 6, 12, and 18, the first bridging portion 41 can be connected to the sixteenth active portion 916 via vias to connect to the first electrode of the fourth transistor T4. The second bridging portion 42 can be connected to the seventeenth active portion 917 and the eleventh active portion 711 via vias to connect to the second electrode of the fifth transistor T5 and the first electrode of the driving transistor T3. The third bridging portion 43 can be connected to the twentieth active portion 920 and the second conductive portion 22 via vias to connect to the second electrode of the fourth transistor T4 and the second electrode of the second capacitor C2. The fourth bridging portion 44 can be connected to the fifteenth active portion 915 and the fourth conductive portion 34 via vias to connect to the second electrode of the first transistor T1 and the gate of the driving transistor T3. The fifth bridging portion 45 can be connected to the thirteenth active portion 913 and the first conductive portion 11 via vias to connect to the second electrode of the second transistor T2 and the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2. The sixth bridging section 46 can be connected to the third conductive section 23, the nineteenth active section 919, and the eighth active section 78 via vias, respectively, to connect the second electrode of the driving transistor T3, the first electrode of the sixth transistor T6, and the second electrode of the first capacitor C1. The seventh bridging section 47 is connected to the tenth active section 710 via vias, to connect the second electrode of the sixth transistor T6, and the seventh bridging section 47 is used to connect the first electrode of the light-emitting unit.

[0169] As shown in Figures 6 and 13, the second source / drain layer includes: a data line Da, a second power line VSS, a signal connection line Lx, and an eighth bridging portion 58. The orthogonal projections of the data line Da, the second power line VSS, and the signal connection line Lx on the substrate extend along the second direction Y. The data line Da provides the data signal terminal shown in Figure 5. The data line Da can be connected to the first bridging portion 41 via a via to connect the data signal terminal and the first electrode of the fourth transistor T4. The second power line VSS provides the second power terminal shown in Figure 5. The second power line VSS can be connected to the common cathode in the display panel to reduce the voltage difference of the second power terminal at different locations on the display panel. The common cathode in the display panel is used to form the cathode of the light-emitting unit. The common cathode can be located on the side of the light-emitting unit L facing away from the substrate. The eighth bridging portion 58 can be connected to the seventh bridging portion 47 via a via. The signal connection line Lx can be any one of the first initial connection line, the second initial connection line, and the first power connection line. The first initial connection line can be connected to the intersecting first initial signal line via a via, the second initial connection line can be connected to the intersecting second initial signal line via a via, and the first power connection line can be connected to the intersecting first power line via a via. Each column of pixel driving circuits can be provided with one signal connection line Lx, and the display panel can be provided with multiple signal connection lines Lx. Some signal connection lines Lx can form the first initial connection line, some signal connection lines Lx can form the second initial connection line, and some signal connection lines Lx can form the first power connection line. For example, the orthographic projections of the first initial connection line, the second initial connection line, and the first power connection line on the substrate can be alternately distributed along the row direction.

[0170] Figure 19 shows a partial cross-sectional view of the display panel shown in Figure 5, cut along the dashed line AA. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a first dielectric layer 105, a passivation layer 106, and a first planarization layer 107. The substrate 100, the first active layer, the first insulating layer 101, the first gate layer, the second insulating layer 102, the second gate layer, the third insulating layer 103, the second active layer, the fourth insulating layer 104, the third gate layer, the first dielectric layer 105, the first source / drain layer, the passivation layer 106, the first planarization layer 107, and the second source / drain layer are sequentially stacked. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be single-layer or multi-layer structures, and the materials of the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 105 can be a silicon nitride layer; the material of the first planarization layer 107 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 106 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of any one of the first and second source / drain layers can be less than the sheet resistance of any one of the first, second, and third gate layers.

[0171] Figure 20 shows a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure. Compared with the pixel driving circuit shown in Figure 1, the fourth transistor T4 in the pixel driving circuit shown in Figure 20 is a low-temperature polysilicon transistor (LTPS). LPS transistors have higher carrier mobility, and correspondingly, the fourth transistor T4 has a higher response speed. This configuration can improve the write speed of data line signals. The fourth transistor T4 can be a P-type LPS transistor.

[0172] As shown in Figures 21-33, Figure 21 is a structural layout diagram of an exemplary embodiment of the display panel of this disclosure; Figure 22 is a structural layout diagram of the first active layer in Figure 21; Figure 23 is a structural layout diagram of the first gate layer in Figure 21; Figure 24 is a structural layout diagram of the second gate layer in Figure 21; Figure 25 is a structural layout diagram of the second active layer in Figure 21; Figure 26 is a structural layout diagram of the third gate layer in Figure 21; Figure 27 is a structural layout diagram of the first source / drain layer in Figure 21; Figure 28 is a structural layout diagram of the second source / drain layer in Figure 21; and Figure 29 is a structural layout diagram of the first source / drain layer in Figure 21. Figure 30 shows the structural layout of the first active layer and the first gate layer in Figure 21. Figure 31 shows the structural layout of the first active layer, the first gate layer, the second gate layer, and the second active layer in Figure 21. Figure 32 shows the structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, and the third gate layer in Figure 21. Figure 33 shows the structural layout of the first active layer, the first gate layer, the second gate layer, the second active layer, the third gate layer, and the first source / drain layer in Figure 21.

[0173] The display panel may include multiple pixel driving circuits as shown in FIG20. The multiple pixel driving circuits may be distributed in an array along the first direction X and the second direction Y. The first direction X and the second direction Y may intersect, for example, the first direction X and the second direction Y may be perpendicular.

[0174] As shown in Figures 21, 22, and 29, the first active layer may include: a fourth active portion 74, a sixteenth active portion 716, and a twentieth active portion 720. The fourth active portion 74 is used to form the channel region of the fourth transistor T4, and the sixteenth active portion 716 and the twentieth active portion 720 are connected to the two ends of the fourth active portion 74. The first active layer may be formed of polycrystalline silicon material, and correspondingly, the fourth transistor T4 may be a P-type low-temperature polycrystalline silicon thin-film transistor.

[0175] As shown in Figures 21, 23, and 29, the first gate layer may include a first gate line G1 and a first conductive portion 11. The first gate line G1 is used to provide the first gate drive signal terminal in Figure 20. The first gate line G1 includes first gate line segments G11 spaced apart and extending along the first direction X. The orthographic projection of the first gate line segments G11 on the substrate covers the orthographic projection of the fourth active portion 74 on the substrate. At least a portion of the structure of the first gate line segments G11 is used to form the gate of the fourth transistor. A portion of the structure of the first conductive portion 11 is used to form the first electrode of the first capacitor C1, and a portion of the structure of the first conductive portion 11 is used to form the first electrode of the second capacitor C2. This display panel can use the first gate layer as a mask to perform conductive processing on the first active layer, that is, the area of ​​the first active layer covered by the first gate layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first gate layer forms a conductive structure.

[0176] As shown in Figures 21, 24, and 30, the second gate layer may include: a third enable signal line 2EM1, a sixth reset signal line 2Re3, a fourth enable signal line 2EM2, a fourth reset signal line 2Re1, a fifth reset signal line 2Re2, a second conductive portion 22, and a third conductive portion 23. The orthogonal projections of the third enable signal line 2EM1, the sixth reset signal line 2Re3, the fourth enable signal line 2EM2, the fourth reset signal line 2Re1, and the fifth reset signal line 2Re2 onto the substrate extend along a first direction X. The third enable signal line 2EM1 provides the first enable signal terminal in Figure 20, the sixth reset signal line 2Re3 provides the third reset signal terminal in Figure 20, the fourth enable signal line 2EM2 provides the second enable signal terminal in Figure 20, the fourth reset signal line 2Re1 provides the first reset signal terminal in Figure 20, and the fifth reset signal line 2Re2 provides the second reset signal terminal in Figure 20. The fourth enable signal line 2EM2 includes fourth enable signal segments 2EM21 spaced apart and extending along the first direction X; the fourth reset signal line 2Re1 includes fourth reset signal segments 2Re11 spaced apart and extending along the first direction X; and the fifth reset signal line 2Re2 includes fifth reset signal segments 2Re21 spaced apart and extending along the first direction X. The orthographic projection of the second conductive portion 22 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate at least partially overlap, and the second conductive portion 22 is used to form the second electrode of the second capacitor C2; the orthographic projection of the third conductive portion 23 on the substrate and the orthographic projection of the first conductive portion 11 on the substrate at least partially overlap, and the third conductive portion 23 is used to form the second electrode of the first capacitor C1.

[0177] As shown in Figures 21, 25, and 31, the second active layer may include a first main active portion 091, a second main active portion 092, and a third main active portion 093. The orthographic projections of the first main active portion 091, the second main active portion 092, and the third main active portion 093 onto the substrate extend along the second direction Y and are spaced apart along the first direction X. The first main active portion 091 includes: a first active portion 91, a fourteenth active portion 914, and a fifteenth active portion 915; the second main active portion 092 includes: a third active portion 93, a fifth active portion 95, a sixth active portion 96, a seventh active portion 97, an eighth active portion 98, a ninth active portion 99, a tenth active portion 910, and a twelfth active portion 912; the third main active portion 093 includes: a second active portion 92, a thirteenth active portion 913, and a nineteenth active portion 919. The first active portion 91 is used to form the channel region of the first transistor T1; the second active portion 92 is used to form the channel region of the second transistor T2; the third active portion 93 is used to form the channel region of the driving transistor T3; the fifth active portion 95 is used to form the channel region of the fifth transistor T5; the sixth active portion 96 is used to form the channel region of the sixth transistor T6; the seventh active portion 97 is used to form the channel region of the seventh transistor T7; and the eighth active portion 98 is connected to the sixth active portion 96 away from the seventh active portion. The seventh active part 97 is located on one side; the ninth active part 99 is connected to the side of the seventh active part 97 away from the sixth active part 96; the tenth active part 910 is connected between the sixth active part 96 and the seventh active part 97; the twelfth active part 912 is connected to the end of the fifth active part 95 away from the sixth active part 96; the thirteenth active part 913 and the nineteenth active part 919 are connected to both ends of the second active part 92; the fourteenth active part 914 and the fifteenth active part 915 are connected to both ends of the first active part 91. The second active layer can be formed of indium gallium zinc oxide, and correspondingly, the first transistor, the second transistor, the driving transistor, the fifth transistor, the sixth transistor, and the seventh transistor can be N-type metal oxide thin-film transistors.

[0178] As shown in Figures 21, 25, and 31, the orthogonal projection of the fourth reset signal segment 2Re11 onto the substrate covers the orthogonal projection of the first active portion 91 onto the substrate, and at least a portion of the structure of the fourth reset signal segment 2Re11 is used to form the bottom gate of the first transistor T1; the orthogonal projection of the fifth reset signal segment 2Re21 onto the substrate covers the orthogonal projection of the second active portion 92 onto the substrate, and at least a portion of the structure of the fifth reset signal segment 2Re21 is used to form the bottom gate of the second transistor T2. The orthogonal projection of the fourth enable signal segment 2EM21 onto the substrate covers the orthogonal projection of the sixth active portion 96 onto the substrate, and at least a portion of the structure of the fourth enable signal segment 2EM21 is used to form the bottom gate of the sixth transistor T6. The orthogonal projection of the third enable signal line 2EM1 onto the substrate covers the orthogonal projection of the fifth active portion 95 onto the substrate, and at least a portion of the structure of the third enable signal line 2EM1 is used to form the bottom gate of the fifth transistor T5. The orthographic projection of the sixth reset signal line 2Re3 on the substrate covers the orthographic projection of the seventh active part 97 on the substrate, and at least a portion of the structure of the sixth reset signal line 2Re3 is used to form the bottom gate of the seventh transistor T7.

[0179] As shown in Figures 21, 26, and 32, the third gate layer may include: a first enable signal line 3EM1, a third reset signal line 3Re3, a second enable signal line 3EM2, a first reset signal line 3Re1, a second reset signal line 3Re2, and a fourth conductive portion 34. The orthogonal projections of the first enable signal line 3EM1, the third reset signal line 3Re3, the second enable signal line 3EM2, the first reset signal line 3Re1, and the second reset signal line 3Re2 onto the substrate extend along a first direction X. The first enable signal line 3EM1 provides the first enable signal terminal in Figure 20, the third reset signal line 3Re3 provides the third reset signal terminal in Figure 20, the second enable signal line 3EM2 provides the second enable signal terminal in Figure 20, the first reset signal line 3Re1 provides the first reset signal terminal in Figure 20, and the second reset signal line 3Re2 provides the second reset signal terminal in Figure 20. The second enable signal line 3EM2 includes second enable signal segments 3EM21 that are spaced apart on the first direction X and extend along the first direction X; the first reset signal line 3Re1 includes first reset signal segments 3Re11 that are spaced apart on the first direction X and extend along the first direction X; and the second reset signal line 3Re2 includes second reset signal segments 3Re21 that are spaced apart on the first direction X and extend along the first direction X.

[0180] The orthographic projection of the first reset signal segment 3Re11 onto the substrate covers the orthographic projection of the first active portion 91 onto the substrate, and at least a portion of the structure of the first reset signal segment 3Re11 is used to form the top gate of the first transistor T1. The orthographic projection of the second reset signal segment 3Re21 onto the substrate covers the orthographic projection of the second active portion 92 onto the substrate, and at least a portion of the structure of the second reset signal segment 3Re21 is used to form the top gate of the second transistor T2. The orthographic projection of the second enable signal segment 3EM21 onto the substrate covers the orthographic projection of the sixth active portion 96 onto the substrate, and at least a portion of the structure of the second enable signal segment 3EM21 is used to form the top gate of the sixth transistor T6. The orthographic projection of the first enable signal line 3EM1 onto the substrate covers the orthographic projection of the fifth active portion 95 onto the substrate, and at least a portion of the structure of the first enable signal line 3EM1 is used to form the top gate of the fifth transistor T5. The orthographic projection of the third reset signal line 3Re3 onto the substrate covers the orthographic projection of the seventh active portion 97 onto the substrate. At least a portion of the structure of the third reset signal line 3Re3 is used to form the top gate of the seventh transistor T7. The orthographic projection of the fourth conductive portion 34 onto the substrate covers the orthographic projection of the third active portion 93 onto the substrate. The fourth conductive portion 34 is used to form the top gate of the driving transistor. This display panel can use the third gate layer as a mask to perform conductive processing on the second active layer, that is, the area of ​​the second active layer covered by the third gate layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third gate layer forms a conductive structure.

[0181] As shown in Figures 21, 27, and 33, the first source / drain layer may include: a first power supply line VDD, a first gate connection line 4G1, a second enable connection line 4EM2, a first reset connection line 4Re1, a second reset connection line 4Re2, a first initial signal line Vinit1, a second initial signal line Vinit2, a first bridge portion 41, a third bridge portion 43, a fifth bridge portion 45, a sixth bridge portion 46, and a seventh bridge portion 47. The orthogonal projection of the first power supply line VDD, the first gate connection line 4G1, the second enable connection line 4EM2, the first reset connection line 4Re1, the second reset connection line 4Re2, the first initial signal line Vinit1, and the second initial signal line Vinit2 onto the substrate can extend along a first direction X.

[0182] As shown in Figures 21, 27, and 33, the first power line VDD is used to provide the first power terminal in Figure 20. The first power line VDD can be connected to the twelfth active part 712 through vias to connect to the first terminal of the fifth transistor T5. The first gate connection line 4G1 can be connected to multiple first gate line segments 3G11 in the same first gate line through vias. At the same time, the first gate connection line 4G1 can be connected to multiple second gate line segments 2G11 in the same second gate line through vias. The second enable connection line 4EM2 can be connected to multiple second enable signal line segments 3EM21 in the same second enable signal line through vias. At the same time, the second enable connection line 4EM2 can be connected to multiple second enable signal line segments 3EM21 in the same second enable signal line through vias. Vias connect multiple fourth enable signal segments 2EM21 within the same fourth enable signal line; the first reset connection line 4Re1 can be connected to multiple first reset signal segments 3Re11 within the same first reset signal line via vias, and simultaneously, the first reset connection line 4Re1 can be connected to multiple fourth reset signal segments 2Re11 within the same fourth reset signal line via vias; the second reset connection line 4Re2 can be connected to multiple second reset signal segments 3Re21 within the same second reset signal line via vias, and simultaneously, the first reset connection line 4Re1 can be connected to multiple fifth reset signal segments 2Re21 within the same fifth reset signal line via vias. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in FIG20. The first initial signal line Vinit1 can be connected to the fourteenth active part 914 and the nineteenth active part 919 via vias to connect the first initial signal terminal to the first electrode of the first transistor T1 and the first electrode of the second transistor T2. The second initial signal line Vinit2 can be used to provide the second initial signal terminal in FIG20. The second initial signal line Vinit2 can be connected to the ninth active part 99 through a via to connect the second initial signal terminal and the first terminal of the seventh transistor T7.

[0183] As shown in Figures 21, 27, and 33, the first bridging portion 41 can be connected to the sixteenth active portion 916 via vias to connect to the first electrode of the fourth transistor T4. The third bridging portion 43 can be connected to the twentieth active portion 920, the second conductive portion 22, the fifteenth active portion 915, and the fourth conductive portion 34 via vias to connect to the second electrode of the fourth transistor T4, the second electrode of the second capacitor C2, the gate of the driving transistor T3, and the second electrode of the first transistor. The fifth bridging portion 45 can be connected to the thirteenth active portion 913 and the first conductive portion 11 via vias to connect to the second electrode of the second transistor T2 and the first electrode of the first capacitor C1 and the first electrode of the second capacitor C2. The sixth bridging portion 46 can be connected to the third conductive portion 23 and the eighth active portion 98 via vias to connect to the second electrode of the driving transistor T3, the first electrode of the sixth transistor T6, and the second electrode of the first capacitor C1.

[0184] As shown in Figures 21 and 28, the second source / drain layer includes: a data line Da, a second power line VSS, a signal connection line Lx, and an eighth bridging portion 58. The orthogonal projections of the data line Da, the second power line VSS, and the signal connection line Lx onto the substrate extend along the second direction Y. The data line Da provides the data signal terminal shown in Figure 5. The data line Da can be connected to the first bridging portion 41 via a via to connect the data signal terminal and the first electrode of the fourth transistor T4. The second power line VSS provides the second power terminal shown in Figure 5. The second power line VSS can be connected to the common cathode in the display panel to reduce the voltage difference of the second power terminal at different locations on the display panel. The common cathode in the display panel forms the cathode of the light-emitting unit. The common cathode can be located on the side of the light-emitting unit L facing away from the substrate. The eighth bridging portion 58 can be connected to the seventh bridging portion 47 via a via. The signal connection line Lx can be any one of the first initial connection line, the second initial connection line, and the first power connection line. The first initial connection line can be connected to the intersecting first initial signal line via a via, the second initial connection line can be connected to the intersecting second initial signal line via a via, and the first power connection line can be connected to the intersecting first power line via a via. Each column of pixel driving circuits can be provided with one signal connection line Lx, and the display panel can be provided with multiple signal connection lines Lx. Some signal connection lines Lx can form the first initial connection line, some signal connection lines Lx can form the second initial connection line, and some signal connection lines Lx can form the first power connection line. For example, the orthographic projections of the first initial connection line, the second initial connection line, and the first power connection line on the substrate can be alternately distributed along the row direction.

[0185] Figure 34 shows a partial cross-sectional view of the display panel shown in Figure 21, taken along the dashed line BB. The display panel may further include a first insulating layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a first dielectric layer 105, a passivation layer 106, and a first planarization layer 107. The substrate 100, the first active layer, the first insulating layer 101, the first gate layer, the second insulating layer 102, the second gate layer, the third insulating layer 103, the second active layer, the fourth insulating layer 104, the third gate layer, the first dielectric layer 105, the first source / drain layer, the passivation layer 106, the first planarization layer 107, and the second source / drain layer are sequentially stacked. The first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be single-layer or multi-layer structures, and the materials of the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, and the fourth insulating layer 104 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 105 can be a silicon nitride layer; the material of the first planarization layer 107 can be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The passivation layer 106 can be a silicon oxide layer. The substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The materials of the first gate layer, the second gate layer, and the third gate layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy or a stacked conductive layer. The materials of the first and second source / drain layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or conductive layers such as titanium / aluminum / titanium stacks. The sheet resistance of any one of the first and second source / drain layers can be less than the sheet resistance of any one of the first, second, and third gate layers.

[0186] In this exemplary embodiment, as shown in FIG6-33, in the same pixel driving circuit, the orthographic projection of the first gate line on the substrate is located between the orthographic projection of the first enable signal line on the substrate and the orthographic projection of the fourth conductive part on the substrate.

[0187] In this exemplary embodiment, as shown in FIG6-33, in the same pixel driving circuit, the orthogonal projection of the second enable signal line on the substrate is located between the orthogonal projection of the first reset signal line on the substrate and the orthogonal projection of the fourth conductive part on the substrate, and the orthogonal projection of the second enable signal line on the substrate is located on the side of the orthogonal projection of the fourth conductive part on the substrate away from the orthogonal projection of the first gate line on the substrate.

[0188] In this exemplary embodiment, as shown in FIG6-33, in the same pixel driving circuit, the orthographic projection of the third reset signal line on the substrate is located on the side away from the orthographic projection of the second reset signal line on the substrate, and the orthographic projection of the second reset signal line on the substrate is located on the side away from the orthographic projection of the fourth conductive portion on the substrate. In the first direction, the orthographic projections of the channel region of the fifth transistor, the channel region of the sixth transistor, and the channel region of the seventh transistor on the substrate are located between the orthographic projections of the channel region of the first transistor and the channel region of the second transistor on the substrate. The orthographic projections of the second and third conductive portions on the substrate are distributed along the second direction.

[0189] In this exemplary embodiment, as shown in FIG6-33, in the same pixel driving circuit, the orthographic projections of the second conductive portion and the third conductive portion on the substrate are located between the orthographic projections of the first enable signal line and the second enable signal line on the substrate. The orthographic projections of the third conductive portion and the third active portion on the substrate at least partially overlap. The third conductive portion can shield the channel region of the driving transistor to improve the stability of the output characteristics of the driving transistor.

[0190] It should be noted that, as shown in Figure 6-33, the black squares drawn on the side of the first source / drain layer away from the substrate represent vias connecting the first source / drain layer to other layers facing the substrate; the black squares drawn on the side of the second source / drain layer away from the substrate represent vias connecting the second source / drain layer to other layers facing the substrate. Vias at different positions can penetrate different insulating layers.

[0191] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channels, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. The same structural layer can be formed by the same patterning process. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction.

[0192] In this exemplary embodiment, the display panel may further include multiple gate driving circuits, which can provide gate driving signals to different transistors respectively. As shown in Figures 1, 5, and 20, the first transistor, second transistor, fourth transistor, fifth transistor, and sixth transistor each need to be configured with a gate driving circuit, that is, the display panel needs to be provided with 6 gate driving circuits. Each gate driving circuit can consist of multiple cascaded shift register units, which sequentially output shift signals. Different shift register units can provide gate driving signals to different row pixel driving circuits. The gate driving circuits can be located in the bezel area of ​​the display panel; too many gate driving circuits will increase the bezel width of the display panel.

[0193] In this exemplary embodiment, different transistors in the pixel driving circuit can share a gate driving circuit to achieve a narrow bezel design for the display panel. For example, the display panel may include a first gate driving circuit, which includes multiple cascaded shift register units. Figure 35 shows a schematic diagram of the structure in another exemplary embodiment of the pixel driving circuit of this disclosure. The first reset signal line and the second reset signal line can be connected to different shift register units in the first gate driving circuit. For example, the gate of the first transistor T1 can be connected to the nth shift register unit in the first gate driving circuit, and the gate of the second transistor T2 can be connected to the (n+x)th shift register unit in the first gate driving circuit, where n and x are positive integers greater than or equal to 1, for example, x can be equal to 4. The timing of this pixel driving circuit driving method can be as shown in Figure 2. It should be noted that this shared gate driving circuit scheme can be applied to the pixel driving circuits shown in Figures 1, 5, and 20.

[0194] In this exemplary embodiment, the display panel further includes a second gate driving circuit, which includes multi-stage cascaded shift register units. Figure 36 shows a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure, and Figure 37 shows a timing diagram of a driving method for the pixel driving circuit shown in Figure 36. This pixel driving circuit driving method can also include: a first reset stage t1, a second reset stage t2, a threshold compensation stage t3, a data writing stage t4, and a light emission stage t5. A first enable signal line and a second enable signal line are connected to different stages of shift register units in the second gate driving circuit. For example, the gate of the fifth transistor is connected to the nth stage shift register unit in the second gate driving circuit, and the gate of the sixth transistor is connected to the nxth stage shift register unit in the second gate driving circuit, where nx is a positive integer greater than or equal to 1; for example, x can be equal to 6. It should be noted that this shared gate driving circuit scheme can be applied to the pixel driving circuits shown in Figures 1, 5, and 20.

[0195] In this exemplary embodiment, the display panel further includes a third gate driving circuit, which includes multi-stage cascaded shift register units. Figure 38 shows a schematic diagram of another exemplary embodiment of the pixel driving circuit of this disclosure, and Figure 39 shows a timing diagram of a driving method for the pixel driving circuit shown in Figure 38. This pixel driving circuit driving method can also include: a first reset stage t1, a second reset stage t2, a threshold compensation stage t3, a data writing stage t4, and a light emission stage t5. The first gate line and the third reset signal line are connected to different stages of shift register units in the same gate driving circuit. For example, the gate of the fourth transistor can be connected to the nth stage shift register unit, and the gate of the seventh transistor can be connected to the nxth stage shift register unit, where nx is a positive integer greater than or equal to 1; for example, x can be equal to 12. It should be noted that this shared gate driving circuit scheme can be applied to the pixel driving circuits shown in Figures 1, 5, and 20.

[0196] It should be noted that any multiple of the three technical solutions—sharing a first gate driving circuit, sharing a second gate driving circuit, and sharing a third gate driving circuit—can be applied to the same pixel driving circuit.

[0197] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0198] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0199] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0200] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes a pixel driving circuit and a light-emitting unit. The pixel driving circuit includes a driving transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The first electrode of the fourth transistor is connected to a data line, and the second electrode of the fourth transistor is connected to the gate of the driving transistor. The first electrode of the fifth transistor is connected to a first power line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit. The display panel also includes: Substrate; The first active layer is located on one side of the substrate. The second active layer is located on the side of the first active layer away from the substrate. The second active layer includes a third active portion, which is used to form the channel region of the driving transistor. The channel regions of one or more of the fourth, fifth, and sixth transistors are located in the first active layer.

2. The display panel according to claim 1, wherein, The transistor formed by the first active layer is a low-temperature polysilicon transistor, and the transistor formed by the second active layer is an oxide transistor.

3. The display panel according to claim 1, wherein, The pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to the second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit; The first active layer includes a fifth active portion, a sixth active portion, and a seventh active portion. The fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor.

4. The display panel according to claim 3, wherein, The pixel driving circuit also includes: The first capacitor has a second electrode connected to the second terminal of the driving transistor; The second capacitor has its first electrode connected to the first electrode of the first capacitor and its second electrode connected to the gate of the driving transistor. A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the gate of the driving transistor; The second transistor has its first terminal connected to the first initial signal line and its second terminal connected to the first electrode of the first capacitor. The channel regions of the first transistor, the driving transistor, and the fourth transistor are located in the second active layer.

5. The display panel according to claim 4, wherein, The display panel further includes a first gate line, the first gate line extending along a first direction in the orthographic projection on the substrate, and at least a portion of the structure of the first gate line is used to form the gate of the fourth transistor; The second active layer includes a first main active portion, a second main active portion, and a third main active portion. The orthographic projections of the first main active portion, the second main active portion, and the third main active portion on the substrate extend along a second direction and are spaced apart along a first direction. The second direction intersects with the first direction. The first main active portion includes a first active portion and a fourth active portion connected in the same layer. The orthographic projections of the first active portion and the fourth active portion on the substrate are distributed at intervals along the second direction. The first active portion is used to form the channel region of the first transistor, and the fourth active portion is used to form the channel region of the fourth transistor. The second main active portion includes the third active portion, and the third main active portion includes the second active portion, which is used to form the channel region of the second transistor.

6. The display panel according to claim 3, wherein, The display panel further includes a third reset signal line, the third reset signal line extending along a first direction in its orthogonal projection on the substrate, and at least a portion of the structure of the third reset signal line being used to form the gate of the seventh transistor; The first active layer includes a fourth main active portion and a fifth main active portion, wherein the orthographic projections of the fourth main active portion and the fifth main active portion on the substrate extend along a second direction and are spaced apart along the second direction; The fourth main active portion includes a fifth active portion, which is used to form the channel region of the fifth transistor; The fifth main active portion includes a sixth active portion and a seventh active portion connected in the same layer. The orthographic projections of the sixth active portion and the seventh active portion on the substrate are distributed at intervals along a second direction. The sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor.

7. The display panel according to claim 1, wherein, The first active layer includes a fourth active portion, which is used to form the channel region of the fourth transistor.

8. The display panel according to claim 7, wherein, The pixel driving circuit also includes: The first capacitor has a second electrode connected to the second terminal of the driving transistor; The second capacitor has its first electrode connected to the first electrode of the first capacitor and its second electrode connected to the gate of the driving transistor. A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the gate of the driving transistor; The second transistor has its first terminal connected to the first initial signal line and its second terminal connected to the first electrode of the first capacitor. A seventh transistor, wherein the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; The channel regions of the first transistor, the driving transistor, the fifth transistor, the sixth transistor, and the seventh transistor are located in the second active layer.

9. The display panel according to claim 8, wherein, The display panel further includes a third reset signal line, the third reset signal line extending along a first direction in its orthogonal projection on the substrate, and at least a portion of the structure of the third reset signal line being used to form the gate of the seventh transistor; The second active layer includes a first main active portion, a second main active portion, and a third main active portion. The orthographic projections of the first main active portion, the second main active portion, and the third main active portion on the substrate extend along a second direction and are spaced apart along a first direction. The second direction intersects with the first direction. The first main active portion includes a first active portion, which is used to form the channel region of the first transistor; The second main active portion includes a fifth active portion, a third active portion, a sixth active portion, and a seventh active portion connected in the same layer. The orthographic projections of the fifth active portion, the third active portion, the sixth active portion, and the seventh active portion on the substrate are distributed sequentially along a second direction. The fifth active portion is used to form the channel region of the fifth transistor, the sixth active portion is used to form the channel region of the sixth transistor, and the seventh active portion is used to form the channel region of the seventh transistor. The third main active portion includes a second active portion, which is used to form the channel region of the second transistor.

10. The display panel according to any one of claims 1-9, wherein, The display panel also includes: A first enable signal line extends along a first direction in its orthogonal projection onto the substrate, and at least a portion of the structure of the first enable signal line is used to form the gate of the fifth transistor. A first gate line, whose orthogonal projection on the substrate extends along the first direction, wherein at least a portion of the structure of the first gate line is used to form the gate of the fourth transistor; A fourth conductive portion, which is used to form the gate of the driving transistor; In the same pixel driving circuit, the orthogonal projection of the first gate line on the substrate is located between the orthogonal projection of the first enable signal line on the substrate and the orthogonal projection of the fourth conductive part on the substrate.

11. The display panel according to any one of claims 1-9, wherein, The pixel driving circuit further includes a first transistor, the first terminal of which is connected to a first initial signal line, and the second terminal of which is connected to the gate of the driving transistor. The display panel also includes: A first gate line extends along a first direction in the orthographic projection on the substrate, and at least a portion of the structure of the first gate line is used to form the gate of the fourth transistor; A first reset signal line extends along a first direction in the orthographic projection on the substrate, and at least a portion of the structure of the first reset signal line is used to form the gate of the first transistor. A fourth conductive portion, which is used to form the gate of the driving transistor; A second enable signal line extends along the first direction in its orthogonal projection onto the substrate, and at least a portion of the structure of the second enable signal line is used to form the gate of the sixth transistor. In the same pixel driving circuit, the orthographic projection of the second enable signal line on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the fourth conductive part on the substrate, and the orthographic projection of the second enable signal line on the substrate is located on the side of the orthographic projection of the fourth conductive part on the substrate that is away from the orthographic projection of the first gate line on the substrate.

12. The display panel according to any one of claims 1-9, wherein, The pixel driving circuit further includes a first capacitor, a second capacitor, a first transistor, a second transistor, and a seventh transistor. The first electrode of the first capacitor and the first electrode of the second capacitor are connected. The second electrode of the first capacitor is connected to the second electrode of the driving transistor. The second electrode of the second capacitor is connected to the gate of the driving transistor. The first electrode of the first transistor is connected to a first initial signal line. The second electrode of the first transistor is connected to the gate of the driving transistor. The first electrode of the second transistor is connected to the first initial signal line. The second electrode of the second transistor is connected to the first electrode of the first capacitor. The first electrode of the seventh transistor is connected to a second initial signal line. The second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit. The display panel also includes: A first reset signal line extends along a first direction in the orthographic projection on the substrate, and at least a portion of the structure of the first reset signal line is used to form the gate of the first transistor. The second reset signal line extends along a first direction in the orthogonal projection on the substrate, and at least a portion of the structure of the second reset signal line is used to form the gate of the second transistor. A third reset signal line, the orthogonal projection of the third reset signal line on the substrate extending along the first direction, and at least a portion of the structure of the third reset signal line being used to form the gate of the seventh transistor; A fourth conductive portion, which is used to form the gate of the driving transistor; In the same pixel driving circuit, the orthogonal projection of the third reset signal line on the substrate is located on the side where the orthogonal projection of the second reset signal line on the substrate is away from the orthogonal projection of the fourth conductive part on the substrate, and the orthogonal projection of the second reset signal line on the substrate is located on the side where the orthogonal projection of the first reset signal line on the substrate is away from the orthogonal projection of the fourth conductive part on the substrate.

13. The display panel according to any one of claims 1-9, wherein, The pixel driving circuit further includes a first capacitor, a second capacitor, a first transistor, a second transistor, and a seventh transistor. The first electrode of the first transistor is connected to a first initial signal line, and the second electrode of the first transistor is connected to the gate of the driving transistor. The first electrode of the first capacitor and the first electrode of the second capacitor are connected. The second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The first electrode of the second transistor is connected to the first initial signal line, and the second electrode of the second transistor is connected to the first electrode of the first capacitor. The gate of the second transistor is connected to a second reset signal line. The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit. The orthogonal projection of the second reset signal line on the substrate extends along a first direction. In a first direction, the orthographic projections of the channel region of the fifth transistor, the sixth transistor, and the seventh transistor on the substrate are located between the orthographic projections of the channel region of the first transistor and the second transistor on the substrate.

14. The display panel according to claim 1, wherein, The pixel driving circuit includes a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The display panel also includes: A first gate layer is located between the substrate and the second active layer. The first gate layer includes a first conductive portion. A portion of the structure of the first conductive portion is used to form a first electrode of the first capacitor, and a portion of the structure of the first conductive portion is used to form a first electrode of the second capacitor. A second gate layer is located between the first gate layer and the second active layer. The second gate layer includes a second conductive portion and a third conductive portion. The orthographic projection of the second conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The second conductive portion is used to form the second electrode of the second capacitor. The orthographic projection of the third conductive portion on the substrate and the orthographic projection of the first conductive portion on the substrate at least partially overlap. The third conductive portion is used to form the second electrode of the first capacitor. The orthographic projections of the second conductive portion and the third conductive portion on the substrate are distributed along a second direction.

15. The display panel according to claim 14, wherein, The display panel also includes: A first enable signal line extends along a first direction in its orthographic projection on the substrate, and at least a portion of the structure of the first enable signal line is used to form the gate of the fifth transistor, wherein the first direction and the second direction intersect. A second enable signal line extends along a first direction in its orthogonal projection on the substrate, and at least a portion of the structure of the second enable signal line is used to form the gate of the sixth transistor. In the same pixel driving circuit, the orthographic projections of the second conductive part and the third conductive part on the substrate are located between the orthographic projections of the first enable signal line on the substrate and the orthographic projections of the second enable signal line on the substrate.

16. The display panel according to claim 1, wherein, The pixel driving circuit includes a first capacitor and a second capacitor. The first electrode of the first capacitor is connected to the first electrode of the second capacitor, the second electrode of the first capacitor is connected to the second electrode of the driving transistor, and the second electrode of the second capacitor is connected to the gate of the driving transistor. The display panel also includes: A second gate layer is located between the first active layer and the second active layer. The second gate layer includes a third conductive portion, which is used to form the second electrode of the first capacitor. Wherein, the orthographic projection of the third conductive part on the substrate and the orthographic projection of the third active part on the substrate at least partially overlap.

17. The display panel according to claim 1, wherein, The gate of the fifth transistor is connected to the first enable signal line, the gate of the sixth transistor is connected to the second enable signal line, and the gate of the fourth transistor is connected to the first gate line. The pixel driving circuit also includes: The first capacitor has a second electrode connected to the second terminal of the driving transistor; The second capacitor has its first electrode connected to the first electrode of the first capacitor and its second electrode connected to the gate of the driving transistor. A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the gate of the driving transistor, and the gate is connected to a first reset signal line; The second transistor has its first terminal connected to the first initial signal line, its second terminal connected to the first electrode of the first capacitor, and its gate connected to the second reset signal line. The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the third reset signal line. The display panel also includes: Multiple grid lines, at least some of which include grid line segments extending along a first direction and spaced apart along the first direction; The first enable signal line, the second enable signal line, the first gate line, the first reset signal line, the second reset signal line, and the third reset signal line form the gate line.

18. The display panel according to claim 1, wherein, The pixel driving circuit also includes: The first capacitor has a second electrode connected to the second terminal of the driving transistor; The second capacitor has its first electrode connected to the first electrode of the first capacitor and its second electrode connected to the gate of the driving transistor. A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the gate of the driving transistor, and the gate is connected to a first reset signal line; The second transistor has its first terminal connected to the first initial signal line, its second terminal connected to the first electrode of the first capacitor, and its gate connected to the second reset signal line. The display panel further includes a first gate driving circuit, which includes multiple cascaded shift register units. The first reset signal line and the second reset signal line are connected to different shift register units in the first gate driving circuit.

19. The display panel according to claim 1, wherein, The gate of the fifth transistor is connected to the first enable signal line, and the gate of the sixth transistor is connected to the second enable signal line. The display panel further includes a second gate driving circuit, which includes multiple cascaded shift register units. The first enable signal line and the second enable signal line are connected to different shift register units in the second gate driving circuit.

20. The display panel according to claim 1, wherein, The gate of the fourth transistor is connected to the first gate line; The pixel driving circuit also includes: The seventh transistor has its first electrode connected to the second initial signal line, its second electrode connected to the first electrode of the light-emitting unit, and its gate connected to the third reset signal line. The display panel further includes a third gate driving circuit, which includes multiple cascaded shift register units. The first gate line and the third reset signal line are connected to different shift register units in the same gate driving circuit.

21. A display device, wherein, The display device includes the display panel as described in any one of claims 1-20.

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