Display panel, display apparatus and driving method

Abstract

A display panel, a display apparatus and a driving method. The display panel comprises: a base substrate (100); a plurality of data lines, provided on the base substrate (100); a plurality of source input signal lines, provided on the base substrate (100); a multipath selection circuit (110), comprising a plurality of selection transistors, wherein first electrodes of at least two selection transistors are electrically connected to one source input signal line, the plurality of selection transistors are in one-to-one correspondence with the plurality of data lines, a second electrode of any selection transistor is electrically connected to a corresponding data line, and, when a selection transistor is turned on, there is a first electric field between an active layer and a gate of the selection transistor; and a plurality of compensation structures (120), which are arranged corresponding to the selection transistors and configured to generate a second electric field, wherein the direction of the first electric field is opposite to that of the second electric field. Thus, the impact of noise can be reduced, and display quality can be improved.

Description

Display panel, display device and driving method Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to display panels, display devices, and driving methods. Background Technology

[0002] Currently, data driver chips in displays output pixel voltages to pixel units via data lines. Because displays have a large number of data lines, the data driver chip requires a corresponding number of pins, resulting in a larger number of data input lines transmitting data signals to each data line, thus increasing production costs. To reduce production costs, a multiplexer (MUX) circuit is used between the data driver chip and the data lines. This significantly reduces the number of data input lines, the number of data driver chips, and ultimately, production costs. However, current multiplexer circuits generate parasitic capacitance, i.e., noise, during normal operation, which affects display quality. Summary of the Invention

[0003] The display panel provided in this embodiment includes:

[0004] Substrate;

[0005] Multiple data lines are disposed on the substrate.

[0006] Multiple source input lines are disposed on the substrate.

[0007] A multiplexing circuit includes multiple selection transistors, at least two of the selection transistors having their first terminals electrically connected to a source input signal line, the multiple selection transistors corresponding one-to-one with the multiple data lines, and the second terminal of any selection transistor being electrically connected to the corresponding data line; when a selection transistor is turned on, a first electric field exists between the active layer and the gate of the selection transistor.

[0008] Multiple compensation structures, corresponding to each of the selected transistors, are configured to generate a second electric field;

[0009] The first electric field is in the opposite direction to the second electric field.

[0010] In some possible implementations, the compensation structure includes: a semiconductor layer, a first conductive layer, and a second conductive layer;

[0011] A first insulating layer is provided between the semiconductor layer and the first conductive layer, and the semiconductor layer and the first conductive layer overlap in the orthographic projection of the substrate.

[0012] A second insulating layer is provided between the first conductive layer and the second conductive layer, and the semiconductor layer and the second conductive layer overlap in the orthographic projection of the substrate.

[0013] In some possible implementations, the substrate has a compensation transistor;

[0014] The semiconductor layer includes the active layer of the compensation transistor, the first conductive layer includes the gate of the compensation transistor, and the second conductive layer includes the first electrode and the second electrode of the compensation transistor.

[0015] In some possible implementations, the substrate has a ground signal line and a compensation signal line;

[0016] The gate of the compensation transistor is electrically connected to the compensation signal line, and both the first and second terminals of the compensation transistor are electrically connected to the ground signal line.

[0017] In some possible implementations, the orthographic projection of the compensation transistor onto the substrate is located between the orthographic projections of the ground signal line and the compensation signal line onto the substrate.

[0018] In some possible implementations, the area of ​​the channel region in the active layer of the compensation transistor and the area of ​​the channel region in the active layer of the selection transistor projected onto the substrate are the same.

[0019] In some possible implementations, the active layer of the compensation transistor has a first width along the first direction, and the active layer of the selection transistor has a second width along the first direction, wherein the first width and the second width are the same.

[0020] In some possible implementations, the active layer of the compensation transistor has a first length along the second direction, and the active layer of the selection transistor has a second length along the second direction, wherein the first length and the second length are the same.

[0021] In some possible implementations, the active layer of the compensation transistor has a first width along a first direction, and the active layer of the selection transistor has a second width along the first direction, wherein the first width is greater than the second width.

[0022] In some possible implementations, the second width is three-fifths of the first width.

[0023] In some possible implementations, the active layer of the compensation transistor has a first length along the second direction, and the active layer of the selection transistor has a second length along the second direction, wherein the first length is less than the second length.

[0024] In some possible implementations, the second length is twice the first length.

[0025] In some possible implementations, the substrate has a conducting transistor; the conducting transistor is disposed correspondingly to the compensation transistor;

[0026] The semiconductor layer includes the active layer of the conducting transistor, the first conductive layer includes the gate of the conducting transistor, and the second conductive layer includes the first electrode and the second electrode of the conducting transistor.

[0027] In some possible implementations, the substrate has a selection signal line;

[0028] The gate of the conducting transistor is electrically connected to the selection signal line, the first terminal of the conducting transistor is electrically connected to the ground signal line, and the second terminal of the conducting transistor is electrically connected to the first and second terminals of the compensation transistor.

[0029] In some possible implementations, the orthographic projection of the conducting transistor onto the substrate lies between the orthographic projections of the ground signal line and the select signal line onto the substrate.

[0030] In some possible implementations, the area of ​​the active layer of the conducting transistor projected onto the substrate is smaller than the area of ​​the active layer of the compensation transistor on the substrate.

[0031] In some possible implementations, the active layers of at least two conducting transistors are integrated.

[0032] In some possible implementations, the substrate has a compensation capacitor;

[0033] The first conductive layer and the second conductive layer overlap in their orthographic projections onto the substrate.

[0034] The first conductive layer includes the first electrode of the compensation capacitor, and the second conductive layer includes the second electrode of the compensation capacitor.

[0035] In some possible implementations, the substrate has a ground signal line and multiple compensation signal lines;

[0036] The first electrode of the compensation capacitor is electrically connected to the compensation signal line, and the second electrode of the compensation capacitor is electrically connected to the ground signal line.

[0037] In some possible implementations, the compensation capacitor is positioned between the ground signal line and the compensation signal line in the orthogonal projection of the substrate.

[0038] In some possible implementations, the orthographic projections of the ground signal line and the compensation signal line onto the substrate overlap with the orthographic projection of the source signal line onto the substrate.

[0039] In some possible implementations, the orthographic projections of the ground signal line and the compensation signal line onto the substrate overlap with the orthographic projections of the data line onto the substrate.

[0040] In some possible implementations, the compensation structure further includes: a third conductive layer and a third insulating layer located between the third conductive layer and the second conductive layer;

[0041] The orthographic projection of the third conductive layer onto the substrate overlaps with the orthographic projection of the second conductive layer onto the substrate.

[0042] In some possible implementations, the third conductive layer includes the third electrode of the compensation capacitor;

[0043] The third electrode of the compensation capacitor located in the third conductive layer is electrically connected to the second electrode of the compensation capacitor located in the second conductive layer through a via.

[0044] In some possible implementations, the length of the compensation capacitor along the second direction is less than the length of the selection transistor along the second direction.

[0045] The display device provided in this disclosure includes the display panel described above.

[0046] The display panel driving method described above, provided in this embodiment of the disclosure, includes:

[0047] A multiplexing circuit includes multiple selection transistors, at least two of the selection transistors having their first terminals connected to a source input signal line, the multiple selection transistors corresponding one-to-one with the multiple data lines, and the second terminal of any of the selection transistors being connected to the corresponding data line.

[0048] When the selection transistor is turned on, there is a first electric field between the active layer and the gate of the selection transistor; the compensation structure provided corresponding to the turned-on selection transistor generates a second electric field.

[0049] The first electric field is in the opposite direction to the second electric field. Attached Figure Description

[0050] Figure 1 is a schematic diagram of some structures of the display panel provided in the embodiments of this disclosure;

[0051] Figure 2 is a schematic cross-sectional view of some of the display panel structures provided in the embodiments of this disclosure;

[0052] Figure 3 is a schematic cross-sectional view of some other display panel structures provided in the embodiments of this disclosure;

[0053] Figure 4 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0054] Figure 5 is a timing diagram of some signals provided in the embodiments of this disclosure;

[0055] Figure 6 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0056] Figure 7 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0057] Figure 8 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0058] Figure 9 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0059] Figure 10 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0060] Figure 11 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0061] Figure 12 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0062] Figure 13 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0063] Figure 14 is a schematic cross-sectional view of the display panel provided in an embodiment of this disclosure;

[0064] Figure 15 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0065] Figure 16 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0066] Figure 17 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0067] Figure 18 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0068] Figure 19 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0069] Figure 20 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0070] Figure 21 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0071] Figure 22 is a schematic diagram of some of the structures of the display panel provided in the embodiments of this disclosure;

[0072] Figure 23 is a schematic cross-sectional view of a display panel provided in an embodiment of this disclosure. Detailed Implementation

[0073] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0074] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0075] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0076] The display panel provided in this embodiment of the present disclosure, as shown in FIG1, includes: a substrate 100;

[0077] Multiple data lines (e.g., DA1, DA2, DA3, DA4, DA5, DA6 in Figure 1) are disposed on the substrate 100;

[0078] Multiple source input lines (such as S1 and S2 in Figure 1) are disposed on the substrate 100;

[0079] The multiplexing circuit 110 includes multiple selection transistors (e.g., T11, T12, T13, T14, T15, and T16 in Figure 1). The first terminal of at least two selection transistors (e.g., T11, T13, and T15 or T12, T14, and T16 in Figure 1) is electrically connected to a source input signal line (e.g., S1 and S2 in Figure 1). The multiple selection transistors (e.g., T11, T12, T13, T14, T15, and T16 in Figure 1) are connected to multiple data lines (e.g., DA1, DA2, DA3, and DA4 in Figure 1). The selection transistors (e.g., T11, T12, T13, T14, T15, T16 in Figure 1) are connected one-to-one with the corresponding data lines (e.g., DA1, DA2, DA3, DA4, DA5, DA6 in Figure 1). When the selection transistors (e.g., T11, T12, T13, T14, T15, T16 in Figure 1) are turned on, there is a first electric field between the active layer and the gate of the selection transistors (e.g., T11, T12, T13, T14, T15, T16 in Figure 1).

[0080] Multiple compensation structures 120, corresponding to each selected transistor (e.g., T11, T12, T13, T14, T15, T16 in Figure 1), are configured to generate a second electric field;

[0081] The first electric field and the second electric field are in opposite directions.

[0082] This embodiment of the invention generates a second electric field by setting a compensation structure corresponding to each selection transistor. The first electric field and the second electric field are in opposite directions, so the first electric field and the second electric field can cancel each other out. That is, a controllable capacitor can be generated by setting the compensation structure. This controllable capacitor can cancel out the parasitic capacitance generated when the multiplexing circuit is working normally, thereby reducing the noise interference of the multiplexing circuit, achieving noise cancellation, and thus improving the display quality.

[0083] For example, as shown in Figure 1, compensation structure 120-1 is configured to correspond to selection transistor T11, compensation structure 120-2 is configured to correspond to selection transistor T12, compensation structure 120-3 is configured to correspond to selection transistor T13, compensation structure 120-4 is configured to correspond to selection transistor T14, compensation structure 120-5 is configured to correspond to selection transistor T15, and compensation structure 120-6 is configured to correspond to selection transistor T16.

[0084] For example, as shown in Figure 1, the first terminals of selection transistors T11, T13, and T15 are all electrically connected to the source signal line S1; the first terminals of selection transistors T12, T14, and T16 are all electrically connected to the source signal line S2; wherein, the second terminal of selection transistor T11 is electrically connected to the data line DA1; the second terminal of selection transistor T12 is electrically connected to the data line DA2; the second terminal of selection transistor T13 is electrically connected to the data line DA3; the second terminal of selection transistor T14 is electrically connected to the data line DA4; the second terminal of selection transistor T15 is electrically connected to the data line DA5; and the second terminal of selection transistor T16 is electrically connected to the data line DA6.

[0085] For example, as shown in FIG1, the substrate 100 further includes: selection signal lines SW1, SW2, and SW3; the gates of selection transistors T11 and T14 are electrically connected to selection signal line SW1; the gates of selection transistors T12 and T15 are electrically connected to selection signal line SW2; and the gates of selection transistors T13 and T16 are electrically connected to selection signal line SW3.

[0086] For example, selection transistors T11 and T14 can be turned on under the control of the effective level of the signal transmitted on selection signal line SW1, and turned off under the control of the ineffective level of the signal transmitted on selection signal line SW1. For instance, selection transistors T11 and T14 can be configured as N-type transistors, in which case the effective level of the signal transmitted on selection signal line SW1 is high, and the ineffective level of the signal transmitted on selection signal line SW1 is low. Alternatively, selection transistors T11 and T14 can be configured as P-type transistors, in which case the effective level of the signal transmitted on selection signal line SW1 is low, and the ineffective level of the signal transmitted on selection signal line SW1 is high.

[0087] For example, selection transistors T12 and T15 can be turned on under the control of the effective level of the signal transmitted on selection signal line SW2, and turned off under the control of the ineffective level of the signal transmitted on selection signal line SW2. For instance, selection transistors T12 and T15 can be configured as N-type transistors, in which case the effective level of the signal transmitted on selection signal line SW2 is high, and the ineffective level of the signal transmitted on selection signal line SW2 is low. Alternatively, selection transistors T12 and T15 can be configured as P-type transistors, in which case the effective level of the signal transmitted on selection signal line SW2 is low, and the ineffective level of the signal transmitted on selection signal line SW2 is high.

[0088] For example, selection transistors T13 and T16 can be turned on under the control of the effective level of the signal transmitted on selection signal line SW3, and turned off under the control of the ineffective level of the signal transmitted on selection signal line SW3. For instance, selection transistors T13 and T16 can be configured as N-type transistors, in which case the effective level of the signal transmitted on selection signal line SW3 is high, and the ineffective level of the signal transmitted on selection signal line SW3 is low. Alternatively, selection transistors T13 and T16 can be configured as P-type transistors, in which case the effective level of the signal transmitted on selection signal line SW3 is low, and the ineffective level of the signal transmitted on selection signal line SW3 is high.

[0089] For example, as shown in Figures 1 and 2, the multiplexing circuit 110 includes: a semiconductor layer 121, a first conductive layer 122, and a second conductive layer 123; a first insulating layer 124 is provided between the semiconductor layer 121 and the first conductive layer 122, and the orthographic projections of the semiconductor layer 121 and the first conductive layer 122 on the substrate 100 overlap; a second insulating layer 125 is provided between the first conductive layer 122 and the second conductive layer 123, and the orthographic projections of the semiconductor layer 121 and the second conductive layer 123 on the substrate overlap.

[0090] The semiconductor layer 121 includes an active layer for selection transistors (e.g., T11, T12, T13, T14, T15, T16 in FIG1); the first conductive layer 122 includes a gate for selection transistors (e.g., T11, T12, T13, T14, T15, T16 in FIG1); and the second conductive layer 123 includes a first electrode and a second electrode for selection transistors (e.g., T11, T12, T13, T14, T15, T16 in FIG1).

[0091] For example, as shown in Figure 2, the active layer of each selection transistor (e.g., T11, T12, T13, T14, T15, T16 in Figure 1) may include a source region S, a drain region D, and a channel region G between the source region S and the drain region D. It should be noted that the source and drain regions are heavily doped regions with good electronic conductivity, while the channel region is lightly doped and has low electronic conductivity. The source and drain regions may be regions doped with n-type or p-type impurities.

[0092] For example, as shown in FIG2, when any selection transistor (e.g., T11, T12, T13, T14, T15, T16 in FIG1) in the multiplexing circuit 110 is turned on, parasitic capacitances C1 and C2 are formed between the active layer and the gate of the turned selection transistor (e.g., T11, T12, T13, T14, T15, T16 in FIG1), thereby generating noise. The electric field of the parasitic capacitances C1 and C2 is the first electric field.

[0093] For example, the active layer of a partial selection transistor can be integrated into a single configuration.

[0094] In some embodiments of this disclosure, as shown in FIG3, the compensation structure 120 includes: a semiconductor layer 121, a first conductive layer 122, and a second conductive layer 123; a first insulating layer 124 is provided between the semiconductor layer 121 and the first conductive layer 122, and the orthographic projections of the semiconductor layer 121 and the first conductive layer 122 on the substrate 100 overlap; a second insulating layer 125 is provided between the first conductive layer 122 and the second conductive layer 123, and the orthographic projections of the semiconductor layer 121 and the second conductive layer 123 on the substrate overlap.

[0095] For example, as shown in Figures 2 and 3, the multiplexing circuit 110 and the compensation structure 120 further include: a third insulating layer 126 and a fourth insulating layer 127; the third insulating layer 126 is located on the side of the second conductive layer 123 away from the substrate 100 and between it and the semiconductor layer 121; the fourth insulating layer 127 is located between the substrate 100 and the semiconductor layer 121.

[0096] For example, the materials of the first conductive layer and the second conductive layer can be conductive materials. For example, conductive materials may include metal materials or alloy materials such as aluminum, molybdenum, and titanium, or metal oxides such as indium tin oxide (ITO). The embodiments of this disclosure do not limit the materials of each conductive layer.

[0097] For example, the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer are all formed of insulating materials. As needed, organic insulating materials, such as polyimide and resin materials, can be selected, or inorganic insulating materials, such as silicon oxide, silicon nitride, and silicon oxynitride, can be selected. The embodiments of this disclosure do not specifically limit the materials of each functional layer.

[0098] For example, the semiconductor layer may be formed by patterning a semiconductor material. For example, the semiconductor layer may be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc.

[0099] In some embodiments of this disclosure, as shown in Figures 3 and 4, the substrate 100 has compensation transistors T20 (e.g., T21, T22, T23, T24, T25, T26 in Figure 4);

[0100] Semiconductor layer 121 includes an active layer of compensation transistors (e.g., T21, T22, T23, T24, T25, T26 in FIG4), first conductive layer 122 includes the gate of compensation transistors (e.g., T21, T22, T23, T24, T25, T26 in FIG4), and second conductive layer 123 includes a first electrode and a second electrode of compensation transistors (e.g., T21, T22, T23, T24, T25, T26 in FIG4).

[0101] For example, as shown in Figure 3, the active layer of each compensation transistor (e.g., T21, T22, T23, T24, T25, and T26 in Figure 4) may include a source region S, a drain region D, and a channel region G between the source region S and the drain region D. It should be noted that the source and drain regions are heavily doped regions with good electronic conductivity, while the channel region is lightly doped and has low electronic conductivity. The source and drain regions may be regions doped with n-type or p-type impurities.

[0102] For example, as shown in Figure 3, when any selection transistor in the multiplexing circuit (e.g., T11, T12, T13, T14, T15, T16 in Figure 1) is turned on, reverse capacitors C10 and C20 are formed between the active layer and the gate of the compensation transistors (e.g., T21, T22, T23, T24, T25, T26 in Figure 4) in the compensation structure corresponding to the turned transistor (e.g., T11, T12, T13, T14, T15, T16 in Figure 1). The electric field of the reverse capacitors C10 and C20 is the second electric field. Then, the reverse capacitor C10 cancels the parasitic capacitor C1, and the reverse capacitor C20 cancels the parasitic capacitor C2, thereby avoiding the influence of noise in the multiplexer and improving the display quality.

[0103] In some embodiments of this disclosure, as shown in FIG4, the substrate 100 has a ground signal line GND and a compensation signal line (e.g., XSW1, XSW2, XSW3 in FIG4).

[0104] The gates of the compensation transistors (e.g., T21, T22, T23, T24, T25, T26 in Figure 4) are electrically connected to the compensation signal lines (e.g., XSW1, XSW2, XSW3 in Figure 4), and the first and second terminals of the compensation transistors (e.g., T21, T22, T23, T24, T25, T26 in Figure 4) are both electrically connected to the ground signal line GND.

[0105] For example, as shown in FIG4, the gates of compensation transistors T21 and T24 are electrically connected to compensation signal line XSW1; the gates of compensation transistors T22 and T25 are electrically connected to compensation signal line XSW2; and the gates of compensation transistors T23 and T26 are electrically connected to compensation signal line XSW3.

[0106] For example, the compensation signal lines XSW1, XSW2, XSW3, the selection signal lines SW1, SW2, SW3, and the ground signal line GND can all be located on the same layer, for example, on the second conductive layer 122; the source signal lines S1, S2, the gate of the compensation transistor, and the gate of the selection transistor can all be located on the same layer, for example, on the first conductive layer 121.

[0107] It should be noted that, as shown in Figure 5, the compensation signal line XSW1 and the selection signal line SW1 can be simultaneously loaded with opposite level signals; the compensation signal line XSW2 and the selection signal line SW2 can be simultaneously loaded with opposite level signals; and the compensation signal line XSW3 and the selection signal line SW3 can be simultaneously loaded with opposite level signals.

[0108] The following will use the structural diagram shown in Figure 4 as an example, combined with the signal timing diagram shown in Figure 5, for a detailed explanation:

[0109] As shown in Figure 5, clk represents the clock signal, and the time clk is high corresponds to the scan time of one row of sub-pixels; sw1 represents the signal loaded on the selection signal line SW1, sw2 represents the signal loaded on the selection signal line SW2, sw3 represents the signal loaded on the selection signal line SW3, da represents the data signal loaded on the data lines (e.g., DA1, DA2, DA3, DA4, DA5, DA6 in Figure 4), xsw1 represents the signal loaded on the compensation signal line XSW1, xsw2 represents the signal loaded on the compensation signal line XSW2, xsw3 represents the signal loaded on the compensation signal line XSW3, and gnd represents the signal loaded on the ground signal line GND.

[0110] During the first time period t1, the signal sw1 loaded on the selection signal line SW1 is at a high level, and the signal xsw1 loaded on the compensation signal line XSW1 is at a low level. Then, selection transistor T11 is turned on, providing the data signal on the source signal line S1 to the data line DA1, and selection transistor T14 is turned on, providing the data signal on the source signal line S2 to the data line DA4. Selection transistors T11 and T14 generate parasitic capacitance. Compensation transistors T21 and T24 generate reverse capacitance based on the low-level signal xsw1 loaded on the compensation signal line XSW1. Since compensation transistor T21 is configured to correspond with selection transistor T11, its reverse capacitance cancels out the parasitic capacitance of selection transistor T11. Similarly, since compensation transistor T24 is configured to correspond with selection transistor T14, its reverse capacitance cancels out the parasitic capacitance of selection transistor T14.

[0111] During the first time period t1, the signal sw1 loaded on the selection signal line SW1 is at a high level, and the signal xsw1 loaded on the compensation signal line XSW1 is at a low level. Then, selection transistor T11 is turned on, providing the data signal on the source signal line S1 to the data line DA1, and selection transistor T14 is turned on, providing the data signal on the source signal line S2 to the data line DA4. Selection transistors T11 and T14 generate parasitic capacitance. Compensation transistors T21 and T24 generate reverse capacitance based on the low-level signal xsw1 loaded on the compensation signal line XSW1. Since compensation transistor T21 is configured to correspond with selection transistor T11, its reverse capacitance cancels out the parasitic capacitance of selection transistor T11. Similarly, since compensation transistor T24 is configured to correspond with selection transistor T14, its reverse capacitance cancels out the parasitic capacitance of selection transistor T14.

[0112] During the second time period t2, the signal sw2 loaded on the selection signal line SW2 is at a high level, and the signal xsw2 loaded on the compensation signal line XSW2 is at a low level. Then, selection transistor T12 is turned on, providing the data signal on the source signal line S2 to the data line DA1, and selection transistor T15 is turned on, providing the data signal on the source signal line S1 to the data line DA5. Selection transistors T12 and T15 generate parasitic capacitance. Compensation transistors T22 and T25 generate reverse capacitance based on the low-level signal xsw2 loaded on the compensation signal line XSW2. Since compensation transistor T22 is configured to correspond with selection transistor T12, its reverse capacitance cancels out the parasitic capacitance of selection transistor T12. Similarly, since compensation transistor T25 is configured to correspond with selection transistor T15, its reverse capacitance cancels out the parasitic capacitance of selection transistor T15.

[0113] During the third time period t3, the signal sw3 loaded on the selection signal line SW3 is at a high level, and the signal xsw3 loaded on the compensation signal line XSW3 is at a low level. Then, selection transistor T13 is turned on, providing the data signal on the source signal line S1 to the data line DA3, and selection transistor T16 is turned on, providing the data signal on the source signal line S2 to the data line DA6. Selection transistors T13 and T16 generate parasitic capacitance. Compensation transistors T23 and T26 generate reverse capacitance based on the low-level signal xsw3 loaded on the compensation signal line XSW3. Since compensation transistor T23 is configured to correspond with selection transistor T13, its reverse capacitance cancels out the parasitic capacitance of selection transistor T13. Similarly, since compensation transistor T26 is configured to correspond with selection transistor T16, its reverse capacitance cancels out the parasitic capacitance of selection transistor T16.

[0114] In some embodiments of this disclosure, as shown in FIG6, the substrate in the display panel includes a display area AA and a non-display area BB (i.e., the area in the substrate excluding the area surrounded by the display area). The display area AA may include multiple pixel units PX arranged in an array. Each pixel unit PX includes multiple sub-pixels spx. A column of sub-pixels spx may correspond to an electrical connection to a data line (e.g., DA1, DA2, DA3, DA4, DA5, DA6). For example, each pixel unit PX may include a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B, thus enabling image display using red-green-blue color mixing. Of course, in practical applications, the emission color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here. Optionally, the display panel may be any one of a liquid crystal display panel (LCD), an organic light-emitting diode display panel (OLED), and an electronic paper display panel.

[0115] It should be noted that, as shown in Figure 5, r represents the voltage of the data signal required by the red sub-pixel R, g represents the voltage of the data signal required by the green sub-pixel G, and b represents the voltage of the data signal required by the blue sub-pixel B.

[0116] For example, the non-display area BB may include: a timing controller, a gate driving circuit, a source driving circuit, a compensation structure, and a multiplexing circuit; the timing controller may be electrically connected to the gate driving circuit and the source driving circuit. Generally, the gate driving circuit is located in the non-display areas on the left and right sides of the display panel. For example, the timing controller can acquire display data of the image to be displayed in the current display frame. The timing controller can input a control signal to the gate driving circuit, so that the gate driving circuit can output a scan signal to each gate line according to the input control signal, thereby driving each gate line to control the conduction of the transistors in the electrically connected sub-pixels. Furthermore, the timing controller inputs the acquired display data to the source driving circuit, so that the source driving circuit can input a data signal to the electrically connected source signal line according to the input display data. The multiplexing circuit inputs the data signal to the corresponding data line, thereby inputting the data signal on the data line to the sub-pixel through the conducting transistor, charging the pixel electrode of the sub-pixel, and thus charging the pixel electrode of each sub-pixel with the corresponding data signal to achieve the image display function. It should be noted that the pixel array structure disclosed herein can also be a dual-gate structure, that is, two gate lines are set between two adjacent rows of sub-pixels. This arrangement can reduce the number of data lines by half, that is, it includes data lines between two adjacent columns of sub-pixels, and does not include data lines between two adjacent columns of sub-pixels. The specific pixel arrangement structure, data lines, and gate line arrangement are not limited.

[0117] In some embodiments of this disclosure, as shown in FIG7, the orthogonal projections of compensation transistors T21, T22, T23, T24, T25, and T26 onto the substrate 100 are located between the orthogonal projections of the ground signal line GND and the compensation signal lines XSW1, XSW2, and XSW3 onto the substrate 100.

[0118] In some embodiments of this disclosure, the area of ​​the channel region in the active layer of the compensation transistor and the area of ​​the channel region in the active layer of the selection transistor projected onto the substrate are the same.

[0119] For example, as shown in FIG7, the channel region in the active layer of compensation transistor T21 has the same area as the channel region in the active layer of selection transistor T11 projected onto the substrate. The channel region in the active layer of compensation transistor T22 has the same area as the channel region in the active layer of selection transistor T12 projected onto the substrate. The channel region in the active layer of compensation transistor T23 has the same area as the channel region in the active layer of selection transistor T13 projected onto the substrate. The channel region in the active layer of compensation transistor T24 has the same area as the channel region in the active layer of selection transistor T14 projected onto the substrate. The channel region in the active layer of compensation transistor T25 has the same area as the channel region in the active layer of selection transistor T15 projected onto the substrate. The channel region in the active layer of compensation transistor T26 has the same area as the channel region in the active layer of selection transistor T16 projected onto the substrate.

[0120] It should be noted that by making the area of ​​the channel region in the active layer of the compensation transistor and the area of ​​the channel region in the active layer of the selection transistor the same as the area of ​​the orthogonal projection onto the substrate, it can be ensured that the parasitic capacitance of the selection transistor and the reverse capacitance of the compensation transistor can just cancel each other out, thus avoiding the parasitic capacitance of the selection transistor and the reverse capacitance of the compensation transistor being unbalanced, and further ensuring display quality.

[0121] For example, as shown in Figure 7, the active layers of selection transistors T11 and T15 are integrated, and the active layers of selection transistors T14 and T16 are integrated. This can improve the space utilization of the substrate and is beneficial for product designs with narrow bezels.

[0122] In some embodiments of this disclosure, as shown in FIG7, the width of the active layer of the compensation transistor T26 along the first direction F1 is a first width W1, and the width of the active layer of the selection transistor T16 along the first direction F1 is a second width W2, wherein the first width W1 and the second width W2 are the same.

[0123] In some embodiments of this disclosure, as shown in FIG7, the length of the active layer of the compensation transistor T26 along the second direction F2 is a first length L1, and the length of the active layer of the selection transistor T16 along the second direction F2 is a second length L2, wherein the first length L1 and the second length L2 are the same.

[0124] Figure 8 shows other structural schematic diagrams of display panels provided in this disclosure, which are modifications of the implementation methods of the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0125] In some embodiments of this disclosure, as shown in FIG8, compensation structure 120-1 is configured to correspond to selection transistor T11 and selection transistor T14, compensation structure 120-2 is configured to correspond to selection transistor T12 and selection transistor T15, and compensation structure 120-3 is configured to correspond to selection transistor T13 and selection transistor T16.

[0126] For example, as shown in FIG9, the gate of compensation transistor T21 is electrically connected to compensation signal line XSW1, the gate of compensation transistor T22 is electrically connected to compensation signal line XSW2, and the gate of compensation transistor T23 is electrically connected to compensation signal line XSW3.

[0127] In some embodiments of this disclosure, as shown in FIG10, the width of the active layer of the compensation transistors T21, T22, and T23 along the first direction F1 is the first width W1, and the width of the active layer of the selected transistors T11, T12, T13, T14, T15, and T16 along the first direction F1 is the second width W2, wherein the first width W1 is greater than the second width W2.

[0128] In some embodiments of this disclosure, as shown in FIG10, the second width W2 is three-fifths of the first width W1.

[0129] In some embodiments of this disclosure, as shown in FIG10, the length of the active layer of the compensation transistors T21, T22, and T23 along the second direction F2 is the first length L1, and the length of the active layer of the selected transistors T11, T12, T13, T14, T15, and T16 along the second direction F2 is the second length L2, wherein the first length L1 is less than the second length L2.

[0130] In some embodiments of this disclosure, as shown in FIG10, the second length L2 is twice the first length L1.

[0131] This embodiment of the invention reduces the length of the active layer of the compensation transistor and increases the width of the active layer of the compensation transistor, thereby enabling the display panel to have a narrow bezel without affecting the size of the reverse capacitance of the compensation transistor. This can offset the parasitic capacitance of the selection transistor and prevent noise from affecting the display quality.

[0132] Figure 11 shows a schematic diagram of the structure of some display panels provided in this disclosure, which are modifications of the implementation methods of the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0133] In some embodiments of this disclosure, as shown in Figures 3 and 11, the substrate 100 has conducting transistors T30 (e.g., T31, T32, T33, T34, T35, T36 in Figure 11); the conducting transistors (e.g., T31, T32, T33, T34, T35, T36 in Figure 11) and the compensation transistors (e.g., T21, T22, T23, T24, T25, T26 in Figure 11) are correspondingly arranged;

[0134] Semiconductor layer 121 includes an active layer of conducting transistors (e.g., T31, T32, T33, T34, T35, T36 in FIG11), first conductive layer 122 includes the gate of conducting transistors (e.g., T31, T32, T33, T34, T35, T36 in FIG11), and second conductive layer 123 includes the first electrode and the second electrode of conducting transistors (e.g., T31, T32, T33, T34, T35, T36 in FIG11).

[0135] In some embodiments of this disclosure, a selection signal line is provided on the substrate; the gate of the conducting transistor is electrically connected to the selection signal line, the first terminal of the conducting transistor is electrically connected to the ground signal line, and the second terminal of the conducting transistor is electrically connected to the first and second terminals of the compensation transistor.

[0136] For example, as shown in Figure 11, the gate of the turn-on transistor T31 is electrically connected to the selection signal line SW1, the first terminal of the turn-on transistor T31 is electrically connected to the ground signal line GND, and the second terminal of the turn-on transistor T31 is electrically connected to the first and second terminals of the compensation transistor T21. The gate of the turn-on transistor T32 is electrically connected to the selection signal line SW2, the first terminal of the turn-on transistor T32 is electrically connected to the ground signal line GND, and the second terminal of the turn-on transistor T32 is electrically connected to the first and second terminals of the compensation transistor T22. The gate of the turn-on transistor T33 is electrically connected to the selection signal line SW3, the first terminal of the turn-on transistor T33 is electrically connected to the ground signal line GND, and the second terminal of the turn-on transistor T33 is electrically connected to the first and second terminals of the compensation transistor T23. The gate of the turn-on transistor T34 is electrically connected to the selection signal line SW1, the first terminal of the turn-on transistor T34 is electrically connected to the ground signal line GND, and the second terminal of the turn-on transistor T34 is electrically connected to the first and second terminals of the compensation transistor T24. The gate of transistor T35 is electrically connected to the select signal line SW2. The first terminal of transistor T35 is electrically connected to the ground signal line GND. The second terminal of transistor T35 is electrically connected to the first and second terminals of compensation transistor T25. The gate of transistor T36 is electrically connected to the select signal line SW3. The first terminal of transistor T36 is electrically connected to the ground signal line GND. The second terminal of transistor T36 is electrically connected to the first and second terminals of compensation transistor T26.

[0137] For example, since the selection signal line and the compensation signal line may have different lengths, the transmission rates of the signals on the selection signal line and the compensation signal line may be different. As a result, the signals on the selection signal line and the compensation signal line may not be synchronized. Therefore, the time when the compensation transistor in the compensation structure forms the second electric field may be later or earlier than the time when the selection transistor in the multiplexing circuit forms the first electric field. However, the embodiments of this disclosure include a conducting transistor and a compensation transistor in the compensation structure. That is, under the control of the signal from the selection signal line, the conducting transistor can provide the signal from the grounding signal line to the compensation transistor, thereby controlling the time when the compensation transistor in the compensation structure forms the second electric field to be synchronized with the time when the selection transistor in the multiplexing circuit forms the first electric field, thereby achieving precise noise reduction and further improving display quality.

[0138] In some embodiments of this disclosure, as shown in FIG12, the orthogonal projections of the turn-on transistors T31, T32, T33, T34, T35, and T36 onto the substrate 100 are located between the orthogonal projections of the ground signal line GND and the select signal lines SW1, SW2, and SW3 onto the substrate 100.

[0139] In some embodiments of this disclosure, as shown in FIG12, the area of ​​the active layer of the conducting transistors T33 and T36 projected onto the substrate 100 is smaller than the area of ​​the active layer of the compensation transistors T23 and TT26 on the substrate 100.

[0140] In some embodiments of this disclosure, as shown in FIG12, the active layers of at least two conducting transistors T31 and T35 are integrated. The active layers of at least two conducting transistors T32 and T34 are also integrated.

[0141] For example, the width of the active layer of the conducting transistors T31 and T35 along the first direction F1 is equal to the width of the active layer of the selecting transistors T11 and T15 along the first direction F1; the width of the active layer of the conducting transistors T32 and T34 along the first direction F1 is equal to the width of the active layer of the selecting transistors T12 and T14 along the first direction F1.

[0142] For example, as shown in FIG12, the active layer of the turn-on transistor T36 has a third width W3 along the first direction F1, and the active layer of the compensation transistor T26 has a first width W1 along the first direction F1. The third width W3 is the same as the first width W1.

[0143] For example, as shown in FIG12, the active layer of the turn-on transistor T36 has a length of the third length L3 along the second direction F2, and the active layer of the compensation transistor T26 has a length of the first length L1 along the second direction F2, and the first length L1 is six times the third length L3.

[0144] Figure 13 shows a schematic diagram of the structure of some display panels provided in this disclosure, which are modifications of the implementation methods of the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0145] In some embodiments of this disclosure, as shown in Figures 13 and 14, the substrate 100 has compensation capacitors (e.g., C11, C12, C13, C14, C15, C16 in Figure 13); the first conductive layer 122 and the second conductive layer 123 overlap in their orthographic projections onto the substrate 100; the first conductive layer 122 includes a first electrode of the compensation capacitors (e.g., C11, C12, C13, C14, C15, C16 in Figure 13), and the second conductive layer 123 includes a second electrode of the compensation capacitors (e.g., C11, C12, C13, C14, C15, C16 in Figure 13).

[0146] In some embodiments of this disclosure, as shown in FIG13, the substrate 100 has a ground signal line GND and multiple compensation signal lines (e.g., XSW1, XSW2, XSW3 in FIG13).

[0147] The first electrode of the compensation capacitor (e.g., C11, C12, C13, C14, C15, C16 in Figure 13) is electrically connected to the compensation signal line (e.g., XSW1, XSW2, XSW3 in Figure 13), and the second electrode of the compensation capacitor (e.g., C11, C12, C13, C14, C15, C16 in Figure 13) is electrically connected to the ground signal line GND.

[0148] It should be noted that the capacitance value of the compensation capacitor is calculated according to the formula: C = εS / 4πkd, where ε is the dielectric constant, S is the overlapping area of ​​the plates of the compensation capacitor, d is the distance between the plates, and k is the electrostatic constant. In specific implementation, the capacitance value of the compensation capacitor is calculated based on the parasitic capacitance generated by the selection transistor and the actual structure of the compensation capacitor (the number of insulating layers between the conductive layers and the dielectric constant), so that the capacitance value of the compensation capacitor can cancel out the capacitance value of the parasitic capacitance generated by the selection transistor.

[0149] For example, as shown in Figure 13, the first plates of compensation capacitors C11 and C14 are electrically connected to compensation signal line XSW1; the first plates of compensation capacitors C12 and C15 are electrically connected to compensation signal line XSW2; and the first plates of compensation capacitors C13 and C16 are electrically connected to compensation signal line XSW3.

[0150] In some embodiments of this disclosure, as shown in FIG15, the orthogonal projection of the compensation capacitors (e.g., C11, C12, C13, C14, C15, C16 in FIG15) onto the substrate 100 is located between the ground signal line GND and the orthogonal projection of the compensation signal lines (e.g., XSW1, XSW2, XSW3 in FIG15) onto the substrate 100.

[0151] In some embodiments of this disclosure, as shown in FIG15, the orthographic projections of the ground signal line GND and the compensation signal lines (e.g., XSW1, XSW2, XSW3 in FIG15) onto the substrate 100 overlap with the orthographic projections of the source signal lines (e.g., S1, S2 in FIG15) onto the substrate 100.

[0152] In some embodiments of this disclosure, as shown in FIG15, the orthographic projections of the ground signal line GND and the compensation signal lines (e.g., XSW1, XSW2, XSW3 in FIG15) onto the substrate 100 overlap with the orthographic projections of the data lines (e.g., DA1, DA2, DA3, DA4, DA5, DA6 in FIG15) onto the substrate 100.

[0153] For example, as shown in Figure 15, compensation capacitors C12, C14, and C16 are located on both sides of the multiplexing circuit, which surrounds the multiplexing circuit. This not only cancels out the parasitic capacitance in the multiplexing circuit, but also isolates the multiplexing circuit from the display area of ​​the display panel, thereby further avoiding the influence of the parasitic capacitance in the multiplexing circuit on the display area of ​​the display panel.

[0154] For example, the display panel can be an irregularly shaped display panel; an irregularly shaped display panel is an unconventional display panel design that breaks away from the conventional rectangular or square display panels, adopting various irregular shapes and sizes to meet specific scenarios or needs. Irregularly shaped display panels are gradually becoming the mainstream direction for products such as automotive display products and wearable display products. The structure shown in Figure 15 can be used for irregularly shaped display panels and can better fit the arc or curve design of irregularly shaped display panels.

[0155] For example, the irregularly shaped display panel can be as shown in Figures 16, 17, 18, 19, 20, and 21. Of course, other irregularly shaped display panels can also be used, and there are no restrictions here. In Figures 17 and 18, the camera TCM can be set in the position shown in the figure.

[0156] Figure 22 shows a schematic diagram of the structure of some display panels provided in this disclosure, which are modifications of the implementation methods of the above embodiments. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0157] In some embodiments of this disclosure, as shown in FIG23, the compensation structure further includes: a third conductive layer 124 and a third insulating layer 126 located between the third conductive layer 124 and the second conductive layer 123; wherein the orthographic projection of the third conductive layer 124 on the substrate 100 overlaps with the orthographic projection of the second conductive layer 123 on the substrate 100.

[0158] In some embodiments of this disclosure, as shown in Figures 22 and 23, the third conductive layer 124 includes the third electrode of a compensation capacitor (e.g., C11, C12, C13, C14, C15, C16 in Figure 22).

[0159] The third electrode of the compensation capacitor (e.g., C11, C12, C13, C14, C15, C16 in FIG22) located in the third conductive layer 124 is electrically connected to the second electrode of the compensation capacitor (e.g., C11, C12, C13, C14, C15, C16 in FIG22) located in the second conductive layer 122 through a via.

[0160] For example, each sub-pixel includes a pixel electrode, wherein the pixel electrode may be disposed in the same layer as the third electrode of the compensation capacitor.

[0161] In this embodiment, the compensation capacitor is relatively small, which is beneficial for achieving a narrow bezel on the display panel. Furthermore, since the compensation capacitor is a three-layer plate, even if the size of the compensation capacitor is reduced, the capacitance value of the compensation capacitor will not decrease. Therefore, while saving space, it can also ensure that the compensation capacitor can offset the parasitic capacitance in the multiplexing circuit.

[0162] In some embodiments of this disclosure, as shown in FIG22, the length L0 of the compensation capacitors (e.g., C11, C12, C13, C14, C15, C16 in FIG22) along the second direction F2 is less than the length L2 of the selection transistors (e.g., T11, T12, T13, T14, T15, T16 in FIG22) along the second direction F2.

[0163] For example, the length L0 of the compensation capacitor (e.g., C11, C12, C13, C14, C15, C16 in FIG22) along the second direction F2 is half the length L2 of the selection transistor (e.g., T11, T12, T13, T14, T15, T16 in FIG22) along the second direction F2.

[0164] For example, the width W0 of the compensation capacitor (e.g., C11, C12, C13, C14, C15, C16 in FIG22) along the first direction F1 is the same as the width W2 of the selection transistor (e.g., T11, T12, T13, T14, T15, T16 in FIG22) along the first direction F1.

[0165] It should be noted that the above-described embodiments are based on the MUX2:6 circuit only, and can be extended to MUX2:4, MUX2:8, MUX2:10 and other circuits.

[0166] This disclosure also provides a driving method for the above-mentioned display panel, including:

[0167] A multiplexing circuit includes multiple selection transistors, at least two selection transistors have their first terminals connected to a source input signal line, the multiple selection transistors correspond one-to-one with multiple data lines, and the second terminal of any selection transistor is connected to the corresponding data line.

[0168] When the selection transistor is turned on, there is a first electric field between the active layer and the gate of the selection transistor; the compensation structure provided corresponding to the turned-on selection transistor generates a second electric field.

[0169] The first electric field and the second electric field are in opposite directions.

[0170] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Implementation of this display device can refer to the embodiments of the display panel described above; repeated details will not be repeated.

[0171] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0172] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0173] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. A display panel, wherein, include: Substrate; Multiple data lines are disposed on the substrate. Multiple source input lines are disposed on the substrate. A multiplexing circuit includes multiple selection transistors, at least two of the selection transistors having their first terminals electrically connected to a source input signal line, the multiple selection transistors corresponding one-to-one with the multiple data lines, and the second terminal of any selection transistor being electrically connected to the corresponding data line; when a selection transistor is turned on, a first electric field exists between the active layer and the gate of the selection transistor. Multiple compensation structures, corresponding to each of the selected transistors, are configured to generate a second electric field; The first electric field is in the opposite direction to the second electric field.

2. The display panel as claimed in claim 1, wherein, The compensation structure includes: a semiconductor layer, a first conductive layer, and a second conductive layer; A first insulating layer is provided between the semiconductor layer and the first conductive layer, and the semiconductor layer and the first conductive layer overlap in the orthographic projection of the substrate. A second insulating layer is provided between the first conductive layer and the second conductive layer, and the semiconductor layer and the second conductive layer overlap in the orthographic projection of the substrate.

3. The display panel as described in claim 2, wherein, The substrate has a compensation transistor; The semiconductor layer includes the active layer of the compensation transistor, the first conductive layer includes the gate of the compensation transistor, and the second conductive layer includes the first electrode and the second electrode of the compensation transistor.

4. The display panel as claimed in claim 3, wherein, The substrate has a ground signal line and a compensation signal line. The gate of the compensation transistor is electrically connected to the compensation signal line, and both the first and second terminals of the compensation transistor are electrically connected to the ground signal line.

5. The display panel as claimed in claim 4, wherein, The orthographic projection of the compensation transistor onto the substrate lies between the orthographic projections of the ground signal line and the compensation signal line onto the substrate.

6. The display panel as claimed in claim 4, wherein, The channel region in the active layer of the compensation transistor and the channel region in the active layer of the selection transistor have the same area when projected onto the substrate.

7. The display panel as claimed in claim 6, wherein, The active layer of the compensation transistor has a first width along the first direction, and the active layer of the selection transistor has a second width along the first direction, wherein the first width and the second width are the same.

8. The display panel as claimed in claim 7, wherein, The active layer of the compensation transistor has a first length along the second direction, and the active layer of the selection transistor has a second length along the second direction, wherein the first length and the second length are the same.

9. The display panel as claimed in claim 6, wherein, The active layer of the compensation transistor has a first width along the first direction, and the active layer of the selection transistor has a second width along the first direction, wherein the first width is greater than the second width.

10. The display panel as claimed in claim 9, wherein, The second width is three-fifths of the first width.

11. The display panel as claimed in claim 9, wherein, The active layer of the compensation transistor has a first length along the second direction, and the active layer of the selection transistor has a second length along the second direction, wherein the first length is less than the second length.

12. The display panel as claimed in claim 11, wherein, The second length is twice the first length.

13. The display panel according to any one of claims 4-12, wherein, The substrate has a conducting transistor; the conducting transistor and the compensation transistor are arranged correspondingly. The semiconductor layer includes the active layer of the conducting transistor, the first conductive layer includes the gate of the conducting transistor, and the second conductive layer includes the first electrode and the second electrode of the conducting transistor.

14. The display panel as claimed in claim 13, wherein, The substrate has a selection signal line; The gate of the conducting transistor is electrically connected to the selection signal line, the first terminal of the conducting transistor is electrically connected to the ground signal line, and the second terminal of the conducting transistor is electrically connected to the first and second terminals of the compensation transistor.

15. The display panel as claimed in claim 14, wherein, The orthographic projection of the conducting transistor on the substrate lies between the orthographic projections of the ground signal line and the select signal line on the substrate.

16. The display panel as claimed in claim 14, wherein, The area of ​​the active layer of the conducting transistor projected onto the substrate is smaller than the area of ​​the active layer of the compensation transistor on the substrate.

17. The display panel as claimed in claim 14, wherein, The active layer of at least two conducting transistors is integrated.

18. The display panel according to any one of claims 2-17, wherein, The substrate has a compensation capacitor. The first conductive layer and the second conductive layer overlap in their orthographic projections onto the substrate. The first conductive layer includes the first electrode of the compensation capacitor, and the second conductive layer includes the second electrode of the compensation capacitor.

19. The display panel as claimed in claim 18, wherein, The substrate has a ground signal line and multiple compensation signal lines. The first electrode of the compensation capacitor is electrically connected to the compensation signal line, and the second electrode of the compensation capacitor is electrically connected to the ground signal line.

20. The display panel as claimed in claim 19, wherein, The compensation capacitor's orthogonal projection onto the substrate lies between the ground signal line and the compensation signal line's orthogonal projection onto the substrate.

21. The display panel as claimed in claim 20, wherein, The orthographic projections of the grounding signal line and the compensation signal line onto the substrate overlap with the orthographic projection of the source signal line onto the substrate.

22. The display panel as claimed in claim 20, wherein, The orthographic projections of the grounding signal line and the compensation signal line onto the substrate overlap with the orthographic projections of the data line onto the substrate.

23. The display panel as claimed in claim 18, wherein, The compensation structure further includes: a third conductive layer and a third insulating layer located between the third conductive layer and the second conductive layer; The orthographic projection of the third conductive layer onto the substrate overlaps with the orthographic projection of the second conductive layer onto the substrate.

24. The display panel as claimed in claim 23, wherein, The third conductive layer includes the third electrode of the compensation capacitor; The third electrode of the compensation capacitor located in the third conductive layer is electrically connected to the second electrode of the compensation capacitor located in the second conductive layer through a via.

25. The display panel as claimed in claim 24, wherein, The length of the compensation capacitor along the second direction is less than the length of the selection transistor along the second direction.

26. A display device, wherein, include: The display panel as described in any one of claims 1-25.

27. A driving method for a display panel as described in any one of claims 1-25, wherein, include: A multiplexing circuit includes multiple selection transistors, at least two of the selection transistors having their first terminals connected to a source input signal line, the multiple selection transistors corresponding one-to-one with the multiple data lines, and the second terminal of any of the selection transistors being connected to the corresponding data line. When the selection transistor is turned on, there is a first electric field between the active layer and the gate of the selection transistor; A compensation structure corresponding to the selected transistor that is turned on generates a second electric field; The first electric field is in the opposite direction to the second electric field.

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