Semiconductor design system and semiconductor design method

Abstract

The present invention is a semiconductor design system that acquires semiconductor design data designed by a customer, and, on the basis of the acquired design data, obtains semiconductor design data for manufacturing a semiconductor. The semiconductor design system comprises: a manufacturing condition optimization unit that acquires design data designed by a customer and performs manufacturing condition optimization thereon to obtains design data; and a design environment optimization processing unit that acquires the design data subjected to the manufacturing condition optimization by the manufacturing condition optimization unit, performs design environment optimization thereon to obtain change content data, and transmits the obtained change content data to the customer, wherein design data that has been changed on the basis of the change content data is acquired from the customer.

Description

Semiconductor Design System and Semiconductor Design Method

[0001] The present invention relates to a semiconductor design system and a semiconductor design method suitable for application to semiconductor design.

[0002] Conventionally, general-purpose semiconductors that can be mounted on various products have been mass-produced. General-purpose semiconductors are, for example, CPUs (Central Processing Units) mounted on personal computers. General-purpose semiconductors based on the conventional von Neumann architecture have been designed to have high sequential processing performance.

[0003] According to Moore's law, it is considered that the production cost of semiconductors can be reduced by increasing the integration density. Therefore, the main goal of conventional semiconductors has been to increase the production volume of general-purpose semiconductors and reduce the production cost. However, a large amount of equipment investment is required to increase the production volume of semiconductors. For this reason, the fabless production method, in which the company mainly responsible for semiconductor design entrusts the production of semiconductors to an external company, has become the mainstream.

[0004] Patent Document 1 discloses a technique related to lithography-based pattern optimization.

[0005] U.S. Patent No. 11,449,659

[0006] By the way, semiconductors not only have the problem of lengthening the TAT (turn-around-time) in the packaging process of semiconductor manufacturing, but also the rules and constraints of semiconductor design have become more complex with the progress of miniaturization, resulting in a longer design period. Therefore, when a problem is found in the design of semiconductor development, rework of design and manufacturing (prototyping) is required, which requires a huge amount of time and cost. Therefore, a design method with less rework has been demanded during semiconductor design.

[0007] In current semiconductor manufacturing methods, it is common for companies that design semiconductors (customers) and companies that manufacture semiconductors (foundries) to exist separately. Therefore, semiconductor manufacturers only learn about optimal manufacturing conditions and the causes of failures after manufacturing semiconductors based on design information from the design companies. In other words, optimal manufacturing conditions and the causes of failures were not shared between semiconductor manufacturers and semiconductor designers.

[0008] Even if the optimal manufacturing conditions and causes of failure were shared between semiconductor design companies and semiconductor manufacturing companies, semiconductor design companies often had to go through a lot of trial and error because they didn't know how to design the semiconductor optimally. Consequently, semiconductor design companies spent a lot of time on conventional semiconductor design. Furthermore, even when semiconductor design companies used the technology disclosed in Patent Document 1, they still required a lot of design time.

[0009] Figure 7 shows an example of the time taken during semiconductor design using a conventional method, as a time series transition. The upper part of Figure 7 is the rehearsal process for the actual design, called the dry run, and the lower part is the design process for the semiconductor that will actually be manufactured, called the main run. First, the first design process ST1 is executed. In this first design process ST1 and the following second design process ST2, there is no distinction between the dry run and the main run. In the first design process ST1, a semiconductor circuit is designed to generate the functions to be realized in the required semiconductor. At this stage of the first design process ST1, a check for conformity to predetermined design rules, called DRC (Design Rule Check), is not performed. In other words, in the first design process ST1, the state is DRC NO Clean.

[0010] Furthermore, in the first design process ST1, a check called STA (Static Timing Analysis), which verifies delays in the circuit path from input to output to ensure that timing conditions are met, is not performed. In other words, the first design process ST1 is in a state of no STA check (STA NO Clean).

[0011] Next, in the second design process ST2, the semiconductor circuit data obtained in the first design process ST1 is modified to become a circuit that has completed the DRC check (DRC Clean). However, even in this second design process ST2, the STA (Static Timing Analysis) check remains unchecked (STA NO Clean). The first design process ST1 and the second design process ST2 up to this point are basically performed by the customer.

[0012] Then, in the second design process ST2, the semiconductor circuit data that has passed the DRC check (DRC Clean) is passed on to the customer for the third design process ST3, where it is checked for STA (STA Clean). This third design process ST3 is executed as the main run, and the process of creating circuit data that can actually be manufactured is completed.

[0013] In this third design process ST3, expertise in semiconductor manufacturing is required to complete the DRC check (DRC Clean) and the STA check (STA Clean). For this reason, the foundry executes the manufacturing condition optimization process ST4 as a dry run. In the manufacturing condition optimization process ST4, it is determined which parts of the semiconductor circuit data obtained in the second design process ST2 need to be modified in order to optimize the manufacturing conditions.

[0014] Then, the parts that the manufacturing conditions optimization process ST4 determines need to be modified are passed on to the customer's third design process ST3. In this third design process ST3, a design change process ST5 is executed in which the foundry instructs the customer to modify the circuit being designed. The customer completes the design in the third design process ST3 while receiving instructions from the design change process ST5 as needed. As a result, the data of the completed semiconductor circuit is passed on to the foundry, and the wafer and package manufacturing process ST6 is executed.

[0015] In the conventional semiconductor design shown in Figure 7, the third design process ST3, which is a modification process performed by the customer, had the problem of requiring a large number of personnel and a long design period (for example, several months). Furthermore, if the design changes in the third design process ST3 were not appropriate, instructions from the foundry's design change process ST5 could occur frequently with each design change, which would further prolong the design process.

[0016] This invention was made in view of the above circumstances, and aims to provide a semiconductor design system and a semiconductor design method that can reduce the time and effort required for semiconductor design.

[0017] The semiconductor design system according to the present invention is a semiconductor design system that acquires semiconductor design data designed by a customer and obtains semiconductor design data for manufacturing the semiconductor based on the acquired design data. The semiconductor design system comprises a manufacturing condition optimization unit that acquires design data designed by a customer and obtains design data with optimized manufacturing conditions, and a design environment optimization processing unit that acquires the design data with optimized manufacturing conditions from the manufacturing condition optimization unit, obtains change data with optimized design environment, and transmits the obtained change data to the customer. Then, the system acquires the design data with changes based on the change data from the customer.

[0018] Furthermore, the semiconductor design method according to the present invention is a semiconductor design method in which a computer performs a process to obtain semiconductor design data for manufacturing the semiconductor based on the acquired design data, after acquiring design data for a semiconductor designed by a customer. The process in which the computer performs the semiconductor design method includes a manufacturing condition optimization process that acquires design data designed by a customer and obtains design data with optimized manufacturing conditions, and a design environment optimization process that acquires the design data with optimized manufacturing conditions obtained through the manufacturing condition optimization process, obtains change data with optimized design environment, and transmits the obtained change data to the customer, thereby acquiring design data with changes based on the change data from the customer.

[0019] According to the present invention, the optimal conditions for semiconductor design and manufacturing can be calculated and reflected in the customer's design data, thereby reducing the time and man-hours required for semiconductor design.

[0020] This figure shows an example of a system configuration according to one embodiment of the present invention. This figure shows the time-series transition of the design process according to one embodiment of the present invention. This flowchart shows the details of the design process according to one embodiment of the present invention. This characteristic diagram shows an example of parameter distribution according to one embodiment of the present invention. This characteristic diagram shows an example of parameter variation according to one embodiment of the present invention. This figure shows an example of design modification according to one embodiment of the present invention. This figure shows the time-series transition of each process during conventional semiconductor design.

[0021] Hereinafter, a semiconductor design system and semiconductor design method according to one embodiment of the present invention (hereinafter referred to as "this example") will be described with reference to Figures 1 to 6.

[0022] [Configuration of the Semiconductor Design System] Figure 1 shows an example configuration of the semiconductor design system in this example. The semiconductor design system shown in Figure 1 shows a configuration in which a semiconductor designer 100 performs the design and a configuration in which a semiconductor manufacturer 200 supports the design. In the following description, the designer 100 will be referred to as the customer and the manufacturer 200 as the foundry. Furthermore, each processing unit, such as the semiconductor design unit and the manufacturing condition optimization unit described below, is composed of one or more computer terminals. When composed of multiple computer terminals, for example, design and modification are performed in block units into which a single semiconductor is divided on each computer terminal.

[0023] To explain the configuration shown in Figure 1, customer 100 comprises a first semiconductor design unit 101 and a second semiconductor design unit 102. In each of these semiconductor design units 101 and 102, designers belonging to customer 100 use a PC (personal computer) or the like to design semiconductors that realize the desired functions. Primarily, the first semiconductor design unit 101 performs basic semiconductor design processing, while the second semiconductor design unit 102 performs design change processing to update the design data. In other words, the second semiconductor design unit 102 functions as a design data update unit.

[0024] The semiconductor design data D1 obtained when the design process begins in the first semiconductor design unit 101 is passed to the foundry 200. Additionally, design data D2 obtained when the design process has progressed to a certain extent in the first semiconductor design unit 101 is also passed to the foundry 200.

[0025] The foundry 200 comprises a manufacturing condition optimization unit 201, a design environment optimization unit 202, and a semiconductor manufacturing apparatus 203. The manufacturing condition optimization unit 201 acquires the initial design data D1 provided by the customer 100 and performs manufacturing condition optimization processing. This manufacturing condition optimization processing in the manufacturing condition optimization unit 201 is a process for optimizing the manufacturing conditions in the semiconductor manufacturing apparatus 203. As part of the manufacturing condition optimization processing, for example, processes such as appropriately correcting parts of the mask layout (mask data) that are not suitable for manufacturing, and optimizing parts that violate mask design standards are executed.

[0026] Furthermore, during the manufacturing condition optimization process in the manufacturing condition optimization unit 201, the big data 204 held by the foundry 200 is referenced and optimization is performed. The big data 204 is stored data in a database that accumulates past design data, and is data from past manufacturing and design operations at the foundry 200. The manufacturing condition optimization unit 201 references the past knowledge accumulated in the big data 204 and performs optimization of the design data D1.

[0027] Furthermore, the big data 204 may not only include accumulated past design data, but may also include data learned by an AI (Artificial Intelligence) model, for example. In other words, silicon big data measured by various measuring devices in the wafer process and packaging process of the semiconductor manufacturing equipment 203 may be used as training data to train the AI ​​model. By making the data learned by the AI ​​model from the data obtained in the manufacturing process into big data 204, the performance of the PDK (Process Design Kit) is improved. Note that the data obtained in the wafer process and packaging process of the semiconductor manufacturing equipment 203 in this example is single-wafer data. Single-wafer data will be described later in Figures 4 and 5.

[0028] When the optimization process is executed in the manufacturing conditions optimization unit 201, change data is supplied to the design environment optimization unit 202. The design environment optimization unit 202 acquires design data D2 from the customer 100, which has progressed to a certain stage of design. Then, the design environment optimization unit 202 applies the changes obtained from the manufacturing conditions optimization unit 201 to the design data D2 and performs further design environment optimization processing to obtain change content data D3. The big data 204 is also referenced when the design environment optimization unit 202 obtains the change content data D3.

[0029] The change data D3 is passed to the customer 100, and the second semiconductor design unit 102 performs a design change process that includes the change data D3, ultimately obtaining design data D4 for manufacturing semiconductors. The design data D4 is passed to the foundry 200, which starts manufacturing using the semiconductor manufacturing equipment 203 based on the design data D4. The semiconductor manufacturing equipment 203 is also supplied with data optimized by the manufacturing condition optimization unit 201. The final obtained design data D4 is added to the big data 204. Additionally, the design data D1, D2, and D3 from each stage may be added to the big data 204 as needed.

[0030] [Time-series transition of the design process] Figure 2 shows an example of the time transition during semiconductor design in this example. The upper part is the rehearsal process for the actual design, called the dry run, and the lower part is the design process for the semiconductor that will actually be manufactured, called the main run. The horizontal axis in Figure 2 represents the time axis, but the time axis in Figure 2 is approximate and does not represent the exact time required for each process.

[0031] First, the first design process ST11 is executed in the first semiconductor design unit 101 of customer 100. In this first design process ST11 and the following second design process ST12, there is no distinction between dry run and main run. As already explained in Figure 7, the DRC shown in Figure 2 is a check of conformity to predetermined circuit design rules (design rule check). Also, STA is a check of timing conditions (static timing check). The checks of DRC and STA are performed using circuit checking tools that are already known, for example, as computer software.

[0032] To explain the transition shown in Figure 2, in the first design process ST11, semiconductor circuit data is designed to generate the functions to be realized by the required semiconductor. At the stage of the first design process ST11, the state is DRC check-free (DRC NO Clean) and STA check-free (STA NO Clean). The design data obtained in this first design process ST11 is the design data D1 shown in Figure 1.

[0033] Next, in the second design process ST12, the customer 100's first semiconductor design unit 101 modifies the semiconductor circuit obtained in the first design process ST11 to a circuit in which the DRC check is completed (DRC Clean). In this second design process ST12 as well, the STA (Static Timing Analysis) check is not performed (STA NO Clean).

[0034] Then, in parallel with the second design process ST12 at customer 100, the manufacturing condition optimization process ST21 is executed in the manufacturing condition optimization unit 201 of the foundry 200. In Figure 2, the second design process ST12 and the design condition optimization process ST21 are shown to be processed in the same amount of time, but for example, the manufacturing condition optimization process ST21 may be completed in a shorter time than the second design process ST12. In the manufacturing condition optimization process ST21, the big data 204, which is past design data accumulated in the foundry 200, is referenced, and the same optimization as the manufacturing condition optimization performed on past design data is executed.

[0035] Then, when the second design process ST12 is completed in the first semiconductor design unit 101 of the customer 100, the design data obtained in the second design process ST12 (design data D2 shown in Figure 1) is passed to the foundry 200, and the design environment optimization process ST22 is executed in the design environment optimization unit 202 to obtain change data D3. Here, the design data used by the design environment optimization unit 202 for design environment optimization is design data that has been verified by DRC checks but has not been verified by STA checks. When executing this design environment optimization process ST22, the big data 204, which is past design data accumulated in the foundry 200, is also referenced, and the same processing as the design changes for design environment optimization performed on past design data is executed.

[0036] Then, the semiconductor circuit design data obtained in the second design process ST12 is passed on to the third design process ST13 at the customer 100's second semiconductor design department 102, where the DRC check is completed (DRC Clean) and the STA check is completed (STA Clean).

[0037] Furthermore, while the third design process ST13 is being executed, the change data D3 obtained in the design environment optimization process ST22 at the foundry 200 is supplied to the customer 100, and the customer 10 executes design changes that reflect the change data D3. Once the design and changes in the third design process ST13 are completed, the data of the completed semiconductor circuit is passed to the foundry 200, where the wafer and package manufacturing process ST14 is executed.

[0038] As can be seen from the time-series transitions during the semiconductor design process in this example shown in Figure 2, the manufacturing condition optimization process ST21 at the foundry 200 starts when the initial design data D1 is obtained in the first design process ST11 at the customer 100. Therefore, after the second design process ST12 at the customer 100 is completed, the foundry 200 only needs to perform the design environment optimization process ST22, which significantly shortens the third design process ST13 at the customer 100, compared to the conventional example (Figure 7). In addition, the amount of work required for the process can be significantly reduced compared to the conventional method.

[0039] Thus, in this example, compared to the example shown in Figure 7 as a conventional method, the period from the start of design in the first design process ST11 to the completion of design in the third design process ST13 can be made extremely short, and the number of personnel required for design can be reduced.

[0040] [Details of Manufacturing Condition Optimization Process and Design Environment Optimization Process] Next, we will explain the details of the manufacturing condition optimization process and the design environment optimization process performed at the foundry 200. Figure 3 is a flowchart showing the manufacturing condition optimization process, the design environment optimization process, and the customer design process. The flowchart in Figure 3 shows the manufacturing condition optimization process (step S10) performed at the manufacturing condition optimization unit 201, the design environment optimization process (step S20) performed at the design environment optimization unit 202, and the customer design process performed at the second semiconductor design unit 102 of the customer 100.

[0041] First, let's explain the manufacturing condition optimization process performed by the manufacturing condition optimization unit 201. When the optimization process starts (step S11), the manufacturing condition optimization unit 201 obtains design data D1 from the customer 100 (step S12). At the stage obtained from the customer 100, the design data D1 is data with no DRC check (DRC NO Clean) and no STA check (STA NO Clean).

[0042] Here, the manufacturing condition optimization unit 201 checks whether the DRC criteria are ensured for the design data D1 (step S13). If the DRC criteria are not ensured in step S13 (No in step S13), a correction request is made to the customer 100. Also, if the DRC criteria are ensured in step S13 (Yes in step S13), the manufacturing condition optimization unit 201 executes optimization of the design data D1 by referring to the big data 204 (step S14). When performing optimization in the manufacturing condition optimization unit 201, there is no DRC check (DRC NO Clean), but the items of the DRC criteria required for the optimization presented from the foundry need to be satisfied. The DRC criteria are, for example, for the DRC items related to FEOL (device formation), no error, and for the DRC items related to BEOL (wiring formation), undefined, and these are items that affect the manufacturing condition optimization if not satisfied.

[0043] After this optimization is performed, the optimized design data is added to the big data 204, and aggregation and utilization of the big data 204 are performed (step S15). Then, when the optimization in step S14 is completed, the optimization process in the manufacturing condition optimization unit 201 ends (step S16).

[0044] When the optimization process in step S16 ends, the design environment optimization unit 202 starts the design change point extraction process (step S21). The design environment optimization unit 202 obtains the design data D2 from the customer 100 (step S22). This design data D2 is data for which the DRC check has been completed (DRC Clean) and the STA check has not been performed (STA NO Clean).

[0045] Here, the design environment optimization unit 202 re-executes the DRC check for the design data D2 and determines whether the DRC check has been completed (step S23). If the DRC check has not been completed in step S23 (No in step S23), the design environment optimization unit 202 makes a correction request to the customer 100.

[0046] Also, when the DRC check is completed in step S23 (Yes in step S23), the design environment optimization unit 202 executes optimization processing of the design environment by referring to the big data 204 (step S24). After performing this optimization processing of the design environment, the design data from which the design change points have been extracted is added to the big data 204, and the big data 204 is aggregated and utilized (step S25). Then, when the extraction process of the design change points is completed in step S24, the change content data D3 is obtained, and the processing in the design environment optimization unit 202 ends (step S26).

[0047] Next, the second semiconductor design unit 102 of the customer 100 performs design change processing of the design data based on the change content data D3 (step S31). After performing this design change processing, the second semiconductor design unit 102 performs checks such as DRC check and STA check to confirm that the design data is for a semiconductor circuit that can be properly manufactured (step S32). After the confirmation in step S32 is completed, the second semiconductor design unit 102 releases the obtained design data (step S33) and passes the released design data to the foundry 200. Then, the semiconductor manufacturing apparatus 203 of the foundry 200 executes the manufacturing of wafers and packages (step S40).

[0048] In addition, if there are items for which the optimization of the manufacturing conditions in step S14 and the optimization of the design environment in step S24 are not completed due to some factors, at that time, the foundry 200 may notify the customer 100 of the data of the items for which the optimization is not completed and instruct the customer 100 to correct the design data.

[0049] [Examples of Data Used as Big Data] Next, examples of the big data 204 used in the manufacturing condition optimization processing in the manufacturing condition optimization unit 201 and the design environment optimization processing in the design environment optimization unit 202 will be described. In the case of this example, the big data 204 is design data of a semiconductor circuit applied to a manufacturing process called a single wafer type.

[0050] Here, we will explain the differences in data obtained from a conventional batch-type manufacturing process and a single-wafer manufacturing process according to this embodiment, as well as the results derived from that data. Figure 4 is a diagram showing the differences in data obtained from batch-type and single-wafer manufacturing processes as experimentally demonstrated. In Figure 4, the horizontal axis represents the number of parameters that can be obtained during semiconductor production, and the vertical axis represents the experimental time. The parameters shown on the horizontal axis are values ​​obtained by varying certain process conditions (e.g., temperature, pressure, flow rate, plasma power, etc.) (for example, for temperature, 850°C, 900°C, 950°C, etc.). The experimental time on the vertical axis is the time it takes to obtain a semiconductor manufactured under certain process conditions.

[0051] In batch processing, the same process is performed on a large number of wafers simultaneously. The black dots in Figure 4 represent data acquired during each processing cycle. As shown in Figure 4 as a "batch," a linear graph is created by connecting the four black dots.

[0052] On the other hand, in the single-wafer method (labeled "single" in Figure 4), the data obtained in the manufacturing process for each wafer is shown as numerous white dots. Figure 4 shows the difference between the data obtained in the single-wafer method and the data obtained in the batch method. In other words, in the batch method in Figure 4, because the processing time is longer, only four data points (black dots) can be obtained in the same experimental time as in the single-wafer method. Therefore, the data obtained in the batch method is arranged in a nearly linear fashion, whereas in the single-wafer method (single), multiple data points can be obtained in the same experimental time, resulting in a nonlinear change.

[0053] Figure 5 shows the data obtained using batch and single-wafer methods. Figure 5(a) shows a graph of the performance power area (PPA). The PPA graph represents the density distribution function of a certain characteristic parameter. The horizontal axis of the graph represents the characteristic variation. For example, the threshold voltage of a transistor has characteristic variation due to manufacturing variations. High characteristic variation results in a slow response, while low characteristic variation results in a fast response.

[0054] PPA is designed using various parameters of the PDK. PPA can be expressed as a function with multiple types of σ as variables, as shown in equation (1): PPA = f(・・・, σ,・・・) …(1)

[0055] Here, σ represents the variation of the most important design parameter. Design parameters are those set by the designer during the semiconductor design process. For example, σ is formed by values ​​directly related to physical manufacturing, such as the alignment accuracy of the equipment, the gas flow rate, and the furnace temperature. Ultimately, the PPA of the chip becomes a function of the manufacturing parameters. Manufacturing parameters are those set in the manufacturing equipment during semiconductor manufacturing. This σ is expressed as a function of multiple manufacturing parameters m, as shown in equation (2): σ = g(m1, m2, ...) …(2)

[0056] Typically, designers perform various designs based on data called σ, which incorporates manufacturing parameters m1, m2, ..., so they don't need to worry about physical information. Furthermore, since the complex processes in semiconductor manufacturing are represented by σ, designers don't need to know how semiconductor manufacturing actually takes place.

[0057] The graphs shown in Figure 4 are reproduced below Figure 5. Graph 5(b) represents data obtained using the batch method, while graph 5(c) represents data obtained using the single-wafer method.

[0058] As mentioned above, σ is a value determined by the correlation of manufacturing parameters. Designers want to minimize the variability of design parameters, and the sooner the variability is reduced, the better. A smaller value for σ is better, but in batch-type data, a linear graph is drawn due to the correlation of only a small number of mi parameters, shown as black dots in Figure 5(b). Therefore, even if a designer fits with the smallest possible σ, it is unclear whether this σ is a local minimum. Furthermore, if the local minimum of σ fluctuates from side to side, the amount of change in σ becomes large, which makes semiconductor manufacturing unstable.

[0059] On the other hand, in the single-wafer method, a nonlinear graph is drawn based on the correlation of numerous mi parameters, shown as white dots in Figure 5(c). In this graph, the local minimum value of σ becomes clear, making it easy to find the optimal solution. Therefore, the manufacturing condition optimization unit 201, which refers to the big data 204 obtained in the single-wafer method, can obtain the local minimum value of a function with multiple manufacturing parameters as variables as the optimal solution for each wafer process information and packaging process information, and appropriately modify the design data.

[0060] Note that the point indicated as an error in the graph of Figure 5(c) is the value that was judged to be the local minimum of σ in the graph of Figure 5(b), which represents the data obtained using the batch method. In reality, it is not the local minimum of σ, but rather a point where the slope of the graph is steep. Therefore, even a small fluctuation in mi can easily cause a large change in σ. On the other hand, the point indicated as the optimal solution in the graph of Figure 5(c) has a small slope, so if this point is the local minimum of σ, σ will not change easily even if mi changes.

[0061] When obtaining design data, if the optimal value of σ is not noticed and the design data is fitted at the wrong position, the quality of the manufactured semiconductors will vary, and a large number of semiconductors will be produced that fail inspection in subsequent processes. In semiconductor design, it is important to find the minimum value of σ as early as possible beforehand, and by using a single-wafer method to find the minimum value of σ rather than a batch method, appropriate design data can be obtained quickly.

[0062] Furthermore, by combining silicon big data and TCAD (Technology CAD) models as Big Data 204, the verification of PDK can be accelerated. For example, the correlation between manufacturing parameters and design parameters can be predicted using TCAD, and the big data of design data obtained from a full-sheet process can be analyzed by a design AI model. Then, the correlation between manufacturing parameters and design parameters using past design data can be verified to create appropriate Big Data 204.

[0063] [Example of Design Environment Optimization Process] Figure 6 shows an example of design environment optimization performed by the design environment optimization unit 202. The example in Figure 6 shows a case where the circuit pattern shown in the design data has been found to have potential hot spots. In the circuit shown on the left side of Figure 6, if the pattern is formed on the wafer according to the design drawing, the circles indicate areas where defects may occur during manufacturing. As shown on the right side of Figure 6, the design environment optimization unit 202 refers to the big data 204 and performs a process to change the layout of the circuit that has the potential to become a hot spot, thereby eliminating the hot spots. Note that the layout change shown in Figure 6 is just one example of design environment optimization; in reality, the design environment optimization unit 202 refers to the big data 204 and performs various design environment optimization processes.

[0064] As explained above, this semiconductor design system can calculate the optimal conditions for semiconductor design and manufacturing and reflect them in the customer's design data, thereby significantly reducing the time and effort required for semiconductor design.

[0065] [Variations] It should be noted that the present invention is not limited to the embodiments described above, and various other applications and modifications can be made as long as they do not depart from the gist of the present invention as described in the claims. For example, the embodiments described above describe the system configuration in detail and concretely in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to having all the configurations described. In addition, it is possible to add, delete, or replace some of the configurations of these embodiments with other configurations.

[0066] Furthermore, the division of processes performed by the customer 100 and the foundry 200 shown in Figure 1 is merely an example and is not limited to this example. For example, the modification of design data after the foundry 200 has optimized manufacturing conditions and the design environment may be performed by the foundry 200. In addition, various forms are conceivable, such as the customer 100 only providing instructions to the foundry 200 regarding the functions of the semiconductor device to be manufactured, and the foundry 200 handling everything from the initial design to the modifications.

[0067] Furthermore, in the configuration shown in Figure 1, in order to clarify the processing flow, a manufacturing condition optimization unit 201 and a design environment optimization unit 202 are provided, and optimization processing is performed in each processing unit. These processing units consist of the execution of a computer program. Therefore, the semiconductor design system and semiconductor design method of the present invention can be realized by preparing and implementing a program on a computer that executes the manufacturing condition optimization processing method and the design environment optimization processing method described in the above-described embodiment. In this case, the program can be prepared on various recording media and implemented on the computer, or it can be transferred from a server or the like via various networks.

[0068] 100...Customer (Designer), 101...First Semiconductor Design Department, 102...Second Semiconductor Design Department, 200...Foundry (Manufacturer), 201...Manufacturing Condition Optimization Department, 202...Design Environment Optimization Department, 203...Semiconductor Manufacturing Equipment, 204...Big Data, D1, D2, D4...Design Data, D3...Change Data

Claims

1. A semiconductor design system that acquires semiconductor design data designed by a customer and obtains semiconductor design data for manufacturing the semiconductor based on the acquired design data, comprising: a manufacturing condition optimization unit that acquires the design data designed by the customer and obtains design data with optimized manufacturing conditions; and a design environment optimization unit that acquires the design data with optimized manufacturing conditions by the manufacturing condition optimization unit, obtains change data with optimized design environment, and transmits the obtained change data to the customer, and acquires design data with changes based on the change data from the customer.

2. The semiconductor design system according to claim 1, wherein the design data for which the manufacturing condition optimization unit performs manufacturing condition optimization is design data that has not been verified by design rule checks and has not been verified by static timing checks.

3. The semiconductor design system according to claim 2, wherein the design data used by the design environment optimization unit to optimize the design environment is design data that has been verified by design rule checks but has not been verified by static timing checks.

4. The semiconductor design system according to claim 2, wherein the design data on which the changes are made using the change data obtained by the design environment optimization unit is design data that has been determined to be appropriate in the verification of the design rule check and also determined to be appropriate in the verification of the static timing check.

5. The semiconductor design system according to claim 2, wherein the manufacturing conditions optimization unit and the design environment optimization unit perform optimization by referring to data accumulated from past design data.

6. The semiconductor design system according to claim 5, wherein the aforementioned past design data is semiconductor design data obtained when a single-wafer manufacturing process is applied.

7. The semiconductor design system according to claim 2, wherein the manufacturing condition optimization unit instructs the customer to modify the design data if there are items in the acquired design data that cannot be optimized.

8. A semiconductor design method in which a computer performs a process to obtain semiconductor design data for manufacturing a semiconductor based on the acquired design data, the process performed by the computer includes: a manufacturing condition optimization process to obtain design data with optimized manufacturing conditions from the customer by acquiring the design data with optimized manufacturing conditions from the customer; and a design environment optimization process to obtain change data with optimized design environment from the design data with optimized manufacturing conditions from the manufacturing condition optimization process, and transmit the obtained change data to the customer, the semiconductor design method to obtain design data with changes based on the change data from the customer.

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