Low-loss full-bandwidth three-dimensional forward tapered edge coupler for photonic integrated circuit

Abstract

A photonic integrated circuit may include a substrate and an optical waveguide formed within a device layer of material formed upon the substrate. The optical waveguide may include an untapered portion and a three-dimensional forward taper edge coupler optically coupled to the untapered portion, the three-dimensional forward taper edge coupler increasing in height and width from the untapered portion to an edge of the device layer.

Description

[0001] ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0002] 1

[0003] LOW-LOSS FULL-BANDWIDTH THREE-DIMENSIONAL FORWARD TAPERED EDGE COUPLER FOR PHOTONIC INTEGRATED CIRCUIT

[0004] RELATED APPLICATION The present application claims priority to United States Provisional Patent

[0005] Application Number 63 / 735,403, filed December 18, 2024, and incorporated by reference herein in its entirety7.

[0006] FIELD OF DISCLOSURE The present disclosure relates in general to methods and systems relating to an edge coupler for a photonic integrated circuit, the coupler having a three-dimensional forward tapered structure.

[0007] 47821056v.1 ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0008] 2

[0009] BACKGROUND

[0010] Optical devices may be integrated on a chip to form a photonic integrated circuit. Such optical devices may include, for example, optical waveguides. Optical waveguides may be used to guide light to and from the different optical devices within a photonic integrated circuit or to guide light to and from optical devices external to a photonic integrated circuit. Various optical devices, such as switches, wavelength multiplexers, and modulators may be implemented using optical waveguides. Further, to couple to other circuits, a photonic integrated circuit may include one or more couplers, including one or more edge couplers located at one or more edges of the photonic integrated circuit. Such couplers may enable coupling of various devices to the photonic integrated circuit and thus a coupler may include a chip-to-fiber coupler, a chip-to-chip coupler, a chip-to-lens coupler, and / or a chip-to-photonic wire bond coupler.

[0011] A photonic integrated circuit may be formed using any suitable material substrate, including without limitation silicon nitride and lithium niobate. To fully unleash the power of thin-film lithium niobate (TFLN) photonic integrated circuits, the capability to communicate with other circuits as a hybrid integrated system to utilize the strength of circuit platforms may be extremely important. Therefore, a low loss mode size converter for passing a full bandwidth of optical signals may be desirable for a TFLN photonic integrated circuit or other photonic integrated circuits.

[0012] However, existing low loss mode coupler solutions are still limited. Accordingly, improved coupler solutions are desired.

[0013] ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0014] 3

[0015] SUMMARY

[0016] In accordance with the teachings of the present disclosure, the disadvantages and problems associated with existing couplers of photonic integrated circuits may be reduced or eliminated.

[0017] In accordance with embodiments of the present disclosure, a photonic integrated circuit may include a substrate and an optical waveguide formed within a device layer of material formed upon the substrate. The optical waveguide may include an untapered portion and a three-dimensional forward taper edge coupler optically coupled to the untapered portion, the three-dimensional forward taper edge coupler increasing in height and width from the untapered portion to an edge of the device layer.

[0018] In accordance with these and other embodiments of the present disclosure, a method may include forming an untapered portion of an optical waveguide within a device layer of birefringent material formed upon a substrate. The method may also include forming, in the device layer of material, a three-dimensional forward taper edge coupler optically coupled to the untapered portion, the three-dimensional forw ard taper edge coupler increasing in height and width from the untapered portion to an edge of the device layer.

[0019] Technical advantages of the present disclosure may be readily apparent to one having ordinary7skill in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims.

[0020] It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory7and are not restrictive of the claims set forth in this disclosure. ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0021] 4

[0022] BRIEF DESCRIPTION OF THE DRAWINGS

[0023] A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein:

[0024] FIGURE 1 illustrates an isometric perspective view of a portion of a photonic integrated circuit with a waveguide having two three-dimensional forward taper edge couplers formed thereon, in accordance with embodiments of the present disclosure;

[0025] FIGURE 2 illustrates an isometric perspective view of a portion of a photonic integrated circuit with a waveguide having two three-dimensional forward taper edge couplers formed thereon with the forward tapered region rotated 90 degrees relative to a main section of the waveguide, in accordance with embodiments of the present disclosure;

[0026] FIGURE 3 illustrates an isometric perspective view of a portion of a slab with a device layer formed thereon, for use in fabricating a photonic integrated circuit, in accordance with embodiments of the present disclosure;

[0027] FIGURE 4 illustrates an isometric perspective view of a portion of a photonic integrated circuit after a fabrication step of the photonic integrated circuit, in accordance with embodiments of the present disclosure;

[0028] FIGURE 5 illustrates an isometric perspective view of a portion of a photonic integrated circuit after another fabrication step of the photonic integrated circuit, in accordance with embodiments of the present disclosure; and

[0029] FIGURE 6 illustrates an isometric perspective view of a portion of a photonic integrated circuit after yet another fabrication step of the photonic integrated circuit, in accordance with embodiments of the present disclosure. ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0030] 5

[0031] DETAILED DESCRIPTION

[0032] The description below sets forth example embodiments according to this disclosure. Further example embodiments and implementations will be apparent to those having ordinary skill in the art. Further, those having ordinary’ skill in the art will recognize that various equivalent techniques may be applied in lieu of, or in conjunction with, the embodiment discussed below, and all such equivalents should be deemed as being encompassed by the present disclosure.

[0033] FIGURE 1 illustrates an isometric perspective view of a portion of a photonic integrated circuit 100 with a waveguide 102 formed from a device layer 104 of birefringent material formed upon a substrate 130, such waveguide 102 having two three-dimensional forward taper edge couplers 106 formed thereon yvithin coupling regions 110 of photonic integrated circuit 100, in accordance with embodiments of the present disclosure. Device layer 104 may comprise any suitable birefringent material, including, without limitation, lithium niobate, lithium tantalate, silicon nitride, or any other suitable birefringent crystalline material. The substrate may be formed from silicon dioxide formed on silicon or other suitable semiconductor material. As shown in FIGURE 1, waveguide 102 may also include, in addition to three-dimensional forward taper edge couplers 106, a mam section 108 within a center region 1 12 of photonic integrated circuit 100 between coupling regions 110.

[0034] As shown in FIGURE 1 , within a coupling region 110, each three-dimensional forward taper edge coupler 106 may taper to increase in height and width from main section 108 of waveguide 102 towards an edge of device layer 104. For example, within main section 108, waveguide 102 may have a thickness of approximately 300 nm to approximately 1 pm and may taper to a thickness in both height and width up to approximately 1 pm to approximately 10 pm in order to match a target mode size for a fiber, lens, or other platform optically coupled to waveguide 102.

[0035] When photonic integrated circuits are formed using thin-film lithium niobate, in order to utilize the nonlinear properties of thin-film lithium niobate, there are beneficial directions of main waveguide. Accordingly, conventional edge couplers are often fabricated in a direction the same as the main waveguide. However, due to the ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0036] 6 birefringent nature of thin-film lithium niobate, directly tapering up in height and width in dimensions in a certain direction may causes several problems. For example, the guided fundamental mode for the waveguide may couple to the mode of the slab (e.g., the remaining lithium niobate layer or other layer on a wafer), rendering a lateral leakage from the waveguide. Moreover, many mode crossings of the fundamental transverse electrical mode of the waveguide may introduce extra loss. To avoid lateral leakage and mode crossing, a rotation of edge couplers can solve the issue. An example approach may be used such as that depicted in FIGURE 2.

[0037] FIGURE 2 illustrates an isometric perspective view of a portion of a photonic integrated circuit 200 with a waveguide 202 formed from a device layer 204 of birefringent material (e.g., an X-cut lithium niobate device layer) formed upon a substrate 230, such waveguide 202 having two three-dimensional forward taper edge couplers 206 formed thereon within coupling regions 210, wherein three-dimensional forward taper edge couplers 206 are rotated 90 degrees relative to a main section 208 of waveguide 202, in accordance with embodiments of the present disclosure. Device layer 204 may comprise any suitable birefringent material, including, without limitation, lithium niobate. lithium tantalate, silicon nitride, or any other suitable birefringent crystalline material. The substrate may be formed from silicon dioxide on silicon or other suitable semiconductor material. Photonic integrated circuit 200 may be preferable over photonic integrated circuit 100 when mode-crossing issues are present due to birefringence material.

[0038] As shown in FIGURE 2, waveguide 202 may also include, in addition to three- dimensional forward taper edge couplers 206, a main section 208 within a center region 212 of photonic integrated circuit 200 between coupling regions 210. Photonic integrated circuit 200 may be similar in many respects to photonic integrated circuit 100 (with waveguide 202 similar to waveguide 102, device layer 204 similar to device layer 104, three-dimensional forward taper edge couplers 206 similar to three- dimensional forward taper edge couplers 106, main section 208 similar to main section 108, etc.), except that three-dimensional forward taper edge couplers 206 and main section 208 may be arranged such that photonic energy travels predominantly through ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0039] 7 three-dimensional forward taper edge couplers 206 in a direction different from the direction in which photonic energy predominantly travels through main section 208. For that reason, main section 208 may be curved at one or both ends to accommodate the rotation of three-dimensional forward taper edge couplers 206 relative to most of main section 208. For example, waveguide 202 may be formed such that photonic energy that travels predominantly in the y-direction of X-cut lithium niobate is rotated 90 degrees before tapering to increase in height and width.

[0040] Such rotation of three-dimensional forward taper edge couplers 206 relative to most of main section 208 may minimize lateral leakage and mode crossing, because both polarizations of photonic energy are in ordinary directions of birefringent materials (e.g., lithium niobate), such that both the refractive index of the transverse electric mode and the transverse magnetic mode are higher than that of the slab modes or radiation modes.

[0041] As shown in FIGURE 2, structures and patterns other than waveguide 202 may be formed within center region 212, such as ring cavity 214 and phase modulator 21 , for example. Dimensions of waveguides 102 and 202, including three-dimensional forward taper edge couplers 106 and 206, may be designed depending on target mode size of the fiber or other optical component to which waveguide 202 is optically coupled.

[0042] Photonic integrated circuit 100 and photonic integrated circuit 200 may be fabricated in any suitable manner. For example, each of FIGURES 3-6 illustrates an isometric perspective view of a portion of a photonic integrated circuit after a respective fabrication step of photonic integrated circuit 200, in accordance with embodiments of the present disclosure. Although FIGURES 3-6 contemplate fabrication of photonic integrated circuit 200, photonic integrated circuit 100 may be fabricated in a similar manner.

[0043] In the fabrication method illustrated in FIGURES 3-6, the process may begin with a thick device layer 204 that may have a thickness of a few micrometers (e.g., approximately 1 pm to approximately 10pm), then using an etching or polishing technique to make center region 212 thinner (e.g., a few hundred nanometers, such as ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0044] 8 approximately 300 nm to approximately 1 pm) while keeping three-dimensional forward taper edge couplers 206 with a thickness of a few micrometers (e.g., approximately 1 pm to approximately 10pm).

[0045] The following description of FIGURES 3-6 considers an example fabrication of photonic integrated circuit 200 with a lithium niobate device layer 204, although the systems and methods similar or identical to those described herein may be used on other device layers. Using a lithium niobate device layer 204 formed on a substrate 230, as shown in FIGURE 3, fabrication may be divided into two main layers. The first main fabrication layer may fabricate three-dimensional forward taper edge couplers 206 (e.g., FIGURES 4 and 5), while the second main fabrication layer may fabricate main section 208 of waveguide 202 interfaced between three-dimensional forward taper edge couplers 206 (e.g., FIGURE 6).

[0046] Fabrication may begin with an x-cut nanophotonic lithium niobate wafer (or other suitable material wafer) with a device layer of suitable thickness (e.g., approximately 3.4 pm in some embodiments). By using any suitable subtractive fabrication process (e g., dry etching such as inductively coupled plasma-reactive ion etching, chemical etching, chemical and / or mechanical polishing, etc.), portions of device layer 204 may be removed, resulting in an untapered section 406a and a plurality of tapered sections 406b, 406c, and 406d and supporting structures 420 proximate to untapered section 406a and tapered sections 406b, as shown in FIGURE 4. Supporting structures 420 may be used to control a polish rate of a later polish process.

[0047] Subsequently, using any suitable subtractive fabrication process (e.g., dry etching, chemical etching, chemical and / or mechanical polishing, etc.), portions of slab tapered sections 406b, 406c, 406d may be removed, to create three-dimensional forward taper edge couplers 206. Untapered section 406a may retain approximately the same dimensions between FIGURES 4 and 5, while thickness of tapered section 406b may vary between its ends (e.g., between approximately 3 pm and approximately 800 nm). The thickness of tapered section 406c may not change from one end of tapered section 406c to the other due to this process step, while tapered section 406d ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0048] 9 may change in thickness (e.g., from approximately 800 nm to approximately 600 nm) such that tapered section 406d smoothly connects with remaining device layer 204 (e.g., also having a thickness of approximately 600 nm). As a result, three-dimensional forward taper edge couplers 206 may be fabricated, resulting in what is depicted in FIGURE 5, in which at one of forward taper edge couplers 206 (e.g., at the end of tapered section 406d), the top surface of three-dimensional forward taper edge couplers 206 are smoothly connected to the remaining substrate 204 (e.g., having a thickness of approximately 600 nm).

[0049] For the second device fabrication layer, any suitable subtractive fabrication process (e.g., chemical etching, chemical and / or mechanical polishing, etc.) may be used to form main section 208 of waveguide 202 or any other structures in center region 212 of photonic integrated circuit 200, resulting in what is depicted in FIGURE 6.

[0050] Although the foregoing description of FIGURES 3-6 contemplates the use of a subtractive process, in some embodiments, an additive fabrication process (e.g., material deposition upon a slab or substrate) may be used to fabricate photonic integrated circuit 100 and / or photonic integrated circuit 200.

[0051] As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in mechanical communication, whether connected indirectly or directly, with or without intervening elements.

[0052] This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0053] 10 function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, ‘"each” refers to each member of a set or each member of a subset of a set.

[0054] Although exemplary' embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above.

[0055] Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale.

[0056] All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure.

[0057] Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary7skill in the art after review of the foregoing figures and description.

[0058] To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)

[0059] 11 intend any of the appended claims or claim elements to invoke 35 U.S.C. § 1 12(f) unless the words ‘'means for” or "step for” are explicitly used in the particular claim.

Claims

ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)12WHAT IS CLAIMED IS:

1. A photonic integrated circuit comprising: a substrate; and an optical waveguide formed within a device layer of material formed upon the substrate, the optical waveguide comprising: an untapered portion; and a three-dimensional forward taper edge coupler optically coupled to the untapered portion, the three-dimensional forward taper edge coupler increasing in height and width from the untapered portion to an edge of the device layer.

2. The photonic integrated circuit of Claim 1, wherein the untapered portion and the three-dimensional forward taper edge coupler are arranged such that, within at least one region of the untapered portion, photonic energy predominantly propagates in a first direction different from a second direction in which photonic energy predominantly propagates in the three-dimensional forw ard taper edge coupler.

3. The photonic integrated circuit of Claim 1, wherein the material comprises a birefringent material.

4. The photonic integrated circuit of Claim 1, wherein the material comprises lithium niobate.

5. The photonic integrated circuit of Claim 1, wherein the substrate comprises silicon dioxide.

6. The photonic integrated circuit of Claim 1, further comprising at least one other component formed on the device layer in a center region of the photonic integrated circuit, wherein the center region comprises the untapered portion.ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)7. The photonic integrated circuit of Claim 1 , wherein: the three-dimensional forward taper edge coupler is formed in a first processing layer of the device layer; and the untapered portion is formed in a second processing layer of the device layer.ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)148. A method comprising: forming an untapered portion of an optical waveguide within a device layer of birefringent material formed upon a substrate; and forming, in the device layer of material, a three-dimensional forward taper edge coupler optically coupled to the untapered portion, the three-dimensional forward taper edge coupler increasing in height and width from the untapered portion to an edge of the device layer.

9. The method of Claim 8, further comprising arranging the untapered portion and the three-dimensional forward taper edge coupler such that, within at least one region of the untapered portion, photonic energy predominantly propagates in a first direction different from a second direction in which photonic energy predominantly propagates in the three-dimensional forward taper edge coupler.

10. The method of Claim 8, wherein the material comprises a birefringent material.

11. The method of Claim 8, wherein the material comprises lithium niobate.

12. The method of Claim 8, wherein the substrate comprises silicon dioxide.

13. The method of Claim 8, further comprising at least one other component formed on the device layer in a center region of the photonic integrated circuit, wherein the center region comprises the untapered portion.ATTORNEY’S DOCKET PATENT APPLICATION 215595.00268 (8405 FAN PCT)1514. The method of Claim 8, further comprising: forming the three-dimensional forward taper edge coupler in a first processing layer of the device layer; and forming the untapered portion in a second processing layer of the device layer.

15. The method of Claim 8, wherein forming the three-dimensional forward taper edge coupler comprises polishing.

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