Silicon wafer, silicon rod, cell and cell assembly

Abstract

The embodiments of the present application provide a silicon wafer, a silicon rod, a cell, and a cell assembly. At least one surface of the silicon wafer is provided with a plurality of stripes; the stripes extend with reference to a first direction, and the plurality of stripes are arranged at intervals in a second direction; the peak-to-valley height difference Rt of the surface profile of the middle region of the surface satisfies: 2 μm ≤ Rt ≤ 8.5 μm; the first direction is the extension direction of a first side edge of the silicon wafer, and the second direction is the extension direction of a second side edge of the silicon wafer; and the middle region refers to a region at least L / 3 away from the first side edge of the silicon wafer in the second direction, wherein L is the length of the second side edge. The flatness of the surface of the silicon wafer is relatively uniform, which can improve the photoelectric conversion efficiency of a cell to which the silicon wafer is applied.

Description

A silicon wafer, silicon rod, solar cell, and solar module

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202423244117.2, filed on December 26, 2024, entitled "A Silicon Wafer, a Solar Cell, and a Solar Module", and Chinese Patent Application No. 202423318473.4, filed on December 31, 2024, entitled "A Silicon Rod, a Silicon Wafer, a Solar Cell, and a Photovoltaic Module", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application belongs to the field of photovoltaic processing technology, specifically relating to a silicon wafer, silicon rod, solar cell, and solar module. Background Technology

[0004] In the processing of solar silicon wafers, dicing wires are used to cut silicon rods into wafers. However, during the process of cutting silicon rods into wafers, dicing wires can easily form marks on the wafers, resulting in an uneven surface profile of the wafers perpendicular to the dicing wires.

[0005] Current technologies focus on the TTV (thickness variation) of silicon wafers. TTV reflects the uniformity of wafer thickness, but not the uniformity of surface flatness. The uniformity of surface flatness directly reflects the quality of the wafer's surface profile. In the battery manufacturing process, after the film layer on the silicon wafer is fabricated, electrode grid lines are printed onto it. The film thickness is typically from a few nanometers to several hundred nanometers, while the electrode grid line thickness is generally around 7 micrometers. Non-uniformity in the silicon wafer surface profile leads to non-uniformity in the width and thickness of the electrode grid lines, increasing grid line resistance, affecting current conduction, and thus impacting the battery's photoelectric conversion efficiency. Summary of the Invention

[0006] This application aims to provide a silicon wafer, silicon rod, solar cell, and solar cell assembly to solve the problem of uneven surface contours of existing silicon wafers affecting photoelectric conversion efficiency.

[0007] To solve the above-mentioned technical problems, this application is implemented as follows:

[0008] In a first aspect, this application discloses a silicon wafer having a plurality of stripes on at least one surface, the stripes extending with a first direction as a reference, and the plurality of stripes being spaced apart along a second direction; wherein, the surface profile peak-valley height difference Rt in the middle region of the surface satisfies 2 micrometers ≤ Rt ≤ 8.5 micrometers;

[0009] The first direction is the extension direction of the first side of the silicon wafer, and the second direction is the extension direction of the second side of the silicon wafer; the intermediate region refers to the region along the second direction that is at least L / 3 away from the first side of the silicon wafer, where L is the length of the second side.

[0010] Optionally, the crest spacing D of the surface profile of the intermediate region satisfies 1.4 mm ≤ D ≤ 3.9 mm.

[0011] Optionally, the maximum line mark value Rmax on the silicon wafer surface is ≤17 micrometers.

[0012] Optionally, the stripe extends in an arc shape over the middle region, and the vertex of the stripe is located in the middle region of the surface along the first direction, and the endpoint of the stripe is located on the second side, wherein the distance between the vertex and the endpoint along the second direction is L2, satisfying: 1.5 mm < L2 < 2.5 mm.

[0013] Optionally, the line connecting the vertex and the endpoint of the stripe is a first line, and the line extending from the vertex of the stripe to the second side along the first direction is a second line. The angle between the first line and the second line is α, satisfying: 1°≤α≤8°.

[0014] Optionally, the surface has a damage layer with a thickness of 3-5 micrometers.

[0015] Optionally, along the second direction, the surface is sequentially arranged with a first region, a second region, and a third region; the intermediate region is at least partially located within the second region; wherein the stripe density on the first region and the third region is greater than the stripe density on the second region;

[0016] The stripe density refers to the number of stripes within a range of at least 5 mm along the second direction.

[0017] Optionally, the width of the first region along the second direction is a first width, the width of the second region along the second direction is a second width, and the width of the third region along the second direction is a third width; wherein,

[0018] The second width is greater than the first width and the third width.

[0019] Optionally, the first width is at least greater than 10 mm, and the third width is at least greater than 5 mm.

[0020] Optionally, along the second direction, at least a portion of the stripe density of the intermediate region is less than the stripe density of the first edge region or the third edge region;

[0021] The first edge region is a region 10 mm away from the first side along the second direction; the third edge region is a region 5 mm away from another first side opposite the first side along the second direction.

[0022] The stripe density refers to the number of stripes within a range of at least 5 mm along the second direction.

[0023] Optionally, the surface includes a first surface and a second surface disposed opposite to each other along a third direction, and a plurality of silicon wafer sides connecting the first surface and the second surface;

[0024] The average roughness Ra of at least one of the silicon wafer sides is 0.05-0.2 μm; and / or, the roughness Rz of at least one of the plurality of silicon wafer sides is 0.5-2.5 μm;

[0025] The third direction is the thickness direction of the silicon wafer, and the first direction, the second direction, and the third direction are all perpendicular to each other.

[0026] Optionally, among the plurality of silicon wafer sides, at least one of the silicon wafer sides has an average roughness Ra greater than the average roughness Ra of the other silicon wafer sides.

[0027] Optionally, the plurality of silicon wafer sides include a first silicon wafer side and a second silicon wafer side disposed opposite to each other. The first silicon wafer side has a first chamfer at both ends, and the second silicon wafer side has a second chamfer at both ends. The edge length of the first chamfer is less than or equal to the edge length of the second chamfer.

[0028] The average roughness Ra of the first silicon wafer side surface is greater than the average roughness Ra of the second silicon wafer side surface; and / or, the roughness Rz of the first silicon wafer side surface is greater than or equal to the roughness Rz of the second silicon wafer side surface.

[0029] Optionally, the edge length of the first chamfer is 1-2 mm, and the edge length of the second chamfer is 1-8 mm.

[0030] Optionally, the average roughness Ra of the side surface of the first silicon wafer is 0.09-0.2 μm, and the average roughness Ra of the side surface of the second silicon wafer is 0.05-0.1 μm;

[0031] And / or, the surface roughness Rz of the first silicon wafer side is 1.1-2.5 μm, and the surface roughness Rz of the second silicon wafer side is 0.8-1.3 μm.

[0032] Optionally, the average roughness Ra of the first surface and the second surface is 0.05-0.18 μm;

[0033] And / or, the roughness Rz of the first surface and the second surface is 0.5-1.0 μm.

[0034] In a second aspect, a silicon rod is provided, including a silicon rod body, the silicon rod body including a plurality of surfaces parallel to the axial direction of the silicon rod;

[0035] The average roughness Ra of at least one of the surfaces is 0.05-0.2 μm; and / or the roughness Rz of at least one of the surfaces is 0.8-2.5 μm.

[0036] Optionally, the silicon rod body includes a third surface and a fourth surface that are parallel to and opposite to the axial direction of the silicon rod, and a plurality of side surfaces connecting the third surface and the fourth surface;

[0037] The average roughness Ra of the third surface is 0.09-0.2 μm, and the average roughness Ra of the fourth surface is 0.05-0.1 μm;

[0038] And / or, the roughness Rz of the third surface is 1.1-2.5 μm, and the roughness Rz of the fourth surface is 0.8-1.3 μm.

[0039] Optionally, the third surface has a first chamfer at both ends, and the fourth surface has a second chamfer at both ends, wherein the edge length of the first chamfer is less than or equal to the edge length of the second chamfer; wherein,

[0040] The average roughness Ra of the third surface is greater than or equal to the average roughness Ra of the fourth surface; and / or, the roughness Rz of the third surface is greater than or equal to the roughness Rz of the fourth surface.

[0041] Thirdly, this application also discloses a solar cell, the solar cell comprising: the silicon wafer described in any of the preceding claims.

[0042] Fourthly, this application also discloses a photovoltaic module, which includes: the aforementioned solar cells.

[0043] In this embodiment, when using diamond wire for wire mesh cutting, the unevenness in the middle region of the silicon wafer is relatively greater than that in the regions at both ends. This application addresses this by adjusting the slicing process to limit the peak-to-valley height difference of the surface profile on the silicon wafer surface within the middle region, and ensuring that the middle region is at least 1 / 3L from the edge of the silicon wafer. This limits the peak-to-valley height difference of the surface profile in the middle region, which reflects the surface flatness quality of the silicon wafer, thereby controlling the overall surface flatness quality of the silicon wafer.

[0044] In this embodiment, the central region of the silicon wafer occupies a large portion of its surface. The peak-to-trough height difference Rt of the surface profile in this central region satisfies 2 μm ≤ Rt ≤ 8.5 μm, resulting in a relatively uniform surface smoothness of the silicon wafer. Therefore, after processing the film layer on the silicon wafer, during the printing of electrode grid lines on the film layer, the uniform smoothness of the silicon wafer leads to correspondingly uniform width and thickness of the electrode grid lines, resulting in lower grid line resistance and facilitating current conduction on the grid lines. This, in turn, improves the photoelectric conversion efficiency of the battery using the silicon wafer.

[0045] Additional aspects and advantages of this invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0046] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0047] Figure 1 is a schematic diagram of a silicon wafer structure according to an embodiment of this application;

[0048] Figure 2 is a simplified schematic diagram of the silicon wafer shown in Figure 1;

[0049] Figure 3 is a simplified schematic diagram of another structure of the silicon wafer shown in Figure 1;

[0050] Figure 4 is a schematic diagram of the cross-sectional structure of the silicon wafer shown in Figure 2 from another angle;

[0051] Figure 5 is a schematic diagram of the structure of a silicon wafer according to another embodiment of this application;

[0052] Figure 6 is a schematic diagram of the cross-sectional structure of a silicon rod according to an embodiment of this application;

[0053] Figure 7 is a schematic diagram of the cutting of a silicon rod according to an embodiment of this application.

[0054] Reference numerals: 10-middle region, 11-first side, 12-second side, 13-stripes, 14-first region, 141-first edge region, 15-third region, 151-third edge region, 16-second region, 20-silicon wafer side, 21-first silicon wafer side, 22-second silicon wafer side, 23-third silicon wafer side, 200-silicon rod body, 210-side, 211-third surface, 212-fourth surface, 214-first chamfer, 215-second chamfer, x-first direction, y-second direction, z-third direction. Specific Implementation

[0055] The embodiments of this utility model will now be described in detail. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0056] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0057] In the description of this utility model, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this utility model and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model.

[0058] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0059] Referring to Figure 1, a schematic diagram of a silicon wafer structure according to an embodiment of this application is shown; referring to Figure 2, a simplified schematic diagram of the silicon wafer structure shown in Figure 1 is shown; referring to Figure 4, a schematic diagram of the cross-sectional structure of the silicon wafer shown in Figure 2 from another angle is shown. In this embodiment, the schematic diagram of the silicon wafer structure in Figure 1 can be a schematic diagram of the structure obtained by a silicon wafer sorting machine. As shown in Figures 1 to 4, the silicon wafer specifically includes: at least one surface of the silicon wafer has a plurality of stripes 13, the stripes 13 extending with a first direction x as a reference, and the plurality of stripes 13 being spaced apart along a second direction y; wherein, the surface profile peak-valley height difference Rt in the middle region of the surface satisfies 2 micrometers ≤ Rt ≤ 8.5 micrometers; the first direction x is the extension direction of the first side 11 of the silicon wafer, and the second direction y is the extension direction of the second side 12 of the silicon wafer; the middle region 10 refers to the region along the second direction y that is at least 1 / 3L away from the first side 11 of the silicon wafer, where L is the length of the second side 12. The first side 11 includes two opposing first side 11s, the second side 12 includes two opposing second side 12s, and the intermediate region 10 is a portion of the region between the two first side 11s. Specifically, as one embodiment, a silicon wafer surface with multiple stripes refers to one or both of the first and second surfaces that are disposed opposite to each other along the silicon wafer thickness direction, i.e., the third direction y.

[0060] In this embodiment, when using diamond wire for wire mesh cutting, the unevenness in the middle region of the silicon wafer is relatively greater than that at the two ends. This application addresses this by adjusting the slicing process to limit the peak-to-trough height difference of the surface profile on the silicon wafer surface within the middle region, and ensuring that the middle region is at least 1 / 3L from the edge of the silicon wafer. This limits the peak-to-trough height difference of the surface profile in the middle region, which reflects the surface flatness quality of the silicon wafer, thereby controlling the overall surface flatness quality of the silicon wafer.

[0061] This application controls the peak-to-trough height difference Rt of the surface profile in the intermediate region 10 to satisfy 2 μm ≤ Rt ≤ 8.5 μm. As an optional implementation, Rt can also be limited to 2 μm-4.5 μm or 4.5 μm-8.5 μm, etc.; the distance between the intermediate region and the edge of the silicon wafer can also be at least 2L / 5, thereby making the flatness of the silicon wafer surface more uniform. Thus, after processing the film layer on the silicon wafer surface, during the printing of electrode grid lines on the film layer, because the silicon wafer exhibits more uniform flatness, the width and thickness of the electrode grid lines are correspondingly more uniform, resulting in lower grid line resistance, which is beneficial for current conduction on the grid lines. Therefore, the photoelectric conversion efficiency of the battery using the silicon wafer can be improved.

[0062] In specific applications, the silicon wafer can be made by wire cutting a silicon rod. The silicon rod is fed perpendicular to the wire mesh, thereby cutting the silicon rod into silicon wafers. During the process of wire cutting the silicon rod to obtain the silicon wafer, stripes 13 are formed on the surface of the silicon wafer, and the density of the stripes 13 is related to the feed speed of the silicon rod. During silicon rod cutting, the silicon rod moves perpendicular to the wire mesh, and the feed speed of the silicon rod refers to the speed perpendicular to the stripe direction, that is, along the y-direction.

[0063] In practical applications, during the process of the dicing wire cutting the silicon rod to obtain the silicon wafer, the cutting speed of the dicing wire and the feed speed of the silicon rod are usually not constant, but are adjusted according to the actual situation. Typically, the feed speed of the silicon rod is adjusted at the infeed side, the middle position, and the exit side, resulting in stripes 13 of varying density on the silicon wafer surface at the infeed side, the middle region 10, and the exit side. Furthermore, during silicon rod cutting, the dicing wire reciprocates, undergoing acceleration, uniform speed, and deceleration in a cyclical motion, with the cutting speed along the X-direction. When the linear speed of the dicing wire accelerates from 0 to the set target speed, it cuts stripes 13 (i.e., bright stripes) on the silicon wafer, the width of which is equal to the acceleration time multiplied by the feed speed. When the wire cuts at the target linear speed, it cuts the texture between the stripes (i.e., dark stripes), the width of which is equal to the cutting time at the target linear speed multiplied by the feed speed. The bright and dark patterns tend to alternate.

[0064] Specifically, in this embodiment, the dicing line can cut the silicon rod along a first direction x to form stripes 13 extending along the first direction x on the silicon wafer. The silicon rod can be fed along a second direction y to form multiple stripes 13 distributed along the second direction y on the silicon wafer. As a cutting method, since the feed speed and linear velocity of the silicon rod are greatest when the dicing line cuts the middle region of the silicon rod, the surface profile of the middle region 10 of the silicon wafer is larger than the surface profile value Rt of the infeed and outfeed areas of the silicon wafer. Therefore, the surface profile condition of the middle region 10 of the silicon wafer can be used to characterize the overall surface profile condition of the silicon wafer.

[0065] As shown in Figure 4, the cross-sectional shape of the multiple stripes 13 distributed along the second direction y in the middle region 10 of the silicon wafer exhibits an alternating distribution of peaks and troughs. Figure 4 is only a schematic diagram of the surface profile data; it could also represent an alternating arrangement of peaks and troughs of a curve. The peak is the center of or near the center of the stripe 13. A trough can be formed between two adjacent stripes 13, creating a surface profile peak-trough height difference Rt. Since Rt satisfies 2 μm ≤ Rt ≤ 8.5 μm, the distribution range of the surface profile peak-trough height difference is small, resulting in a relatively uniform surface flatness of the silicon wafer. Therefore, after processing the film layer on the silicon wafer surface, during the printing of electrode grid lines on the film layer, the relatively uniform flatness of the silicon wafer leads to a more uniform width and thickness of the electrode grid lines, resulting in lower grid line resistance and facilitating current conduction on the grid lines. This improves the photoelectric conversion efficiency of the battery using the silicon wafer.

[0066] In specific applications, as a detection method: a laser scans an 11mm window perpendicular to the silicon wafer surface, taking points at 6μm intervals, resulting in approximately 1800 points within the 11mm window, forming the corresponding contour within this window range; the laser uses the principle of triangulation displacement measurement to acquire the contour data of the silicon wafer surface. In this embodiment, a laser displacement sensor moves along a direction perpendicular to the silicon wafer surface (knife marks), i.e., along the second direction, selecting a 11mm measurement area in the middle region 10, and collecting contour data of 1800 measurement points on the silicon wafer surface. Of course, depending on the laser model, such as different laser power, other window ranges can be selected, such as 15mm, 20mm windows, etc., and other point density can also be selected. The data collected by the laser displacement measurement sensor shows an alternating arrangement of peaks and troughs along the measurement direction. The difference between multiple adjacent peaks and troughs is calculated, and the average of the differences is taken, which is the peak-trough height difference Rt of the silicon wafer surface contour; or, the average of multiple peak data and the average of multiple trough data are calculated, and the difference is taken, which is Rt. Preferably, at least three sets of data are measured for each silicon wafer, and the average value is calculated. In this embodiment, Rt is data on the surface contour of the silicon wafer collected within a certain area, rather than randomly selected single-point data; therefore, it can be used to characterize the contour flatness of the silicon wafer surface and reflect the uniformity of the silicon wafer surface flatness.

[0067] In some optional embodiments of this application, as shown in FIG2, the crest spacing D of the surface profile of the intermediate region 10 satisfies 1.4mm≤D≤3.9mm. The crest spacing D can be the width between two adjacent troughs or two adjacent crests along the measurement direction in the acquired profile data, which is approximately the distance between the centers of two adjacent stripes 13.

[0068] In practical applications, during the process of wire cutting the silicon rod to obtain the silicon wafer, a damage layer is easily formed on the surface of the silicon wafer. The greater the depth of the damage layer, the lower the strength of the silicon wafer. In practical applications, the severely damaged area on the surface of the silicon wafer is prone to have trough regions. By controlling the peak spacing D, the width of the severely damaged area along the second direction y can be controlled, thereby reasonably controlling the strength of the silicon wafer.

[0069] In this embodiment, by controlling the peak spacing D of the surface contour of the intermediate region 10 between 1.4 mm and 3.9 mm, the peak spacing D can be made neither too large to affect the strength of the silicon wafer, nor too small to affect the cutting efficiency of the silicon wafer, thus simultaneously balancing the cutting efficiency and strength of the silicon wafer.

[0070] For example, the crest spacing D of the surface profile of the intermediate region 10 can be any one of 1.4mm, 2.0mm, 2.7mm, 3.2mm and 3.9mm. In this embodiment of the application, the specific value of the crest spacing D of the surface profile of the intermediate region 10 is not limited.

[0071] In specific applications, the peak spacing D of the surface profile of the intermediate region 10 can be measured using tools such as a sorting machine or vernier calipers, or it can be obtained from the spacing between adjacent peaks or troughs arranged alternately along the measurement direction, as collected by a displacement sensor. This application embodiment does not specifically limit the method for measuring the peak spacing D of the surface profile of the intermediate region 10.

[0072] Optionally, the silicon wafer surface has a damage layer with a thickness of 3-5 micrometers to keep the thickness of the damage layer within a reasonable range. This avoids the damage layer being too deep and affecting the strength of the silicon wafer, while also preventing the damage layer from being too shallow and affecting the cutting efficiency of the silicon wafer. In practical applications, the thickness of the damage layer can be controlled by adjusting the cutting speed and quality of the cutting lines.

[0073] For example, the thickness of the damage layer on the silicon wafer surface can be 3 mm, 3.5 mm, 4.2 mm, 4.6 mm or 5 mm, etc. The embodiments of this application do not specifically limit the thickness of the damage layer.

[0074] As shown in Figures 1 and 2, stripe 13 extends in an arc shape on the middle region 10, with the vertex of stripe 13 located in the middle region 10 along the first direction x, and the endpoint of stripe 13 located on the second side 12. The distance between the vertex and the endpoint along the second direction y is L2, satisfying: 1.5 mm < L2 < 2.5 mm. Since L2 can be used to characterize the maximum span of a single stripe 13 along the second direction y, satisfying 1.5 mm < L2 < 2.5 mm allows for a smaller area spanned by a single stripe 13.

[0075] In practical applications, when printing gate lines on the silicon wafer, the gate lines can extend along the first direction x. When the peak spacing D on the silicon wafer surface satisfies 1.4mm ≤ D ≤ 3.9mm, and the distance L2 between the apex and the endpoint along the second direction y satisfies 1.5mm < L2 < 2.5mm, it facilitates the printing of gate lines on the silicon wafer surface while minimizing the peak and trough areas that a single gate line needs to cross, thus avoiding breakage of the gate line when crossing areas. Specifically, as one implementation, by controlling the peak spacing D and the distance L2, any gate line crosses no more than three stripes.

[0076] In practical applications, the dicing lines that form marks on the silicon wafer can affect the uniformity of the texturing pyramid and the depth of the etching process. The morphology of the peak regions on the silicon wafer surface (e.g., those cut at linear speed acceleration) is similar, as are the morphologies of the valley regions (e.g., those cut at a uniform speed). Controlling the width of the peak or valley regions allows most or all of a single cell gate line to be located within a single peak or valley region, ensuring better contact between the gate line and the silicon substrate in that region and thus preventing breakage when the gate line crosses regions.

[0077] For example, the distance L2 between the vertex and the endpoint of stripe 13 along the second direction y can be 1.5 mm, 1.8 mm, 1.9 mm, 2.0 mm, 2.3 mm or 2.5 mm, etc. In this embodiment of the application, the distance L2 between the vertex and the endpoint along the second direction y is not specifically limited.

[0078] As shown in Figure 2, the line connecting the vertex and endpoint of stripe 13 is the first line, and the line extending from the vertex of stripe 13 along the first direction x to the second side 12 is the second line. The angle between the first line and the second line is α, satisfying: 1°≤α≤8°. In practical applications, by controlling the size of the angle α, the distance L2 between the vertex and endpoint of stripe 13 along the second direction y can be controlled to satisfy 1.5 mm < L2 < 2.5 mm. Furthermore, during the process of cutting the silicon wafer with a dicing wire, considering the direction of movement of the dicing wire, the dicing wire first contacts the second side 12. The angle between the extension direction of stripe 13 and the first direction x is the largest. If the maximum angle α is less than 45°, the 45° dissociation angle of the silicon rod can be avoided, reducing edge defects on the silicon wafer. That is, under the condition of satisfying 1°≤α≤8°, edge defects on the silicon wafer can also be avoided, reducing the breakage rate of the silicon wafer. Furthermore, the angle α between the first and second lines on the silicon wafer reflects the bow of the cutting wire during silicon rod cutting. The bow, or the degree of curvature of the cutting wire, is smaller. A smaller bow results in a stronger cutting ability and a smoother silicon wafer surface. Conversely, a larger angle α leads to greater deformation of the diamond wire under stress, potentially causing breakage. Therefore, based on the stress conditions during wire mesh cutting and the required silicon wafer surface flatness, the angle α obtained from the cutting must satisfy 1° ≤ α ≤ 8°.

[0079] For example, α can be 1°, 3°, 4°, 6° or 8°, etc. The specific value range of α is not limited in this embodiment of the application.

[0080] In practical applications, during the wire cutting process of the silicon wafer, wire marks are also formed on the surface of the silicon wafer. Wire marks are a combination of macroscopically undulating grooves on the silicon wafer surface. They are below the surface plane, similar to trenches below the ground plane, and are arranged in the cutting direction. Wire marks are caused by the accumulation of abrasive particles on the wire; during cutting, a large amount is removed, resulting in a relatively deep groove. In the embodiments of this application, the maximum value of the wire marks on the silicon wafer surface can be less than or equal to 17 micrometers, and further, the maximum value of the wire marks on the silicon wafer surface can be limited to less than or equal to 13 micrometers to reduce the impact of wire marks on the strength of the silicon wafer, thereby reducing the breakage rate of the silicon wafer. In this application, based on limiting the height difference Rt of the surface profile peaks and valleys, that is, limiting the surface flatness uniformity, the maximum value of the wire marks is further limited, thereby limiting the maximum value of the unevenness in the thickness direction, thereby further controlling the quality of the silicon wafer surface.

[0081] In some optional embodiments of this application, as shown in Figures 1 and 2, the surface is sequentially provided with a first region 14, a second region 16, and a third region 15, arranged sequentially along the second direction y; wherein the stripe density on the first region 14 and the third region 15 is greater than the stripe density on the second region 16. Stripe density refers to the number of stripes within a range of at least 5 mm along the second direction. In actual silicon wafer products, the region division of the silicon wafer can be adjusted according to the actual process and the distribution of stripe density, and the number of stripes within a range such as 8 mm, 10 mm, or 12 mm can also be selected as the stripe density. Specifically, the first region 14 can be the infeed area of ​​the silicon wafer surface, and the third region 15 can be the outfeed area of ​​the silicon wafer surface. The intermediate region 10 is located within the second region 16. In practical applications, during the process of wire cutting the silicon rod to obtain a silicon wafer, the silicon rod has a chamfer when the wire enters from the infeed surface. To reduce the breakage rate in the chamfered area, the feed speed of the silicon rod is slow, and the number of wire reciprocating cuts is high, resulting in denser stripes 13. In the middle of the cutting process, the wire cutting speed is faster, and the silicon rod feed speed is also faster, resulting in sparser stripes 13. Upon reaching the exit position, the silicon rod has a chamfered area and is close to the resin plate. To reduce the breakage rate at the exit position, the cutting speed is slowed down significantly, and the number of wire reciprocating cuts is also high, resulting in denser stripes 13. Optionally, the width of the first region 14 along the second direction y is a first width, the width of the second region along the second direction y is a second width, and the width of the third region 15 along the second direction y is a third width; wherein the second width is greater than the first width and the third width. Since the cutting speed of the second region is faster, by controlling the second width of the second region to be greater than the width of the infeed position and the exit position, the overall cutting speed of the silicon wafer can be made faster.

[0082] Optionally, the width of the silicon wafer along the second direction y is the total width, the first width accounts for 25%-35% of the total width, the second width accounts for 54%-65% of the total width, and the third width accounts for 10%-20% of the total width. In the actual slicing process, the area corresponding to the first width can be the width of the infeed area, and the width of the third area 15 can be the width of the outfeed area.

[0083] In practical applications, during the silicon wafer cutting process, by controlling the proportions of the first region 14, the second region, and the third region 15, production costs are controlled through the mixed use of new and old wires while ensuring the surface morphology quality of the silicon wafer, thereby producing silicon wafer products with three regions. Since the entry and exit areas of the silicon wafer have chamfers, to reduce edge defects, damage, and fragmentation in the chamfered areas during diamond wire cutting, the feed speed of the entry and exit areas is controlled to be different from that of the second region. This difference in feed speed between the entry / exit areas and the second region results in different widths and numbers of stripes 13. Furthermore, considering the chamfers at the four corners of the silicon wafer, adjusting the widths of the first region 14 and the third region 15 can reduce the defect rate when slicing the chamfered areas. Simultaneously, adjusting the feed speed in the second region improves cutting efficiency. In other words, by adjusting the cutting speed of the cutting wire, three regions with different widths and densities of stripes 13 can be formed on the surface of the silicon wafer, balancing cutting efficiency and cutting quality.

[0084] For example, the first width is at least greater than 10 mm, specifically greater than 10 mm and less than 50 mm; the third width is at least greater than 5 mm, specifically greater than 5 mm and less than 35 mm. In practical applications, by controlling the first width and the third width, both poor silicon wafer cutting caused by excessively small widths and excessively large widths can be avoided, thus preventing both high-quality and low-efficiency silicon wafer cutting. In other words, by controlling the first width and the third width, both cutting quality and efficiency can be balanced.

[0085] In some optional embodiments of this application, referring to FIG3, the region 10 mm away from the first side 11 along the second direction y is the first edge region 141; the first edge region 141 is located within or coincides with the first region 14. The region 5 mm away from another first side 11 along the second direction is the third edge region 151; the third edge region 151 is located within or coincides with the third region 15. The stripe density of the middle region 10 is less than the stripe density of the first edge region 141 or the third edge region 151. In this embodiment, the stripes are arc-shaped, and the direction from the concave side of the arc to the convex side is the direction of the second direction. Along the direction of the second direction, the surface sequentially includes the third region 15, the second region 16, and the first region 14. The first side 11 includes two opposing first side 11s, respectively located in the first region 14 and the third region 15.

[0086] In practical applications, the first region 14 is the feed area during silicon rod cutting, and the silicon rod itself has a chamfer. During cutting, the process of the first region needs to be adjusted. The feed speed of the first region is slower to reduce problems such as edge defects, damage, and fragmentation that may occur during cutting in the first region. The first edge region 141 is selected as a smaller range of the first region, that is, the first edge region 141 is the area 10 mm away from the first side 11. Minimizing the first region can reduce the area with a slower feed speed, thereby reducing the time required for cutting the first region. In this embodiment, the stripe density of the first edge region 141 is greater than that of the middle region; the stripe density of the first edge region can be determined by reading the bright and dark stripes in any area of ​​the first edge region.

[0087] The third region 15 is the exit area during silicon rod cutting. In this region, the cutting line is arc-shaped and prioritizes cutting both ends of the first side 11 of the silicon rod. The feed speed of the third region 15 is relatively slow to reduce edge defects, damage, and fragmentation during cutting. Therefore, selecting the smallest area of ​​the third region 15 as the third edge region 151 ensures that the cutting line completes the cutting of the exit area. Simultaneously, adjusting the process of the third region can minimize the fragmentation rate during cutting. In this embodiment, the distance between the cut third edge region and the first side is 5 mm; the stripe density of the third edge region is greater than that of the middle region; the stripe density of the first edge region can be determined by reading the bright and dark patterns in any area of ​​the first edge region.

[0088] The following is an example of a silicon wafer cutting process according to an embodiment of this application:

[0089] Step 1: Provide a square bar, wherein the infeed and outfeed sides of the square bar are chamfered, the first side length of the square bar is 182.2~210, and the second side length of the square bar is 182.2~210.

[0090] Step 2: Use a slicing machine to cut the square rod into silicon wafers. The slicing process specifically includes:

[0091] ① The table speed (feed speed of silicon rod) in the feed zone is 1.8~2.2mm / min, the acceleration of diamond wire is 5~6.5m / s2, the depth of the feed zone is 3~7mm, and the cutting line is used for reciprocating cyclic cutting.

[0092] ② After completing the cutting in the feed area, adjust the table speed to 2.0~2.5mm / min, the acceleration of the cutting line to 4.5~7m / s2, and the depth of the feed area to 155~175mm, and use the cutting line to cut in a reciprocating cycle.

[0093] ③ In the cutting zone, adjust the table speed to 0.2~1.0mm / min, the acceleration of the cutting line to 5~6.5m / s2, and the depth of the feed zone to 10~20mm, and use the cutting line to perform reciprocating cyclic cutting.

[0094] The silicon wafer obtained through the above process has a surface profile peak-to-trough height difference Rt in the middle region of its surface that satisfies 2 μm ≤ Rt ≤ 8.5 μm. The peak-to-peak spacing D of the surface profile in the middle region satisfies 1.4 mm ≤ D ≤ 3.9 mm. The maximum line mark value Rmax on the silicon wafer surface is ≤ 17 μm, and can be further limited to ≤ 13 μm. The distance L2 between the vertex and endpoint of the stripe 13 along the second direction y satisfies: 1.5 mm < L2 < 2.5 mm. The breaking force of the vertical cut of the silicon wafer is 3.5–5 N.

[0095] In summary, the silicon wafer described in the embodiments of this application may include at least the following advantages:

[0096] In this embodiment, the central region of the silicon wafer occupies most of its surface. Due to the use of diamond wire mesh cutting, the unevenness of the central region is relatively greater than that of the regions at the ends of the wafer. This application controls the peak-to-trough height difference Rt of the surface profile in the central region to satisfy 2 μm ≤ Rt ≤ 8.5 μm, thus achieving a more uniform surface smoothness for the silicon wafer. Therefore, after processing the film layer on the silicon wafer, during the printing of electrode grid lines on the film layer, the uniform smoothness of the silicon wafer results in more uniform width and thickness of the electrode grid lines, leading to lower grid line resistance and improved current conduction. This, in turn, improves the photoelectric conversion efficiency of the battery using the silicon wafer.

[0097] As another embodiment of this application, referring to FIG5, a schematic diagram of the structure of a silicon wafer according to an embodiment of this application is shown. As shown in FIG5, the surface includes a first surface and a second surface disposed opposite to each other along a third direction y, and a plurality of silicon wafer side surfaces 20 connecting the first surface and the second surface, wherein the average roughness Ra of at least one silicon wafer side surface 20 is 0.05-0.2 μm. The plurality of silicon wafer side surfaces 20 include a first silicon wafer side surface 21, a second silicon wafer side surface 22, and a third silicon wafer side surface 23.

[0098] In this embodiment, the first surface and the second surface are at least one surface, the third direction y is the thickness direction of the silicon wafer, and the first and second surfaces of the silicon wafer, which are disposed opposite to each other along the third direction y, refer to the two surfaces formed after the square rod is wire-cut, and the side surface of the silicon wafer refers to the surface along the thickness direction of the silicon rod. Specifically, as one implementation, one or both of the first and second surfaces have stripes.

[0099] Based on the above embodiments, as one implementation method, the average roughness Ra of at least one of the plurality of silicon wafer sides 20 is 0.05-0.2 μm; and / or, the roughness Rz of at least one silicon wafer side 20 is 0.5-2.5 μm.

[0100] Specifically, in this embodiment, the roughness data of the silicon wafer side surface 20, such as the average roughness Ra and roughness Rz, can be measured by direct contact, such as with a roughness meter, or by non-contact measurement, such as with an optical measurement method like a laser scanning microscope. In this embodiment, by limiting the average roughness Ra of at least one silicon wafer side surface 20 to 0.05-0.2 μm and the roughness Rz of at least one silicon wafer side surface to 0.5-2.5 μm, the micro-defects on the silicon wafer side surface 20 can be reduced, thereby reducing the breakage rate of the silicon wafer during slicing, cleaning, and other processes, and correspondingly reducing the breakage rate of the solar cells and solar modules using the silicon wafer.

[0101] In specific applications, the breakage rate of the silicon wafer during slicing and subsequent production processes (such as at the battery end) is related to the average roughness Ra of the silicon wafer side surface 20. Experimental results show that the larger the average roughness Ra and roughness Rz of the silicon wafer side surface 20, the greater the breakage rate at the battery end.

[0102] For example, the average roughness Ra reflects the average quality of micro-defects on the side surface of the silicon wafer. When the average roughness Ra of the silicon wafer side surface 20 is less than 0.2 μm, the breakage rate at the cell end is less than 1%. When the average roughness Ra is greater than 0.2 μm, the breakage rate at the cell end is greater than 1%. For example, when the average roughness Ra is 0.3 μm, the breakage rate at the cell end is 1.02%; when the average roughness Ra is 0.5 μm, the breakage rate is 1.05%.

[0103] Roughness Rz reflects the maximum value of micro-defects on the side surface of the silicon wafer. When the roughness Rz of the silicon wafer side surface 20 is less than 0.5 μm, the fragmentation rate at the cell end is less than 1%. When the average roughness Ra is greater than 2.5 μm, the fragmentation rate at the cell end is greater than 1%. For example, when the roughness Rz is 3 μm, the fragmentation rate at the cell end is 1.03%; when the roughness Rz is 3.5 μm, the fragmentation rate is 1.04%.

[0104] In practical applications, the average roughness Ra of the silicon wafer side surface 20 is also related to the processing difficulty of the silicon wafer side surface 20. During the process of forming the silicon wafer using silicon rod slicing, the outer surface of the silicon rod needs to be polished to control the roughness of the silicon wafer side surface 20. The smaller the average roughness of the silicon wafer side surface 20, the higher the workload and quality requirements for polishing the silicon rod. In specific production processes, when the average roughness Ra of the silicon wafer side surface 20 is less than 0.05 μm, the workload for polishing the silicon rod becomes extremely large, resulting in very high production costs. Furthermore, when the average roughness Ra of the silicon wafer side surface is less than 0.05 μm, the breakage rate during slicing and subsequent production processes (cell end) is already very low. Therefore, considering processing performance and production costs, the average roughness Ra of the silicon wafer side surface 20 should be controlled above 0.05 μm.

[0105] In this embodiment, by controlling the average roughness Ra of the silicon wafer side surface 20 to 0.05-0.2 μm, the breakage rate of the silicon wafer during the slicing process can be significantly reduced, and the breakage rate of the silicon wafer at the battery end can be reduced accordingly, thereby reducing the overall production cost of the silicon wafer. At the same time, the polishing operation and production cost of the silicon rod can be taken into account, which is easy to implement.

[0106] For example, the average roughness Ra of the silicon wafer side surface 20 can be 0.05um, 0.08um, 0.12um, 0.17um and 0.2um, etc. In this embodiment of the application, the average roughness Ra of the silicon wafer side surface 20 is not specifically limited.

[0107] It should be noted that in practical applications, after the silicon ingot is wire-cut, the first silicon wafer side 21 is part of the third surface 211 of the silicon ingot, and the second silicon wafer side 22 is part of the fourth surface 212 of the silicon ingot. The cut silicon wafers generally need to be cleaned with acid or alkali to obtain the final silicon wafer product. The roughness of the silicon wafer side 20 is basically the same as the roughness data of the silicon ingot from which the silicon wafer was cut, or the roughness of the silicon wafer side 20 is slightly smaller than the roughness data of the silicon ingot surface. Specifically, one optional measurement method is to directly measure the roughness of the silicon ingot, thereby defining or characterizing the roughness of the silicon wafer side 20 by measuring and defining the average surface roughness of the silicon ingot. Another optional measurement method is to measure the roughness of the silicon wafer side using a roughness meter or a laser scanning microscope.

[0108] For example, the surface roughness data of the silicon rod can be measured using a roughness meter (e.g., an SJ-210 roughness meter). For instance, in the case where the silicon rod is a square silicon rod, the surface roughness of the silicon rod can be measured radially using a roughness measuring device.

[0109] In some optional embodiments of this application, among the plurality of silicon wafer sides 20 of the silicon wafer body 20, at least one silicon wafer side 20 has an average roughness Ra greater than the average roughness Ra of the other silicon wafer sides 20. During the process of cutting the silicon rod into silicon wafers, one surface of the silicon rod needs to be bonded to a resin plate. To improve the bonding reliability between the silicon rod and the resin plate, the surface on which the silicon rod is bonded to the resin plate needs to have a certain roughness.

[0110] Specifically, when the roughness of the adhesive surface on the silicon rod bonded to the resin plate is relatively large, the adhesive surface has a larger surface area, providing more contact area to enhance adhesion and thus making the adhesive bond stronger. Furthermore, due to the larger roughness of the adhesive surface, there are more pits and cracks. During bonding, within the same area, the adhesive can fill more surface pits and cracks, forming a stronger physical bond, thereby improving the adhesive bonding strength. In addition, the large roughness of the adhesive surface helps the wire mesh maintain stability when it is cut into the contact area between the wire mesh and the resin plate, reducing the risk of wafer breakage. That is, the silicon rod must have at least one surface (the adhesive surface) with a rougher surface than the others, which can be used for bonding with the resin plate. Therefore, after the silicon rod is cut into silicon wafers, the average roughness Ra of the silicon wafer side surface 20 formed by the rougher surface bonded to the resin plate is greater than the average roughness Ra of the other silicon wafer side surfaces 20.

[0111] It should be noted that in practical applications, the silicon rod can be bonded to the resin plate on one or more surfaces. Correspondingly, the silicon wafer can also have one or more silicon wafer sides 20 with an average roughness Ra greater than other silicon wafer sides 20. This application embodiment does not limit this.

[0112] In some optional embodiments of this application, the plurality of silicon wafer sides 20 include a first silicon wafer side 21 and a second silicon wafer side 22 disposed opposite to each other. The first silicon wafer side 21 has a first chamfer 214 at both ends, and the second silicon wafer side 22 has a second chamfer 215 at both ends. The length of the first silicon wafer side 21 is greater than the size of the second silicon wafer side 22; the edge length of the first chamfer 214 is less than or equal to the edge length of the second chamfer. The average roughness Ra of the first silicon wafer side 21 is greater than the average roughness Ra of the second silicon wafer side 22.

[0113] In this embodiment, the first silicon wafer side 21 and the second silicon wafer side 22 are two oppositely arranged sides of the silicon wafer. The first chamfers at both ends of the first silicon wafer side 21 correspond to the first chamfers of the silicon rod; the second silicon wafer side 22 has second chamfers at both ends, corresponding to the second chamfers of the silicon rod. Specifically, in this embodiment, the edge length of the first chamfer 214 is less than or equal to the edge length of the second chamfer 215, resulting in the length of the first silicon wafer side 21 being greater than or equal to the length of the second silicon wafer side 22. This provides more contact surface during the adhesive bonding of the silicon rod, enhancing adhesion and making the bonding between the silicon rod and the resin board more robust. Furthermore, the two first chamfers 214 of the first silicon wafer side 21 are identical, and the two second chamfers 215 of the second silicon wafer side 22 are identical, facilitating tension control of the wire mesh during silicon rod cutting.

[0114] Optionally, the average roughness Ra of the first silicon wafer side surface 21 is greater than the average roughness Ra of the second silicon wafer side surface 22; and / or, the roughness Rz of the first silicon wafer side surface 21 is greater than or equal to the roughness Rz of the second silicon wafer side surface 22.

[0115] In practical applications, as one implementation method, by defining the roughness Ra or Rz of the third surface of the silicon rod as greater than the roughness of the fourth surface, when selecting the first silicon wafer side surface 21 as the adhesive surface, the greater roughness provides more surface area, which can provide more contact surface to enhance adhesion, thereby making the adhesive bond between the silicon rod and the resin board stronger. Furthermore, the surface with greater roughness has more pits and cracks; during bonding, in the same area, the adhesive can fill more surface pits and cracks, forming a stronger physical connection, thereby improving the adhesive bonding strength and reducing wafer detachment during slicing.

[0116] In practical applications, by setting a first chamfer 214 at both ends of the first silicon wafer side 21 and a second chamfer 215 at both ends of the second silicon wafer side 22, the breakage rate of the silicon wafer during slicing and production can be effectively reduced.

[0117] In some optional embodiments of this application, the edge length of the first chamfer 214 is less than the edge length of the second chamfer 215, so that the size of the first chamfer 214 is less than the size of the second chamfer 215, thereby making the length of the first silicon wafer side surface 21 between the two first chamfers 214 greater than the length of the second silicon wafer side surface 22 between the two second chamfers 215.

[0118] The edge length of the first chamfer 214 refers to the length of the chamfer along the circumferential direction of the side of the silicon wafer. The edge length of the second chamfer 215 refers to the length of the chamfer along the circumferential direction of the side of the silicon wafer. In practical applications, the edge length of the first chamfer 214 can specifically be the length of the hypotenuse of the first chamfer 214, and the edge length of the second chamfer 215 can specifically be the length of the hypotenuse of the second chamfer 215.

[0119] Optionally, the edge length of the first chamfer 214 is 1-2 mm, and the edge length of the second chamfer 215 is 1-8 mm. In this way, on the one hand, the edge length of the first chamfer 214 is smaller than the edge length of the second chamfer 215, and on the other hand, the first chamfer 214 and the second chamfer 215 are easier to process.

[0120] Specifically, the side 100 between the first silicon wafer side 21 and the second silicon wafer side 22 can be collectively referred to as the third silicon wafer side 23. That is, the first chamfer 214 is located between the first silicon wafer side 21 and the third silicon wafer side 23, and the second chamfer 215 is located between the second silicon wafer side 22 and the third silicon wafer side 23. In practical applications, while controlling the edge lengths of the first chamfer 214 and the second chamfer 215, the included angles between the first chamfer 214 and the second chamfer 215 and the third silicon wafer side 23 can also be controlled to reduce the breakage rate of the silicon wafer during slicing. For example, by controlling the included angles between the first chamfer 214, the second chamfer 215 and the third silicon wafer side 23 to 40°-50°, it is convenient to process the first chamfer 214 and the second chamfer 215, and at the same time, the breakage rate of the silicon wafer during slicing and subsequent processing can be significantly reduced.

[0121] Optionally, in any silicon wafer, the average roughness Ra of the first silicon wafer side surface 21 is greater than or equal to the average roughness Ra of the second silicon wafer side surface 22.

[0122] Optionally, the average roughness Ra of the first silicon wafer side surface 21 is 0.09-0.2 μm, specifically including but not limited to any one of 0.09 μm, 0.12 μm, 0.16 μm, 0.17 μm, and 0.2 μm. The average roughness Ra of the second silicon wafer side surface 22 is 0.05-0.1 μm, specifically including but not limited to any one of 0.05 μm, 0.12 μm, 0.16 μm, 0.17 μm, and 0.2 μm. In this embodiment, the value of the average roughness Ra of the first silicon wafer side surface 21 and the second silicon wafer side surface 22 is not specifically limited.

[0123] Optionally, in any silicon wafer, the roughness Rz of the first silicon wafer side surface 21 is greater than or equal to the roughness Rz of the second silicon wafer side surface 22.

[0124] Optionally, the roughness Rz of the first silicon wafer side surface 21 is 1.1-2.5 μm, specifically including but not limited to any one of 1.1 μm, 1.4 μm, 1.7 μm, 2.0 μm and 2.5 μm; the roughness Rz of the second silicon wafer side surface 22 is 0.8-1.3 μm, specifically including but not limited to any one of 0.8 μm, 0.95 μm, 1.0 μm, 1.1 μm and 1.3 μm.

[0125] Optionally, the average roughness Ra of the first surface and the second surface is 0.05-0.18 μm; and / or, the roughness Rz of the first surface and the second surface is 0.5-1.0 μm. By adjusting the average roughness Ra and roughness Rz of the first and second surfaces, the overall surface quality of the silicon wafer can be improved, avoiding an excessively thick damage layer on the silicon wafer surface and excessive removal at the battery end.

[0126] In summary, the silicon wafer described in the embodiments of this application may include at least the following advantages:

[0127] In this embodiment of the application, by limiting the average roughness Ra of at least one side surface of the silicon wafer to 0.05-0.2 μm, and / or, the roughness Rz of at least one of the plurality of silicon wafer sides to 0.5-2.5 μm, the average micro-defect and maximum micro-defect values ​​of the silicon wafer sides can be reduced, thereby reducing the breakage rate of the silicon wafer during the slicing process, and correspondingly reducing the breakage rate of the solar cells and solar modules using the silicon wafer.

[0128] This application also provides a silicon rod, including a silicon rod body, the silicon rod body including a plurality of surfaces parallel to the axial direction of the silicon rod. The average roughness Ra of at least one of the surfaces is 0.05-0.2 μm; and / or, the roughness Rz of at least one of the surfaces is 0.8-2.5 μm.

[0129] Specifically, as one embodiment, this application provides a silicon rod, as shown in FIG6. The silicon rod may specifically include: a silicon rod body 10, which may specifically include a third surface 211 and a fourth surface 212 parallel to and opposite to the axial direction of the silicon rod, and a plurality of side surfaces 100 connecting the third surface 211 and the fourth surface 212. At least one of the third surface 211 and the fourth surface 212, or the plurality of side surfaces 100 connecting the third surface 211 and the fourth surface 212, has an average surface roughness Ra of 0.05-0.2 μm.

[0130] In this embodiment, the silicon rod is a square rod. The axial direction of the silicon rod refers to the length direction of the square rod prism. After the silicon rod is cut to obtain a silicon wafer, the axial direction of the silicon rod is consistent with the thickness direction of the silicon wafer, i.e., the third direction y. The surface parallel to the axial direction of the silicon rod refers to the side surface of the square rod.

[0131] Specifically, the average roughness Ra represents the arithmetic mean of the absolute values ​​of the profile offsets over a sampling length. In this embodiment, a roughness meter is used to measure the roughness along the axial direction perpendicular to the silicon rod, with a measurement range of 13.5 mm and a measurement speed of 0.5 mm / s. During actual measurement, different areas on the surface of a single silicon rod are selected for measurement, such as five areas at distances of 20 mm, 40 mm, 60 mm, 80 mm, and 100 mm from the axial edge of the silicon rod. At least three silicon rods are measured simultaneously; finally, the average value of the measured data is calculated.

[0132] In this embodiment, by limiting the average roughness Ra of at least one surface of the silicon rod to 0.05-0.2 μm, the overall quality of the silicon rod surface is limited, thereby reducing micro-defects on the silicon rod surface. This reduces the breakage rate of the silicon rod during the slicing process, and correspondingly reduces the breakage rate of the solar cells and solar modules using the silicon wafers.

[0133] In practical applications, the silicon rod is cut into silicon wafers using a diamond wire mesh. During the cutting process, the surface roughness of the silicon rod is related to the fragmentation rate of the silicon wafers. Furthermore, during the cutting process, the silicon rod needs to be bonded to a resin board. The surface roughness of the silicon rod is related to the bonding strength and stability of the resin board. Excessive roughness leads to an increased fragmentation rate. This application addresses this by optimizing the grinding and polishing process of the silicon rod to improve its surface roughness, thereby reducing the fragmentation rate of the silicon wafers during cutting.

[0134] For example, when the average surface roughness Ra of the silicon rod is less than 0.2 μm, the breakage rate at the silicon wafer end is less than 0.8%. When the average surface roughness Ra is greater than 0.2 μm, the breakage rate at the silicon wafer end is greater than 0.8%. For instance, when the average surface roughness Ra is 0.3 μm, the breakage rate at the silicon wafer end is 1.02%; when the average surface roughness Ra is 0.5 μm, the breakage rate is 1.05%.

[0135] Based on the above embodiments, a silicon rod is provided, wherein the roughness Rz of at least one of the third surface 211, the fourth surface 212, or the plurality of side surfaces 100 of the silicon rod is 0.8-2.5 μm.

[0136] Specifically, Rz represents the sum of the maximum profile peak height and the maximum profile valley depth within a sampling length; this parameter reflects the microscopic roughness of the surface. In this embodiment, a roughness meter is used for roughness measurement, measured along the axial direction perpendicular to the silicon rod, with a measurement range of 13.5 mm and a measurement speed of 0.5 mm / s. In actual measurement, different areas on the surface of a single silicon rod are selected for measurement, such as five areas at distances of 20 mm, 40 mm, 60 mm, 80 mm, and 100 mm from the axial edge of the silicon rod. At least three silicon rods are measured simultaneously; finally, the average value of the measured data is calculated.

[0137] In this embodiment, the maximum defect on the silicon rod surface is further limited by defining the roughness Rz, thereby further defining the quality of the silicon rod surface. When the silicon rod is polished, limiting the surface roughness reduces the thickness of the damage layer on the surface and sides of the silicon rod; simultaneously, when the surface or sides of the silicon rod contact the diamond wire mesh, it avoids the problem of excessively large micro-defects causing micro-crack propagation and leading to increased silicon wafer fragmentation.

[0138] Specifically, for example, when the surface roughness Rz of the silicon rod is less than 0.8 μm, the fragmentation rate at the silicon wafer end is less than 0.8%. When the roughness Rz is greater than 2.5 μm, the fragmentation rate at the silicon wafer end is greater than 0.8%. For example, when the roughness Rz is 3 μm, the fragmentation rate at the silicon wafer end is 1.02%; when the roughness Rz is 3.5 μm, the fragmentation rate is 1.04%.

[0139] Based on the above embodiments or other optional embodiments, as shown in Figures 6 and 7, the silicon rod is a half-rod, which is cut from a finished square silicon rod. The third surface 211 of the silicon rod has a first chamfer 214 at both ends, and the fourth surface has a second chamfer 215 at both ends. The edge length of the first chamfer 214 is less than or equal to the edge length of the second chamfer 215.

[0140] In this embodiment, the third surface and the fourth surface refer to two opposite sides of the square bar. The two ends of the third surface refer to the ends of the third surface closest to its two adjacent sides. The first chamfer is provided on the two side edges adjacent to the third surface, i.e., the side edges are chamfered. The second chamfer is provided on the two side edges adjacent to the fourth surface. The edge length of the first chamfer refers to the length of the first chamfer circumferentially on the square bar. The edge length of the second chamfer refers to the length of the second chamfer circumferentially on the square bar.

[0141] Specifically, in this embodiment, the edge length of the first chamfer 214 is less than or equal to the edge length of the second chamfer 215, resulting in a larger surface area of ​​the third surface 211 than the fourth surface 212. This provides more contact surface during the adhesive bonding of the silicon rod, enhancing adhesion and making the bond between the silicon rod and the resin board stronger. Furthermore, the two first chamfers 214 of the third surface 211 are identical, and the two second chamfers 215 of the fourth surface 212 are identical, facilitating tension control of the wire mesh during silicon rod cutting.

[0142] In this embodiment, the average roughness Ra of the third surface 211 is greater than or equal to the average roughness Ra of the fourth surface 212; and / or, the roughness Rz of the third surface 211 is greater than or equal to the roughness Rz of the fourth surface 212.

[0143] Optionally, in any silicon rod, the average roughness Ra of the third surface 211 of the silicon rod is greater than or equal to the average roughness Ra of the fourth surface 212.

[0144] Optionally, the average roughness Ra of the third surface 211 of the silicon rod is 0.09-0.2 μm, specifically including but not limited to any one of 0.09 μm, 0.12 μm, 0.16 μm, 0.17 μm, and 0.2 μm. The average roughness Ra of the fourth surface 212 is 0.05-0.1 μm, specifically including but not limited to any one of 0.05 μm, 0.12 μm, 0.16 μm, 0.17 μm, and 0.2 μm. In this embodiment of the application, the values ​​of the average roughness Ra of the third surface 211 and the fourth surface 212 are not specifically limited.

[0145] Optionally, in any silicon rod, the roughness Rz of the third surface 211 of the silicon rod is greater than or equal to the roughness Rz of the fourth surface 212.

[0146] Optionally, the roughness Rz of the third surface 211 of the silicon rod is 1.1-2.5 μm, specifically including but not limited to any one of 1.1 μm, 1.4 μm, 1.7 μm, 2.0 μm and 2.5 μm; the roughness Rz of the fourth surface 212 is 0.8-1.3 μm, specifically including but not limited to any one of 0.8 μm, 0.95 μm, 1.0 μm, 1.1 μm and 1.3 μm.

[0147] In practical applications, as one implementation, the roughness Ra or Rz of the third surface 211 of the silicon rod is defined to be greater than the roughness of the fourth surface 212. When selecting the third surface 211 as the adhesive surface, the greater roughness provides a larger surface area, which can provide more contact surface to enhance adhesion, thereby making the adhesive bond between the silicon rod and the resin board stronger. Furthermore, the surface with greater roughness has more pits and cracks; during bonding, the adhesive can fill more surface pits and cracks in the same area, forming a stronger physical connection, thereby improving the adhesive bonding strength and reducing fragmentation caused by silicon wafers falling off during dicing.

[0148] Furthermore, when selecting the third surface 211 as the adhesive surface, its high roughness ensures stability and reduces the risk of wafer cracking during cutting when the wire mesh enters the contact area between the resin plate and the fourth surface 212. This is because the silicon rod and resin plate are firmly bonded together. The fourth surface 212, with its lower roughness, is preferred for initial contact with the silicon rod. As the cutting surface, its smaller roughness results in fewer pits or defects on the silicon rod surface, reducing edge defects such as notches and microcracks during wire mesh cutting.

[0149] In practical applications, by limiting the roughness of the third surface 211 to be greater than or equal to the roughness of the fourth surface 212, the processing steps for the third surface 211 can be reduced. For example, after the finished silicon rod is cut into the silicon rod of this embodiment, the more refined polishing of the third surface 211 is eliminated. This reduces the processing steps or processing time for the third surface 211 while improving the processing efficiency and quality during silicon rod cutting. In this embodiment, the fourth surface 212 of the silicon rod still undergoes more refined polishing. In specific production processes, if the average roughness Ra of the fourth surface 212 of the silicon rod is less than 0.05 μm, the workload of polishing the silicon rod becomes extremely large, resulting in very high production costs. Therefore, considering processing performance and production costs, the average roughness Ra of the fourth surface 212 should be controlled above 0.05 μm. In this embodiment, limiting the average roughness Ra of the fourth surface 212 to 0.05-0.1 μm or the roughness Rz to 0.8-1.3 μm can improve the quality of the silicon wafers during silicon rod cutting.

[0150] The following provides another example of the silicon wafer cutting process described in this application:

[0151] Step 1: Provide a silicon rod with the following specifications: dimensions of 183.6*195.2; use a grinding wheel to polish the four chamfers and four surfaces of the silicon rod, resulting in a finished square rod with dimensions of 182.3*183.9.

[0152] Step 2: Preparation of half rod: As shown in Figure 7, the finished square rod is cut transversely along the third direction z at the middle position of the long side at 183.9 using a loop. Then, the newly generated wire-cut surface is polished with a grinding wheel to produce a finished half rod with a size of 182.3*91.1, which is the silicon rod of this application.

[0153] Step 3: Slicing: The surface of the silicon rod generated in step 2, i.e. the third surface, is attached to the adhesive board and then cut along the short side direction with a length of 91.1 mm, i.e. the second direction y, to produce a silicon wafer.

[0154] In this embodiment, the roughness of the silicon rod obtained in step 2 is measured using a roughness meter. The measurement is performed along the axial direction perpendicular to the silicon rod, with a measurement range of 13.5 mm and a measurement speed of 0.5 mm / s. During the actual measurement, different areas on the surface of a single silicon rod are selected for measurement, such as five areas at distances of 20 mm, 40 mm, 60 mm, 80 mm, and 100 mm from the axial edge of the silicon rod (the position 80 mm from the axial edge is approximately the center position of the square rod's edge). At least three silicon rods are measured simultaneously. The final data for the fourth and third surfaces of the silicon rod are shown in the table below.

[0155] Table 1: Fourth surface of silicon rod (surface with lower roughness)

[0156] Table 2: Third surface of silicon rod (surface with greater roughness)

[0157] This application also provides a battery cell, which can be made from the silicon wafer described in any of the above embodiments.

[0158] In practical applications, during the fabrication of the aforementioned solar cell from silicon wafers, a film layer needs to be formed on the surface of the silicon wafer, and then grid lines are printed on the film layer. The central region of the silicon wafer surface reflects the uniformity of its surface flatness. Since the peak-to-trough height difference Rt of the surface profile in the central region satisfies 2 μm ≤ Rt ≤ 8.5 μm, the surface flatness of the silicon wafer is relatively uniform. During the cell manufacturing process, the silicon wafer undergoes wet processing, such as damage layer removal and etching, removing a portion of the silicon wafer surface thickness, such as approximately 1 μm. Thus, after processing the film layer on the silicon wafer surface, during the printing of the electrode grid lines, the relatively uniform surface flatness of the silicon wafer, especially after wet processing, results in more uniform width and thickness of the electrode grid lines, lower grid line resistance, and improved current conduction on the grid lines. This, in turn, improves the photoelectric conversion efficiency of the solar cell using the aforementioned silicon wafer.

[0159] This application also provides a photovoltaic module, which may specifically include the solar cells described in any of the above embodiments.

[0160] In this embodiment, the structure of the battery cell is the same as that of the battery cell described in any of the above embodiments, and its beneficial effects are similar, so it will not be described in detail here.

[0161] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0162] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A silicon wafer, characterized in that, At least one surface of the silicon wafer has a plurality of stripes extending in a first direction, and the plurality of stripes are spaced apart along a second direction; wherein the surface profile peak-valley height difference Rt in the middle region of the surface satisfies 2 micrometers ≤ Rt ≤ 8.5 micrometers. The first direction is the extension direction of the first side of the silicon wafer, and the second direction is the extension direction of the second side of the silicon wafer; the intermediate region refers to the region along the second direction that is at least L / 3 away from the first side of the silicon wafer, where L is the length of the second side.

2. The silicon wafer according to claim 1, characterized in that, The peak spacing D of the surface profile of the intermediate region satisfies 1.4 mm ≤ D ≤ 3.9 mm.

3. The silicon wafer according to claim 1, characterized in that, The maximum line mark value Rmax on the surface of the silicon wafer is ≤17 micrometers.

4. The silicon wafer according to claim 1 or 2, characterized in that, The stripe extends in an arc shape over the middle region, with the vertex of the stripe located in the middle region of the surface along the first direction and the endpoint of the stripe located on the second side. The distance between the vertex and the endpoint along the second direction is L2, satisfying: 1.5 mm < L2 < 2.5 mm.

5. The silicon wafer according to claim 4, characterized in that, The line connecting the vertex and the endpoint of the stripe is the first line, and the line extending from the vertex of the stripe to the second side along the first direction is the second line. The angle between the first line and the second line is α, which satisfies: 1°≤α≤8°.

6. The silicon wafer according to claim 1, characterized in that, The surface has a damage layer with a thickness of 3-5 micrometers.

7. The silicon wafer according to claim 1, characterized in that, Along the second direction, the surface is sequentially arranged with a first region, a second region, and a third region; the intermediate region is at least partially located within the second region; wherein the stripe density on the first region and the third region is greater than the stripe density on the second region; The stripe density refers to the number of stripes within a range of at least 5 mm along the second direction.

8. The silicon wafer according to claim 7, characterized in that, The width of the first region along the second direction is the first width, the width of the second region along the second direction is the second width, and the width of the third region along the second direction is the third width; wherein, The second width is greater than the first width and the third width.

9. The silicon wafer according to claim 8, characterized in that, The first width is at least greater than 10 mm, and the third width is at least greater than 5 mm.

10. The silicon wafer according to claim 1, characterized in that, Along the second direction, at least a portion of the stripe density of the intermediate region is less than the stripe density of the first edge region or the third edge region; The first edge region is a region 10 mm away from the first side along the second direction; the third edge region is a region 5 mm away from another first side opposite the first side along the second direction. The stripe density refers to the number of stripes within a range of at least 5 mm along the second direction.

11. The silicon wafer according to claim 1, characterized in that, The surface includes a first surface and a second surface disposed opposite to each other in a third direction, and a plurality of silicon wafer sides connecting the first surface and the second surface; The average roughness Ra of at least one of the silicon wafer sides is 0.05-0.2 μm; and / or, the roughness Rz of at least one of the plurality of silicon wafer sides is 0.5-2.5 μm; The third direction is the thickness direction of the silicon wafer, and the first direction, the second direction, and the third direction are all perpendicular to each other.

12. The silicon wafer according to claim 11, characterized in that, Of the plurality of silicon wafer sides, the average roughness Ra of at least one silicon wafer side is greater than the average roughness Ra of the other silicon wafer sides.

13. The silicon wafer according to claim 11, characterized in that, The plurality of silicon wafer sides include a first silicon wafer side and a second silicon wafer side disposed opposite to each other. The first silicon wafer side has a first chamfer at both ends, and the second silicon wafer side has a second chamfer at both ends. The edge length of the first chamfer is less than or equal to the edge length of the second chamfer. The average roughness Ra of the first silicon wafer side surface is greater than the average roughness Ra of the second silicon wafer side surface; and / or, the roughness Rz of the first silicon wafer side surface is greater than or equal to the roughness Rz of the second silicon wafer side surface.

14. The silicon wafer according to claim 11 or 13, characterized in that, The edge length of the first chamfer is 1-2mm, and the edge length of the second chamfer is 1-8mm.

15. The silicon wafer according to claim 11 or 13, characterized in that, The average roughness Ra of the side surface of the first silicon wafer is 0.09-0.2 μm, and the average roughness Ra of the side surface of the second silicon wafer is 0.05-0.1 μm; And / or, the surface roughness Rz of the first silicon wafer side is 1.1-2.5 μm, and the surface roughness Rz of the second silicon wafer side is 0.8-1.3 μm.

16. The silicon wafer according to claim 11, characterized in that, The average roughness Ra of the first surface and the second surface is 0.05-0.18 μm; And / or, the roughness Rz of the first surface and the second surface is 0.5-1.0 μm.

17. A silicon rod, characterized in that, Includes a silicon rod body, the silicon rod body including a plurality of surfaces parallel to the axial direction of the silicon rod; The average roughness Ra of at least one of the surfaces is 0.05-0.2 μm; and / or the roughness Rz of at least one of the surfaces is 0.8-2.5 μm.

18. The silicon rod according to claim 17, characterized in that, The silicon rod body includes a third surface and a fourth surface that are parallel to and opposite to the axial direction of the silicon rod; The average roughness Ra of the third surface is 0.09-0.2 μm, and the average roughness Ra of the fourth surface is 0.05-0.1 μm; And / or, the roughness Rz of the third surface is 1.1-2.5 μm, and the roughness Rz of the fourth surface is 0.8-1.3 μm.

19. The silicon rod according to claim 17 or 18, characterized in that, The third surface has a first chamfer at both ends, and the fourth surface has a second chamfer at both ends, wherein the edge length of the first chamfer is less than or equal to the edge length of the second chamfer; wherein, The average roughness Ra of the third surface is greater than or equal to the average roughness Ra of the fourth surface; and / or, the roughness Rz of the third surface is greater than or equal to the roughness Rz of the fourth surface.

20. A battery cell, characterized in that, The solar cell comprises: a silicon wafer as described in any one of claims 1 to 16.

21. A photovoltaic module, characterized in that, The photovoltaic module includes the solar cell as described in claim 20.

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