Solar cell and photovoltaic module

Abstract

The present application relates to the technical field of photovoltaics, and discloses a solar cell and a photovoltaic module. The solar cell comprises: a cell body comprising a first surface and a second surface arranged opposite to each other; a conductive barrier layer partially provided on the first surface; and a plurality of first grid lines provided on the conductive barrier layer, extending along a first direction, and arranged along a second direction, wherein a cross-sectional area of each of the first grid lines is greater than or equal to 250 μm2; along the thickness direction of the cell body, the height of each of the first grid lines is h; the width of each of the first grid lines is w, h / w is 0.1-0.5, and w is greater than or equal to 30 μm; and the distance between two adjacent first grid lines ranges from 0.6 mm to 1.3 mm. The manufacturing costs of the solar cell are reduced while the power generation performance of the solar cell is ensured. The addition of relatively low-price conductive metals such as a copper paste to a non-burn-through paste can reduce the manufacturing costs of grid lines.

Description

A solar cell and a photovoltaic module

[0001] Cross-reference of related applications

[0002] This application claims priority to the following Chinese patent applications filed on January 17, 2025, with application number 202510080740.9, entitled "Solar Cell and Photovoltaic Module"; filed on January 20, 2025, with application number 202510088946.6, entitled "A Solar Cell and Photovoltaic Module"; filed on February 25, 2025, with application number 202510214993.0, entitled "A Solar Cell and Photovoltaic Module"; and filed on May 27, 2025, with application number 202510697042.3, entitled "A Solar Cell and Photovoltaic Module", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of photovoltaic technology, and more particularly to a solar cell and a photovoltaic module. Background Technology

[0004] Solar cells are increasingly being used as a new energy alternative. Photovoltaic solar cells, in particular, are devices that convert sunlight into electrical energy. Specifically, solar cells utilize the photovoltaic principle to generate charge carriers, which are then extracted using electrodes, thus facilitating the efficient use of electrical energy.

[0005] As the photovoltaic industry market and production capacity continue to expand, the industry's demand for silver paste has also surged, causing the price of silver paste to rise accordingly, increasing costs and squeezing profit margins. Summary of the Invention

[0006] The purpose of this application is to provide a solar cell and a photovoltaic module that can reduce the manufacturing cost of solar cells while ensuring the power generation performance of solar cells.

[0007] To achieve the above objectives, this application provides the following technical solution:

[0008] A solar cell, comprising:

[0009] The battery body includes a first surface and a second surface that are disposed opposite to each other;

[0010] A conductive barrier layer is disposed on at least the first surface;

[0011] Multiple first gate lines are disposed on a conductive barrier layer, extending along a first direction and arranged along a second direction, the first and second directions intersecting; along a plane perpendicular to the first direction, the cross-sectional area of ​​the first gate lines is greater than or equal to 250 μm². 2 ;

[0012] Along the thickness direction of the battery body, the height of the first grid line is h; the width of the first grid line is w, h / w is 0.1 to 0.5, and w ≥ 30 μm;

[0013] The spacing between two adjacent first grid lines is 0.6mm to 1.3mm.

[0014] This application addresses the technical problems of low current collection efficiency and high contact resistance in gate lines. It comprehensively considers various parameters such as the cross-sectional area of ​​the first gate line, its aspect ratio h / w, its width w, and the spacing between adjacent first gate lines. This ensures that the cross-sectional area, aspect ratio h / w, width w, and spacing between adjacent first gate lines are all within the aforementioned reasonable ranges and are mutually matched, thereby guaranteeing low current collection efficiency and reducing contact resistance. Simultaneously, to prevent the paste from damaging the passivation effect of the doped semiconductor layer, this application also includes a conductive barrier layer. This conductive barrier layer separates the first gate line from the first doped semiconductor layer, ensuring both the passivation effect of the doped semiconductor layer and the conductivity between the first gate line and the first doped semiconductor layer.

[0015] A photovoltaic module includes: a plurality of battery strings connected in series and / or in parallel, each battery string including: an electrical connector and the aforementioned solar cells, the electrical connector electrically connecting at least two of the solar cells.

[0016] Compared with the prior art, the beneficial effects of the photovoltaic modules provided in this application are the same as those of the solar cells described above, and will not be repeated here.

[0017] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a top view of the solar cell provided in an embodiment of this application;

[0020] Figure 2 is a partial cross-sectional view of the solar cell provided in an embodiment of this application;

[0021] Figure 3 is a top-view SEM image of the first gate line provided in an embodiment of this application;

[0022] Figure 4 is a top view of a solar cell provided in another embodiment of this application;

[0023] Figure 5 is a partial sectional view along A1-A2 in Figure 4;

[0024] Figure 6 is a top view of a solar cell provided in another embodiment of this application;

[0025] Figure 7 is a SEM image of the conductive barrier layer provided in the embodiment of this application;

[0026] Figure 8 is a SEM image of the first gate line provided in an embodiment of this application;

[0027] Figure 9 is a SEM image of the modified layer provided in another embodiment of this application;

[0028] Figure 10 is a partial cross-sectional view of Figure 9;

[0029] Figure 11 is a partial enlarged view of Figure 9;

[0030] Figure 12 is a partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0031] Figure 13 is a partial cross-sectional view of a solar cell provided in another embodiment of this application;

[0032] Figure 14 is a cross-sectional SEM image of the conductive barrier layer and the first gate line provided in another embodiment of this application;

[0033] Figure 15 is a top view of the solar cell provided in an embodiment of this application;

[0034] Figure 16 is a cross-sectional view of BB in Figure 15;

[0035] Figure 17 is a schematic diagram of the connection between the first grid line and the main grid;

[0036] Figure 18 is a partial TEM structure schematic diagram of a solar cell according to an embodiment of this application;

[0037] Figure 19 is a partial structural schematic diagram of a solar cell according to an embodiment of the present invention;

[0038] Figure 20 is a partially enlarged structural schematic diagram of a solar cell in an embodiment of the present invention;

[0039] Figure 21 is a partially enlarged schematic diagram of another solar cell structure in an embodiment of the present invention;

[0040] Figure 22 is a partial cross-sectional view of a solar cell provided in an embodiment of this application;

[0041] Figure 23 is a partial cross-sectional view of another solar cell provided in an embodiment of this application;

[0042] Figure 24 is a schematic diagram showing the change in the concentration of the first element with depth in the first doped semiconductor layer of the first region and the second region provided in the embodiments of this application;

[0043] Figure 25 is a schematic diagram showing the change in the concentration of the second element with depth in the second doped semiconductor layer of the third and fourth regions provided in the embodiments of this application;

[0044] Figure 26 is a top view of a solar cell provided in another embodiment of this application;

[0045] Figure 27 is a cross-sectional view of CC in Figure 26;

[0046] Figure 28 is a schematic diagram of the connection between the first grid line and the solder strip.

[0047] Reference numerals: 1-First gate line, 1a-Linear particle, 1b-Spherical particle, 1c-Sheet particle, 1d-V-shaped particle, 1e-Thickened section, 101-Main body, 102-Spreading part, 2-Passivation layer, 211-First hole, 21-Gap, 2a-Opening, 2b-Heat affected zone, 3-First doped semiconductor layer, 31-Amorphous silicon region, 32-Polycrystalline silicon region, 3a-Modified layer, 3a1-Pit, 3b-Metal crystal layer, 3A-First region, 3B-Second region, 4-Semiconductor substrate, 5-Conductive barrier layer, 5a-Conductive material, 5b-Conductive channel, 5c-Pore, 6-Insulating block, 7-First conductive element, 7a-Side protrusion, 8-Second gate line, 9-First interface layer, 10-Second doped semiconductor layer, 10A-Third region, 10B-Fourth region, 11-Second interface layer, 12-Bond layer. Specific Implementation

[0048] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0050] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0051] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0052] The solar cells and photovoltaic modules provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0053] In the manufacturing process of solar cells, the reliance on silver for grid lines has always been significant. Currently, the main method for forming electrode patterns is to use silver paste printed on a screen to create silver grid lines. Silver grid lines are a major limiting factor for cost reduction in solar cells or photovoltaic modules. Copper, as a metal element with decent electrical conductivity and low price, has received much attention. However, grid lines formed from copper paste currently suffer from problems such as low current collection efficiency and high contact resistance, which hinders the mass production of copper paste.

[0054] In view of the above, referring to Figures 1-2, the solar cell provided in this embodiment includes a cell body, a conductive barrier layer 5, and a plurality of first grid lines 1. The cell body includes opposing first and second surfaces, that is, two opposing surfaces along the thickness direction of the cell body are respectively the first surface and the second surface. The first surface may correspond to the back surface of the solar cell, and the second surface may correspond to the light-facing surface of the solar cell; or, the first surface may correspond to the light-facing surface of the solar cell, and the second surface may correspond to the back surface of the solar cell.

[0055] The battery body may include a semiconductor substrate 4, a first doped semiconductor layer 3, a second doped semiconductor layer 10, and a passivation layer 2. A conductive barrier layer 5 is disposed at least on the first surface, i.e., a conductive barrier layer 5 is disposed on the first surface; or a conductive barrier layer 5 is disposed on both the first and second surfaces. Specifically, the conductive barrier layer 5 may be partially disposed on the first surface. Multiple first gate lines 1 are disposed on the conductive barrier layer 5, i.e., the conductive barrier layer 5 is located between the battery body and the first gate lines 1. The function of the conductive barrier layer 5 is to separate the first gate lines 1 from the first doped semiconductor layer 3, while ensuring the conductivity between the first gate lines 1 and the first doped semiconductor layer 3.

[0056] As shown in Figure 1, multiple first grid lines 1 extend along a first direction and are arranged along a second direction, meaning the length of the first grid lines 1 is set along the first direction. The first and second directions intersect, meaning the first direction is different from the second direction, and the angle between the first and second directions can be an acute angle or a right angle. The first direction can be either the length direction of the battery body or the width direction of the battery body. When the first direction is the length direction of the battery body, the second direction is the width direction of the battery body; when the first direction is the width direction of the battery body, the second direction is the length direction of the battery body.

[0057] The first grid line 1 can be formed in the area corresponding to the opening 2a by processes such as screen printing, electroplating, sputtering or vapor deposition.

[0058] In some embodiments, if the cross-sectional area of ​​the first gate line 1 is too small, it will result in excessive line resistance of the first gate line 1, affecting current transmission. Therefore, in this application, the cross-sectional area of ​​the first gate line 1 along the plane perpendicular to the first direction is greater than or equal to 250 μm. 2 .

[0059] Furthermore, along the thickness direction of the battery body, the height of the first gate line 1 is h; the width of the first gate line 1 is w, and h / w ​​is 0.1 to 0.5. When the aspect ratio of the first gate line 1 is less than 0.1, the width of the first gate line 1 needs to be wider, which leads to an increase in the light-shielding area of ​​the first gate line 1, reducing the light absorption utilization rate. At the same time, the area of ​​the passivation layer 2 opening 2a needs to be increased accordingly, and the damage to the first doped semiconductor layer 3 caused by the opening 2a process will also increase. When the aspect ratio of the first gate line 1 is greater than 0.5, the height of the first gate line 1 needs to be higher, which makes it easy for the gate to break during printing. Therefore, in order to balance the above two aspects, h / w is 0.1 to 0.5 in this application to reduce the light-shielding area and light loss, improve the light absorption utilization rate, reduce the damage to the first doped semiconductor layer 3, and reduce the risk of gate breakage during printing.

[0060] To ensure the cross-sectional area is greater than or equal to 250 μm 2 Furthermore, the height and width are between 0.1 and 0.5, and the width w of the first gate line 1 needs to be greater than or equal to 30 μm to ensure the transmission efficiency of the first gate line 1 and reduce the contact resistance of the first gate line 1.

[0061] Furthermore, the spacing between two adjacent first grid lines 1 also affects the light-transmitting area. If the spacing between two adjacent first grid lines 1 is too small, the light-transmitting area between them will be small, affecting the light absorption and utilization rate; if the spacing between two adjacent first grid lines 1 is too large, the current collection efficiency will be reduced. Therefore, in this application, the spacing between two adjacent first grid lines 1 is 0.6mm to 1.3mm to ensure a reasonable light-transmitting area between them and to guarantee the current collection efficiency while improving the current collection efficiency on both sides of the first grid line 1.

[0062] As can be seen from the above, this application addresses the technical problems of low collection efficiency and high contact resistance of the gate line current. This application comprehensively considers various parameters such as the cross-sectional area of ​​the first gate line 1, the aspect ratio h / w of the first gate line 1, the width w of the first gate line 1, and the spacing between two adjacent first gate lines 1. This ensures that the cross-sectional area, aspect ratio h / w, width w, and spacing between two adjacent first gate lines 1 are all within the aforementioned reasonable ranges and are mutually matched, thereby guaranteeing low collection efficiency and reducing contact resistance of the first gate line 1. Simultaneously, to prevent the paste from damaging the passivation effect of the doped semiconductor layer, this application also provides a conductive barrier layer 5. The conductive barrier layer 5 can separate the first gate line 1 and the first doped semiconductor layer 3, ensuring both the passivation effect of the doped semiconductor layer and the conductivity between the first gate line 1 and the first doped semiconductor layer 3.

[0063] Along a plane perpendicular to the first direction, the cross-sectional area of ​​the first gate line 1 is 250 μm. 2260μm 2 270μm 2 280μm 2 290μm 2 300μm 2 320μm 2 350μm 2 380μm 2 400μm 2 420μm 2 450μm 2 480μm 2 or 500μm 2 wait.

[0064] The aspect ratio h / w of the first grid line 1 is 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, or 0.5, etc. Optionally, the aspect ratio h / w of the first grid line 1 is 0.1 to 0.25.

[0065] The width w of the first gate line 1 is 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, 150μm, 160μm, 170μm or 180μm, etc.

[0066] The spacing between two adjacent first grid lines 1 can be 0.6mm, 0.7mm, 0.8mm, 0.9mm, 1mm, 1.1mm, 1.2mm or 1.3mm, etc.

[0067] The applicant selected the above-mentioned printable paste with the required resistivity to form the first grid line 1. The first grid line 1 is a fine grid with a spacing of 0.9 mm between adjacent first grid lines 1. The battery was tested using a 182 mm * 91 mm half-cell cell. The test results are shown in the table below:

[0068] As shown in the table above, when other parameters meet the requirements, the efficiency of solar cells can be maintained above 26% when the aspect ratio of the fine grid is between 0.1 and 0.5.

[0069] Considering that if the first gate line 1 is too wide, it will increase the light-blocking area and light loss, reducing the light absorption and utilization rate; if the first gate line 1 is too narrow, it will increase the contact resistance of the first gate line 1, reducing the photoelectric conversion efficiency. In view of these two situations, in this technical solution, the width w of the first gate line 1 is set within a reasonable range of 140μm ≥ w ≥ 30μm, in order to reduce the light-blocking area and light loss, improve the light absorption and utilization rate, and at the same time reduce the contact resistance of the first gate line 1, thereby improving the current transmission efficiency.

[0070] In other embodiments, considering that if the height of the first gate line 1 is too high, it is prone to gate breakage during printing, affecting product yield; if the height of the first gate line 1 is too small, the width of the first gate line 1 will need to be wider, which will lead to an increase in the light-blocking area of ​​the first gate line 1 and reduce the light absorption and utilization rate. In view of the above two situations, in this technical solution, the height h of the first gate line 1 is set within a reasonable range of 5μm≥h≥25μm, which reduces the light-blocking area and light loss while ensuring product yield.

[0071] For example, the height h of the first gate line 1 can be 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm or 25μm, etc.

[0072] In some embodiments, the first gate line 1 is made of copper paste material, and the cured first gate line 1 includes copper powder and organic matter. Copper has acceptable electrical conductivity and is inexpensive, so the inclusion of copper powder in the first gate line 1 in this technical solution reduces manufacturing costs compared to the prior art where the first gate line 1 only includes silver. Furthermore, the organic matter has good adhesion; the particles contained in the copper powder can be bonded together by the organic matter, and the organic matter can improve the adhesion between the first gate line 1 and the first surface, preventing the first gate line 1 from detaching from the first surface.

[0073] As shown in Figure 8, the copper powder includes at least flake-shaped particles 1c and spherical particles 1b. The flake-shaped particles 1c are generally flat, and their edges can be rounded, serrated, or any irregular edge. The spherical particles 1b can be spherical, ellipsoidal, near-spherical, or near-ellipsoidal in shape. The flake-shaped particles 1c have a larger contact area with other conductive particles, which is beneficial for reducing contact resistance, while the spherical particles 1b have a larger contact area with organic matter, which is beneficial for the formation of the gate line. Therefore, in this technical solution, the copper powder includes both flake-shaped particles 1c and spherical particles 1b, which not only ensures that the first gate line 1 has a suitable resistivity but also facilitates the printing and forming of the first gate line 1.

[0074] As shown in Figure 8, the copper powder may also include one or more of the following: linear particles 1a, V-shaped particles 1d, polygonal particles, and cylindrical particles. Specifically, the copper powder may include particles of any shape. The various shapes of particles have more contact points, which is beneficial for the contact and conduction between adjacent conductive particles, thereby ensuring that the first gate line 1 has a suitable resistivity.

[0075] In some embodiments, if the diameter of the flake particles 1c is too large, it will prevent them from passing through the printing mesh during the printing process; if the diameter of the flake particles 1c is too small, the content of organic matter in the gaps between the particles will be insufficient, which is not conducive to the formation of the first grid line 1. Based on this, in this technical solution, the median diameter of the flake particles 1c is 0.8μm to 5μm. The diameter of the flake particles 1c can be an equivalent diameter, specifically, it can be a sieve equivalent diameter, a volume equivalent diameter, or a surface area equivalent diameter. Using this technical solution, the diameter of most of the flake particles 1c is within a reasonable range, which can prevent the flake particles 1c from being too large to pass through the mesh, and also ensure the content of organic matter in the gaps between the particles, thereby improving the adhesion of the first grid line 1.

[0076] For example, the median diameter of the sheet-like particles 1c is 0.8 μm, 1 μm, 1.2 μm, 1.5 μm, 1.8 μm, 2 μm, 2.2 μm, 2.5 μm, 2.8 μm, 3 μm, 3.2 μm, 3.5 μm, 3.8 μm, 4 μm, 4.2 μm, 4.5 μm, 5.8 μm, or 5 μm, etc.

[0077] Furthermore, the median thickness of the sheet-like particles 1c is between 100 nm and 500 nm, ensuring that the thickness of most sheet-like particles 1c is within a reasonable range. This guarantees low contact resistance between the sheet-like particles 1c and other conductive particles, while preventing excessively thin sheet-like particles 1c from having excessively high transmission resistance, thus resulting in a low transmission resistance of the sheet-like particles 1c themselves. For example, the median thickness of the sheet-like particles 1c can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm.

[0078] In some embodiments, if the spacing between spherical particles 1b is too large, the contact area between spherical particles 1b and other conductive particles will be further reduced, increasing the resistivity of the first grid line 1. If the spacing between spherical particles 1b is too small, the content of organic matter in the gaps between particles will be low, which is not conducive to the formation of the first grid line 1. Based on this, in this technical solution, the median particle size of the spherical particles 1b is 100nm to 500nm. The diameter of the spherical particles 1b can be an equivalent diameter, specifically, it can be a sieve equivalent diameter, a volume equivalent diameter, or a surface area equivalent diameter. Using this technical solution, the diameter of most spherical particles 1b is within a reasonable range, which not only keeps the resistivity of the first grid line 1 within a reasonable range but also ensures the content of organic matter in the gaps between particles, improving the adhesion of the first grid line 1.

[0079] For example, the median particle size of spherical particle 1b is 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm or 500nm, etc.

[0080] In other embodiments, the mass percentage of the flake particles 1c is 35% to 60%, meaning that the mass percentage of the flake particles 1c in the slurry forming the first grid line 1 is 35% to 60% of the total slurry mass. This ensures that the content of the flake particles 1c in the slurry is within a reasonable range, and that the contact area between the flake particles 1c and other conductive particles is large, which is beneficial for reducing the resistivity of the first grid line 1 formed by the slurry. For example, the mass percentage of the flake particles 1c is 35%, 38%, 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, or 60%, etc.

[0081] In other embodiments, the mass percentage of spherical particles 1b is 35% to 60%, meaning that the mass percentage of spherical particles 1b in the slurry forming the first grid line 1 is 35% to 60% of the total slurry mass. This ensures that the content of spherical particles 1b in the material is within a reasonable range, resulting in a larger contact area between the spherical particles 1b and the organic matter, which is beneficial for the formation of the first grid line 1. For example, the mass percentage of spherical particles 1b can be 35%, 38%, 40%, 42%, 45%, 48%, 50%, 52%, 55%, 58%, or 60%, etc.

[0082] In some embodiments, the tap density of the sheet-like particles 1c is 3 g / ml to 6 g / ml, which ensures the compactness of the sheet-like particles 1c and further guarantees the current transmission efficiency of the sheet-like particles 1c. For example, the tap density of the sheet-like particles 1c is 3 g / ml, 3.5 g / ml, 4 g / ml, 4.5 g / ml, 5 g / ml, 5.5 g / ml, or 6 g / ml.

[0083] In some embodiments, the tap density of the spherical particles 1b is 3.5 g / ml to 5.5 g / ml, thus ensuring the compactness of the spherical particles 1b. For example, the tap density of the spherical particles 1b is 3.5 g / ml, 4 g / ml, 4.5 g / ml, 5 g / ml, or 5.5 g / ml, etc.

[0084] Tap density, or bulk density of powder after compaction, refers to the density of powder after it has been packed into a specific container and the container has been vibrated to break up the voids in the powder and bring it into a tightly packed state. Measuring tap density can determine the flowability and porosity of the powder. It can be calculated by measuring the volume after 1000 vibrations using a BT-301 tap density meter.

[0085] Furthermore, the specific surface area of ​​the flaky particles 1c is 0.4 m².2 / g~0.7m 2 / g, so that the plate-like particles 1c can have a reasonable contact area with other conductive particles, thereby reducing the resistivity of the first gate line 1. For example, the specific surface area of ​​the plate-like particles 1c is 0.4m². 2 / g, 0.45m 2 / g, 0.5m 2 / g, 0.55m 2 / g, 0.6m 2 / g, 0.65m 2 / g or 0.7m 2 / g etc.

[0086] The specific surface area of ​​spherical particle 1b is 1.5 m². 2 / g~3.5m 2 / g, so that the spherical particles 1b can have a larger contact area with the organic matter, thereby improving the adhesion of the first grid line 1. For example, the specific surface area of ​​the spherical particles 1b is 1.5m². 2 / g, 1.52m 2 / g, 1.55m 2 / g, 1.58m 2 / g、2m 2 / g, 2.2m 2 / g, 2.5m 2 / g, 2.8m 2 / g、3m 2 / g, 3.2m 2 / g or 3.5m 2 / g etc.

[0087] Specific surface area refers to the surface area per unit mass of porous solid material, which can be tested using conventional methods, such as GB / T 13390-2008, the method for determining the specific surface area of ​​metal powders.

[0088] In some embodiments, the organic material includes one or more of the following: saturated / unsaturated fatty acids containing 8-18 carbon atoms, silane coupling agents, PVP, and thiols. These organic materials have high adhesion and are reasonably priced, making them suitable for forming the first grid line 1.

[0089] As shown in Figures 2 and 3, the first grid line 1 includes a main body portion 101 and a spreading portion 102 arranged along a second direction, while the main body portion 101 and the spreading portion 102 extend along a first direction. Specifically, the spreading portion 102 is formed on both sides of the main body portion 101. During the grid line fabrication process, after slurry printing or laser transfer, and before the slurry solidifies, the slurry (such as one or more organic substances in the slurry) diffuses onto the battery cell surfaces on both sides of the main body portion 101, forming the spreading portion 102 on both sides of the main body portion 101. Using this technical solution, forming the spreading portion 102 on both sides of the main body portion 101 increases the width of the root of the first grid line 1, thereby increasing the contact area between the first grid line 1 and the first surface, thus reducing the contact resistance of the first grid line 1, and simultaneously improving the adhesion between the first grid line 1 and the first surface, preventing the first grid line 1 from detaching.

[0090] In some embodiments, as shown in FIG2, the width W1 of the main body portion 101 along the second direction is 30μm to 120μm, so as to facilitate controlling the cross-sectional area of ​​the first gate line 1 within a reasonable range according to the width W1 of the main body portion 101. For example, the width W1 of the main body portion 101 is 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, 60μm, 65μm, 70μm, 75μm, 80μm, 85μm, 90μm, 95μm, 100μm, 105μm, 110μm, 105μm, or 120μm, etc.

[0091] As shown in Figure 2, considering that an excessively wide spreading portion 102 (W2) would extend into areas with opposite polarity, leading to leakage, and that an excessively small spreading portion 102 (W2) would reduce the adhesion between the first gate line 1 and the first surface, this technical solution uses a spreading portion 102 width of 1μm-60μm along the second direction to reduce the risk of leakage while ensuring adhesion between the first gate line 1 and the first surface. For example, the spreading portion 102 width (W2) can be 1μm, 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, 35μm, 40μm, 45μm, 50μm, 55μm, or 60μm, etc.

[0092] Along the second direction, the width of the spreading portion 102 is 5%-50% of the width of the main body portion 101 to reduce the risk of leakage current while ensuring the adhesion between the first grid line 1 and the first surface. For example, the width of the spreading portion 102 is 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, or 50% of the width of the main body portion 101.

[0093] It should be noted that, as mentioned above, the width of the first grid line 1 is the sum of the widths of the main body 101 and the spreading part 102. The height of the first grid line 1 is the same as the height of the main body 101.

[0094] As shown in Figure 2, the height h1 of the main body 101 along the thickness direction of the battery body is 8μm to 25μm. This is to prevent the height h1 of the main body 101 from being too high, which would increase the risk of grid breakage, and at the same time to prevent the height of the main body 101 from being too low, which would affect the current transmission efficiency of the grid lines. For example, the height h1 of the main body 101 is 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm, or 25μm, etc.

[0095] Along the thickness direction of the battery body, the height of the main body 101 is h1, and the height of the spreading part 102 is h2, where h2 ≤ 1 / 3h1. This technical solution ensures that the height h2 of the spreading part 102 and the height h1 of the main body 101 are in a reasonable ratio. This prevents the spreading part 102 from being too high, which would reduce the cross-sectional area of ​​the main body 101 and increase its resistivity, thereby guaranteeing the overall current transmission efficiency of the first grid line 1. For example, h2 can be 1 / 3h1, 0.3h1, 0.25h1, 0.2h1, 0.15h1, or 0.1h1, etc.

[0096] In some embodiments, the median particle size of the copper powder contained in the spreading portion 102 is smaller than the median particle size of the copper powder contained in the main body portion 101, wherein the copper powder particle size can also be an equivalent diameter. That is, the particle size of most of the copper powder contained in the spreading portion 102 is smaller than the particle size of most of the copper powder contained in the main body portion 101. This arrangement makes the particle size of the copper powder contained in the spreading portion 102 more closely match the thickness of the spreading portion 102, thereby improving the conductivity of the spreading portion 102.

[0097] In some embodiments, the solar cells of this application may also satisfy at least one of the following conditions:

[0098] 1) The first gate line 1 is formed from a non-burn-through paste. A non-burn-through paste refers to a paste that cannot directly penetrate the passivation layer 2 through sintering to achieve contact with the first doped semiconductor layer 3. For example, a non-burn-through paste may include one or more of low-temperature silver paste, copper paste, and aluminum paste. Generally, the first gate line 1 formed from this non-burn-through paste still retains a binder material, such as an organic component. The first gate line 1 formed from the non-burn-through paste generally has a higher resistivity because it contains organic materials that cannot be sintered and volatilized. These organic materials can increase adhesion, but the resistivity of the first gate line 1 needs to be kept within a reduced range, for example, less than 80 μΩ·cm. When using a non-burn-through paste to prepare the gate line, relatively inexpensive conductive metals such as copper paste can be added to the non-burn-through paste, which can reduce the manufacturing cost of the gate line.

[0099] 2) The resistivity of the first gate line 1 is 6μΩ·cm to 60μΩ·cm, so that the cross-sectional area of ​​the first gate line 1 can be kept within a reasonable range. This prevents the first gate line 1 from having too high a resistivity, which would result in a large cross-sectional area, wasting raw materials and causing severe light shading. At the same time, it avoids the first gate line 1 having too low a resistivity, which would require higher raw materials and increase the raw material cost of the first gate line 1.

[0100] The cross-sectional area of ​​the first gate line 1 is greater than or equal to 250 μm. 2 When the resistivity of the first gate line 1 is matched to 6μΩ·cm to 60μΩ·cm, the first gate line 1 can achieve high efficiency in collecting current and ensure low transmission resistance.

[0101] For example, the resistivity of the first grid line 1 may be 6 μΩ·cm, 8 μΩ·cm, 10 μΩ·cm, 12 μΩ·cm, 15 μΩ·cm, 18 μΩ·cm, 20 μΩ·cm, 22 μΩ·cm, or 25 μΩ·cm. cm, 28μΩ·cm, 30μΩ·cm, 32μΩ·cm, 35μΩ·cm, 38μΩ·cm, 40μΩ·cm, 45μΩ·cm, 50μΩ·cm, 55μΩ·cm or 60μΩ·cm, etc.

[0102] Regarding the resistivity measurement method of the first gate line 1, in this embodiment of the application, at least one of the following measurement methods can be adopted according to the actual structure of the first gate line 1:

[0103] 1) For the first gate line 1 sample, which exists in isolation from the semiconductor substrate 4, a square sample with an area of ​​10mm*10mm can be formed by printing paste on a ceramic substrate. After the paste solidifies to form the first gate line 1 sample, a four-probe measuring instrument is used to measure the volume resistivity of the first gate line 1 sample. The volume resistivity of the first gate line 1 sample can be calculated by the formula ρ=R*h, where ρ is the volume resistivity of the sample in μΩ·cm, R is the sheet resistance of the sample in mΩ / □ or mΩ / sq, where “□” represents a square, and h is the film thickness of the sample in μm.

[0104] 2) When measuring the first gate line 1 that has been printed onto the surface of the semiconductor substrate 4, a four-probe measuring instrument can also be used. The difference is that the calculation formula is ρ=R*S / L, where R is the resistance of the first gate line 1 in Ω, and S is the area of ​​at least a local part of the first gate line 1 in mm. 2The cross-sectional area S can be measured and calculated using a two-dimensional measuring instrument. If S is the cross-sectional area, then S is the product of the width and height of at least a local region on the cross-section of the first gate line 1; if S refers to the area on the surface of the gate line, then S is the product of the length and width of at least a local region on the surface of the first gate line 1 away from the silicon substrate. The width can be the linewidth measured by two-dimensional or 3D measurement, the height can be the average line height measured by 3D measurement, and L is the length of the first gate line 1 being tested, in mm.

[0105] It should be noted that in the second measurement method, since the first gate line 1 is already bonded to the semiconductor substrate 4, its current transport performance may be affected by the passivation layer and the doped semiconductor layer during testing. Although the resistivity of the first gate line 1 measured at this time may contain interference factors from the passivation layer and the doped semiconductor layer, the data obtained by testing and calculating the gate line conductivity on the solar cell as described in this application is considered to include the above-mentioned interference factors, and the measurement result is still used to represent the resistivity of the first gate line 1, and can also be used to evaluate and measure the electrical performance of the first gate line 1. Another testing method can also be to peel the first gate line 1 off from the semiconductor substrate 4 and then perform the test using method 2).

[0106] In this embodiment, the battery body includes a semiconductor substrate 4, a first doped semiconductor layer 3, a second doped semiconductor layer 10, and a passivation layer 2. The first doped semiconductor layer 3 and the second doped semiconductor layer 10 have opposite conductivity types to collect and export electrons and holes respectively, which is beneficial for the formation of photocurrent. The two opposite sides of the semiconductor substrate 4 correspond to the first surface and the second surface, respectively. The first doped semiconductor layer 3 is disposed on the first surface of the semiconductor substrate 4. The first doped semiconductor layer 3 can be formed in the semiconductor substrate 4 by diffusion, ion implantation, or other methods, or it can also be additionally formed on the semiconductor substrate 4 by deposition technology. The passivation layer 2 at least covers the side of the first doped semiconductor layer 3 facing away from the semiconductor substrate 4. A conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3. The charge carriers collected by the first doped semiconductor layer 3 are exported through the conductive barrier layer 5 and the first gate line 1.

[0107] The passivation layer 2 can be a single layer or multiple layers, including at least one of aluminum oxide, silicon oxide, and silicon nitride. The thickness of the passivation layer 2 is 50 nm to 400 nm, for example, 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, or 400 nm. The passivation layer 2 can passivate the surface of the battery body or the doped layer, reducing its carrier recombination rate and further improving the photoelectric conversion efficiency of the solar cell.

[0108] In some embodiments, as shown in FIG12, the conductive barrier layer 5 may be discontinuously disposed along the first direction. This can appropriately reduce the consumption of raw materials for the conductive barrier layer 5, save raw materials, and reduce the manufacturing cost of the solar cell. Alternatively, as shown in FIG13, the conductive barrier layer 5 may be continuously disposed along the first direction, which can increase the contact area between the conductive barrier layer 5 and the first grid line 1, and reduce the contact resistance and current transmission loss between the conductive barrier layer 5 and the first grid line 1.

[0109] In some embodiments, the passivation layer 2 has an opening 2a that exposes the first doped semiconductor layer 3; the first gate line 1 covers the opening 2a and is electrically connected to the first doped semiconductor layer 3 to facilitate the collection and discharge of carriers collected by the first doped semiconductor layer 3 by the first gate line 1.

[0110] As shown in Figure 4, the multiple openings 2a corresponding to the same gate line can be arranged in at least one row along the first direction, that is, the multiple openings 2a can be distributed in one row and arranged sequentially along the first direction. Alternatively, the multiple openings 2a can be distributed in multiple rows, with each row of openings 2a arranged sequentially along the first direction. For example, the multiple openings 2a can also be distributed in two, three, or more rows. In this way, the distribution of the multiple openings 2a is more uniform, and the position distribution of the electrical connection between the first gate line 1 and the first doped semiconductor layer 3 is more uniform, which is beneficial for the first gate line 1 to conduct the current at each position of the first doped semiconductor layer 3 in a timely manner, avoiding local overheating. Alternatively, as shown in Figure 6, the openings 2a corresponding to the same gate line can be strip-shaped. In this case, the orthographic projection of the opening 2a corresponding to the same gate line on the first surface is located inside the orthographic projection of the gate line on the first surface.

[0111] In some embodiments, direct contact between the copper paste in the first gate line 1 and the first doped semiconductor layer 3 reduces the passivation effect of the first doped semiconductor layer 3. Therefore, as shown in Figures 5 and 7, in this technical solution, a conductive barrier layer 5 fills the opening 2a to completely separate the first doped semiconductor layer 3 and the first gate line 1, thereby improving the passivation effect of the first doped semiconductor layer 3. The thickness of the conductive barrier layer 5 can be greater than or equal to the thickness of the passivation layer 2 to ensure the isolation effect. During manufacturing, multiple through openings 2a can be formed on the passivation layer 2 using a patterning process (e.g., laser aperture forming process), and then the conductive barrier layer 5 can be formed through processes such as electroplating and chemical plating. The conductive barrier layer 5 can be a metal barrier material such as nickel, silver, or titanium.

[0112] In some embodiments, as shown in FIG2, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is greater than the thickness of the passivation layer 2. With this configuration, the portion of the conductive barrier layer 5 extending beyond the opening 2a can extend to the side surface of the passivation layer 2 facing away from the semiconductor substrate 4, thereby increasing the width of the conductive barrier layer 5, and thus increasing the contact area between the conductive barrier layer 5 and the first gate line 1, reducing the contact resistance and current transmission loss between the conductive barrier layer 5 and the first gate line 1.

[0113] On the one hand, if the thickness of the conductive barrier layer 5 is too large, it wastes raw materials and requires a longer processing time for electroplating, electroless plating, etc., reducing processing efficiency. On the other hand, if the thickness of the conductive barrier layer 5 is too small, it cannot effectively isolate the first gate line 1 and the first doped semiconductor layer 3, ensuring the passivation effect of the passivation layer 2. Therefore, in order to balance the above two aspects, in this technical solution, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is set within a reasonable range of 0.5μm to 5μm. This effectively isolates the first gate line 1 and the first doped semiconductor layer 3, ensuring the passivation effect of the passivation layer 2, while reducing the waste of raw materials for the conductive barrier layer 5 and improving processing efficiency. For example, the thickness of the portion of the conductive barrier layer 5 corresponding to the area of ​​the opening 2a is 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, 4.5μm, or 5μm, etc.

[0114] As shown in Figure 5, the solar cell also includes a modified layer 3a. The modified layer 3a is formed in the region corresponding to the first doped semiconductor layer 3 and the opening 2a. Alternatively, the modified layer 3a can also be formed in the region surrounding the opening 2a. This modified layer 3a can be formed under the influence of laser heat during the laser-induced opening 2a process. For example, in Figure 9, the modified layer 3a is formed in the region corresponding to the circular opening of the first doped semiconductor layer 3.

[0115] As shown in Figure 10, the roughness of the modified layer 3a is greater than that of the other parts of the first doped semiconductor layer 3. This configuration increases the contact area between the conductive barrier layer 5 and the modified layer 3a, improves the adhesion between them, and reduces the contact resistance.

[0116] The modified layer 3a has a lower degree of crystallinity than the first doped semiconductor layer 3 in other parts, thus enabling the modified layer 3a to better block copper paste. The degree of crystallinity includes indicators such as crystallinity, number of grains, and grain size.

[0117] The thickness of the modified layer 3a can be 5nm to 20nm, for example, the thickness of the modified layer 3a can be 5nm, 8nm, 10nm, 12nm, 15nm, 18nm or 20nm, etc.

[0118] In some embodiments, as shown in FIG5, the passivation layer 2 has a heat-affected zone 2b surrounding the opening 2a. Specifically, during the process of grooving the passivation layer 2 using laser technology, the area near the edge of the opening 2a, although not removed, is affected by laser heat and is called the heat-affected zone 2b. This heat-affected zone 2b is formed around the opening 2a. The shape of the opening 2a can be circular, elliptical, rectangular, or other shapes, and the surrounding shape of the heat-affected zone 2b also changes with the shape of the opening 2a; its annular shape can be a circular ring, an elliptical ring, or a rectangular ring, etc. The width of the modified layer 3a can reach the boundary of the heat-affected zone 2b.

[0119] In some embodiments, the width of the heat-affected zone 2b is D, where 1 μm ≤ D ≤ 5 μm. This avoids the heat-affected zone 2b being too wide, which would reduce the passivation effect. For example, D can be 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm, etc.

[0120] In some embodiments, as shown in FIG5, during the laser drilling of hole 2a, the laser energy at the edge position is appropriately increased, for example, to greater than 200 J / cm. 2 The passivation layer 2 material in the heat-affected zone 2b will be opened, forming multiple holes and / or cracks. The purpose of this arrangement is that if holes and / or cracks do not form in the heat-affected zone 2b, the thermal damage to the first doped semiconductor layer 3 corresponding to the location of the heat-affected zone 2b cannot be repaired. In this embodiment, the holes and / or cracks are filled with conductive material 5a, which is electrically connected to the first doped semiconductor layer 3. Specifically, the conductive material 5a within the holes and / or cracks can contact the modified layer 3a or other parts of the first doped semiconductor layer 3. With this arrangement, the first gate line 1, while passing through the opening 2a and electrically connecting to the first doped semiconductor layer 3, can also be electrically connected to the first doped semiconductor layer 3 through the conductive material 5a within the holes and / or cracks. Furthermore, the first doped semiconductor layer 3 at the location corresponding to the holes is also a heat concentration area with significant damage (heat concentration areas are prone to forming holes), and the conductive material 5a can repair the damage at this location. The conductive material 5a is distributed in granular form within the heat-affected zone 2b, and the granular conductive material 5a at the position furthest from the center of the opening 2a defines the width D of the heat-affected zone 2b. The conductive material 5a within the holes and / or cracks can be the same as the conductive barrier layer 5, and can be formed together with the conductive barrier layer 5 by electroplating or chemical plating.

[0121] On the one hand, if the total area of ​​the orthographic projection of the aperture 2a corresponding to the same first gate line 1 on the first surface is too large, it will increase the damage to the semiconductor substrate 4 during the aperture 2a opening process. On the other hand, if the total area of ​​the orthographic projection of the aperture 2a corresponding to the same first gate line 1 on the first surface is too small, it will result in an excessively large contact area of ​​the first gate line 1, affecting the current transmission efficiency. Considering both aspects, in this application, the total area of ​​the orthographic projection of the aperture 2a corresponding to the same first gate line 1 on the first surface is 20% to 80% of the orthographic projection area of ​​the first gate line 1 on the first surface, so as to reduce the damage to the semiconductor substrate 4 during the aperture 2a opening process while ensuring the current transmission efficiency of the first gate line 1.

[0122] In other embodiments, as shown in FIG11, the region corresponding to the opening 2a in the first doped semiconductor layer 3 includes multiple pits 3a1, which can be of any shape, such as circular or elliptical. The inner diameter of the pit 3a1 is 0.5μm to 2μm, and can be the inner diameter of the position with the largest size of the pit 3a1 or an equivalent inner diameter. For example, the inner diameter of the pit 3a1 is 0.5μm, 0.8μm, 1.0μm, 1.2μm, 1.5μm, 1.8μm, or 2μm. By adopting this technical solution, the setting of the pits 3a1 can also increase the surface area of ​​the region, thereby increasing the contact area between the conductive barrier layer 5 and the region, and further reducing the contact resistance.

[0123] In other embodiments, the conductive barrier layer 5 is electrically connected to the first doped semiconductor layer 3 by burning through the passivation layer 2. As shown in FIG12, the portion of the conductive barrier layer 5 that passes through the passivation layer 2 includes multiple conductive channels 5b. That is, one end of the multiple conductive channels 5b (the upper end in FIG12) is electrically connected to the first gate line 1, and the other end of the multiple conductive channels 5b (the lower end in FIG12) is electrically connected to the first doped semiconductor layer 3, so as to achieve conductivity between the first gate line 1 and the first doped semiconductor layer 3 through the multiple conductive channels 5b. Any two adjacent conductive channels 5b are partially connected, that is, the portions of any two adjacent conductive channels 5b can be continuously arranged; or, any two adjacent conductive channels 5b are not connected, that is, the multiple conductive channels 5b are independent of each other and are discretely distributed. This helps to reduce the process difficulty of forming multiple conductive channels 5b by burning through the passivation layer 2 of the conductive barrier layer 5, and helps to improve processing efficiency.

[0124] When the conductive barrier layer 5 is electrically connected to the first doped semiconductor layer 3 by burning through the passivation layer 2, the passivation layer 2 below the conductive barrier layer 5 does not need to be patterned to create openings. The conductive barrier layer 5 can be formed using a burn-through paste, and can be formed by printing, transfer, or spraying. Specifically, it can be annealed at high temperature to allow the corrosive material in the conductive barrier layer 5 (e.g., glass frit in silver paste) to etch the passivation layer 2, thereby forming a conductive channel 5b in the passivation layer 2. The conductive channel 5b is the contact between the metal material of the conductive barrier layer 5 and the doped semiconductor layer through the passivation layer 2.

[0125] When the conductive barrier layer 5 is discontinuously disposed along the first direction, the conductive barrier layer 5b includes a plurality of sub-conductive barrier layers spaced apart along the first direction. Each sub-conductive barrier layer may include a plurality of conductive channels 5b.

[0126] On the one hand, if the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is too large, it will lead to a decrease in carrier transport efficiency; on the other hand, if the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is too small, it will increase the difficulty of forming the sub-conductive barrier layers, resulting in a decrease in production efficiency. Therefore, in order to balance the above two aspects, as shown in Figure 12, the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction is set within a reasonable range of 0.2mm to 3mm, so as to improve the carrier transport efficiency while reducing the difficulty of forming the sub-conductive barrier layers and improving production efficiency. It can be understood that the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction refers to the distance between the closest points of the boundaries of the two adjacent sub-conductive barrier layers. For example, the minimum distance L between any two adjacent sub-conductive barrier layers along the first direction can be 0.2mm, 0.4mm, 0.5mm, 0.8mm, 1mm, 1.2mm, 1.4mm, 1.5mm, 1.8mm, 2mm, 2.2mm, 2.4mm, 2.5mm, 2.8mm or 3mm.

[0127] In some embodiments, the orthographic projection of the sub-conductive barrier layer on the first surface is a circle, an ellipse, a strip, or a polygon, wherein the polygon can be a square, a triangle, a trapezoid, an irregular polygon, etc.

[0128] In some embodiments, the first doped semiconductor layer 3 further includes a metal crystal layer 3b located on the side of the conductive barrier layer 5 near the semiconductor substrate 4. For example, silver in the conductive barrier layer 5 forms an AgSi alloy phase with silicon, which has high thermal stability and mechanical strength. In this technical solution, the adhesion between the metal elements contained in the conductive barrier layer 5 and silicon is enhanced by chemical bonding in the metal crystal layer 3b, reducing the problem of peeling off the conductive barrier layer 5 due to thermal or mechanical stress; furthermore, the metal crystal layer 3b has high conductivity, and the presence of the metal crystal layer 3b can also improve the carrier transport efficiency between the conductive barrier layer 5 and the first doped semiconductor layer 3.

[0129] In some embodiments, the thickness of the metal crystal layer 3b along the thickness direction of the semiconductor substrate 4 is less than or equal to the thickness of the first doped semiconductor layer 3. In this technical solution, the metal crystal layer 3b is formed at least in the region near the surface of the first doped semiconductor layer 3 facing away from the semiconductor substrate 4, which improves the adhesion of the conductive barrier layer 5 and the carrier transport efficiency while reducing the processing difficulty of the metal crystal layer 3b. In some embodiments, a portion of the metal crystal layer 3b may abut against the interface layer (e.g., an oxide layer including first and second interface layers) between the first doped semiconductor layer 3 and the semiconductor substrate 4, or the distance between it and the interface layer may be less than 10 nm.

[0130] In some embodiments, the thickness of the metal crystal layer 3b along the thickness direction of the semiconductor substrate 4 is 2 / 3 of the thickness of the first doped semiconductor layer 3. This improves the adhesion and carrier transport efficiency of the conductive barrier layer 5 while preventing excessive heat from reaching the semiconductor substrate 4 and damaging it during burn-through. For example, the thickness of the metal crystal layer 3b can be 2 / 3, 1 / 3, 1 / 2, 3 / 5, etc., of the thickness of the first doped semiconductor layer 3.

[0131] In some embodiments, as shown in FIG14, the conductive barrier layer 5 includes a plurality of pores 5c inside, and the pores 5c are free of organic matter and / or metal particles. This configuration helps to improve the heat dissipation effect of the conductive barrier layer 5 and prevents local overheating.

[0132] When the conductive barrier layer 5 is electrically connected to the first doped semiconductor layer 3 by burning through the passivation layer 2, the thickness of the conductive barrier layer 5 is 0.1 μm to 10 μm. This ensures that the conductive barrier layer 5 can burn through the passivation layer 2 while reducing the waste of raw materials for the conductive barrier layer 5 and improving processing efficiency. It can be understood that at the location of the conductive channel 5b, the thickness of the conductive barrier layer 5 is the distance from the side of the conductive barrier layer 5 facing away from the semiconductor substrate 4 to the end of the conductive channel 5b near the semiconductor substrate 4 along the thickness direction of the semiconductor substrate 4. For example, in this technical solution, the thickness of the conductive barrier layer 5 is 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, or 10 μm.

[0133] In some embodiments, the solar cell further includes a second doped semiconductor layer 10 and a plurality of second gate lines 8, wherein the second gate lines 8 are disposed on the side of the second doped semiconductor layer 10 facing away from the semiconductor substrate 4. The first gate line 1 and the second gate line 8 are made of the same material, and the polarities of the first gate line 1 and the second gate line 8 are opposite. The resistivity, cross-sectional area, height, width, and spacing between adjacent second gate lines 8 of the second gate line 8 can be referred to the description of the first gate line 1 above, and will not be repeated here.

[0134] In the case of a back-contact solar cell, both the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are located on the first surface, and the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are arranged at intervals along a second direction. Specifically, the second doped semiconductor layer 10 and the first doped semiconductor layer 3 can be arranged in alternating stripe patterns or in alternating interdigitated patterns. Both the first gate line 1 and the second gate line 8 are formed on the first surface. The first gate line 1 is electrically connected to the first doped semiconductor layer 3, and the second gate line 8 is electrically connected to the second doped semiconductor layer 10. The second gate line 8 also extends along the first direction and is arranged along the second direction, with multiple first gate lines 1 and multiple second gate lines 8 alternating along the second direction. In this technical solution, the passivation layer 2 can cover the side of the first doped semiconductor layer 3 and the second doped semiconductor layer 10 facing away from the semiconductor substrate 4. The first gate line 1 passes through the opening 2a of the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3, and the second gate line 8 passes through the opening 2a of the passivation layer 2 and is electrically connected to the second doped semiconductor layer 10.

[0135] In the case of a bifacial solar cell, the first doped semiconductor layer 3 and the second doped semiconductor layer 10 are located on the first surface and the second surface, respectively, and the first gate line 1 is formed on the first surface and electrically connected to the first doped semiconductor layer 3, and the second gate line 8 is formed on the second surface and electrically connected to the second semiconductor layer.

[0136] In some embodiments, the passivation layer 2 further covers the side of the second doped semiconductor layer 10 facing away from the semiconductor substrate 4, and the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the second doped semiconductor layer 10. A plurality of second gate lines 8 are disposed on the conductive barrier layer 5. Specifically, a portion of the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the first doped semiconductor layer 3, and another portion of the conductive barrier layer 5 passes through the passivation layer 2 and is electrically connected to the second doped semiconductor layer 10. It is understood that the conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 and the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 should not conduct electricity to prevent leakage. With this configuration, the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 can separate the second gate lines 8 and the second doped semiconductor layer 10, ensuring both the passivation effect of the doped semiconductor layer and the conductivity between the second gate lines 8 and the second doped semiconductor layer 10.

[0137] The conductive barrier layer 5, which is electrically connected to the second doped semiconductor layer 10, can be electrically connected to the second doped semiconductor layer 10 by burning through or by opening a hole in the passivation layer 2. The technical characteristics of the conductive barrier layer 5, which is electrically connected to the second doped semiconductor layer 10, such as its material, thickness, and structure, can be referred to the description of the conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 above, and will not be repeated here.

[0138] When the conductive barrier layer 5 can be electrically connected to the first doped semiconductor layer 3 or the second doped semiconductor layer 10 through the passivation layer 2 by burning through, the first doped semiconductor layer 3 and the semiconductor substrate 4 have the same doping type. With this setting, the transmission resistance between the first doped semiconductor layer 3 and the semiconductor substrate 4 is lower, and the charge carriers can more easily pass through the interface between the first doped semiconductor layer 3 and the semiconductor substrate 4.

[0139] The conductive barrier layer 5 electrically connected to the first doped semiconductor layer 3 includes a plurality of sub-conductive barrier layers spaced apart along a first direction, with a minimum distance L1 between two adjacent sub-conductive barrier layers electrically connected to the first doped semiconductor layer 3 along the first direction; the conductive barrier layer 5 electrically connected to the second doped semiconductor layer 10 also includes a plurality of sub-conductive barrier layers spaced apart along the first direction, with a minimum distance L2 between two adjacent sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 along the first direction. Since the transmission resistance between the first doped semiconductor layer 3 and the semiconductor substrate 4 is lower than the transmission resistance between the second doped semiconductor layer 10 and the semiconductor substrate 4, in this technical solution, L2 < L1, so that the distance between the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 is smaller, and the density of the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 is greater, thereby balancing the transmission efficiency of charge carriers through the first doped semiconductor layer 3 and the second doped semiconductor layer 10, reducing the current difference of charge carriers through the first doped semiconductor layer 3 and the second doped semiconductor layer 10, and thus improving the overall power generation efficiency of the solar cell.

[0140] In some embodiments, the minimum distance between the plurality of sub-conductive barrier layers electrically connected to the first doped semiconductor layer 3 is set within a reasonable range of 1 mm ≤ L1 ≤ 3 mm, so as to improve the carrier transport efficiency while reducing the process difficulty of forming the sub-conductive barrier layers and improving production efficiency. For example, L1 can be 1 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.8 mm, 2 mm, 2.2 mm, 2.4 mm, 2.5 mm, 2.8 mm or 3 mm.

[0141] In some embodiments, the minimum distance between the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer 10 is set within a reasonable range of 0.2 mm ≤ L2 ≤ 2 mm, so as to improve the carrier transport efficiency while reducing the process difficulty of forming the sub-conductive barrier layers and improving production efficiency. For example, L2 can be 0.2 mm, 0.4 mm, 0.5 mm, 0.8 mm, 1 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.8 mm or 2 mm.

[0142] In practical applications, the semiconductor substrate 4 can be made of materials such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 4 can be an intrinsically conductive substrate, an n-type conductive substrate, or a p-type conductive substrate. Optionally, the semiconductor substrate 4 can be a p-type conductive substrate or an n-type conductive substrate. Compared to an intrinsically conductive substrate, a p-type or n-type conductive substrate has better conductivity, resulting in a lower bulk resistivity in the final solar cell, thereby improving the efficiency of the solar cell.

[0143] For example, the semiconductor substrate 4 can be a p-type substrate or an n-type substrate. The n-type substrate has advantages such as high minority carrier lifetime, no light decay, and good performance in low light.

[0144] The first doped semiconductor layer 3 comprises one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. In this case, the doped polycrystalline silicon layer has higher carrier transport characteristics, therefore, when the first doped semiconductor layer 3 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which is beneficial to improving the photoelectric conversion efficiency of the solar cell. Of course, the first doped semiconductor layer 3 can also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The second doped semiconductor layer 10 also comprises one or more of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0145] In some embodiments, a first interface layer 9 is disposed between the first doped semiconductor layer 3 and the semiconductor substrate 4, and a second interface layer 11 is disposed between the second doped semiconductor layer 10 and the semiconductor substrate 4. The passivated contact structure composed of the interface layer and the semiconductor layer has excellent interface passivation effect and can achieve selective collection of charge carriers, reducing the carrier recombination rate in the region where the semiconductor layer is formed on the surface of the semiconductor substrate 4, and further improving the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 9 can be set according to the material of the first doped semiconductor layer 3 and actual requirements, and the material and thickness of the second interface layer 11 can be set according to the material of the second doped semiconductor layer 10 and actual requirements; no specific limitations are made here.

[0146] For example, the first doped semiconductor layer 3 can be a doped polysilicon layer, and the first interface layer 9 can be a tunneling oxide layer. The second doped semiconductor layer 10 can be a doped polysilicon layer, and the second interface layer 11 can be a tunneling oxide layer.

[0147] Of course, when the first doped semiconductor layer 3 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the first interface layer 9 includes one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon. When the second doped semiconductor layer 10 includes one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon, the second interface layer 11 includes one or more of intrinsic amorphous silicon, intrinsic microcrystalline silicon, and intrinsic nanocrystalline silicon.

[0148] The materials of the first doped semiconductor layer 3 and the second doped semiconductor layer 10 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs), etc. Regarding the conductivity type, the first doped semiconductor layer 3 can be an n-type doped layer, and the second doped semiconductor layer 10 can be a p-type doped layer; or, the first doped semiconductor layer 3 can be a p-type doped layer, and the second doped semiconductor layer 10 can be an n-type doped layer.

[0149] It should be noted that the first gate line 1 can be a fine gate or a main gate.

[0150] For a gridless solar cell, the solar cell's grid includes a first grid and a second grid, and the first and second grids are arranged alternately along a second direction. The first grid can be the first grid line 1 mentioned above. In this embodiment, the first and second grids can be continuously and uninterruptedly arranged along the first direction or can be intermittently formed into multiple segments.

[0151] For a solar cell with a main grid, the solar cell's fine grid includes a first fine grid and a second fine grid, and the solar cell's main grid includes a first main grid and / or a second main grid. The first fine grid and / or the first main grid is the aforementioned first grid line 1. In this embodiment, the first fine grid and the second fine grid can be continuously and uninterruptedly arranged along a first direction or can be intermittently formed into multiple segments. In one case, there are multiple first main grids and multiple second main grids, which are sequentially spaced along the first direction. Any first fine grid and any second fine grid between adjacent first main grids and second main grids are continuously and uninterruptedly arranged along the first direction. All the multiple first fine grids are electrically connected to the first main grid, and all the multiple second fine grids are electrically connected to the second main grid. In another case, when there is only one first main grid and one second main grid, at least one first fine grid is electrically connected to the first main grid, and at least one second fine grid is electrically connected to the second main grid.

[0152] When the first grid line 1 is the main grid, the width of the first grid line 1 is greater than or equal to 400μm, for example, it can be 400μm, 420μm, 450μm, 480μm, 500μm, 520μm, 550μm, 580μm, or 600μm, etc. This can prevent the main grid width from being too small, causing the slurry of the main grid to flow into the gap between adjacent insulating blocks 6, resulting in the main grid breaking.

[0153] In the case of a back-contact solar cell, both the first grid line 1 and the second grid line 8 are formed on the first surface. The solar cell also includes a first conductive element 7 and a second conductive element. The first conductive element 7 is electrically connected to the plurality of first grid lines 1 and has an insulating block 6 between itself and the plurality of second grid lines 8; the second conductive element is electrically connected to the plurality of second grid lines 8 and has an insulating block 6 between itself and the plurality of first grid lines 1. This arrangement uses the insulating blocks 6 to separate the first conductive element 7 from the plurality of second grid lines 8, and at the same time separates the second conductive element from the plurality of first grid lines 1, reducing the risk of leakage.

[0154] Along the second direction, the spacing between adjacent insulating blocks 6 is greater than or equal to 100 μm. This sufficiently large distance between adjacent insulating blocks 6 provides a safe distance for slurry flow, preventing the slurry flowing to form the insulating blocks 6 from covering grid lines that shouldn't be covered. This ensures the stability of the electrical connections between the first grid line 1 and the first conductive element 7, and between the second grid line 8 and the second conductive element, thereby improving the stability of the solar cell's performance. For example, the spacing between adjacent insulating blocks 6 can be 100 μm, 110 μm, 120 μm, or 130 μm, etc.

[0155] Along the thickness direction of the cell body, the thickness of the insulating block 6 is less than or equal to 80 μm, for example, the thickness of the insulating block 6 is 80 μm, 70 μm, 60 μm, 50 μm, 40 μm, 30 μm, or 20 μm. This ensures the isolation effect of the insulating block 6 and prevents the paste forming the insulating block 6 from climbing up and covering the grid lines that it should not cover, thereby improving the stability of the solar cell performance.

[0156] As shown in Figures 15 and 16, when the first conductive element 7 is the main grid, the main grid can be directly physically contacted and electrically connected to the first grid line 1 (first fine grid). As shown in Figure 17, the intersection of the first conductive element 7 (main grid) and the first grid line 1 (first fine grid) has a side protrusion 7a protruding along a first direction. That is, along the first direction, the width of the position where the first conductive element 7 (main grid) has the side protrusion 7a is greater than the width of the other positions of the first conductive element 7. With this configuration, the side protrusion 7a can increase the contact area between the first conductive element 7 (main grid) and the first grid line 1 (first fine grid), thereby reducing the transmission resistance between the first conductive element 7 and the first grid line 1, reducing current loss, and improving the photoelectric conversion efficiency of the solar cell. In addition, in this technical solution, when there are spreading portions 102 on both sides of the first grid line 1, the spreading portions 102 can limit the flow distance of the paste forming the first conductive element 7 along the first direction from being too large, thus preventing the side protrusion 7a from becoming too wide.

[0157] In some embodiments, at least one of the first doped semiconductor layer 3 and the second doped semiconductor layer 10 may include a polycrystalline silicon region and an amorphous silicon region. Figures 18 to 21 illustrate the distribution of the polycrystalline silicon region and the amorphous silicon region in the first doped semiconductor layer 3. The distribution of the polycrystalline silicon region and the amorphous silicon region in the second doped semiconductor layer 10 is similar and will not be described again.

[0158] Figure 18 shows a partial TEM structure schematic diagram of a solar cell according to an embodiment of the present invention, illustrating the distribution of amorphous silicon region 31 and polycrystalline silicon region 32 (shown as open dashed lines in Figure 4) in the first doped semiconductor layer 3. Polycrystalline silicon region 32 contains polycrystalline silicon, and amorphous silicon region 31 contains amorphous silicon. Referring to the illustration in Figure 19, amorphous silicon region 31 is located at a portion of the corresponding doped semiconductor layer (the first doped semiconductor layer 3 shown in the figure) facing away from the semiconductor substrate 4.

[0159] Referring to the diagrams in Figures 19 to 21, the passivation layer 2 is disposed on the side of the first doped semiconductor layer 3 facing away from the semiconductor substrate 4, and the passivation layer 2 can be disposed adjacent to the first doped semiconductor layer 3; the passivation layer 2 has a plurality of openings 2a, and the number of openings 2a in the passivation layer 2 is not specifically limited. Referring to Figures 19 to 21, the amorphous silicon region 31 is located below the openings 2a, and at the same time, the amorphous silicon region 31 is also located between the passivation layer 2 and the polycrystalline silicon region, and is close to the position of the openings 2a. It should be noted that in the thickness direction Q of the semiconductor substrate 4, the polycrystalline silicon region 32 is closer to the semiconductor substrate 4 than the amorphous silicon region 31.

[0160] In addition, in the embodiments of this application, the first gate line 1 and the second gate line 8 are each located on the side of the corresponding opening 2a away from the semiconductor substrate 4 and in contact with the amorphous silicon region 31 to realize current collection and conduction.

[0161] The amorphous silicon in the amorphous silicon region 31 is more resistant to acid corrosion. Therefore, the amorphous silicon region 31 located below the opening 2a and between the passivation layer 2 and the polycrystalline silicon region 32, and near the opening 2a, can protect the film layer under the amorphous silicon region 31. For example, it can protect the corresponding first doped semiconductor layer 3 or second doped semiconductor layer 10, making the film layer under it more weather-resistant during long-term service, thus maintaining the reliability and stability of the solar cell during long-term service. Moreover, the passivation layer 2 is located between the polycrystalline silicon region 32 and near the opening 2a. The non-electrode region 31, located between the passivation layer 2 and the polycrystalline silicon region 32, and near the opening 2a, has slightly weaker conductivity than the corresponding doped semiconductor layer. This region blocks charge carriers in the non-electrode region, reducing recombination between the doped semiconductor layer and the metal in the gate lines. Furthermore, the amorphous silicon has a different refractive index than both the doped semiconductor layer and the passivation layer 2, increasing the light path in the solar cell and reducing reflected light, thus improving light trapping and overall cell performance. For example, the layer furthest from the semiconductor substrate 4 in the passivation layer 2 is the silicon nitride layer. The amorphous silicon has a different refractive index than both the silicon nitride layer and the doped semiconductor layer, further increasing the light path in the solar cell and reducing reflected light, thus improving light trapping and overall cell performance.

[0162] In some embodiments, in Figures 19 and 20, the direction M is parallel to the semiconductor substrate 4, and the direction M parallel to the semiconductor substrate 4 is perpendicular to the thickness direction Q of the semiconductor substrate 4. The leftmost position in Figure 21 is an opening 2a. Optionally, referring to Figure 20, starting from the edge of the opening 2a in the passivation layer 2 along a direction parallel to the semiconductor substrate 4, or in other words, on one side of an opening 2a, the length d1 of the amorphous silicon region 31 along the width of the opening 2a in the direction away from the opening 2a is less than or equal to 6 μm. Here, d1 is greater than 0. A d1 that is too large may be detrimental to the transport and collection of charge carriers. This opening 2a is usually formed by laser, and a d1 that is too large may cause significant laser damage. For example, referring to Figure 20, starting from the edge of the opening 2a in the passivation layer 2 along a direction parallel to the semiconductor substrate 4, the length d1 of the amorphous silicon region 31 is approximately 2.4 μm. For example, d1 can be 6μm, 5.5μm, 5.3μm, 5μm, 4.5μm, 4μm, 3.5μm, 3μm, 2.5μm, 2.45μm, 2.42μm, 2.41μm, 2.37μm, 2.35μm, 2.32μm, 2.2μm, 2.1μm, 2μm, 1.5μm, 1μm, 0.5μm, or 0.2μm.

[0163] It should be noted that, in the embodiments of this application, the direction parallel to the semiconductor substrate 4, starting from the edge of the opening 2a in the passivation layer 2, can be a direction from the opening 2a toward the passivation layer 2 and parallel to the semiconductor substrate 4. For example, in Figure 20, the left side of the opening 2a, starting from the edge of the opening 2a in the passivation layer 2 and parallel to the semiconductor substrate 4, is M2; the right side of the opening 2a, starting from the edge of the opening 2a in the passivation layer 2 and parallel to the semiconductor substrate 4, is M1. As another example, in Figure 21, if the opening 2a is located at the far left, then for the right side of the opening 2a, starting from the edge of the opening 2a in the passivation layer 2 and parallel to the semiconductor substrate 4, it is M1.

[0164] In some embodiments, a gap containing a first hole is formed between the passivation layer 2 located at the edge of the opening 2a and the corresponding first doped semiconductor layer 3 or second doped semiconductor layer 10. The following description and accompanying drawings use the gap between the first doped semiconductor layer 3 and the passivation layer 2 as an example.

[0165] Referring to Figure 21, a gap 21 containing a first hole 211 is formed between the passivation layer 2 at the edge of the opening 2a and the first doped semiconductor layer 3. In other words, at the edge of the opening 2a, along the aforementioned direction M1, there is a gap 21 containing a first hole 211 between the first doped semiconductor layer 3 and the passivation layer 2. The gap 21 and / or the first hole 211 here provide space for the gas escaping from the passivation layer 2, avoiding film bursting, improving the passivation effect, and compensating for the damage caused by laser film opening.

[0166] For example, hydrogen elements are typically formed in the passivation layer 2 during its formation. For instance, if the passivation layer 2 is made of aluminum oxide, excess hydrogen is generated during the aluminum oxide deposition process due to the presence of water in the reaction. During the laser-induced delamination of the passivation layer 2, hydrogen can escape from the passivation layer 2 under thermal effects, leading to film bursting and damaging both the passivation layer 2 and the first doped semiconductor layer 3, thus affecting the passivation effect. In this embodiment, the gap 21 is located near the edge of the passivation layer 2 close to the opening 2a, providing space for hydrogen to escape during the laser delamination process. This helps to mitigate or prevent film bursting, reduce damage caused by laser delamination, and effectively ensure the passivation effect of the solar cell. The gap 21 is mainly formed due to the thermal effects of laser delamination. Specifically, the passivation layer 2 in the unopened area near the edge of the opening 2a may slightly warp, or the doped semiconductor layer may develop micropores due to etching during the pre-treatment for forming the gate lines, thus forming the aforementioned gap 21. The shape of the first hole 211 is not specifically limited.

[0167] In some embodiments, referring to FIG21, the length of the amorphous silicon region 31 is greater than the length of the gap 21 in a direction parallel to the semiconductor substrate 4, starting from the edge of the opening 2a of the passivation layer 2. In other words, when taking a side view from a cross-section, the length of the amorphous silicon region 31 along the aforementioned direction M1 is greater than the length of the gap 21 on one side of the opening 2a. That is, on one side of the opening 2a, the length of the amorphous silicon region 31 is greater than the gap 21 in a direction parallel to the semiconductor substrate 4, starting from the edge of the opening 2a of the passivation layer 2. The greater length of the amorphous silicon region 31 provides greater protection to the underlying film layer, such as the first doped semiconductor layer 3, resulting in better weather resistance during long-term service and maintaining the reliability and stability of the solar cell during long-term service. Furthermore, it can further reduce recombination between the doped semiconductor layer and the metal in the grid lines. Additionally, the larger amorphous silicon region further enhances the effect of increasing the light travel path in the solar cell.

[0168] It should be noted that, starting from the edge of the opening 2a in the passivation layer 2 and moving parallel to the semiconductor substrate 4, the length of the amorphous silicon region 31 is greater than the length of the gap 21. Specifically, for an opening 2a, on both sides of the opening 2a, the length of the amorphous silicon region 31 on the side of the passivation layer 2 closer to the semiconductor substrate 4, starting from the edge of the opening 2a in the passivation layer 2 and moving parallel to the semiconductor substrate 4, is greater than the length of the gap 21 on the corresponding side; or, on only one of the two sides of the opening 2a, the length of the amorphous silicon region 31 starting from the edge of the opening 2a in the passivation layer 2 and moving parallel to the semiconductor substrate 4 is greater than the length of the gap 21 on that side. The specific amount by which the length of the amorphous silicon region 31 on one side of an opening 2a exceeds the length of the gap 21 is not limited.

[0169] In some embodiments, referring to FIG20, the thickness d2 of the amorphous silicon region 31 in the direction Q where the thickness of the semiconductor substrate 4 is located is 1 nm to 70 nm. In a solar cell, if the thickness of the amorphous silicon region 31 is greater than 70 nm, the carrier transport capability will be affected. If the thickness of the amorphous silicon region 31 is less than 1 nm, the blocking effect on recombination between the doped semiconductor layer and the metal in the gate line is poor. The thickness d2 of the amorphous silicon region 31 is 1 nm to 70 nm, which at least achieves an optimized balance between carrier transport capability and recombination blocking, not only providing good carrier transport but also providing good recombination blocking. For example, if the average thickness of the amorphous silicon region 31 is about 15 nm, an amorphous silicon region with a thickness of 52.84 nm may appear. This is mainly due to the uneven energy of the laser. The location with higher laser energy has higher heat and will form a thicker amorphous silicon layer.

[0170] For example, the thickness d2 at different locations in the amorphous silicon region 31 can be 8.38 nm, 13.04 nm, or 12.18 nm. Alternatively, referring to Figure 18, the thickness d2 at different locations in the amorphous silicon region 31 can be 8.65 nm or 12.01 nm. Furthermore, the thickness d2 of the amorphous silicon region 31 can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 14.5 nm, 15 nm, 15.5 nm, 16 nm, 16.5 nm, 17 nm, 18 nm, 18.99 nm, 20 nm, 26.76 nm, 30 nm, 31.05 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, or 70 nm.

[0171] For example, at the edge of the opening 2a, the thickness d2 of the amorphous silicon region 31 can be 14nm, 14.5nm, 14.8nm, 15nm, 15.5nm, 16nm, 16.5nm, or 17nm. For example, below the opening 2a, the thickness d2 of the amorphous silicon region 31 can be 8nm, 9nm, 8.5nm, 9.5nm, 10nm, 10.5nm, 10.8nm, 11nm, 11.5nm, 11.8nm, 12nm, 12.5nm, 13nm, or 16nm.

[0172] Referring to the illustrations in Figures 19 to 21, it should be noted that in the embodiments of this application, the amorphous silicon region 31 can be located at the edge of the opening 2a, or it can extend along the M direction shown in the figure to below the passivation layer 2. The amorphous silicon region 31 can be located within the orthographic projection area of ​​the opening 2a, or it can extend beyond the orthographic projection area of ​​the opening 2a.

[0173] For the opening 2a shown in Figure 20, the right side of the opening 2a, along the direction from the passivation layer 2 to the opening 2a, or in other words, towards the opening 2a, is shown in the opposite direction of arrow M1. The left side of the opening 2a, along the direction from the passivation layer 2 to the opening 2a, or in other words, towards the opening 2a, is shown in the opposite direction of arrow M2. Optionally, the thickness of the amorphous silicon region 31 increases along the direction from the passivation layer 2 to the opening 2a, pointing towards the opening 2a. The thickness of the amorphous silicon region 31 increases at various points on one or both sides of the opening 2a; the direction of the thickness is parallel to the direction Q of the thickness of the semiconductor substrate 4. On the one hand, the laser energy is higher near the opening 2a. When the opening 2a is subsequently subjected to wet processing such as acid etching, the thicker amorphous silicon region 31 near the opening 2a is more resistant to acid. The opening 2a and the area closer to the opening 2a are more easily exposed to the external environment, which can fully protect the doped semiconductor layer on the side close to the semiconductor substrate 4 and protect the film layer under the amorphous silicon region 31, such as the first doped semiconductor layer 3. This makes the film layer under it more weather-resistant during long-term service, maintaining the reliability and stability of the solar cell during long-term service. On the other hand, the amorphous silicon in the non-electrode region far away from the opening 2a is thinner. Since the parasitic absorption of amorphous silicon is more severe than that of the doped semiconductor layer, it is necessary to minimize the parasitic absorption caused by amorphous silicon. Therefore, thinner amorphous silicon has lower parasitic absorption, and the amorphous silicon region 31 of suitable thickness can also achieve the aforementioned good technical effects.

[0174] It should be noted that the increase in thickness of the amorphous silicon region 31 along the direction from the passivation layer 2 to the opening 2a refers to the direction closer to the opening 2a. The thickness of the amorphous silicon region 31 should generally show an increasing trend, and the method of increase is not limited. For example, it can be a linear increase, an exponential increase, etc.

[0175] In some embodiments, as shown in Figures 22 and 23, Figure 22 is a side view of one side of a bifacial battery, and Figure 23 is a side view of a back-contact battery. Gate lines of different conductivity types are insulated; however, the insulation treatment method is not shown in Figure 23. The first doped semiconductor layer 3 has a first region 3A and a second region 3B, wherein the first region 3A and the second region 3B can be distributed along a direction parallel to the first surface of the semiconductor substrate 4. The doping concentration of the first element in the first region 3A is C. a1 The doping concentration of the first element in the second region 3B is C. a2 C a2 >C a1 .

[0176] As shown in Figure 24, the horizontal axis represents the depth along the first region 3A and the second region 3B from the side away from the semiconductor substrate 4 (i.e., from the outermost surface of the N-type doped semiconductor layer away from the silicon substrate) to the side close to the semiconductor substrate 4. The vertical axis represents the doping concentration of the first element. The activated doping concentration curve was obtained by testing with an ECV instrument. The doping concentration mentioned in the embodiments of this application refers to the activated doping element concentration.

[0177] As can be seen from Figure 24, from the side of the first region 3A and the second region 3B away from the semiconductor substrate 4 to a certain depth, C a2 >C a1 In this design, the second region 3B can be a region electrically connected to the first gate line 1. Compared to the first region 3A, which is not electrically connected to the first gate line 1, the second region 3B, which is electrically connected to the first gate line 1, has a higher doping concentration. This results in higher conductivity in the second region 3B of the first doped semiconductor layer 3, thereby reducing the transmission resistance between the first gate line 1 and the second region 3B, which is more conducive to the transmission of charge carriers and reduces current loss. Simultaneously, the thickness, number of openings, or opening area of ​​the first doped semiconductor layer 3 can be further reduced, saving material costs and reducing process-related damage.

[0178] The second doped semiconductor layer 10 has a third region 10A and a fourth region 10B, wherein the third region 10A and the fourth region 10B can be distributed along a direction parallel to the first surface of the semiconductor substrate 4. It can be understood that the distribution direction of the third region 10A and the fourth region 10B is the same as the distribution direction of the first region 3A and the second region 3B. The doping concentration of the second element in the third region 10A is C. b1 The doping concentration of the second element in the fourth region 10B is C. b2 C b2 >C b1 Furthermore, C a2 >C b2 .

[0179] As shown in Figure 25, the horizontal axis represents the depth along the side of the third region 10A and the fourth region 10B away from the semiconductor substrate 4 (i.e., from the outermost surface of the P-type doped semiconductor layer away from the silicon substrate) to the side closest to the semiconductor substrate 4. The vertical axis represents the doping concentration of the second element. It can be seen from Figure 25 that from the side of the third region 10A and the fourth region 10B away from the semiconductor substrate 4 to a certain depth, C... b2 >C b1 .

[0180] In this design, the fourth region 10B can be a region electrically connected to the second gate line 8. Compared to the third region 10A, which is not electrically connected to the second gate line 8, the fourth region 10B, which is electrically connected to the second gate line 8, has a higher doping concentration. This results in higher conductivity in the fourth region 10B of the second doped semiconductor layer 10, thereby reducing the transport resistance between the second gate line 8 and the fourth region 10B, which is more conducive to the transport of charge carriers and reduces current loss. Simultaneously, the thickness, number of apertures, or aperture area of ​​the second doped semiconductor layer 10 can be further reduced, saving material costs and reducing process-related damage.

[0181] In this embodiment of the application, C a2 >C b2 That is, the doping concentration C of the first element in the second region 3B. a2 The doping concentration C of the second element in region 10B is greater than that in region 4. b2 This configuration makes the conductivity of the second region 3B of the thinner first doped semiconductor layer 3 closer to that of the fourth region 10B of the thicker second doped semiconductor layer 10, thereby reducing the current difference between the first gate line 1 and the first doped semiconductor layer 3 and between the second gate line 8 and the second doped semiconductor layer 10, reducing the current loss of the battery and ensuring the performance of the battery.

[0182] In some embodiments, C a2 and C b2 These refer to the doping concentrations of the second region 3B and the fourth region 10B extending into the semiconductor substrate 4 to the same depth. For example, this could be the doping concentration at the outermost surface of the corresponding doped semiconductor layer, or the doping concentration extending from the outermost surface into the semiconductor substrate 4 to 10nm, 20nm, 25nm, 30nm, 40nm, or 50nm. To avoid unstable or missing test data for the outermost surface doping concentration, and for easier evidence collection, the extension to 20nm, 25nm, or 30nm is preferred.

[0183] If the first region 3A, the second region 3B, the third region 10A, and the fourth region 10B are all distributed along a direction parallel to the first surface of the semiconductor substrate 4, then the first region 3A refers to the region of the first doped semiconductor layer 3 that does not correspond to the opening 2a of the passivation layer 2, the second region 3B refers to the region of the first doped semiconductor layer 3 that corresponds to the opening 2a of the passivation layer 2, the third region 10A refers to the region of the second doped semiconductor layer 10 that does not correspond to the opening 2a of the passivation layer 2, and the fourth region 10B refers to the region of the second doped semiconductor layer 10 that corresponds to the opening 2a of the passivation layer 2. The average doping concentration of several sites within the first region 3A is taken as C. a1 The average doping concentration of several sites in the third region 10A is calculated as C. b1 .

[0184] In practical applications, the first doped semiconductor layer 3 (N-type semiconductor layer) has a higher solid solubility of P element, allowing for a higher doping content into the semiconductor substrate 4. Therefore, the thickness of the first doped semiconductor layer 3 (N-type semiconductor layer) is set to be smaller. This reduces material usage and minimizes parasitic absorption losses caused by the first doped semiconductor layer 3. While reducing the thickness of the first doped semiconductor layer 3 (N-type semiconductor layer), it is necessary to maintain the conductivity of the first doped semiconductor layer 3 at a comparable level to before thinning. Therefore, in this embodiment, ΔC... a =C a2 -C a1 , △C b =C b2 -C b1 , △C a >△C b In other words, the difference in doping concentration between the second region 3B and the first region 3A of the first doped semiconductor layer 3 is greater than the difference in doping concentration between the third region 10A and the fourth region 10B of the second doped semiconductor layer 10. This configuration ensures that the current transport efficiency of the first doped semiconductor layer 3 can be maintained at a comparable level before thinning. In addition, it can also reduce the current difference between the first gate line 1 and the first doped semiconductor layer 3 and between the second gate line 8 and the second doped semiconductor layer 10, thereby reducing the current loss of the battery.

[0185] In some embodiments, if △C a If the value is too large, it increases the complexity of the process and leads to an increase in the raw material cost of the first element; if △C a If the doping concentration is too low, the doping concentration of 3B in the second region will be low, affecting the efficiency of carrier extraction in the second region 3B. Therefore, in this technical solution, 4*E21atom / cm 3 ≤△C a ≤9*E22 atom / cm 3This ensures the efficiency of carrier extraction in the second region 3B, while reducing process complexity and raw material costs. For example, △C a It can be 4*E21atom / cm 3 6*E21atom / cm 3 7*E21atom / cm 3 8*E21atom / cm 3 9*E21atom / cm 3 1*E22atom / cm 3 2*E22atom / cm 3 4*E22atom / cm 3 5*E22atom / cm 3 7*E22atom / cm 3 8*E22atom / cm 3 Or 9*E22atom / cm 3 wait.

[0186] In this technical solution, 3*E19atom / cm 3 ≤△C b ≤2*E21 atom / cm 3 This ensures that the fourth region 10B has high conductivity and high efficiency in extracting charge carriers, while also reducing manufacturing complexity and the raw material cost of the second element. For example, ΔC b It can be 3*E19atom / cm 3 5*E19atom / cm 3 6*E19atom / cm 3 8*E19atom / cm 3 9*E19atom / cm 3 9*E19atom / cm 3 9*E19atom / cm 3 1*E20atom / cm 3 2*E20atom / cm 3 4*E20atom / cm 3 6*E20atom / cm 3 8*E20atom / cm 3 9*E20atom / cm 3 1*E21atom / cm 3 Or 2*E21atom / cm 3 wait.

[0187] In some embodiments, K a =Ca2 / C a1 K b =C b2 / C b1 K a ≥K b In other words, the ratio of the doping concentration between the second region 3B and the first region 3A of the first doped semiconductor layer 3 is greater than or equal to the difference in doping concentration between the fourth region 10B and the third region 10A of the second doped semiconductor layer 10. Using this technical solution, the doping concentrations of the second region 3B and the fourth region 10B can be adjusted according to actual conditions, thereby making the conductivity of the second region 3B and the fourth region 10B closer, balancing the extraction efficiency of holes and electrons, and thus reducing current loss.

[0188] ΔC of the first doped semiconductor layer 3 a Larger and / or K a The larger thickness of the first doped semiconductor layer 3 allows for a thinner layer, or fewer openings or smaller opening areas. This design brings three benefits: it saves material costs, improves the carrier transport capacity of the first doped semiconductor layer 3, reduces the carrier recombination rate, improves the photoelectric conversion efficiency of the solar cell, and reduces damage to the first doped semiconductor layer 3 during fabrication.

[0189] In some embodiments, if K a If K is too small, the doping concentration of the second region 3B will be low, resulting in low conductivity of the second region 3B and affecting the efficiency of carrier extraction in the second region 3B; if K a If the value is too large, it increases the complexity of the process and leads to an increase in the raw material cost of the first element; in view of the above, in this technical solution, 2≤K a ≤1000, to ensure the efficiency of carrier extraction in the second region 3B, while reducing process difficulty and raw material costs. For example, K a The values ​​can be 2, 50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, or 1000.

[0190] In this technical solution, 2≤K b ≤1000 is used to ensure that the fourth region 10B has high conductivity. The fourth region 10B has high efficiency in extracting charge carriers, while reducing the difficulty of the process and the raw material cost of the second element. For example, K bThe values ​​can be 2, 50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700, 750, 800, 850, 900, 950, or 1000.

[0191] In some embodiments, as shown in FIG24, the horizontal axis represents the depth from the surface of the first doped semiconductor layer 3 to its interior, and the vertical axis represents the doping concentration of the first element. As shown in FIG25, the horizontal axis represents the depth from the surface of the second doped semiconductor layer 10 to its interior, and the vertical axis represents the doping concentration of the second element. Comparing FIG24 and FIG25, it can be seen that the rate of change of the doping concentration of the first element with depth in the second region 3B is significantly greater than the rate of change of the doping concentration of the second element with depth in the fourth region 10B.

[0192] The doping concentration of the first element in the second region 3B and the doping concentration of the second element in the fourth region 10B can be used as long as they are applicable to the solar cell provided in the embodiments of this application. For example, the doping concentration of the first element in the second region 3B is 5*E21~6*E22 atom / cm. 3 This approach not only prevents excessively high doping concentrations from affecting the crystal structure distribution to meet current transport efficiency requirements, but also saves on the raw materials for the first element. For example, the doping concentration of the first element in the second region 3B is 5*E21atom / cm³. 3 6*E21atom / cm 3 7*E21atom / cm 3 8*E21atom / cm 3 9*E21atom / cm 3 1*E22atom / cm 3 3*E22atom / cm 3 4*E22atom / cm 3 5*E22atom / cm 3 Or 6*E22atom / cm 3 The doping concentration of the second element in the fourth region 10B is 1*E20~3*E21 atom / cm³. 3 This approach prevents excessively high doping concentrations from affecting the crystal structure, thus ensuring current transport efficiency, and also saves on the raw materials for the second element. For example, the doping concentration of the second element in the fourth region of 10B is 1*E20atom / cm³. 3 3*E20atom / cm 3 5*E20atom / cm 3 8*E20atom / cm 3 1*E21atom / cm 32*E21atom / cm 3 Or 3*E21atom / cm 3 etc. Among them, the doping concentration of the first element in the second region 3B is the average doping concentration of the first element in the second region 3B; the doping concentration of the second element in the fourth region 10B is the average doping concentration of the second element in the fourth region 10B.

[0193] In addition, this application also provides a photovoltaic module, which includes the solar cell provided in any of the above embodiments.

[0194] Electrically connecting at least two solar cells provided in any of the foregoing embodiments via electrical connectors (also known as solder ribbons) can form a cell string for lamination in a photovoltaic module. Multiple cell strings are electrically connected in at least one of series and parallel configurations. The cell strings are then sandwiched between a backsheet and a cover glass, with adhesive films applied between the two surfaces of the cell strings and the backsheet and cover glass, respectively, for bonding and fixing. This laminated structure, after lamination, yields a laminated component. Assembling the laminated component with a frame yields the photovoltaic module of this application embodiment. Of course, some photovoltaic modules can also be frameless products; this application embodiment does not limit this.

[0195] As shown in Figure 26, a first conductive element 7 on the surface of the solar cell according to an embodiment of this application is also shown. The first conductive element 7 extends along a second direction and is electrically connected to the first grid line 1. The first conductive element 7 and the first grid line 1 can be electrically connected through direct physical contact or through a bonding layer.

[0196] In the photovoltaic module of this application embodiment, as shown in FIG26, the first conductive element 7 is a solder ribbon, which connects at least two solar cells to form a cell structure (i.e., a cell string structure). In this case, the solar cell can be a gridless cell. As shown in FIG27, the solder ribbon is electrically connected to the first grid line 1 through a bonding layer 12. The bonding layer 12 can specifically be solder or conductive adhesive. Using this technical solution, the solder ribbon is directly electrically connected to the first grid line 1, achieving the effect of reducing shading and resistance loss. When the first conductive element 7 is a grid, the photovoltaic module will also include a solder ribbon, which needs to be soldered to the grid using a bonding material, thereby realizing the series or parallel connection of multiple cells at the module end.

[0197] In some embodiments, as shown in FIG28, the first grid line 1 includes thickened segments 1e spaced apart along a first direction, and the width of the thickened segments 1e is greater than the width of the rest of the first grid line 1 along a second direction. That is, the thickened segments 1e are provided at the location where the first grid line 1 connects to the first conductive element 7. The thickened segments 1e can be integrally formed with the rest of the first grid line 1 or formed separately. Using this technical solution, the thickened segments 1e can increase the contact area between the first grid line 1 and the bonding layer 12, thereby reducing the transmission resistance between the bonding layer 12 and the first grid line 1, reducing current loss, and improving the photoelectric conversion efficiency of the solar cell.

[0198] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0199] The terms "an embodiment," "embodiment," or "one or more embodiments" as used herein mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment of this application. Furthermore, please note that the examples of the phrase "in one embodiment" do not necessarily all refer to the same embodiment.

[0200] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0201] In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

[0202] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A solar cell, characterized in that, include: The battery body includes a first surface and a second surface that are disposed opposite to each other; A conductive barrier layer is disposed at least on the first surface; Multiple first gate lines are disposed on the conductive barrier layer, extending along a first direction and arranged along a second direction, the first and second directions intersecting; along a plane perpendicular to the first direction, the cross-sectional area of ​​the first gate lines is greater than or equal to 250 μm². 2 ; Along the thickness direction of the battery body, the height of the first grid line is h; the width of the first grid line is w, h / w is 0.1 to 0.5, and w ≥ 30 μm; The spacing between two adjacent first gate lines is 0.6 mm to 1.3 mm.

2. The solar cell according to claim 1, characterized in that, 140μm≥w≥30μm; and / or, 5μm≥h≥25μm.

3. The solar cell according to claim 1, characterized in that, The first gate line comprises copper powder and organic matter; The copper powder includes at least flaky particles and spherical particles.

4. The solar cell according to claim 3, characterized in that, The copper powder further includes one or more of linear particles, V-shaped particles, polygonal particles, and columnar particles; and / or, the median diameter of the sheet-like particles is 0.8 μm to 5 μm; and / or, the median thickness of the sheet-like particles is 100 nm to 500 nm; and / or, the median particle size of the spherical particles is 100 nm to 500 nm.

5. The solar cell according to claim 4, characterized in that, The mass percentage of the flaky particles is 35% to 60%; and / or, the mass percentage of the spherical particles is 35% to 60%; and / or, the tapped density of the flaky particles is 3 g / ml to 6 g / ml; and / or, the tapped density of the spherical particles is 3.5 g / ml to 5.5 g / ml; and / or, the specific surface area of ​​the flaky particles is 0.4 m². 2 / g~0.7m 2 / g; and / or, the specific surface area of ​​the spherical particles is 1.5m². 2 / g~3.5m 2 / g; and / or, the organic compound includes one or more of the following: saturated / unsaturated fatty acids containing 8-18 carbons, silane coupling agents, PVP, and thiols.

6. The solar cell according to claim 1, characterized in that, The first grid line includes a main body portion and a spreading portion arranged along the second direction, and the main body portion and the spreading portion extend along the first direction; Along the second direction, the width W1 of the main body portion is 30μm to 120μm; and / or, along the second direction, the width W2 of the spreading portion is 1μm to 60μm; and / or, along the second direction, the width of the spreading portion is 5% to 50% of the width of the main body portion; and / or, along the thickness direction of the battery body, the height h1 of the main body portion is 8μm to 25μm; and / or, along the thickness direction of the battery body, the height of the main body portion is h1, the height of the spreading portion is h2, and h2 ≤ 1 / 3h1; and / or, the median particle size of the copper powder contained in the spreading portion is less than the median particle size of the copper powder contained in the main body portion.

7. The solar cell according to claim 1, characterized in that, The first grid line is formed from a non-burn-through slurry; and / or, the resistivity of the first grid line is 6 μΩ·cm to 60 μΩ·cm.

8. The solar cell according to claim 1, characterized in that, The battery body includes a semiconductor substrate, a first doped semiconductor layer, and a passivation layer; The first doped semiconductor layer is disposed on the first surface of the semiconductor substrate, the passivation layer covers the side of the first doped semiconductor layer away from the semiconductor substrate, and the conductive barrier layer passes through the passivation layer and is electrically connected to the first doped semiconductor layer.

9. The solar cell according to claim 8, characterized in that, The passivation layer has an opening that exposes the first doped semiconductor layer; the first gate line covers the opening and is electrically connected to the first doped semiconductor layer.

10. The solar cell according to claim 9, characterized in that, The conductive barrier layer fills the opening; The thickness of the portion of the conductive barrier layer corresponding to the area of ​​the opening is greater than the thickness of the passivation layer; and / or, the thickness of the portion of the conductive barrier layer corresponding to the area of ​​the opening is 0.5 μm to 5 μm.

11. The solar cell according to claim 10, characterized in that, The first doped semiconductor layer forms a modified layer in the region corresponding to the opening; The roughness of the modified layer is greater than the roughness of the other parts of the first doped semiconductor layer, and / or the crystallization degree of the modified layer is lower than the crystallization degree of the other parts of the first doped semiconductor layer.

12. The solar cell according to claim 9, characterized in that, The passivation layer has a heat-affected zone surrounding the opening; The width of the heat-affected zone is D, 1μm≤D≤5μm; and / or, the heat-affected zone includes multiple holes and / or cracks, the holes and / or cracks are filled with conductive material, and the conductive material is electrically connected to the first doped semiconductor layer.

13. The solar cell according to claim 9, characterized in that, The total area of ​​the orthographic projection of the openings corresponding to the same first grid line on the first surface is 20% to 80% of the orthographic projection area of ​​the first grid line on the first surface; or, the number of openings corresponding to the same first grid line is multiple and distributed at intervals; or, the openings corresponding to the same first grid line are arranged in a strip shape.

14. The solar cell according to claim 9, characterized in that, The region corresponding to the opening in the first doped semiconductor layer includes multiple pits; the inner diameter of the pits is 0.5 μm to 2 μm.

15. The solar cell according to claim 8, characterized in that, The conductive barrier layer is electrically connected to the first doped semiconductor layer by burning through the passivation layer.

16. The solar cell according to claim 15, characterized in that, The first doped semiconductor layer further includes a metal crystal layer located on the side of the conductive barrier layer near the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the thickness of the metal crystal layer is less than or equal to the thickness of the first doped semiconductor layer; Alternatively, along the thickness direction of the semiconductor substrate, the thickness of the metal crystal layer is 2 / 3 of the thickness of the first doped semiconductor layer; or, along the thickness direction of the semiconductor substrate, the distance between the metal crystal layer and the interface layer between the first doped semiconductor layer and the semiconductor substrate is less than 10 nm.

17. The solar cell according to claim 15, characterized in that, The conductive barrier layer includes multiple pores; and / or the thickness of the conductive barrier layer is 0.1 μm to 10 μm.

18. The solar cell according to claim 9, characterized in that, The solar cell further includes a second doped semiconductor layer and a plurality of second gate lines. The second doped semiconductor layer has the opposite conductivity type to the first doped semiconductor layer, and the second gate lines are disposed on the side of the second doped semiconductor layer away from the semiconductor substrate. The first gate line and the second gate line are made of the same material, and the polarities of the first gate line and the second gate line are opposite. The second doped semiconductor layer and a plurality of second gate lines are disposed on the first surface, the plurality of second gate lines extend along a first direction and are arranged along a second direction, the first doped semiconductor layer and the second doped semiconductor layer are alternately distributed along the second direction, and the plurality of first gate lines and the second gate lines are alternately distributed along the second direction; or, the second doped semiconductor layer and a plurality of second gate lines are disposed on the second surface, the plurality of second gate lines extend along a first direction and are arranged along a second direction.

19. The solar cell according to claim 18, characterized in that, The passivation layer also covers the side of the second doped semiconductor layer away from the semiconductor substrate, and the conductive barrier layer also passes through the passivation layer and is electrically connected to the second doped semiconductor layer, with a plurality of second gate lines disposed on the conductive barrier layer.

20. The solar cell according to claim 19, characterized in that, The conductive barrier layer is electrically connected to the first doped semiconductor layer or the second doped semiconductor layer by burning through the passivation layer; the first doped semiconductor layer has the same doping type as the semiconductor substrate; the conductive barrier layer includes a plurality of sub-conductive barrier layers spaced apart along a first direction. Among the plurality of sub-conductive barrier layers electrically connected to the first doped semiconductor layer, the minimum distance between two adjacent sub-conductive barrier layers along the first direction is L1; among the plurality of sub-conductive barrier layers electrically connected to the second doped semiconductor layer, the minimum distance between two adjacent sub-conductive barrier layers along the first direction is L2. L2 < L1; and / or, 1mm ≤ L1 ≤ 3mm; and / or, 0.2mm ≤ L2 ≤ 2mm.

21. The solar cell according to claim 18, characterized in that, The first doped semiconductor layer and / or the second doped semiconductor layer have polycrystalline silicon regions and amorphous silicon regions, wherein the amorphous silicon regions are located on the side of the corresponding semiconductor doped layer away from the semiconductor substrate.

22. The solar cell according to claim 21, characterized in that, The length of the amorphous silicon region is less than or equal to 6 μm, starting from the edge of the opening in the passivation layer and running parallel to the semiconductor substrate.

23. The solar cell according to claim 21, characterized in that, A gap containing a first hole is formed between the passivation layer located at the edge of the opening and the first doped semiconductor layer or the second doped semiconductor layer.

24. The solar cell according to claim 23, characterized in that, Starting from the edge of the opening in the passivation layer and along a direction parallel to the semiconductor substrate, the length of the amorphous silicon region is greater than the length of the gap.

25. The solar cell according to claim 21, characterized in that, In the direction along which the thickness of the semiconductor substrate lies, the thickness of the amorphous silicon region is from 1 nm to 70 nm; and / or, The thickness of the amorphous silicon region increases along the direction from the passivation layer to the opening.

26. The solar cell according to claim 18, characterized in that, The first doped semiconductor layer has a first region and a second region, which are arranged in a direction parallel to the surface of the semiconductor substrate; the doping concentration of the first element in the first region is C. a1 The doping concentration of the first element in the second region is C. a2 C a2 >C a1 ; The second doped semiconductor layer has a third region and a fourth region, which are arranged in a direction parallel to the surface of the semiconductor substrate; the doping concentration of the second element in the third region is C. b1 The doping concentration of the second element in the fourth region is C. b2 C b2 >C b1 ; Furthermore, C a2 >C b2 .

27. The solar cell according to claim 26, characterized in that, △C a =C a2 -C a1 ,△C b =C b2 -C b1 ,△C a >△C b ; And / or, K a =C a2 / C a1 K b =C b2 / C b1 K a ≥K b .

28. The solar cell according to claim 26, characterized in that, K a =C a2 / C a1 2≤K a ≤1000; and / or, K b =C b2 / C b1 2≤K b ≤1000; and / or, △C a =C a2 -C a1 4*E21atom / cm 3 ≤△C a ≤9*E22 atom / cm 3 ; and / or, △C b =C b2 -C b1 3*E19atom / cm 3 ≤△C b ≤2*E21 atom / cm 3 .

29. The solar cell according to any one of claims 26 to 28, characterized in that, The doping concentration of the first element in the second region is 5*E21~6*E22 atom / cm³. 3 ; and / or, The doping concentration of the second element in the fourth region is 1*E20~3*E21 atom / cm³. 3 .

30. A photovoltaic module, characterized in that, include: Multiple battery strings connected in series and / or in parallel, the battery strings comprising: electrical connectors and solar cells according to any one of claims 1 to 29, the electrical connectors electrically connecting at least two of the solar cells.

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