Ultrasonic pixel circuit and driving method, and ultrasonic detection panel

Abstract

Embodiments of the present disclosure provide an ultrasonic pixel circuit and a driving method, and an ultrasonic detection panel. The ultrasonic pixel circuit comprises an ultrasonic detection circuit and a delay mitigation circuit; the delay mitigation circuit is coupled between a driving signal terminal and the ultrasonic detection circuit, and is configured to reduce the duration of a rising edge and of a falling edge of a signal of the driving signal terminal and then output the signal to the ultrasonic detection circuit; the ultrasonic detection circuit is configured to perform ultrasonic detection in response to the received signal, so that the delay of level transition of a control signal inputted to the ultrasonic pixel circuit can be mitigated by means of the delay mitigation circuit, improving the collection precision of the ultrasonic pixel circuit, and the problem of signal distortion at a near-end and a far-end caused by the difference in durations of rising edges and falling edges of received signals can also be effectively mitigated.

Description

Ultrasonic pixel circuit and driving method, ultrasonic detection panel Technical Field

[0001] This invention relates to the field of ultrasonic imaging technology, and in particular to an ultrasonic pixel circuit and driving method, and an ultrasonic detection panel. Background Technology

[0002] With the rapid development of science and technology and major breakthroughs in various fields, the application of ultrasound has crossed most fields. It not only occupies a pivotal position in the defense industry, military industry, medical field and daily life, but its importance in the economy is also becoming more and more obvious.

[0003] In ultrasonic applications, the ultrasonic pixel circuit is a key component. Ultrasonic pixel circuits typically contain switching transistors, whose control terminals are controlled by control signals. However, currently, the level transition delay of these control signals is relatively long, affecting the acquisition accuracy of the ultrasonic pixel circuit. Summary of the Invention

[0004] This disclosure provides an ultrasonic pixel circuit, including: an ultrasonic detection circuit and a delay improvement circuit;

[0005] The delay improvement circuit is coupled between the drive signal terminal and the ultrasonic detection circuit, and is configured to reduce the duration of the rising and falling edges of the signal at the drive signal terminal before outputting it to the ultrasonic detection circuit.

[0006] The ultrasonic detection circuit is configured to perform ultrasonic detection in response to a received signal.

[0007] In some possible implementations, the delay improvement circuit includes cascaded n inverters, where n is an integer not less than 1;

[0008] The first power supply terminal of each inverter is used to receive the first power supply voltage, and the second power supply terminal of each inverter is used to receive the second power supply voltage.

[0009] The input terminal of the first-stage inverter is coupled to the drive signal terminal;

[0010] Except for the last stage inverter, the output of the previous stage inverter in two adjacent stages is coupled to the input of the next stage inverter.

[0011] The output of the final stage inverter is coupled to the ultrasonic detection circuit.

[0012] In some possible implementations, the delay improvement circuit reduces the duration of the rising and falling edges of the signal at the drive signal terminal in a manner proportional to the number of inverters in the delay improvement circuit.

[0013] In some possible implementations, the ultrasonic detection circuit includes: a reset circuit and an ultrasonic sensing unit, wherein the reset circuit is coupled to a first terminal of the ultrasonic sensing unit.

[0014] The delay improvement circuit includes a first delay improvement circuit;

[0015] The drive signal terminal includes a reset control terminal, and the first delay improvement circuit is coupled between the reset control terminal and the reset circuit.

[0016] In some possible implementations, the first delay improvement circuit is configured to: output the first power supply voltage to the reset circuit in response to a high-level signal in the signal of the reset control terminal; and output the second power supply voltage to the reset circuit in response to a low-level signal in the signal of the reset control terminal.

[0017] Wherein, the voltage of the low-level signal in the reset control terminal signal is less than the sum of the low voltage of the first power supply voltage and the second power supply voltage and the first preset voltage, and the voltage of the high-level signal in the reset control terminal signal is greater than the difference between the high voltage of the first power supply voltage and the second power supply voltage and the second preset voltage.

[0018] In some possible implementations, the number of inverters in the first delay improvement circuit is an odd number, and the first power supply voltage is less than the second power supply voltage; or,

[0019] The number of inverters in the first delay improvement circuit is even, and the first power supply voltage is greater than the second power supply voltage.

[0020] In some possible implementations, the ultrasonic detection circuit includes: a detection circuit and an ultrasonic sensing unit, wherein the detection circuit is coupled between a first end and a first node of the ultrasonic sensing unit.

[0021] The delay improvement circuit includes a second delay improvement circuit;

[0022] The drive signal terminal includes a detection control terminal, and the second delay improvement circuit is coupled between the detection control terminal and the detection circuit.

[0023] In some possible implementations, the second delay improvement circuit is configured to: output the first power supply voltage to the detection circuit in response to a high-level signal in the signal of the detection control terminal; and output the second power supply voltage to the detection circuit in response to a low-level signal in the signal of the detection control terminal.

[0024] Wherein, the voltage of the low-level signal in the signal of the detection control terminal is less than the sum of the low voltage of the first power supply voltage and the second power supply voltage and the first preset voltage, and the voltage of the high-level signal in the signal of the detection control terminal is greater than the difference between the high voltage of the first power supply voltage and the second power supply voltage and the second preset voltage.

[0025] In some possible implementations, the number of inverters in the second delay improvement circuit is an odd number, and the first power supply voltage is less than the second power supply voltage; or,

[0026] The number of inverters in the second delay improvement circuit is even, and the first power supply voltage is greater than the second power supply voltage.

[0027] In some possible implementations, the ultrasonic detection circuit includes: a detection circuit, a storage circuit, and a reading circuit coupled to the first node;

[0028] The delay improvement circuit includes a third delay improvement circuit;

[0029] The drive signal terminal includes a read control terminal, and the third delay improvement circuit is coupled between the read control terminal and the read circuit.

[0030] In some possible implementations, the third delay improvement circuit is configured to: output the first power supply voltage to the read circuit in response to a high-level signal in the signal of the read control terminal; and output the second power supply voltage to the read circuit in response to a low-level signal in the signal of the read control terminal.

[0031] Wherein, the voltage of the low-level signal in the signal of the reading control terminal is less than the sum of the low voltage of the first power supply voltage and the second power supply voltage and the first preset voltage, and the voltage of the high-level signal in the signal of the reading control terminal is greater than the difference between the high voltage of the first power supply voltage and the second power supply voltage and the second preset voltage.

[0032] In some possible implementations, the number of inverters in the third delay improvement circuit is an odd number, and the first power supply voltage is less than the second power supply voltage; or,

[0033] The number of inverters in the third delay improvement circuit is an even number, and the first power supply voltage is greater than the second power supply voltage.

[0034] In some possible implementations, the inverter includes a first transistor and a second transistor;

[0035] The control terminals of the first transistor and the second transistor are both coupled to the input terminal of the inverter.

[0036] The first terminal of the first transistor is used to receive the first power supply voltage, and the first terminal of the second transistor is used to receive the second power supply voltage.

[0037] The second terminal of the first transistor and the second terminal of the second transistor are both coupled to the output terminal of the inverter.

[0038] In some possible implementations, the first transistor is an N-type transistor and the second transistor is a P-type transistor;

[0039] The first preset voltage is the threshold voltage of the first transistor, and the second preset voltage is the absolute value of the threshold voltage of the second transistor.

[0040] In some possible implementations, the number of delay improvement circuits is multiple, and the number of inverters in at least two of the delay improvement circuits is different, or the number of inverters in at least two of the delay improvement circuits is the same.

[0041] This disclosure also provides an ultrasonic detection panel, including a plurality of the ultrasonic pixel circuits described above.

[0042] In some possible implementations, the ultrasonic detection panel includes multiple first power voltage lines for transmitting a first power voltage.

[0043] The delay improvement circuit in a row of ultrasonic pixel circuits is coupled to a first power supply voltage line, or...

[0044] The delay improvement circuit in a series of ultrasonic pixel circuits is coupled to a first power supply voltage line.

[0045] In some possible implementations, the ultrasonic detection panel includes multiple second power supply voltage lines for transmitting a second power supply voltage.

[0046] The delay improvement circuit in a row of ultrasonic pixel circuits is coupled to a second power supply voltage line, or...

[0047] The delay improvement circuit in a series of ultrasonic pixel circuits is coupled to a second power supply voltage line.

[0048] This disclosure also provides a driving method for the above-described ultrasonic pixel circuit, wherein the ultrasonic pixel circuit includes an ultrasonic detection circuit and a delay improvement circuit, the delay improvement circuit being coupled between a driving signal terminal and the ultrasonic detection circuit, and the driving method includes:

[0049] The delay improvement circuit responds to the signal at the drive signal terminal by reducing the duration of the rising and falling edges of the signal at the drive signal terminal before outputting it to the ultrasonic detection circuit.

[0050] The ultrasonic detection circuit performs ultrasonic detection in response to the received signal.

[0051] This disclosure also provides an ultrasonic imaging apparatus, including the ultrasonic detection panel described above. Attached Figure Description

[0052] Figure 1 shows some structural schematic diagrams of ultrasonic pixel circuits in related technologies;

[0053] Figures 2, 3, 4A to 4G, 5A to 5B, 10, 12, 14, and 16 are schematic diagrams of some structures of the ultrasonic pixel circuit provided in the embodiments of this disclosure.

[0054] Figures 6, 8, 11, 13, 15, and 17 are some signal timing diagrams of the ultrasonic pixel circuit provided in the embodiments of this disclosure;

[0055] Figures 7 and 9 are schematic diagrams showing the voltage variation relationship between the input signal and the output signal of the delay improvement circuit provided in the embodiments of this disclosure;

[0056] Figures 18 to 20 are some structural schematic diagrams of the ultrasonic testing panel provided in the embodiments of this disclosure. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0058] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0059] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual scale and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals are used throughout to denote the same or similar elements or elements having the same or similar functions.

[0060] Typically, an ultrasonic detection panel includes multiple pixels, each pixel comprising an ultrasonic pixel circuit. For example, the ultrasonic pixel circuit may include a switching transistor, a storage capacitor, and an ultrasonic sensing unit, as shown in Figure 1. Typically, the control terminal of the switching transistor receives a control signal via a signal line. However, the RC (resistor-capacitor) delay on the signal line causes a delay in the level switching of the control signal, resulting in the switching transistor not being able to turn on and off in a timely manner, thus affecting the acquisition accuracy of the ultrasonic pixel circuit.

[0061] To address the aforementioned issues, the ultrasonic pixel circuit provided in this embodiment improves the acquisition accuracy of the ultrasonic pixel circuit by incorporating a delay improvement circuit.

[0062] The ultrasonic pixel circuit provided in this embodiment of the present disclosure, as shown in FIG2, includes: an ultrasonic detection circuit 1 and a delay improvement circuit 2.

[0063] The delay improvement circuit 2 is coupled between the drive signal terminal Gate_F and the ultrasonic detection circuit 1. It is configured to reduce the duration of the rising and falling edges of the signal at the drive signal terminal Gate_F before outputting to the ultrasonic detection circuit 1.

[0064] The ultrasonic detection circuit 1 is configured to perform ultrasonic detection in response to a received signal.

[0065] The ultrasonic pixel circuit provided in this embodiment improves the acquisition accuracy of the ultrasonic pixel circuit by setting a delay improvement circuit between the drive signal terminal and the ultrasonic detection circuit, thereby reducing the delay phenomenon of level reversal of the control signal input to the ultrasonic pixel circuit.

[0066] For example, as shown in FIG3, the delay improvement circuit 2 includes n cascaded inverters 20, where n is an integer not less than 1;

[0067] The first power supply terminal of each stage inverter 20 is used to receive the first power supply voltage Vss, and the second power supply terminal of each stage inverter 20 is used to receive the second power supply voltage Vdd.

[0068] The input terminal of the first-stage inverter 20 is coupled to the drive signal terminal Gate_F;

[0069] Except for the last stage inverter 20, the output terminal of the previous stage inverter 20 in two adjacent stages is coupled to the input terminal of the next stage inverter 20.

[0070] The output of the final stage inverter 20 is coupled to the ultrasonic detection circuit 1.

[0071] For example, as shown in FIG3, the delay improvement circuit 2 reduces the duration of the rising and falling edges of the signal at the drive signal terminal Gate_F in a manner proportional to the number of inverters 20 in the delay improvement circuit 2.

[0072] The more inverters 20 in the delay improvement circuit 2, the longer the rising and falling edges of the signal at the Gate_F drive signal terminal will be in the delay improvement circuit 2. Conversely, the fewer inverters 20 in the delay improvement circuit 2, the shorter the rising and falling edges of the signal at the Gate_F drive signal terminal will be in the delay improvement circuit 2.

[0073] For example, as shown in Figures 4A to 4G, the ultrasonic detection circuit 1 may include a reset circuit 11, an ultrasonic sensing unit 12, a detection circuit 13, a storage circuit 14, and a reading circuit 15, wherein the first end of the ultrasonic sensing unit 12 is coupled to the reset circuit 11 and the detection circuit 13, respectively, and the detection circuit 13, the storage circuit 14, and the reading circuit 15 are coupled to the first node N1.

[0074] Medical ultrasound imaging typically uses linear array probes and single-frequency scanning, but its detection depth and resolution are often limited. Large-area two-dimensional detector arrays, however, can significantly increase the amount of information detected, and through two-dimensional imaging, can improve detection depth and resolution.

[0075] Ultrasonic imaging typically uses frequencies of 2MHz to 20MHz. Higher frequencies result in higher imaging accuracy. Therefore, pixels used for ultrasonic detection usually need to acquire high-frequency signals of 2MHz to 20MHz, corresponding to periods of 500ns to 50ns. Acquiring signals within such a short time requires pixels to achieve nanosecond-level on / off speeds. However, for large-area pixel arrays, the long traces and millions of pixels result in large capacitive and resistive loads on the signal lines driving the pixels. This leads to longer rise and fall times for the input signal, reaching hundreds of nanoseconds or even microseconds. Consequently, the on and off times of the reset circuit 11 are delayed, and the on and off speeds become slower. This prevents the detection circuit 13 from effectively capturing waveforms within a portion of the ultrasonic signal period (tens to hundreds of nanoseconds per period).

[0076] To address the aforementioned issues, a delay improvement circuit is installed between the reset circuit and the reset control terminal. This circuit shortens the rise and fall times of the signal input to the reset circuit, enabling the reset circuit to turn on and off promptly, thereby improving the ultrasonic signal acquisition capability.

[0077] For example, as shown in FIG4A, the ultrasonic detection circuit 1 includes: a reset circuit 11 and an ultrasonic sensing unit 12, wherein the reset circuit 11 is coupled to the first end of the ultrasonic sensing unit 12.

[0078] Delay improvement circuit 2 includes a first delay improvement circuit 21;

[0079] The drive signal terminal Gate_F includes a reset control terminal Gate_F1, and the first delay improvement circuit 21 is coupled between the reset control terminal Gate_F1 and the reset circuit 11.

[0080] For example, as shown in FIG4A, the first delay improvement circuit 21 is configured to: output a first power supply voltage Vss to the reset circuit 11 in response to a high-level signal in the signal of the reset control terminal Gate_F1; and output a second power supply voltage Vdd to the reset circuit 11 in response to a low-level signal in the signal of the reset control terminal Gate_F1.

[0081] Specifically, the voltage of the low-level signal in the reset control terminal Gate_F1 is less than the sum of the low voltages in the first power supply voltage Vss and the second power supply voltage Vdd and the first preset voltage, and the voltage of the high-level signal in the reset control terminal Gate_F1 is greater than the difference between the high voltages in the first power supply voltage Vss and the second power supply voltage Vdd and the second preset voltage.

[0082] For example, if the first power supply voltage Vss is less than the second power supply voltage Vdd, then the voltage of the low-level signal in the reset control terminal Gate_F1 is less than the sum of the first power supply voltage Vss and the first preset voltage, and the voltage of the high-level signal in the reset control terminal Gate_F1 is greater than the difference between the second power supply voltage Vdd and the second preset voltage.

[0083] For example, if the first power supply voltage Vss is greater than the second power supply voltage Vdd, then the voltage of the low-level signal in the reset control terminal Gate_F1 is less than the sum of the second power supply voltage Vdd and the first preset voltage, and the voltage of the high-level signal in the reset control terminal Gate_F1 is greater than the difference between the first power supply voltage Vss and the second preset voltage.

[0084] For example, as shown in FIG4A, the number of inverters 20 in the first delay improvement circuit 21 is an odd number, and the first power supply voltage Vss is less than the second power supply voltage Vdd; or,

[0085] The number of inverters 20 in the first delay improvement circuit 21 is even, and the first power supply voltage Vss is greater than the second power supply voltage Vdd.

[0086] For example, as shown in Figures 4B and 4C, the ultrasonic detection circuit 1 includes: a detection circuit 13 and an ultrasonic sensing unit 12, wherein the detection circuit 13 is coupled between the first end of the ultrasonic sensing unit 12 and the first node N1.

[0087] Delay improvement circuit 2 includes a second delay improvement circuit 22;

[0088] The drive signal terminal Gate_F includes the detection control terminal Gate_F2, and the second delay improvement circuit 22 is coupled between the detection control terminal Gate_F2 and the detection circuit 13.

[0089] For example, as shown in Figures 4B and 4C, the second delay improvement circuit 22 is configured to: output the first power supply voltage Vss to the detection circuit 13 in response to a high-level signal in the signal of the detection control terminal Gate_F2; and output the second power supply voltage Vdd to the detection circuit 13 in response to a low-level signal in the signal of the detection control terminal Gate_F2.

[0090] Specifically, the voltage of the low-level signal in the detection control terminal Gate_F2 is less than the sum of the low voltage in the first power supply voltage Vss and the second power supply voltage Vdd and the first preset voltage, and the voltage of the high-level signal in the detection control terminal Gate_F2 is greater than the difference between the high voltage in the first power supply voltage Vss and the second power supply voltage Vdd and the second preset voltage.

[0091] For example, if the first power supply voltage Vss is less than the second power supply voltage Vdd, then the voltage of the low-level signal in the signal of the detection control terminal Gate_F2 is less than the sum of the first power supply voltage Vss and the first preset voltage, and the voltage of the high-level signal in the signal of the detection control terminal Gate_F2 is greater than the difference between the second power supply voltage Vdd and the second preset voltage.

[0092] For example, if the first power supply voltage Vss is greater than the second power supply voltage Vdd, then the voltage of the low-level signal in the signal of the detection control terminal Gate_F2 is less than the sum of the second power supply voltage Vdd and the first preset voltage, and the voltage of the high-level signal in the signal of the detection control terminal Gate_F2 is greater than the difference between the first power supply voltage Vss and the second preset voltage.

[0093] For example, as shown in Figures 4B and 4C, the number of inverters 20 in the second delay improvement circuit 22 is an odd number, and the first power supply voltage Vss is less than the second power supply voltage Vdd; or,

[0094] The number of inverters 20 in the second delay improvement circuit 22 is even, and the first power supply voltage Vss is greater than the second power supply voltage Vdd.

[0095] For example, as shown in Figures 4D to 4G, the ultrasonic detection circuit 1 includes: a detection circuit 13, a storage circuit 14, and a reading circuit 15 coupled to the first node N1;

[0096] Delay improvement circuit 2 includes a third delay improvement circuit 23;

[0097] The drive signal terminal Gate_F includes the read control terminal Gate_F3, and the third delay improvement circuit 23 is coupled between the read control terminal Gate_F3 and the read circuit 15.

[0098] For example, as shown in Figures 4D to 4G, the third delay improvement circuit 23 is configured to: output a first power supply voltage Vss to the read circuit 15 in response to a high-level signal in the read control terminal Gate_F3; and output a second power supply voltage Vdd to the read circuit 15 in response to a low-level signal in the read control terminal Gate_F3.

[0099] Wherein, the voltage of the low-level signal in the signal of the read control terminal Gate_F3 is less than the sum of the low voltage in the first power supply voltage Vss and the second power supply voltage Vdd and the first preset voltage, and the voltage of the high-level signal in the signal of the read control terminal Gate_F3 is greater than the difference between the high voltage in the first power supply voltage Vss and the second power supply voltage Vdd and the second preset voltage.

[0100] For example, if the first power supply voltage Vss is less than the second power supply voltage Vdd, then the voltage of the low-level signal in the signal of the control terminal Gate_F3 is less than the sum of the first power supply voltage Vss and the first preset voltage, and the voltage of the high-level signal in the signal of the control terminal Gate_F3 is greater than the difference between the second power supply voltage Vdd and the second preset voltage.

[0101] For example, if the first power supply voltage Vss is greater than the second power supply voltage Vdd, then the voltage of the low-level signal in the signal of the control terminal Gate_F3 is less than the sum of the second power supply voltage Vdd and the first preset voltage, and the voltage of the high-level signal in the signal of the control terminal Gate_F3 is greater than the difference between the first power supply voltage Vss and the second preset voltage.

[0102] For example, as shown in Figures 4D to 4G, the number of inverters 20 in the third delay improvement circuit 23 is an odd number, and the first power supply voltage Vss is less than the second power supply voltage Vdd; or,

[0103] The number of inverters 20 in the third delay improvement circuit 23 is even, and the first power supply voltage Vss is greater than the second power supply voltage Vdd.

[0104] For example, as shown in Figures 4C, 4E, 4F, and 4G, there are multiple delay improvement circuits 2, and the number of inverters 20 in at least two delay improvement circuits 2 is different, or the number of inverters 20 in at least two delay improvement circuits 2 is the same.

[0105] For example, as shown in FIG4C, the delay improvement circuit 2 includes a first delay improvement circuit 21 and a second delay improvement circuit 22. The drive signal terminal Gate_F includes a reset control terminal Gate_F1 and a detection control terminal Gate_F2. The number of inverters in the first delay improvement circuit 21 can be the same as the number of inverters in the second delay improvement circuit 22. Of course, the number of inverters in the first delay improvement circuit 21 can also be different from the number of inverters in the second delay improvement circuit 22.

[0106] For example, as shown in FIG4E, the delay improvement circuit 2 includes a first delay improvement circuit 21 and a third delay improvement circuit 23, and the drive signal terminal Gate_F includes a reset control terminal Gate_F1 and a read control terminal Gate_F3. The number of inverters in the first delay improvement circuit 21 can be the same as the number of inverters in the third delay improvement circuit 23. Of course, the number of inverters in the first delay improvement circuit 21 can also be different from the number of inverters in the third delay improvement circuit 23.

[0107] For example, as shown in FIG4F, the delay improvement circuit 2 includes a second delay improvement circuit 22 and a third delay improvement circuit 23, and the drive signal terminal Gate_F includes a detection control terminal Gate_F2 and a read control terminal Gate_F3. The number of inverters in the second delay improvement circuit 22 can be the same as the number of inverters in the third delay improvement circuit 23. Of course, the number of inverters in the second delay improvement circuit 22 can also be different from the number of inverters in the third delay improvement circuit 23.

[0108] For example, as shown in Figure 4G, the delay improvement circuit 2 includes a first delay improvement circuit 21, a second delay improvement circuit 22, and a third delay improvement circuit 23. The drive signal terminal Gate_F includes a reset control terminal Gate_F1, a detection control terminal Gate_F2, and a read control terminal Gate_F3. The number of inverters in the first delay improvement circuit 21, the second delay improvement circuit 22, and the third delay improvement circuit 23 can be different, partially the same, or the same.

[0109] For example, the first power supply voltage Vss received by at least two delay improvement circuits 2 is output from the same first power supply voltage line.

[0110] For example, as shown in FIG4G, the first power supply voltage Vss received by the first delay improvement circuit 21 and the first power supply voltage Vss received by the second delay improvement circuit 22 are output from the same first power supply voltage line. Of course, the first power supply voltage Vss received by the first delay improvement circuit 21 and the first power supply voltage Vss received by the second delay improvement circuit 22 can also be output from different first power supply voltage lines.

[0111] For example, the second power supply voltage Vdd received by at least two delay improvement circuits 2 is output from the same second power supply voltage line.

[0112] For example, as shown in FIG4G, the second power supply voltage Vdd received by the first delay improvement circuit 21 and the second power supply voltage Vdd received by the second delay improvement circuit 22 are output from the same second power supply voltage line. Of course, the second power supply voltage Vdd received by the first delay improvement circuit 21 and the second power supply voltage Vdd received by the second delay improvement circuit 22 can also be output from different second power supply voltage lines.

[0113] For example, as shown in Figures 5A and 5B, the first delay improvement circuit 21 may include an inverter 20, and may also include two cascaded inverters 20.

[0114] For example, as shown in Figures 5A and 5B, the inverter 20 includes a first transistor T1 and a second transistor T2;

[0115] The control terminals of the first transistor T1 and the second transistor T2 are both coupled to the input terminal of the inverter 20.

[0116] The first terminal of the first transistor T1 is used to receive the first power supply voltage Vss, and the first terminal of the second transistor T2 is used to receive the second power supply voltage Vdd.

[0117] The second terminal of the first transistor T1 and the second terminal of the second transistor T2 are both coupled to the output terminal of the inverter 20.

[0118] For example, as shown in Figures 5A and 5B, the first transistor T1 is an N-type transistor and the second transistor T2 is a P-type transistor;

[0119] The first preset voltage is the threshold voltage of the first transistor T1, and the second preset voltage is the absolute value of the threshold voltage of the second transistor T2.

[0120] For example, the first power supply voltage Vss is less than the second power supply voltage Vdd, the voltage of the low-level signal in the reset control terminal Gate_F1 is less than the sum of the first power supply voltage Vss and the threshold voltage of the first transistor T1, and the voltage of the high-level signal in the reset control terminal Gate_F1 is greater than the absolute difference between the second power supply voltage Vdd and the threshold voltage of the second transistor T2.

[0121] For example, as shown in Figures 5A and 5B, the reset circuit 11 may include a first switching transistor M1, the detection circuit 13 may include a second switching transistor M2, the storage circuit 14 may include a storage capacitor C1, and the read circuit 15 may include a third switching transistor M3 and a fourth switching transistor M4.

[0122] As shown in Figures 5A and 5B, the input terminal of the first delay improvement circuit 21 is coupled to the reset control terminal Gate_F1, the control terminal of the first switching transistor M1 is coupled to the output terminal of the first delay improvement circuit 21, the first terminal of the first switching transistor M1 is coupled to the first signal terminal V1, and the second terminal of the first switching transistor M1 is coupled to the first terminal of the ultrasonic sensing unit 12; the control terminal of the second switching transistor M2 is coupled to the detection control terminal Gate_F2, the first terminal of the second switching transistor M2 is coupled to the first terminal of the ultrasonic sensing unit 12, and the second terminal of the second switching transistor M2 is coupled to the first node N1; the control terminal of the third switching transistor M3 is coupled to the first node N1, the first terminal of the third switching transistor M3 is coupled to the second signal terminal V2, and the second terminal of the third switching transistor M3 is coupled to the first terminal of the fourth switching transistor M4; the control terminal of the fourth switching transistor M4 is coupled to the readout control terminal Gate_F3, and the second terminal of the fourth switching transistor M4 is coupled to the output terminal R.

[0123] For example, as shown in Figures 5A and 5B, the first transistor T1 can be an N-type transistor, and its manufacturing materials include low-temperature polycrystalline silicon, oxide, amorphous silicon, silicon-based materials and other semiconductor materials; the second transistor T2 can be a P-type transistor, and its manufacturing materials include low-temperature polycrystalline silicon, silicon-based materials and other semiconductor materials; the manufacturing materials of each switching transistor M1, M2, M3, M4 include low-temperature polycrystalline silicon, oxide, amorphous silicon, silicon-based materials and other semiconductor materials.

[0124] The signals received by the reset control terminal, the detection control terminal, and the read control terminal are adjusted accordingly based on the type of transistor and the parity of the number of inverters in the delay improvement circuit. For example, as shown in Figures 5A and 5B, the first switching transistor M1 is an N-type transistor, and the first power supply voltage Vss is less than the second power supply voltage Vdd. When no delay improvement circuit is provided between the reset control terminal Gate_F1 and the reset circuit 11, the first switching transistor M1 is turned on when the signal at the reset control terminal Gate_F1 is high, and turned off when the signal received at the reset control terminal Gate_F1 is low. A first delay improvement circuit 21 is provided between the reset control terminal Gate_F1 and the reset circuit 11, and the inverters in the first delay improvement circuit 21... When the number of inverters is odd, and the signal at the reset control terminal Gate_F1 is high, the first delay improvement circuit 21 outputs the first power supply voltage Vss, and the first switching transistor M1 is turned off; when the signal at the reset control terminal Gate_F1 is low, the first delay improvement circuit 21 outputs the second power supply voltage Vdd, and the first switching transistor M1 is turned on. That is, when a delay improvement circuit including an odd number of inverters is set between the reset control terminal and the detection circuit, the original signal input to the reset control terminal needs to be adjusted by, for example, a timing controller, in order to control the first switching transistor M1 to turn on or off.

[0125] For example, as shown in Figures 5A and 5B, the first switching transistor M1 is an N-type transistor, and the voltage of the signal provided by the first signal terminal V1 is positive. Of course, the first switching transistor M1 can also be a P-type transistor, and the voltage of the signal provided by the first signal terminal V1 is negative.

[0126] For example, as shown in Figures 5A and 5B, the third switching transistor M3 is an N-type transistor, and the voltage of the signal provided by the second signal terminal V2 is positive. Of course, the third switching transistor M3 can also be a P-type transistor, and the voltage of the signal provided by the second signal terminal V2 is negative.

[0127] The working process of the ultrasonic pixel circuit provided in this embodiment of the present disclosure is described below using the ultrasonic pixel circuit shown in Figure 5A as an example and in conjunction with the signal timing diagram shown in Figure 6. In this case, the first power supply voltage Vss is less than the second power supply voltage Vdd.

[0128] Specifically, the reset phase t1, detection phase t2, hold phase t3, and readout phase t4 are selected from the signal timing diagram shown in Figure 6. It should be noted that the signal timing diagram shown in Figure 6 only represents the operation of a single ultrasonic pixel circuit within one frame. The operation of this ultrasonic pixel circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0129] During the reset phase t1, the signal gate1 of the reset control terminal Gate_F1 is low, the signal gate2 of the detection control terminal Gate_F2 is high, and the signal gate3 of the read control terminal Gate_F3 is low.

[0130] The first delay improvement circuit 21 responds to the signal gate1 of the reset control terminal Gate_F1 and provides the second power supply voltage Vdd to the output terminal VA, and the output terminal VA outputs the second power supply voltage Vdd; the first switching transistor M1 is turned on under the control of the second power supply voltage Vdd, and the second switching transistor M2 is turned on under the control of the signal gate2 of the detection control terminal Gate_F2. The turned-on first switching transistor M1 and second switching transistor M2 provide the signal of the first signal terminal V1 to the first node N1 to reset the first node N1.

[0131] During detection phase t2, the signal gate1 of the reset control terminal Gate_F1 switches from low level to high level at the peak of the ultrasonic signal, the signal gate2 of the detection control terminal Gate_F2 switches from high level to low level at the trough of the ultrasonic signal, and the signal gate3 of the read control terminal Gate_F3 is low level.

[0132] The first delay improvement circuit 21 responds to the signal gate1 of the reset control terminal Gate_F1 and provides the first power supply voltage Vss to the output terminal VA. The output terminal VA outputs the first power supply voltage Vss. The first switching transistor M1 is turned off under the control of the first power supply voltage Vss. The second switching transistor M2 is kept on under the control of the signal gate2 of the detection control terminal Gate_F2 and provides the electrical signal output from the first terminal of the ultrasonic sensing unit 12 to the first node N1.

[0133] Due to the time delay effect of the first delay improvement circuit 21, the timing of the signal gate1 of the reset control terminal Gate_F1 can be compensated accordingly to ensure that the signal output by the first delay improvement circuit 21 switches from low level to high level at the peak of the ultrasonic signal.

[0134] During the holding phase t3, the gate1 signal of the reset control terminal Gate_F1 is high, the gate2 signal of the detection control terminal Gate_F2 is low, and the gate3 signal of the read control terminal Gate_F3 is low.

[0135] The first delay improvement circuit 21 responds to the signal gate1 of the reset control terminal Gate_F1 and provides the first power supply voltage Vss to the output terminal VA. The output terminal VA outputs the first power supply voltage Vss. The first switching transistor M1 is turned off under the control of the first power supply voltage Vss. The second switching transistor M2 is turned off under the control of the signal gate2 of the detection control terminal Gate_F2. The third switching transistor M3 is turned off under the control of the signal of the first node N1. The fourth switching transistor M4 is turned off under the control of the signal gate3 of the read control terminal Gate_F3.

[0136] During the reading phase t4, the gate1 signal of the reset control terminal Gate_F1 is high, the gate2 signal of the detection control terminal Gate_F2 is low, and the gate3 signal of the reading control terminal Gate_F3 is high.

[0137] The first delay improvement circuit 21 responds to the signal gate1 of the reset control terminal Gate_F1, providing the first power supply voltage Vss to the output terminal VA. The output terminal VA outputs the first power supply voltage Vss. The first switching transistor M1 is turned off under the control of the first power supply voltage Vss. The second switching transistor M2 is turned off under the control of the signal gate2 of the detection control terminal Gate_F2. The third switching transistor M3 is turned on under the control of the signal of the first node N1, transmitting the signal of the second signal terminal V2 to the first terminal of the fourth switching transistor M4. The fourth switching transistor M4 is turned on under the control of the signal gate3 of the read control terminal Gate_F3, providing the signal of the second signal terminal V2 received at the first terminal to the output terminal R. The output terminal R outputs the detection signal.

[0138] As shown in Figure 6, at the beginning of the detection phase, the signal of the reset control terminal Gate_F1 switches from low level to high level, and the signal of the output terminal of the first delay improvement circuit 21 switches from high level to low level. The specific principle of the first delay improvement circuit 21 reducing the rising edge duration of the signal of the reset control terminal Gate_F1 will be explained below.

[0139] As shown in Figure 5A, the first transistor T1 is an N-type transistor. When Vgs1 - Vth1 > 0, the first transistor T1 is turned on; when Vgs1 - Vth1 < 0, the first transistor T1 is turned off. The second transistor T2 is a P-type transistor. When Vgs2 - Vth2 < 0, the second transistor T2 is turned on; when Vgs2 - Vth2 > 0, the second transistor T2 is turned off. Here, Vgs1 represents the gate-source voltage difference of the first transistor T1, Vgs2 represents the gate-source voltage difference of the second transistor T2, Vth1 represents the threshold voltage of the first transistor T1, and Vth2 represents the threshold voltage of the second transistor T2.

[0140] For the timing shown in Figure 6, the signal gate1 of the reset control terminal Gate_F1 switches from low level to high level at the peak of the ultrasonic signal. For example, if the voltage of gate1 is V, then when gate1 is at a low voltage, for example, when V is the first power supply voltage Vss, V < Vss + Vth1, that is, V - Vss - Vth1 < 0, the first transistor T1 is turned off, and at the same time V < Vdd + Vth2, that is, V - Vdd - Vth2 < 0, the second transistor T2 is turned on. At this time, the voltage Va of the signal output by the output terminal VA of the first delay improvement circuit 21 is the second power supply voltage Vdd, as shown in Figure 7.

[0141] When the voltage V of gate1 rises to Vss+Vth1<V<Vdd+Vth2 (i.e., Vdd-|Vth2|), that is, V-Vss-Vth1>0 and V-Vdd-Vth2<0, both the first transistor T1 and the second transistor T2 are turned on. At this time, the first power supply voltage Vss and the second power supply voltage Vdd are divided by the first transistor T1 and the second transistor T2. The voltage Va of the signal output by the output terminal VA of the first delay improvement circuit 21 is reduced to the voltage after the voltage division compared with the second power supply voltage Vdd. When V continues to rise to V>Vdd+Vth2, that is, V-Vdd-Vth2>0, the second transistor T2 is turned off. At the same time, V>Vss+Vth1, that is, V-Vss-Vth1>0, the first transistor T1 is still in the on state. At this time, the voltage Va of the signal output by VA is the first power supply voltage Vss, as shown in Figure 7.

[0142] The first transistor T1 and the second transistor T2 have very fast turn-on and turn-off response speeds, and the capacitance of the output terminal VA is only in the nF range. Therefore, the voltage change of the signal output from the output terminal VA is almost simultaneous with the switching of the first transistor T1 and the second transistor T2. During the process of the voltage V of gate1 rising from low, when V rises above Vss+Vth1, the first transistor T1 turns on, and the voltage of the signal output from the output terminal VA begins to be configured from the second power supply voltage Vdd to the first power supply voltage Vss. When V rises above Vdd+Vth2, the second transistor T2 turns off, and the voltage Va of the signal output from the output terminal VA completes the configuration from the second power supply voltage Vdd to the first power supply voltage Vss. Therefore, the time required for the signal at the output terminal VA of the first delay improvement circuit 21 to switch from high to low is less than the time required for the signal at the reset control terminal Gate_F1 to switch from low to high. That is, the first delay improvement circuit 21 reduces the rising edge duration of the signal at the reset control terminal Gate_F1, improving the delay phenomenon of the level flipping of the control signal input to the ultrasonic pixel circuit.

[0143] The working process of the ultrasonic pixel circuit provided in this embodiment of the present disclosure is described below using the ultrasonic pixel circuit shown in Figure 5B as an example and in conjunction with the signal timing diagram shown in Figure 8. In this case, the first power supply voltage Vss is less than the second power supply voltage Vdd.

[0144] Specifically, the reset phase t1, detection phase t2, hold phase t3, and readout phase t4 are selected from the signal timing diagram shown in Figure 8. It should be noted that the signal timing diagram shown in Figure 8 only represents the operation of a single ultrasonic pixel circuit within one frame. The operation of this ultrasonic pixel circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0145] During the reset phase t1, the signal gate1 of the reset control terminal Gate_F1 is high, the signal gate2 of the detection control terminal Gate_F2 is high, and the signal gate3 of the read control terminal Gate_F3 is low.

[0146] In the first delay improvement circuit 21, the first-stage inverter responds to the signal gate1 of the reset control terminal Gate_F1 and provides the first power supply voltage Vss to the output terminal VA1. The second-stage inverter responds to the signal at the output terminal VA1 and provides the second power supply voltage Vdd to the output terminal VA2. The output terminal VA2 outputs the second power supply voltage Vdd. The first switching transistor M1 is turned on under the control of the second power supply voltage Vdd. The second switching transistor M2 is turned on under the control of the signal gate2 of the detection control terminal Gate_F2. The turned-on first switching transistor M1 and second switching transistor M2 provide the signal at the first signal terminal V1 to the first node N1 to reset the first node N1.

[0147] During detection phase t2, the signal gate1 of the reset control terminal Gate_F1 switches from high level to low level at the peak of the ultrasonic signal, the signal gate2 of the detection control terminal Gate_F2 switches from high level to low level at the trough of the ultrasonic signal, and the signal gate3 of the read control terminal Gate_F3 is low level.

[0148] In the first delay improvement circuit 21, the first-stage inverter responds to the signal gate1 of the reset control terminal Gate_F1 and provides the second power supply voltage Vdd to the output terminal VA1. The second-stage inverter responds to the signal of the output terminal VA1 and provides the first power supply voltage Vss to the output terminal VA2. The output terminal VA2 outputs the first power supply voltage Vss. The first switching transistor M1 is turned off under the control of the first power supply voltage Vss. The second switching transistor M2 remains on under the control of the signal gate2 of the detection control terminal Gate_F2 and provides the electrical signal output from the first terminal of the ultrasonic sensing unit 12 to the first node N1.

[0149] During the holding phase t3, the gate1 signal of the reset control terminal Gate_F1 is low, the gate2 signal of the detection control terminal Gate_F2 is low, and the gate3 signal of the read control terminal Gate_F3 is low.

[0150] In the first delay improvement circuit 21, the first-stage inverter responds to the signal gate1 of the reset control terminal Gate_F1 and provides the second power supply voltage Vdd to the output terminal VA1. The second-stage inverter responds to the signal at the output terminal VA1 and provides the first power supply voltage Vss to the output terminal VA2. The output terminal VA2 outputs the first power supply voltage Vss. The first switching transistor M1 is turned off under the control of the first power supply voltage Vss. The second switching transistor M2 is turned off under the control of the signal gate2 of the detection control terminal Gate_F2. The third switching transistor M3 is turned off under the control of the signal at the first node N1. The fourth switching transistor M4 is turned off under the control of the signal gate3 of the read control terminal Gate_F3.

[0151] During the reading phase t4, the gate1 signal of the reset control terminal Gate_F1 is low, the gate2 signal of the detection control terminal Gate_F2 is low, and the gate3 signal of the reading control terminal Gate_F3 is high.

[0152] In the first delay improvement circuit 21, the first-stage inverter responds to the signal gate1 of the reset control terminal Gate_F1 and provides the second power supply voltage Vdd to the output terminal VA1. The second-stage inverter responds to the signal at the output terminal VA1 and provides the first power supply voltage Vss to the output terminal VA2. The output terminal VA2 outputs the first power supply voltage Vss. The first switching transistor M1 is turned off under the control of the first power supply voltage Vss. The second switching transistor M2 is turned off under the control of the signal gate2 of the detection control terminal Gate_F2. The third switching transistor M3 is turned on under the control of the signal at the first node N1 and transmits the signal at the second signal terminal V2 to the first terminal of the fourth switching transistor M4. The fourth switching transistor M4 is turned on under the control of the signal gate3 of the read control terminal Gate_F3 and provides the signal at the second signal terminal V2 received at the first terminal to the output terminal R. The output terminal R outputs the detection signal.

[0153] As shown in Figure 8, at the beginning of the detection phase, the signal of the reset control terminal Gate_F1 switches from high level to low level, and the signal of the output terminal of the first delay improvement circuit 21 switches from high level to low level. The following explains the specific principle of the first delay improvement circuit 21 reducing the duration of the falling edge of the signal of the reset control terminal Gate_F1.

[0154] As shown in Figure 5B, the first transistors T1 and T3 are N-type transistors. When Vgs1 - Vth1 > 0, the first transistors T1 and T3 are turned on; when Vgs1 - Vth1 < 0, the first transistors T1 and T3 are turned off. The second transistors T2 and T4 are P-type transistors. When Vgs2 - Vth2 < 0, the second transistors T2 and T4 are turned on; when Vgs2 - Vth2 > 0, the second transistors T2 and T4 are turned off. Here, Vgs1 represents the gate-source voltage difference of the first transistor, Vgs2 represents the gate-source voltage difference of the second transistor, Vth1 represents the threshold voltage of the first transistor, and Vth2 represents the threshold voltage of the second transistor.

[0155] For the timing shown in Figure 8, the signal gate1 of the reset control terminal Gate_F1 switches from high level to low level at the peak of the ultrasonic signal. For example, if the voltage of gate1 is V, then when gate1 is at a high voltage, for example, when V is the second power supply voltage Vdd, V>Vss+Vth1, that is, V-Vss-Vth1>0, the first transistor T1 is turned on. At the same time, V>Vdd+Vth2, that is, V-Vdd-Vth2>0, the second transistor T2 is turned off. At this time, the voltage Va1 of the signal output by the output terminal VA1 of the first delay improvement circuit 21 is the first power supply voltage Vss, as shown in Figure 9; Va1<Vss+Vth1, that is, Va1-Vss-Vth1<0, the first transistor T3 is turned off. At the same time, Va1<Vdd+Vth2, that is, Va1-Vdd-Vth2<0, the second transistor T4 is turned on. The voltage Va2 of the signal output by the output terminal VA2 of the first delay improvement circuit 21 is the second power supply voltage Vdd.

[0156] When V decreases to Vss+Vth1<V<Vdd+Vth2, i.e., V-Vss-Vth1>0 and V-Vdd-Vth2<0, both transistors T1 and T2 are turned on. At this time, the first power supply voltage Vss and the second power supply voltage Vdd are divided by transistors T1 and T2, and the voltage Va1 of the signal output at VA1 is increased to the voltage after the voltage division compared to the first power supply voltage Vss. When Va1<Vss+Vth1, i.e., Va1-Vss-Vth1<0, transistor T3 is turned off, and at the same time, Va1<Vdd+Vth2, i.e., Va1-Vdd-Vth2<0, transistor T4 is turned on. At this time, the voltage Va2 of the signal output at VA2 is still the second power supply voltage Vdd. When Va1 increases to Vss+Vth1... When th1 < Va1 < Vdd + Vth2, i.e., Va1 - Vss - Vth1 > 0 and Va1 - Vdd - Vth2 < 0, both the first transistor T3 and the second transistor T4 are turned on. The first power supply voltage Vss and the second power supply voltage Vdd are divided by the first transistor T3 and the second transistor T4. The voltage Va2 of the signal output at the output terminal VA2 is reduced to the voltage after the voltage division compared to the second power supply voltage Vdd. When Va1 continues to rise to Va1 > Vdd + Vth2, i.e., Va1 - Vdd - Vth2 > 0, the second transistor T4 is turned off. At the same time, Va1 > Vss + Vth1, i.e., Va1 - Vss - Vth1 > 0, the first transistor T3 is still in the conducting state. At this time, the voltage Va2 of the signal output at the output terminal VA2 is the first power supply voltage Vss, as shown in Figure 9.

[0157] When V continues to decrease to V < Vss + Vth1, that is, V - Vss - Vth1 < 0, the first transistor T1 is turned off. At the same time, V < Vdd + Vth2, that is, V - Vdd - Vth2 < 0, the second transistor T2 is still in the conducting state. At this time, the voltage Va1 of the signal output by the output terminal VA1 is the second power supply voltage Vdd, as shown in Figure 9.

[0158] During the transition from high to low level of gate1, when V drops below Vdd+Vth2, the second transistor T2 turns on, and the voltage Va1 of the signal output from VA1 begins to shift from the first power supply voltage Vss to the second power supply voltage Vdd. When V drops below Vss+Vth1, the first transistor T1 turns off, and the voltage Va1 of the signal output from VA1 completes the shift from the first power supply voltage Vss to the second power supply voltage Vdd, meaning the signal at output VA1 completes the transition from low to high level. When Va1 rises above Vss+Vth1, the first transistor T3 turns on, and the voltage of the signal output from VA2 begins to shift from the second power supply voltage Vdd to the first power supply voltage Vss. When Va1 rises above Vdd+Vth2, the second transistor T4 turns off, and the voltage Va2 of the signal output from VA2 completes the shift from the second power supply voltage Vdd to the first power supply voltage Vss, meaning the signal at output VA2 completes the transition from high to low level. Therefore, the time required for the signal output from the output terminal VA2 to switch from high level to low level is less than the time required for the signal output from the output terminal VA1 to switch from low level to high level. Conversely, the time required for the signal output from the output terminal VA1 to switch from low level to high level is less than the time required for the signal gate1 of the reset control terminal Gate_F1 to switch from high level to low level. In other words, the first delay improvement circuit 21 reduces the falling edge duration of the signal at the reset control terminal Gate_F. Furthermore, as the number of inverters in the first delay improvement circuit 21 increases, the rising and falling edge times of the signal input to the reset circuit 11 will be further shortened, as shown in Figure 9.

[0159] Figure 10 shows a schematic diagram of another ultrasonic pixel circuit provided in an embodiment of this application. Referring to Figure 10, this embodiment modifies the implementation of the structure shown in Figure 5A. The differences between this embodiment and the above embodiments are described below; the similarities are not repeated here.

[0160] For example, as shown in FIG10, the drive signal terminal further includes a read control terminal Gate_F2, and the delay improvement circuit 2 further includes a second delay improvement circuit 22 coupled between the read control terminal Gate_F2 and the read circuit 13. The output terminal VB of the second delay improvement circuit 22 is coupled to the control terminal of the second switching transistor M2; the second delay improvement circuit 22 includes an inverter.

[0161] The working process of the ultrasonic pixel circuit provided in this embodiment of the present disclosure is described below using the ultrasonic pixel circuit shown in Figure 10 as an example and in conjunction with the signal timing diagram shown in Figure 11. In this case, the first power supply voltage Vss is less than the second power supply voltage Vdd.

[0162] Specifically, the reset phase t1, detection phase t2, hold phase t3, and readout phase t4 are selected from the signal timing diagram shown in Figure 11. It should be noted that the signal timing diagram shown in Figure 11 only represents the operation of a single ultrasonic pixel circuit within one frame. The operation of this ultrasonic pixel circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0163] During the reset phase t1, the signal gate1 of the reset control terminal Gate_F1 is low, the signal gate2 of the detection control terminal Gate_F2 is low, and the signal gate3 of the read control terminal Gate_F3 is low.

[0164] The first delay improvement circuit 21 responds to the signal gate1 of the reset control terminal Gate_F1, providing the second power supply voltage Vdd to the output terminal VA, and the output terminal VA outputs the second power supply voltage Vdd; the second delay improvement circuit 22 responds to the signal gate2 of the detection control terminal Gate_F2, providing the second power supply voltage Vdd to the output terminal VB, and the output terminal VB outputs the second power supply voltage Vdd; the first switching transistor M1 and the second switching transistor M2 are respectively turned on under the control of the second power supply voltage Vdd, providing the signal of the first signal terminal V1 to the first node N1, resetting the first node N1.

[0165] During detection phase t2, the signal gate1 of the reset control terminal Gate_F1 switches from low level to high level at the peak of the ultrasonic signal, the signal gate2 of the detection control terminal Gate_F2 switches from low level to high level at the trough of the ultrasonic signal, and the signal gate3 of the read control terminal Gate_F3 is low level.

[0166] The first delay improvement circuit 21 responds to the signal gate1 of the reset control terminal Gate_F1 and provides the first power supply voltage Vss to the output terminal VA, and the output terminal VA outputs the first power supply voltage Vss; the second delay improvement circuit 22 responds to the signal gate2 of the detection control terminal Gate_F2 and provides the second power supply voltage Vdd to the output terminal VB, and the output terminal VB outputs the second power supply voltage Vdd; the first switching transistor M1 is turned off under the control of the first power supply voltage Vss, and the second switching transistor M2 remains on under the control of the second power supply voltage Vdd, providing the electrical signal output from the first terminal of the ultrasonic sensing unit 12 to the first node N1.

[0167] During the holding phase t3, the signal gate1 of the reset control terminal Gate_F1 is high, the signal gate2 of the detection control terminal Gate_F2 is high, and the signal gate3 of the read control terminal Gate_F3 is low.

[0168] The first delay improvement circuit 21 responds to the signal gate1 of the reset control terminal Gate_F1 and provides the first power supply voltage Vss to the output terminal VA, and the output terminal VA outputs the first power supply voltage Vss; the second delay improvement circuit 22 responds to the signal gate2 of the detection control terminal Gate_F2 and provides the first power supply voltage Vss to the output terminal VB, and the output terminal VB outputs the first power supply voltage Vss; the first switching transistor M1 and the second switching transistor M2 are turned off under the control of the first power supply voltage Vss, the third switching transistor M3 is turned off under the control of the signal of the first node N1, and the fourth switching transistor M4 is turned off under the control of the signal gate3 of the read control terminal Gate_F3.

[0169] During the reading phase t4, the gate1 signal of the reset control terminal Gate_F1 is high, the gate2 signal of the detection control terminal Gate_F2 is high, and the gate3 signal of the reading control terminal Gate_F3 is high.

[0170] The first delay improvement circuit 21 responds to the signal gate1 of the reset control terminal Gate_F1, providing the first power supply voltage Vss to the output terminal VA, and the output terminal VA outputs the first power supply voltage Vss; the second delay improvement circuit 22 responds to the signal gate2 of the detection control terminal Gate_F2, providing the first power supply voltage Vss to the output terminal VB, and the output terminal VB outputs the first power supply voltage Vss; the first switching transistor M1 and the second switching transistor M2 are turned off under the control of the first power supply voltage Vss, and the third switching transistor M3 is turned on under the control of the signal of the first node N1, transmitting the signal of the second signal terminal V2 to the first terminal of the fourth switching transistor M4; the fourth switching transistor M4 is turned on under the control of the signal gate3 of the read control terminal Gate_F3, providing the signal of the second signal terminal V2 received at the first terminal to the output terminal R, and the output terminal R outputs the detection signal.

[0171] Figure 12 shows a schematic diagram of another ultrasonic pixel circuit provided in an embodiment of this application. Referring to Figure 12, this embodiment modifies the implementation method of the embodiment shown in Figure 5B. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0172] As shown in Figure 12, the drive signal terminal also includes a detection control terminal Gate_F2, and the delay improvement circuit 2 also includes a second delay improvement circuit 22 coupled between the detection control terminal Gate_F2 and the detection circuit 13. The output terminal VB of the second delay improvement circuit 22 is coupled to the control terminal of the second switching transistor M2. The second delay improvement circuit 22 includes an inverter.

[0173] The working process of the ultrasonic pixel circuit provided in this embodiment of the present disclosure is described below using the ultrasonic pixel circuit shown in Figure 12 as an example and in conjunction with the signal timing diagram shown in Figure 13. In this case, the first power supply voltage Vss is less than the second power supply voltage Vdd.

[0174] During the reset phase t1, the signal gate1 of the reset control terminal Gate_F1 is at a high level, the signal gate2 of the detection control terminal Gate_F2 is at a low level, and the signal gate3 of the read control terminal Gate_F3 is at a low level.

[0175] In the first delay improvement circuit 21, the first-stage inverter responds to the signal gate1 of the reset control terminal Gate_F1 and provides the first power supply voltage Vss to the output terminal VA1. The second-stage inverter responds to the signal at the output terminal VA1 and provides the second power supply voltage Vdd to the output terminal VA2. The output terminal VA2 outputs the second power supply voltage Vdd. The second delay improvement circuit 22 responds to the signal gate2 of the detection control terminal Gate_F2 and provides the second power supply voltage Vdd to the output terminal VB. The output terminal VB outputs the second power supply voltage Vdd. The first switching transistor M1 and the second switching transistor M2 are turned on under the control of the second power supply voltage Vdd, respectively, and provide the signal at the first signal terminal V1 to the first node N1 to reset the first node N1.

[0176] During detection phase t2, the signal gate1 of the reset control terminal Gate_F1 switches from high level to low level at the peak of the ultrasonic signal, the signal gate2 of the detection control terminal Gate_F2 switches from low level to high level at the trough of the ultrasonic signal, and the signal gate3 of the read control terminal Gate_F3 is low level.

[0177] In the first delay improvement circuit 21, the first-stage inverter responds to the signal gate1 of the reset control terminal Gate_F1 and provides the second power supply voltage Vdd to the output terminal VA1. The second-stage inverter responds to the signal of the output terminal VA1 and provides the first power supply voltage Vss to the output terminal VA2. The output terminal VA2 outputs the first power supply voltage Vss. The second delay improvement circuit 22 responds to the signal gate2 of the detection control terminal Gate_F2 and provides the second power supply voltage Vdd to the output terminal VB. The output terminal VB outputs the second power supply voltage Vdd. The first switching transistor M1 is turned off under the control of the first power supply voltage Vss, and the second switching transistor M2 remains on under the control of the second power supply voltage Vdd, providing the electrical signal output from the first terminal of the ultrasonic sensing unit 12 to the first node N1.

[0178] During the holding phase t3, the gate1 signal of the reset control terminal Gate_F1 is low, the gate2 signal of the detection control terminal Gate_F2 is high, and the gate3 signal of the read control terminal Gate_F3 is low.

[0179] In the first delay improvement circuit 21, the first-stage inverter responds to the signal gate1 of the reset control terminal Gate_F1 and provides the second power supply voltage Vdd to the output terminal VA1. The second-stage inverter responds to the signal of the output terminal VA1 and provides the first power supply voltage Vss to the output terminal VA2. The output terminal VA2 outputs the first power supply voltage Vss. The second delay improvement circuit 22 responds to the signal gate2 of the detection control terminal Gate_F2 and provides the first power supply voltage Vss to the output terminal VB. The output terminal VB outputs the first power supply voltage Vss. The first switching transistor M1 and the second switching transistor M2 are turned off under the control of the first power supply voltage Vss. The third switching transistor M3 is turned off under the control of the signal of the first node N1. The fourth switching transistor M4 is turned off under the control of the signal gate3 of the read control terminal Gate_F3.

[0180] During the reading phase t4, the gate1 signal of the reset control terminal Gate_F1 is low, the gate2 signal of the detection control terminal Gate_F2 is high, and the gate3 signal of the reading control terminal Gate_F3 is high.

[0181] In the first delay improvement circuit 21, the first-stage inverter responds to the signal gate1 of the reset control terminal Gate_F1 and provides the second power supply voltage Vdd to the output terminal VA1. The second-stage inverter responds to the signal of the output terminal VA1 and provides the first power supply voltage Vss to the output terminal VA2. The output terminal VA2 outputs the first power supply voltage Vss. The second delay improvement circuit 22 responds to the signal gate2 of the detection control terminal Gate_F2 and provides the first power supply voltage Vss to the output terminal VB. The output terminal VB outputs the first power supply voltage Vss. The first switching transistor M1 and the second switching transistor M2 are turned off under the control of the first power supply voltage Vss. The third switching transistor M3 is turned on under the control of the signal of the first node N1 and transmits the signal of the second signal terminal V2 to the first terminal of the fourth switching transistor M4. The fourth switching transistor M4 is turned on under the control of the signal gate3 of the read control terminal Gate_F3 and provides the signal of the second signal terminal V2 received at the first terminal to the output terminal R. The output terminal R outputs the detection signal.

[0182] Figure 14 shows a schematic diagram of another ultrasonic pixel circuit provided in an embodiment of this application. Referring to Figure 14, this embodiment modifies the implementation method of the embodiment shown in Figure 5B. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated here.

[0183] As shown in Figure 14, the drive signal terminal also includes a detection control terminal Gate_F2, and the delay improvement circuit 2 also includes a second delay improvement circuit 22 coupled between the detection control terminal Gate_F2 and the detection circuit 13. The output terminal VB2 of the second delay improvement circuit 22 is coupled to the control terminal of the second switching transistor M2. The second delay improvement circuit 22 includes two stages of inverters.

[0184] The working process of the ultrasonic pixel circuit provided in this embodiment of the present disclosure is described below using the ultrasonic pixel circuit shown in Figure 14 as an example and in conjunction with the signal timing diagram shown in Figure 15. In this case, the first power supply voltage Vss is less than the second power supply voltage Vdd.

[0185] Specifically, the reset phase t1, detection phase t2, hold phase t3, and readout phase t4 are selected from the signal timing diagram shown in Figure 15. It should be noted that the signal timing diagram shown in Figure 15 only represents the operation of a single ultrasonic pixel circuit within one frame. The operation of this ultrasonic pixel circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0186] During the reset phase t1, the signal gate1 of the reset control terminal Gate_F1 is high, the signal gate2 of the detection control terminal Gate_F2 is high, and the signal gate3 of the read control terminal Gate_F3 is low.

[0187] The output terminal VA2 of the first delay improvement circuit 21 outputs the second power supply voltage Vdd, and the first switching transistor M1 is turned on under the control of the second power supply voltage Vdd; the output terminal VB2 of the second delay improvement circuit 22 outputs the second power supply voltage Vdd, and the second switching transistor M2 is turned on under the control of the second power supply voltage Vdd. The turned-on first switching transistor M1 and second switching transistor M2 provide the signal of the first signal terminal V1 to the first node N1, and reset the first node N1.

[0188] During detection phase t2, the signal gate1 of the reset control terminal Gate_F1 switches from high level to low level at the peak of the ultrasonic signal, the signal gate2 of the detection control terminal Gate_F2 switches from high level to low level at the trough of the ultrasonic signal, and the signal gate3 of the read control terminal Gate_F3 is low level.

[0189] The first delay improvement circuit 21 outputs a first power supply voltage Vss at its output terminal VA2, and the first switching transistor M1 is turned off under the control of the first power supply voltage Vss; the second delay improvement circuit 22 outputs a second power supply voltage Vdd at its output terminal VB2, and the second switching transistor M2 remains on under the control of the second power supply voltage Vdd, providing the electrical signal output from the first terminal of the ultrasonic sensing unit 12 to the first node N1.

[0190] During the holding phase t3, the gate1 signal of the reset control terminal Gate_F1 is low, the gate2 signal of the detection control terminal Gate_F2 is low, and the gate3 signal of the read control terminal Gate_F3 is low.

[0191] The first delay improvement circuit 21 outputs the first power supply voltage Vss at its output terminal VA2, and the first switching transistor M1 is turned off under the control of the first power supply voltage Vss; the second delay improvement circuit 22 outputs the first power supply voltage Vss at its output terminal VB2, and the second switching transistor M2 is turned off under the control of the first power supply voltage Vss; the third switching transistor M3 is turned off under the control of the signal of the first node N1; and the fourth switching transistor M4 is turned off under the control of the signal gate3 of the read control terminal Gate_F3.

[0192] During the reading phase t4, the gate1 signal of the reset control terminal Gate_F1 is low, the gate2 signal of the detection control terminal Gate_F2 is low, and the gate3 signal of the reading control terminal Gate_F3 is high.

[0193] The first delay improvement circuit 21 outputs the first power supply voltage Vss at its output terminal VA2, and the first switching transistor M1 is turned off under the control of the first power supply voltage Vss. The second delay improvement circuit 22 outputs the first power supply voltage Vss at its output terminal VB2, and the second switching transistor M2 is turned off under the control of the first power supply voltage Vss. The third switching transistor M3 is turned on under the control of the signal of the first node N1, transmitting the signal of the second signal terminal V2 to the first terminal of the fourth switching transistor M4. The fourth switching transistor M4 is turned on under the control of the signal gate3 of the read control terminal Gate_F3, providing the signal of the second signal terminal V2 received at the first terminal to the output terminal R. The output terminal R outputs a detection signal.

[0194] Figure 16 shows a schematic diagram of another ultrasonic pixel circuit provided in an embodiment of this application. Referring to Figure 16, this embodiment modifies the implementation method of the embodiment shown in Figure 5A. The differences between this embodiment and the above embodiments will be described below, while the similarities will not be repeated.

[0195] As shown in Figure 16, the drive signal terminal also includes a detection control terminal Gate_F2, and the delay improvement circuit also includes a second delay improvement circuit 22 coupled between the detection control terminal Gate_F2 and the detection circuit 13. The output terminal VB2 of the second delay improvement circuit 22 is coupled to the control terminal of the second switching transistor M2. The second delay improvement circuit 22 includes two stages of inverters.

[0196] The working process of the ultrasonic pixel circuit provided in this embodiment of the present disclosure is described below using the ultrasonic pixel circuit shown in Figure 16 as an example and in conjunction with the signal timing diagram shown in Figure 17. In this case, the first power supply voltage Vss is less than the second power supply voltage Vdd.

[0197] Specifically, the reset phase t1, detection phase t2, hold phase t3, and readout phase t4 are selected from the signal timing diagram shown in Figure 17. It should be noted that the signal timing diagram shown in Figure 17 only represents the operation of a single ultrasonic pixel circuit within one frame. The operation of this ultrasonic pixel circuit in other frames is basically the same as that in this frame, and will not be elaborated upon here.

[0198] During the reset phase t1, the signal gate1 of the reset control terminal Gate_F1 is low, the signal gate2 of the detection control terminal Gate_F2 is high, and the signal gate3 of the read control terminal Gate_F3 is low.

[0199] The output terminal VA of the first delay improvement circuit 21 outputs the second power supply voltage Vdd, and the first switching transistor M1 is turned on under the control of the second power supply voltage Vdd; the output terminal VB2 of the second delay improvement circuit 22 outputs the second power supply voltage Vdd, and the second switching transistor M2 is turned on under the control of the second power supply voltage Vdd. The turned-on first switching transistor M1 and second switching transistor M2 provide the signal of the first signal terminal V1 to the first node N1, and reset the first node N1.

[0200] During detection phase t2, the signal gate1 of the reset control terminal Gate_F1 switches from low level to high level at the peak of the ultrasonic signal, the signal gate2 of the detection control terminal Gate_F2 switches from high level to low level at the trough of the ultrasonic signal, and the signal gate3 of the read control terminal Gate_F3 is low level.

[0201] The first delay improvement circuit 21 outputs a first power supply voltage Vss at its output terminal VA, and the first switching transistor M1 is turned off under the control of the first power supply voltage Vss; the second delay improvement circuit 22 outputs a second power supply voltage Vdd at its output terminal VB2, and the second switching transistor M2 remains on under the control of the second power supply voltage Vdd, providing the electrical signal output from the first terminal of the ultrasonic sensing unit 12 to the first node N1.

[0202] During the holding phase t3, the gate1 signal of the reset control terminal Gate_F1 is high, the gate2 signal of the detection control terminal Gate_F2 is low, and the gate3 signal of the read control terminal Gate_F3 is low.

[0203] The first delay improvement circuit 21 outputs the first power supply voltage Vss at its output terminal VA, and the first switching transistor M1 is turned off under the control of the first power supply voltage Vss; the second delay improvement circuit 22 outputs the first power supply voltage Vss at its output terminal VB2, and the second switching transistor M2 is turned off under the control of the first power supply voltage Vss; the third switching transistor M3 is turned off under the control of the signal of the first node N1; and the fourth switching transistor M4 is turned off under the control of the signal gate3 of the read control terminal Gate_F3.

[0204] During the reading phase t4, the gate1 signal of the reset control terminal Gate_F1 is high, the gate2 signal of the detection control terminal Gate_F2 is low, and the gate3 signal of the reading control terminal Gate_F3 is high.

[0205] The first delay improvement circuit 21 outputs the first power supply voltage Vss at its output terminal VA, and the first switching transistor M1 is turned off under the control of the first power supply voltage Vss. The second delay improvement circuit 22 outputs the first power supply voltage Vss at its output terminal VB2, and the second switching transistor M2 is turned off under the control of the first power supply voltage Vss. The third switching transistor M3 is turned on under the control of the signal from the first node N1, transmitting the signal from the second signal terminal V2 to the first terminal of the fourth switching transistor M4. The fourth switching transistor M4 is turned on under the control of the signal gate3 from the read control terminal Gate_F3, providing the signal from the second signal terminal V2 received at the first terminal to the output terminal R. The output terminal R outputs a detection signal.

[0206] The difference in resistance and capacitance between the near and far ends of a large-area pixel array will cause differences in the rising and falling edge times of the signals received by the reset control terminal, detection control terminal, and read control terminal of the near and far ultrasonic pixel circuits. This will result in differences in the duration of the ultrasonic signal intercepted by the near and far ultrasonic pixel circuits, causing signal distortion.

[0207] To address the aforementioned issues, this disclosure also provides an ultrasonic detection panel, as shown in FIG18, which includes multiple ultrasonic pixel circuits (px) as described above. This panel can effectively improve the signal distortion problem caused by the difference in the timing of the rising and falling edges of the received signal at the near and far ends.

[0208] For example, as shown in FIG18, the ultrasonic detection panel includes multiple first power voltage lines VSS, which are used to transmit the first power voltage Vss.

[0209] The delay improvement circuit in a row of ultrasonic pixel circuits (px) is coupled to a first power supply voltage line (VSS), or...

[0210] The delay improvement circuit in a column of ultrasonic pixel circuits (px) is coupled to a first power supply voltage line (VSS) (not shown in the figure).

[0211] For example, as shown in FIG18, the ultrasonic detection panel includes multiple second power supply voltage lines VDD, which are used to transmit the second power supply voltage Vdd.

[0212] The delay improvement circuit in a single-row ultrasonic pixel circuit (px) is coupled to a second power supply voltage line VDD, or...

[0213] The delay improvement circuit in a column of ultrasonic pixel circuits (px) is coupled to a second power supply voltage line VDD (not shown in the figure).

[0214] Figure 19 shows a schematic diagram of another ultrasonic testing panel provided in an embodiment of this application. Referring to Figure 19, this embodiment modifies the implementation method of the embodiment shown in Figure 18. The differences between this embodiment and the above embodiments are described below, while the similarities are not repeated here.

[0215] As shown in Figure 19, the ultrasonic detection panel includes multiple control signal lines G1 and multiple control signal line traces L1. The multiple control signal lines G1 extend along the row direction, and the multiple control signal line traces L1 extend along the column direction. The control signal line traces L1 are coupled to the control signal lines G1 and are used to transmit the signals provided by the control signal lines G1. For example, the read control terminal in a column of ultrasonic pixel circuits is coupled to one control signal line trace L1. Of course, the multiple control signal lines G1 can also extend along the column direction, and the multiple control signal line traces L1 can also extend along the row direction. For example, the read control terminal in a row of ultrasonic pixel circuits is coupled to one control signal line trace L1.

[0216] Figure 20 shows a schematic diagram of another ultrasonic testing panel provided in an embodiment of this application. Referring to Figure 20, this embodiment modifies the implementation of the structure shown in Figure 18. The differences between this embodiment and the above embodiments are described below; the similarities are not repeated here.

[0217] As shown in Figure 20, the ultrasonic detection panel includes multiple ultrasonic pixel circuits as shown in Figure 5A. The ultrasonic detection panel may also include multiple readout control signal lines G3 and multiple readout lines R1. For example, the control terminal of the fourth switching transistor M4 in a row of ultrasonic pixel circuits is coupled to one readout control signal line G3; the second terminal of the fourth switching transistor M4 in a column of ultrasonic pixel circuits is coupled to one readout line R1.

[0218] This disclosure also provides an ultrasonic imaging device, which includes the ultrasonic detection panel described above.

[0219] This disclosure also provides a driving method for the ultrasonic pixel circuit shown in FIG2, including:

[0220] The delay improvement circuit 2 responds to the signal at the drive signal terminal Gate_F, reduces the duration of the rising and falling edges of the signal at the drive signal terminal Gate_F, and then outputs it to the ultrasonic detection circuit 1.

[0221] The ultrasonic detection circuit 1 performs ultrasonic detection in response to the received signal.

[0222] The driving method for the ultrasonic pixel circuit provided in this embodiment improves the delay phenomenon of level flipping of the control signal input to the ultrasonic pixel circuit by using a delay improvement circuit, so as to drive the corresponding circuit to turn on or off faster and improve the accuracy of ultrasonic signal acquisition.

[0223] The ultrasonic pixel circuit and driving method, and ultrasonic detection panel provided in this disclosure can improve the delay phenomenon of level flipping of the control signal input to the ultrasonic pixel circuit by using a delay improvement circuit, thereby improving the acquisition accuracy of the ultrasonic pixel circuit. It can also effectively improve the signal distortion problem caused by the difference in the time of the rising and falling edges of the received signal at near and far ends.

[0224] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0225] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, if these modifications and variations to the embodiments of this disclosure fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include these modifications and variations.

Claims

1. An ultrasonic pixel circuit, wherein, include: Ultrasonic detection circuit and delay improvement circuit; The delay improvement circuit is coupled between the drive signal terminal and the ultrasonic detection circuit, and is configured to reduce the duration of the rising and falling edges of the signal at the drive signal terminal before outputting it to the ultrasonic detection circuit. The ultrasonic detection circuit is configured to perform ultrasonic detection in response to a received signal.

2. The ultrasonic pixel circuit as described in claim 1, wherein, The delay improvement circuit includes n cascaded inverters, where n is an integer not less than 1; The first power supply terminal of each inverter is used to receive the first power supply voltage, and the second power supply terminal of each inverter is used to receive the second power supply voltage. The input terminal of the first-stage inverter is coupled to the drive signal terminal; Except for the last stage inverter, the output of the previous stage inverter in two adjacent stages is coupled to the input of the next stage inverter. The output of the final stage inverter is coupled to the ultrasonic detection circuit.

3. The ultrasonic pixel circuit as described in claim 2, wherein, The delay improvement circuit reduces the duration of the rising and falling edges of the signal at the drive signal terminal in a manner proportional to the number of inverters in the delay improvement circuit.

4. The ultrasonic pixel circuit as described in claim 2 or 3, wherein, The ultrasonic detection circuit includes: a reset circuit and an ultrasonic sensing unit, wherein the reset circuit is coupled to a first end of the ultrasonic sensing unit. The delay improvement circuit includes a first delay improvement circuit; The drive signal terminal includes a reset control terminal, and the first delay improvement circuit is coupled between the reset control terminal and the reset circuit.

5. The ultrasonic pixel circuit as described in claim 4, wherein, The first delay improvement circuit is configured to: output the first power supply voltage to the reset circuit in response to a high-level signal in the signal of the reset control terminal; and output the second power supply voltage to the reset circuit in response to a low-level signal in the signal of the reset control terminal. Wherein, the voltage of the low-level signal in the reset control terminal signal is less than the sum of the low voltage of the first power supply voltage and the second power supply voltage and the first preset voltage, and the voltage of the high-level signal in the reset control terminal signal is greater than the difference between the high voltage of the first power supply voltage and the second power supply voltage and the second preset voltage.

6. The ultrasonic pixel circuit as described in claim 5, wherein, The number of inverters in the first delay improvement circuit is odd, and the first power supply voltage is less than the second power supply voltage; or, The number of inverters in the first delay improvement circuit is even, and the first power supply voltage is greater than the second power supply voltage.

7. The ultrasonic pixel circuit according to any one of claims 2-6, wherein, The ultrasonic detection circuit includes: a detection circuit and an ultrasonic sensing unit, wherein the detection circuit is coupled between a first end and a first node of the ultrasonic sensing unit. The delay improvement circuit includes a second delay improvement circuit; The drive signal terminal includes a detection control terminal, and the second delay improvement circuit is coupled between the detection control terminal and the detection circuit.

8. The ultrasonic pixel circuit as described in claim 7, wherein, The second delay improvement circuit is configured to: output the first power supply voltage to the detection circuit in response to a high-level signal in the signal of the detection control terminal; and output the second power supply voltage to the detection circuit in response to a low-level signal in the signal of the detection control terminal. Wherein, the voltage of the low-level signal in the signal of the detection control terminal is less than the sum of the low voltage of the first power supply voltage and the second power supply voltage and the first preset voltage, and the voltage of the high-level signal in the signal of the detection control terminal is greater than the difference between the high voltage of the first power supply voltage and the second power supply voltage and the second preset voltage.

9. The ultrasonic pixel circuit as described in claim 8, wherein, The number of inverters in the second delay improvement circuit is odd, and the first power supply voltage is less than the second power supply voltage; or, The number of inverters in the second delay improvement circuit is even, and the first power supply voltage is greater than the second power supply voltage.

10. The ultrasonic pixel circuit according to any one of claims 2-9, wherein, The ultrasonic detection circuit includes: a detection circuit, a storage circuit, and a reading circuit coupled to the first node; The delay improvement circuit includes a third delay improvement circuit; The drive signal terminal includes a read control terminal, and the third delay improvement circuit is coupled between the read control terminal and the read circuit.

11. The ultrasonic pixel circuit as described in claim 10, wherein, The third delay improvement circuit is configured to output the first power supply voltage to the read circuit in response to a high-level signal in the signal of the read control terminal. In addition, in response to a low-level signal in the signal of the read control terminal, the second power supply voltage is output to the read circuit; Wherein, the voltage of the low-level signal in the signal of the reading control terminal is less than the sum of the low voltage of the first power supply voltage and the second power supply voltage and the first preset voltage, and the voltage of the high-level signal in the signal of the reading control terminal is greater than the difference between the high voltage of the first power supply voltage and the second power supply voltage and the second preset voltage.

12. The ultrasonic pixel circuit as described in claim 11, wherein, The number of inverters in the third delay improvement circuit is odd, and the first power supply voltage is less than the second power supply voltage; or... The number of inverters in the third delay improvement circuit is an even number, and the first power supply voltage is greater than the second power supply voltage.

13. The ultrasonic pixel circuit as described in any one of claims 5-6, 8-9, and 11-12, wherein, The inverter includes a first transistor and a second transistor; The control terminals of the first transistor and the second transistor are both coupled to the input terminal of the inverter. The first terminal of the first transistor is used to receive the first power supply voltage, and the first terminal of the second transistor is used to receive the second power supply voltage. The second terminal of the first transistor and the second terminal of the second transistor are both coupled to the output terminal of the inverter.

14. The ultrasonic pixel circuit as described in claim 13, wherein, The first transistor is an N-type transistor and the second transistor is a P-type transistor; The first preset voltage is the threshold voltage of the first transistor, and the second preset voltage is the absolute value of the threshold voltage of the second transistor.

15. The ultrasonic pixel circuit according to any one of claims 2-14, wherein, The delay improvement circuits may be multiple, with at least two delay improvement circuits having different numbers of inverters, or at least two delay improvement circuits having the same number of inverters.

16. An ultrasonic testing panel, wherein, It includes multiple ultrasonic pixel circuits as described in any one of claims 1-15.

17. The ultrasonic testing panel as claimed in claim 16, wherein, It includes multiple first power supply voltage lines, which are used to transmit the first power supply voltage; The delay improvement circuit in a row of ultrasonic pixel circuits is coupled to a first power supply voltage line, or... The delay improvement circuit in a series of ultrasonic pixel circuits is coupled to a first power supply voltage line.

18. The ultrasonic testing panel as claimed in claim 16, wherein, It includes multiple second power supply voltage lines, which are used to transmit the second power supply voltage; The delay improvement circuit in a row of ultrasonic pixel circuits is coupled to a second power supply voltage line, or... The delay improvement circuit in a series of ultrasonic pixel circuits is coupled to a second power supply voltage line.

19. A driving method for an ultrasonic pixel circuit as described in any one of claims 1-15, wherein, The ultrasonic pixel circuit includes an ultrasonic detection circuit and a delay improvement circuit, wherein the delay improvement circuit is coupled between the drive signal terminal and the ultrasonic detection circuit, and the driving method includes: The delay improvement circuit responds to the signal at the drive signal terminal by reducing the duration of the rising and falling edges of the signal at the drive signal terminal before outputting it to the ultrasonic detection circuit. The ultrasonic detection circuit performs ultrasonic detection in response to the received signal.

Images