A method for preparing a memory array

Abstract

The invention relates to a method for preparing a memory array (1) comprising a plurality of capacitors (SC) and a plurality of access transistor (AT) respectively associated to each other's. The method comprises depositing a mold oxide layer (MOL) on a receiving substrate (S), etching an exposed surface (MOL1) of the mold oxide layer (MOL) to form a plurality of holes extending through the mold oxide layer and forming bottom electrodes (BE) of the plurality of capacitors (SC) within the plurality of holes (H). The method further comprises transferring a semiconductor layer (SL) on contact portions (CP) of the bottom electrodes (BE) and patterning the semiconductor layer (SL) to define the plurality of access transistors (AT), wherein channels of the access transistors (AT) are in electrical contact with the contact portions (CP) of the bottom electrodes (BE).

Description

A method for preparing a memory arrayFIELD OF THE INVENTION

[0001] The present invention relates generally to the field of semiconductor memory devices, and more particularly, to methods for fabricating memory arrays, such as DRAM memory array, that include capacitors associated with access transistors.BACKGROUND OF THE INVENTION

[0002] Dynamic random-access memory (DRAM) devices play a crucial role in the electronics industry, especially in computers, where they are used to store data in binary form (1s and 0s) as electrical charge within storage capacitors. These devices are manufactured on semiconductor wafers, which are later divided into individual DRAM chips. Each chip comprises an array of memory cells, with each cell holding binary data in the form of charge stored on its capacitor. The process of storing and retrieving data is controlled by a single access transistor in each memory cell. This is a well-established technique, as illustrated in, whereby the gate of the access transistor AT is activated or deactivated by a word line signal WL to connect or disconnect the cell capacitor SC to a bit line BL.

[0003] Given the limited space available for capacitors within each memory cell, the challenge of integrating a large number of cells onto a single DRAM chip has driven the need for innovative solutions to increase capacitance without expanding the surface area occupied by each capacitor. One effective approach that has gained traction in recent years involves constructing capacitors vertically, stacking them over the access transistors. This vertical stacking allows to extend vertically the capacitor’s surface area and, in turn, its capacitance, while preserving the compact horizontal footprint on the substrate, allowing for more efficient use of space in densely packed DRAM chips.

[0004] Typically, as this is illustrated in US7161204, a bottom electrode of the capacitor is connected to the source or drain of the access transistor, while the top electrode and dielectric layer complete the capacitor structure.

[0005] The access electrode may be a planar transistor, as illustrated in the previously cited document. The access transistor may alternatively be a vertical transistor as illustrated in the publication of A. Yoo et al., "High-Performance Gate-all-around Junctionless Vertical-Channel Transistors with the Ultra-low Sub-threshold Swing for Next-generation 4F2 DRAM," 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109 / IEDM45741.2023.10413667.

[0006] In both instances, irrespective of whether the transistor is planar or vertical, the high aspect ratio capacitors are formed over a substrate comprising the previously formed access transistors. Each transistor's channel is electrically connected to a landing pad situated at the surface of the substrate. In order to accommodate the high aspect ratio of the capacitors, a layer of material, known as a "mold oxide layer," is deposited on the substrate. This layer has a thickness that is typically close to, or greater than, 1 micrometer. Etching processes, typically a high aspect ratio contact (HARC) etching process combined with photolithography patterning, are employed to create a plurality of holes extending through the mold oxide layer thickness to the landing pads. The bottom electrode is formed by depositing conductive material onto the holes' sidewalls and bottom, thus contacting the landing pad.

[0007] The HARC etching process must strike a balance between precision and speed. The creation of high aspect ratio structures can result in the formation of unwanted sidewall passivation, characterized by the accumulation of material on the sidewalls. The uniformity of the etching process, and the maintenance of profile accuracy (for example, the prevention of bowing or tapering of the walls) are common challenges associated with HARC etching. The misalignment of the bottom electrode with the landing pad inevitably results in the malfunction of the DRAM memory.

[0008] The document titled“Oxide-semiconductor Channel Transistor DRAM (OCTRAM) with 4F2 Architecture”by Shosuke Fujii et al., presented at IEDM in December 2024, introduces a DRAM array featuring InGaZnO (IGZO) vertical access transistors integrated atop a high-aspect-ratio capacitor using a capacitor-first process. While this approach may mitigate challenges associated with HARC etching, it comes with the drawback of reduced performance.

[0009] Oxide semiconductors like IGZO have significantly lower carrier mobility (approximately 10–50 cm² / V·s) compared to monocrystalline semiconductors like silicon (~1400 cm² / V·s), which is typically used as the channel material for access transistors. This reduced mobility limits the drive current of transistors in oxide-semiconductor-based devices, making them less suitable for high-speed applications such as DRAM.

[0010] Additionally, IGZO is usually amorphous or polycrystalline in nature. Efforts to enhance drive current, such as increasing the gate voltage, often exacerbate issues such as carrier scattering at grain boundaries or irregular atomic arrangements. These factors restrict carrier movement, causing increased channel resistance and reduced current conduction efficiency, especially under high electric fields.

[0011] Moreover, oxide semiconductors have lower thermal conductivity than silicon. During high-current operations, localized heating can occur, leading to performance degradation or even structural damage within the channel.

[0012] Document US20220199625 describes a method for fabricating a DRAM structure including vertically stacked capacitors and access transistors.OBJECT OF THE INVENTION

[0013] The present invention addresses the limitations of the prior art, specifically the challenges associated with high-aspect-ratio capacitor (HARC) etching, without compromising the performance of the memory array. More precisely, an object of the invention is to provide a method of preparing a memory array comprising a plurality of capacitors and a plurality of access transistor respectively associated with each other’s.SUMMARY OF THE INVENTION

[0014] To this effect, the invention relates to a method for preparing a memory array, the memory array comprising at least one bit line, at least one word line, a plurality of capacitors, and a plurality of access transistor, wherein each capacitor of the plurality of capacitors is respectively associated with an access transistor of the plurality of access transistors, each capacitor comprising a bottom electrode and a top electrode.

[0015] The method comprises:depositing a mold oxide layer on a receiving substrate, the mold oxide layer having an exposed surface;etching the exposed surface of the mold oxide layer to form a plurality of holes extending through the mold oxide layer;forming the bottom electrodes of the plurality of capacitors within the plurality of holes, each bottom electrode presenting a contact portion on the side of the exposed surface;transferring a semiconductor layer on the contact portions of the bottom electrodes;patterning the semiconductor layer to define the plurality of access transistors, wherein channels of the access transistors are in electrical contact with the contact portions of the bottom electrodes.

[0016] According to further non limitative features of the invention, either taken alone or in any technically feasible combination:the method further comprises removing the remaining portion of the mold oxide layer and subsequently forming a dielectric layer and a top electrode on each of the bottom electrodes to complete the capacitors;the completion of the capacitors is performed before the transfer of the semiconductor layer;the completion of the capacitors is performed after the transfer of the semiconductor layer;forming the bottom electrodes comprises forming a superficial contact pad;the method further comprises forming a silicide precursor layer onto the contact portions, before transferring the semiconductor layer;transferring the semiconductor layer comprises directly bonding the semiconductor layer to the silicide precursor layer;the semiconductor layer is initially supported by a handle substrate, and transferring the semiconductor layer comprises removing the handle substrate after bonding the semiconductor layer to the silicide precursor layer;patterning the semiconductor layer is carried out after transferring the semiconductor layer on the contact portions of the bottom electrodes;patterning the semiconductor layer comprises forming an array of semiconductor pillars, each semiconductor pillar being respectively positioned on a contact portion of a bottom electrode;patterning the semiconductor layer further comprises forming interconnected gate electrodes around selected semiconductor pillars, the interconnected gate electrodes being integrated within a word line of the memory array;the method further comprising forming the bit line over selected semiconductor pillars in the memory array;the semiconductor layer is monocrystalline;the semiconductor layer is made of silicon.

[0017] Many other features and advantages of the present invention will become apparent from reading the following detailed description, when considered in conjunction with the accompanying drawings, in which:

[0018] Figures 1 represents the general architecture of a DRAM memory cell;

[0019] Figures 2a,2b,2c respectively represents a top view, a cross sectional view across a bit line and a cross section view across a wordline of one embodiment of a memory array 1;

[0020]

[0021] Figures 3a,3b,3c,3d,3e,3f,3g,3h,3i,3i,3j,3k,3l,3m,3n,3o represent an embodiment of a process for preparing a memory array represented on,2b,2c.

[0022] DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION

[0023] The illustrations presented herein are not meant to be actual views of any particular semiconductor structure, device, system, or method, but are merely idealized representations that are used to describe embodiments of the disclosure.

[0024] Referring to Figures 2a, 2b, and 2c, a memory array 1 in one embodiment is arranged in a matrix configuration of memory cells distributed across a main plane (x, y). Each memory cell incorporates an access transistor AT paired with a capacitor SC. This assembly is oriented along the z-axis, perpendicular to the main plane (x, y) such that the access transistor AT is stacked above the capacitor SC. The memory cells are interlinked through a network of word lines WL and bit lines BL that create a grid pattern. The electrical setup of each memory cell is depicted schematically in, which illustrates a conventional DRAM memory cell.

[0025] For clarity of the present description, the main plane (x,y) will hereafter also be referred to as the “horizontal plane” and any direction lying in that plane as “horizontal” and the z-direction will be referred to as “vertical”.

[0026] In the represented embodiment, the access transistor AT is a vertical transistor and comprises a channel C made of a pilar of semiconductor material, typically of silicium and preferably a semiconductor material in monocrystalline form, extending perpendicularly to the main plain. The channel C is surrounded by the gate dielectric GO, typically a thin layer of silicon oxide. The channels C of the access transistor have been represented with a square cross section along the main plane, but in other embodiments, they may present a different shape. The channel C of an access transistor AT spans vertically from a lower plane, where it contacts the paired capacitor SC, to an upper plane where the bit lines extend along a first direction. At this upper plane, the channel C establishes a connection with a bit line.

[0027] Word lines WL run horizontally, in a direction perpendicular to the extension direction of the bit line, and lie in between the upper plane and lower plane, as it can be best seen on. Each word line WL intersects a row of access transistors AT, serving as the gate for these transistors. The signal from the word line WL controls the flow of charge into the channels C of the access transistors, thereby regulating the memory operations of each cell in the array. The remaining space between the upper plane and the lower plane is filled with an interlayer dielectric material IM, such as silicon nitride.

[0028] Pursuing the description of the memory array of,2b and 2C, each capacitor SC paired with an access transistor AT is made of a bottom electrode BE, contacting the access transistor channel via a landing pad LD, and of a top electrode TE. The two electrodes BE, TE are separated by a dielectric material D, as this is well known in the art. A layer I made of electrically insulating material is separating the plurality of capacitor SC from the plurality of access transistors AT.

[0029] Referring to Figures 3a through 3o, the following details the method for preparing the memory array previously described.

[0030] Generally, the method comprises transferring a semiconductor layer onto at least a portion of the capacitors SC, using a conductive bond between the semiconductor layer and the bottom electrode of the capacitors, and then patterning the semiconductor layer to define the plurality of access transistors AT. Since the access transistor AT is formed on the capacitors SC after the HARC etching of the mold oxide and definition of the bottom electrode, the access transistor AT can be easily aligned with the electrodes with photolithographic precision and the process is less sensitive to the profile accuracy of the HARC etching process.

[0031] The method first comprises forming at least part of the capacitor SC. This is achieved by depositing a mold oxide layer MOL on a receiving substrate S, for instance a silicon substrate. The mold oxide layer MOL may consist of a silicon dioxide layer and present a thickness that is typically close to, or greater than, 1 micrometer. In a subsequent step (), the exposed surface MOLD1 of the mold oxide layer MOL is processed, to define by etching a plurality of holes H extending through the mold oxide layer to the underlying receiving substrate S. The etching may be made using a HARC (“high-aspect-ratio-contact”) process and the diameter of the holes pattern is typically several tens of nanometers. The holes may be arranged according to a hexagonal or an orthogonal pattern on the exposed surface MOLD1.

[0032] In a next step illustrated on, a conductive material CM, typically titanium nitride, is deposited into the holes to fill the holes, for instance by CVD or ALD process, and to entirely cover the mold oxide layer MOLD with a thin layer of conductive material CM. The conductive material will constitute the bottom electrodes BE of the capacitors SC. Then () a redistribution layer RDL made of conductive material such as tungsten may, in some instance, be formed over the exposed surface.

[0033] Then the layer of conductive material CM and redistribution layer RDL are patterned to electrically isolate the bottom electrodes BE from each other’s. The local removal of the conductive materials exposes the underlying mold oxide layer surface MOL1 and define contact portions CP of the bottom electrodes BE, on the side of the exposed surface MOL1 as this can be seen on. Each contact portion CP associated to a bottom electrode comprises a superficial contact pad RDL. The contact portion CP allows to redistribute the capacitors SC layout to the access transistor AT contact location.

[0034] An insulating separation layer I made of electrically insulating material is formed over the receiving substrate S and planarized to encapsulate the extended contact portion CP of the bottom electrodes and provides a smooth and planar surface (). The insulating separation layer may be made of silicon dioxide or silicon nitride.

[0035] Over the insulating separation layer I, a thin-film silicide precursor layer CON is deposited and possibly planarized. The thin-film silicide precursor layer CON may be constituted of a metal, such as Ni, Co, Ti, Ru, Pt. It will be contacted by a semiconductor layer, as this will be disclosed in greater details in a further section of the description, to form a thin film silicide layer. This thin film silicide layer is used to facilitate the formation of an ohmic contacts between the semiconductor layer and the contact portions

[0036] The capacitor SC being now partially completed on the receiving substrate S, the method of the present embodiment proposes to transfer a semiconductor layer SL on, and in electrical contact with, the contact portions CP of the bottom electrodes BE. As mentioned above, the electrical contact may be facilitated by the presence, between the contact portion and the semiconductor layer SL of the thin film silicide layer, although this layer is not imperative. Typically, the semiconductor layer may consist or comprise silicon. Its thickness, as this will be made apparent in a later portion of this disclosure, is defined by the length of the access transistors TA channels. This thickness may therefore be comprised between a 10nm to 1 micrometer, and preferably between 80nm to 200nm.

[0037] The transfer of the semiconductor layer SL may be achieved in many ways. It generally involves the bonding of a donor substrate, comprising superficially the semiconductor layer to be transferred, onto the exposed face of the receiving substrate S, i.e. thin film silicide precursor layer CON or the contact portions CP and insulating separation layer I as the case may be. This bonding step may be achieved by molecular bonding. After bonding, the assembled structure may be thermally treated at moderated temperature of a few hundred degrees to reinforce the adhesion force at the interface between the two substrates. The anneal, in case the thin film silicide precursor layer CON is present, also forms the thin film silicide layer and complete the ohmic contact formation at this interface. The thickness of the donor substrate is then reduced up to the thickness of the semiconductor layer.

[0038] According to the embodiment represented on, the donor substrate DS is consisting of a semiconductor on insulator substrate. Such a substrate, as this is well known in the art, comprises the semiconductor layer SL disposed on and in contact with a buried dielectric layer BOX disposed on and in contact with a handle substrate HL. After the bonding step, and the potential anneal at moderated temperature, the handle substrate HS may be removed at least in part by mechanical means, such as grinding, and a remaining part selectively etch with respect with the buried dielectric layer BOX. This buried dielectric layer BOX may then be removed leaving the semiconductor layer SL on the receiving substrate S.

[0039] In differing approach, the donor substrate DS may comprise a bulk semiconductor substrate, and the semiconductor layer transferred on to the receiving substrate S by either thinning the bulk semiconductor substrate by mechanical and / or chemical or by exfoliating the semiconductor layer SL. The exfoliation may be realized according to the principle of the Smart Cut® technology according to which a weakened plane if form into the donor substrate, before the bonding step, by introduction of light species, and the donor substrate DS fractured in the weakened plane, after the bonding step.

[0040] In the embodiment disclosed with respect toto 3n the removal of the handle substrate HS from the donor substrate DS does not follow directly the bonding step. In between these two stages, the formation of the capacitors SC is finalized. This is performed by removing the receiving substrate, as this is shown onto expose an end portion of the bottom electrode BE and the mold oxide MOL.

[0041] As shown on, the remaining portion of the mold oxide MOL is selectively removed, and a dielectric layer D and a top electrode layer TE are successively deposited onto the exposed bottom electrode BE to complete the formation of the capacitors SC. It is to be noted that the completion of the capacitors SC does not require any alignment steps, as the successive layers are deposited over the full exposed substrate.

[0042] Although not represented in the figures, a support may be provided on the top electrode TE, by deposition of a supporting layer and / or by attachment to a support structure.

[0043] Turning to the next step of this embodiment illustrated on, the handle substrate HS of the donor substrate DS is removed as this has been explained in a previous passage.

[0044] It is not necessary to complete the formation the capacitors SC while the bottom electrode BE resides on the donor substrate DS, i.e. before the transfer of the semiconductor layer SL, as this is the case in the illustrated embodiment. In other embodiments, the completion of the capacitors SC may be achieved at a later stage of the method, i.e. after the transfer of the semiconductor layer SL or after the completion of the access transistors. In such embodiments, the reduction of thickness of the donor substrate DS, that finalizes the transfer of the semiconductor layer SL, is performed directly after the bonding step.

[0045] Pursuing the description of the illustrated embodiment, the method then comprises patterning the semiconductor layer SL to define the plurality of access transistors AT. This patterning is achieved by defining the channels of the access transistors AT to be in electrical contact with the contact portions CP of the bottom electrodes BE. As represented on, an array A of semiconductor pillars is defined, with each semiconductor pillar being respectively positioned on the contact portion CP of a bottom electrode BE. Each pilar is defined by photolithography to be aligned on the underlying contact portion CP of the bottom electrode BE, and is intended to form a channel C of the access transistor TA.

[0046] As represented on, the gate oxide is then formed over the pillars of the array, and interconnected gate electrodes are subsequently formed around selected semiconductor pillars. The interconnected gate electrodes are integrated within the word line WL of the memory array 1. The remaining space is filled with the interlayer dielectric material IM, and planarized. Finally, as represented on, the bit lines are formed over the structure, by deposition and pattering of a conductive material, each bit line BL being in contact with selected semiconductor pillars in the memory array. This completes the memory array 1 initially presented with reference to figures 2a to 2c.

[0047] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.

Claims

A method for preparing a memory array (1), the memory array (1) comprising at least one bit line (BL), at least one word line (WL), a plurality of capacitors (SC), and a plurality of access transistor (AT), wherein each capacitor (SC) of the plurality of capacitors is respectively associated with an access transistor (AT) of the plurality of access transistors, each capacitor (SC) comprising a bottom electrode (BE) and a top electrode (TE), the method comprising:depositing a mold oxide layer (MOL) on a receiving substrate (S), the mold oxide layer (MOL) having an exposed surface (MOL1);etching the exposed surface (MOL1) of the mold oxide layer (MOL) to form a plurality of holes extending through the mold oxide layer;forming the bottom electrodes (BE) of the plurality of capacitors (SC) within the plurality of holes (H), each bottom electrode (BE) presenting a contact portion (CP) on the side of the exposed surface (MOL1);transferring a semiconductor layer (SL) on the contact portions (CP) of the bottom electrodes (BE);patterning the semiconductor layer (SL) to define the plurality of access transistors (AT), wherein channels of the access transistors (AT) are in electrical contact with the contact portions (CP) of the bottom electrodes (BE).The method of claim 1 further comprising removing the remaining portion of the mold oxide layer (MOL) and subsequently forming a dielectric layer (D) and a top electrode (TE) on each of the bottom electrodes (BE) to complete the capacitors (SC).The method of claim 2 wherein the completion of the capacitors (SC) is performed before the transfer of the semiconductor layer (SL).The method of claim 2 wherein the completion of the capacitors (SC) is performed after the transfer of the semiconductor layer (SL).The method according to any of claim 1 to 4, wherein forming the bottom electrodes (BE) comprises forming a superficial contact pad (RDL).The method of claim 5 further comprising forming a silicide precursor layer (CON) onto the contact portions (CP), before transferring the semiconductor layer.The method of claim 6 wherein transferring the semiconductor layer (SL) comprises directly bonding the semiconductor layer (SL) to the silicide precursor layer (CON).The method of claim 7 wherein the semiconductor layer (SL) is initially supported by a handle substrate (HS), and transferring the semiconductor layer (SL) comprises removing the handle substrate (HS) after bonding the semiconductor layer (SL) to the silicide precursor layer (CON).The method according to any of claim 1 to 4 wherein patterning the semiconductor layer (SL) is carried out after transferring the semiconductor layer (SL) on the contact portions (CP) of the bottom electrodes (BE).The method of any preceding claims wherein patterning the semiconductor layer (SL) comprises forming an array (A) of semiconductor pillars, each semiconductor pillar being respectively positioned on a contact portion (CP) of a bottom electrode (BE).The method of claim 10 wherein patterning the semiconductor layer further comprises forming interconnected gate electrodes around selected semiconductor pillars, the interconnected gate electrodes being integrated within a word line (WL) of the memory array (1).The method of claim 11 further comprising forming the bit line (BL) over selected semiconductor pillars in the memory array (1).The method of any preceding claims wherein the semiconductor layer (SL) is monocrystalline.The method of any preceding claims wherein semiconductor layer (SL) is made of silicon.

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