This application provides a three-dimensional ferroelectric memory and its fabrication method. A substrate has a source layer and a stacked layer, with a channel hole extending to the source layer formed in the stacked layer. A charge
trapping potential structure layer, a ferroelectric layer, and a second
dielectric layer are sequentially formed within the channel hole. The charge
trapping potential structure layer includes a
trapping layer. A channel layer and a third
dielectric layer are sequentially formed within the channel hole. The channel layer is in contact with the source layer. A sacrificial layer is removed and filled with a
metal gate material to form a
metal gate layer. Source holes, gate holes, and drain holes are formed by
etching. The source holes extend to the source layer, the gate holes extend to each
metal gate layer, and the drain holes extend to the channel layer. The defect energy levels in the trapping layer are sufficiently deep, requiring a large
energy level for electrons to escape from the trapping layer (i.e., the energy from the defect
energy level to the
conduction band). This makes it difficult for electrons to escape, and the electrons in the trapping layer can promote ferroelectric polarization, thereby increasing the storage window and improving the storage characteristics of the three-dimensional ferroelectric memory device.