A realization method of self-erasable fpga configuration module

A technology for configuration modules and implementation methods, applied in information storage, static memory, instruments, etc., can solve the problems that the digital system cannot be completed by itself, FPGA and PROM cannot work, and cannot provide protection, etc. The implementation method is simple, convenient, and guaranteed Normal work, avoiding the effect of accidental erase operation

CN103474094BActive Publication Date: 2016-05-04BEIJING RES INST OF TELEMETRY +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Publication Date
2016-05-04

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Abstract

The invention relates to an implementation method of a self-erasable FPGA (field programmable gate array) configuration module, which comprises the steps of storing the configuration information of an FPGA in a PROM (programmable read-only memory); when the whole configuration module is power-on, loading the configuration information into the FPGA, so that the FPGA runs normally, and an external computer can implement the operations of accessing, programming and erasing the PROM by a JTAG (joint test action group). According to the invention, signals similar to JTAG erasing instructions are generated by using the FPGA, and the signals are transmitted to the PROM through the JTAG, thereby realizing a purpose of erasing the configuration information stored in the PROM; for ensuring the normal running of the whole configuration module, the control on a self-erasing operation is performed by using a CPLD (complex programmable logic device), thereby avoiding the occurrence of a mis-erasing situation. According to the invention, the self-erasing operation of the FPGA configuration module can be completed, the configuration information in the PROM can be completely erased, and the mis-erasing operation is avoided, thereby ensuring the normal running of a digital system.
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Description

technical field

[0001] The invention relates to a method for realizing a self-erasable FPGA configuration module, which belongs to the technical field of electronic products. Background technique

[0002] Existing methods for erasing the FPGA configuration information stored on the PROM include a software erasing method and a physical destruction method.

[0003] The software erasing method is to use the software provided by FPGA and PROM design manufacturers to erase. Taking Xilinx products as an example, the IMPACT software provided by this manufacturer can complete the erasing operation of configuration information, but this method must rely on the computer And the corresponding software to complete, the digital system cannot complete by itself, so there are certain limitations.

[0004] The method of physical destruction usually adopts the method of electric burning, so that FPGA and PROM cannot work. However, it has been proved by experiments that electric burning onl...

Examples

Embodiment Construction

[0035] Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail:

[0036] In order to meet the requirements of technical confidentiality, the digital system needs to erase the configuration information of the FPGA to avoid obtaining relevant technical information through the configuration information. For digital systems designed based on FPGA and PROM, due to the storage characteristics of FPGA, the configuration information on it will be lost after power off, so it is only necessary to erase the configuration information on the PROM. The access, programming and erasing of PROM can be realized through JTAG. The present invention designs a self-erasable FPGA configuration module, which simulates JTAG to issue erasing instructions to the PROM by generating relevant signals through the FPGA, thereby completing the self-erasing operation.

[0037] Such as figure 1 Shown is the schematic diagram of the FPGA confi...