A composite dielectric passivation layer structure solar cell and its preparation process

Abstract

The present invention discloses a solar cell with a composite dielectric passivation layer structure and a preparation process thereof, wherein a silicon oxide film, an aluminum oxide film, a silicon nitride or a silicon oxynitride film composite dielectric film layer are sequentially deposited on the front, back and peripheral surfaces of a P-type silicon substrate, and a window is opened locally for electrode extraction. The back surface passivation layer of aluminum oxide, silicon dioxide, silicon oxynitride, silicon nitride with different refractive indices and their laminated structures of the present invention greatly reduces the back surface recombination rate, improves the back reflectivity, and simultaneously reduces the component CTM, improves the cell light decay and thermally assisted light decay performance, and anti-PID performance; the structure can be made on boron-doped or gallium-doped P-type monocrystalline silicon, P-type polycrystalline silicon and P-type quasi-monocrystalline silicon substrates, and is compatible with the passivation method based on the composite dielectric film passivation structure for manufacturing PERC cells, double-sided PERC+ cells and shingled PERC cells; the preparation process steps and sequence of the laminated structure, the corresponding preparation method and the process parameter range can well complete the cell production.

Description

Technical Field

[0001] The present invention relates to the technical field of PERC solar cells, and in particular to a solar cell with a composite dielectric passivation film structure and a preparation process thereof. Background Art

[0002] Photovoltaic power generation is an effective way to utilize solar energy by directly converting sunlight into electrical energy through the photovoltaic effect of semiconductors, reducing consumption losses during energy conversion, and then supplying the generated electricity to users. Photovoltaic power generation can reduce the proportion of petrochemical energy use, thereby reducing carbon emissions and improving the environment. After more than ten years of technological catch-up, it has gradually become an emerging strategic manufacturing industry that can compete with developed countries such as Europe, the United States, and Japan. At the same time, photovoltaic power generation is also one of the country's precise poverty alleviation methods. Through the "photovoltaic poverty alleviation" project, more remote, poor, and power-deficient mountainous areas are provided with clean electricity and electricity sales income. However, due to the current low light utilization rate and high technical routes and equipment and auxiliary material costs, photovoltaic power generation cannot achieve the same kilowatt-hour cost and price as traditional fossil energy. Photovoltaic power can only expand its application scope and achieve the ultimate goal of "grid parity" by reducing the kilowatt-hour cost and improving energy conversion efficiency. How to achieve grid parity for photovoltaic power generation and achieve a fundamental change in the way of energy acquisition has become a key challenge for the popularization and application of photovoltaics. The main way to achieve this is to improve the photovoltaic conversion efficiency of solar cells and maintain long-term sustainable and stable power generation. This requires a large amount of product research and development and technology upgrades in the early stages to gradually improve, while taking into account reducing the manufacturing costs of the entire industry chain.

[0003] The traditional BSF solar cell manufacturing process in the past 20 years is as follows: Figure 3As shown, after continuous improvement of the front emission junction process formula, upgrading of the gold-semiconductor contact electrode process, velvet preparation methods and equipment transformation, such as selective emission junction, high-resistance dense grid, black silicon, DP and other mass production technologies, the efficiency can be improved by 0.8%-1.1%. However, the aluminum back field formed by the concentrated aluminum doping on the back surface of the traditional BSF solar cell has always been an effective recombination center due to the direct contact between the metal and the semiconductor. The recombination electrical loss and long-wave optical loss on the back surface have always existed. In order to solve this structural design problem, major research institutions at home and abroad focus on the passivation treatment and structural improvement of the surface of high-efficiency cells. For example, the design principles of PERC, HJT, IBC, and TopCon cells are all focused on reducing the carrier recombination in the interface layer and improving the quantum efficiency of photoelectric conversion in each band, which will greatly improve the photoelectric conversion efficiency of solar cells. Among them, PERC cells can greatly improve the photoelectric conversion efficiency of solar cells and are compatible with existing cell production lines. Through product design and process optimization, the introduction of back passivation and laser equipment, and the selective introduction of cleaning equipment, the absolute photoelectric conversion efficiency of the battery can be increased by 1.0%-1.5%, thereby increasing the wattage of the photovoltaic panels. The actual power generation of PERC monocrystalline modules in actual outdoor power generation tests is about 3.1% higher than that of conventional multicrystalline modules, thereby reducing the cost per kilowatt-hour and contributing to the grid parity of photovoltaic power generation.

[0004] The passivated emitter and back local contact cell PERC technology reduces the recombination of carriers by introducing a dielectric passivation layer on the back of the cell, thereby increasing the open circuit voltage of the device, increasing the back surface reflection, and increasing the short-circuit current. This process can increase the conversion efficiency of monocrystalline silicon cells by 1.5% absolute value. The process path is relatively simple, cost-effective, and fully compatible with existing cell production lines. Among them, it is crucial to select a passivation film suitable for industrial high-efficiency silicon solar cells. The film layer should be prepared at a relatively low temperature, without destroying the microscopic chemical bonds and material properties of the internal formed cell, and has comparable passivation performance with laboratory thermally oxidized SiO2. In recent years, through continuous accumulation and attempts, it has been found that negatively charged aluminum oxide dielectric films can passivate the P-type silicon surface well and obtain a lower surface recombination rate. It has been proven that the SRVs of ALD using low-temperature plasma are <13cm / s on low-resistivity P-type silicon; and aluminum oxide films can be deposited at a lower temperature, generally lower than the laboratory SiO2 deposition temperature, and comparable to or lower than the deposition temperature of the passivation anti-reflection protective film SixNy that has been applied in the industry.

[0005] At present, the industrialized PERC cells are based on the dielectric passivation film structure of back aluminum oxide and back silicon nitride, and front silicon nitride. However, due to the possible presence of -OH and -CH3 groups in the aluminum oxide dielectric film layer, if the annealing process is not strictly matched, it may react with the H in the SixNy:H stack from the capping stack during sintering, thereby destroying the passivation effect of the stack passivation film under the high temperature conditions of the back-end sintering (>860℃), resulting in a decrease in electrical performance and the production of EL detection defective pieces; at the same time, after being placed for a period of time, a certain combination of light and temperature conditions may accumulate and escape residual secondary reactants, causing the LID / LeTID phenomenon in PERC cells. The cause of the LeTID phenomenon is complex, and many research institutions such as SCHOTT, UNSW, Konstan University, ISFH, and Aalto University are conducting further research. The current mainstream view is that hydrogen is the main factor, and the attenuation caused by metal ions such as BO / FeB and Cu in the raw materials is also relatively serious.

[0006] Therefore, the current industrialized PERC solar cells generally have problems such as easy damage to the passivation film layer, severe back-end attenuation and EL abnormalities; on the other hand, there is a lot of room for improvement in the double-sided PID phenomenon of double-sided PERC+ cells. The PID attenuation of EVA-packaged double-sided PERC modules can be reduced to a certain extent through the design of the dielectric passivation film structure and the matching of module packaging materials such as POE. As the modules and system ends require solar cells to have better CTM, light decay and thermally assisted light decay performance, and anti-PID performance, improving the above stability and reliability of PERC cells is becoming increasingly important.

[0007] However, since bifacial cells combined with PID are new product failure phenomena that have appeared in recent years, and the generation mechanism, inducing conditions, and influencing factors of the original PID phenomenon are all unclear and subject to multiple constraints, matching component packaging materials will inevitably increase back-end manufacturing costs to a certain extent. Therefore, solar cell manufacturers are more inclined to reduce the PID failure phenomenon of industrialized PERC series solar cells through the design of the front-end dielectric film layer structure of the cell and the optimized combination of process formulas. Summary of the invention

[0008] The purpose of the present invention is to provide a composite dielectric passivation layer structure solar cell and its preparation process to solve the problems raised in the above background technology.

[0009] To achieve the above object, the present invention provides the following technical solutions:

[0010] A preparation process of a composite dielectric passivation layer structure solar cell,

[0011] Preparing a P-type silicon substrate;

[0012] On the front side of the P-type silicon substrate, an N-type emitter junction region, a silicon oxide film, a silicon nitride film with a relatively high n value or a silicon nitride oxide film, and a silicon nitride film with a low n value are sequentially deposited; on the back side and the periphery, a silicon oxide film, an aluminum oxide film, and a silicon nitride film with a low n value are sequentially deposited to form a full-surface laminated composite dielectric passivation film layer;

[0013] The front side of the P-type silicon substrate with the above-mentioned stacked coating is laser doped to form an N++SE heavily doped area, and a Ag positive electrode that penetrates the composite dielectric passivation film layer is printed to match it, and a local window is opened on the back side for electrode extraction.

[0014] Preferably, a plurality of full-surface composite dielectric passivation film layers are sequentially deposited on the front side, the back side and the periphery of the P-type silicon substrate, and specifically include:

[0015] Oxidation annealing silicon oxide deposition: using any oxidation process of dry oxygen thermal oxidation, ozone oxidation, N20 oxidation or nitric acid oxidation, a full-surface silicon oxide film is formed on the front, back and periphery of the P-type silicon substrate. During the annealing process, oxygen is introduced to fully cover the surface of the P-type silicon substrate to form a 1.5-8nm full-surface silicon oxide film, and its refractive index n value is controlled at 1.4-1.65;

[0016] Alumina deposition: A 3-30nm thick aluminum oxide film is formed on the front, back and periphery of the P-type silicon substrate by any of the formation processes of ALD, PECVD, CVD deposition or solid target material by PVD. The refractive index n value is controlled at 1.58-1.76 and the formation time is 25-35min. The aluminum oxide film diffracted to the front is washed away by wet chemical solution;

[0017] The aluminum oxide film on the front side is removed on one side using an online roller trough device, and pickled with 5%-20% dilute HCl to remove the aluminum oxide film formed on the front surface of the silicon oxide film, and then the residual acid on the surface is cleaned with DI water and blown dry with an air knife;

[0018] Silicon nitride deposition: using tubular PECVD process, first deposit a silicon nitride or silicon oxynitride film with a higher n value on the front of the P-type silicon substrate, and then generate a layer of low-n value silicon nitride film covering the entire surface on the front, back and periphery of the P-type silicon substrate. The temperature of the tubular PECVD process is 360-480°C, ammonia and silane are injected, and laughing gas is added when depositing the silicon oxynitride film, and a radio frequency electric field is applied;

[0019] The refractive index n value of the silicon nitride or silicon oxynitride film with a higher n value on the front side is set to be controlled within the range of 2.06-2.38, and the film thickness is controlled within the range of 8-60 nm;

[0020] The refractive index n value of the low n value silicon nitride film on the front side is set to be controlled within the range of 1.86-2.2, and the film thickness is controlled within the range of 12-72 nm;

[0021] The refractive index n value of the low-n silicon nitride film covering the back and the entire peripheral surface is set to be controlled at 1.86-2.36, and the film thickness is controlled at 90-200nm;

[0022] The silicon nitride or silicon oxynitride film with a higher n value on the front side and the silicon nitride film with a low n value on the front side are deposited once, and when depositing the silicon oxynitride film, nitrous oxide is first added and then turned off;

[0023] The low n-value silicon nitride film on the front and back sides is set to be coated in batches, and the order of the coating is to coat the front side first and then the back side or to coat the back side first and then the front side. During the coating process, the vacuum needs to be broken to take out the film and then turn it over.

[0024] Preferably, preparing a P-type silicon substrate specifically includes:

[0025] S1, damage layer removal and texturing: cleaning and texturing the P-type silicon substrate, removing the damage layer of 3-5 μm on the surface of the P-type silicon substrate, and making a velvet surface on the front surface of the P-type silicon substrate;

[0026] S2, diffusion to form PN junction: depositing a doping source on the surface of a P-type silicon substrate and performing thermal diffusion to prepare a PN junction region, wherein the doping source is phosphorus oxychloride and oxygen, and the heating time is 30-60 minutes;

[0027] S3, laser SE doping: use a laser with a wavelength of 532nm to irradiate the diffused P-type silicon substrate to form a localized heavily doped area, and the area of ​​the N++SE heavily doped area accounts for 4.5%-8.5%;

[0028] S4, etching and backside polishing: The P-type silicon substrate is sequentially etched, cleaned and backside polished, with a backside polishing thickness of 3-8um.

[0029] Preferably, laser grooving: locally grooving the back side of the P-type silicon substrate with the laminated coating by using a 532nm-1064nm ps or ns laser, with the grooving area accounting for 0.5%-6%;

[0030] Back electrode screen printing: screen printing Ag-Al or Ag back electrode on the back of the P-type silicon substrate prepared above and drying;

[0031] Aluminum back field screen printing: corresponding to the local grooved area on the back, screen print aluminum paste on the non-Ag-Al or Ag back electrode area on the back of the P-type silicon substrate and dry it to form an Al back field with a thickness of 10-30μm and a distance of 0.8-1.6mm from the edge;

[0032] Positive electrode screen printing: Match the N++SE heavily doped area on the front side of the P-type silicon substrate, screen print the Ag positive electrode that penetrates the composite passivation film layer and dry it.

[0033] Preferably, preparing a P-type silicon substrate further comprises:

[0034] If the P-type silicon substrate is a polycrystalline cell, acid texturing is used, and the solution used is a mixed solution of nitric acid, hydrofluoric acid and water, nitric acid: hydrofluoric acid: water = 2:1:2-5:1:2;

[0035] If the P-type silicon substrate is a single crystal cell, alkali texturing is used, and the solvent ratio is NaOH or KOH, isopropanol, single crystal silicon texturing additive and water.

[0036] Preferably, in step S2, phosphorus oxychloride is carried by nitrogen, the nitrogen flow rate is 1000-2000sccm, the time is 25-35 minutes, the oxygen flow rate is 1000-3000sccm, the time is 40-55 minutes, and the temperature is controlled at 830-870°C.

[0037] Preferably, in step S3, the sheet resistance of the N++SE heavily doped region is 50-90Ω / □.

[0038] Preferably, in step S4, the back N-type layer is corroded and removed by a mixed solution of HF, HNO3 and H2SO4 and a KOH / NaOH solution in a subsequent alkaline bath, and the front phosphosilicate glass is removed, and a 3-8 μm polishing treatment is performed on the back surface of the P-type silicon substrate.

[0039] Preferably, in the laser grooving step, the grooving pattern is any one of a linear shape, a cross shape, a dash shape, a square shape, a diamond shape and a hexagon shape.

[0040] A composite dielectric passivation layer structure solar cell, prepared by the preparation process, comprises a P-type silicon substrate, and a full-surface deposited silicon oxide film, a front-side silicon nitride or silicon nitride oxide film with a higher n value, a back-side and peripheral aluminum oxide film, and a full-surface low-n value silicon nitride film sequentially coated on the outside of the P-type silicon substrate;

[0041] An emitter junction region is arranged on the upper side of the P-type silicon substrate, and an N++SE heavily doped region is arranged between the emitter junction region and the P-type silicon substrate;

[0042] The other side of the P-type silicon substrate having an emitter junction region is provided with a Local-BSF P++ region, the bottom of the low-n-value silicon nitride film is provided with an Al back field, the Al back field is provided with an electrode column, the electrode column sequentially passes through the low-n-value silicon nitride film, the back and peripheral aluminum oxide film, and the entire surface silicon oxide film, and the top of the electrode column is connected to the Local-BSF P++ region.

[0043] Preferably, a Ag positive electrode penetrating the composite dielectric passivation film layer is provided on one side of the P-type silicon substrate provided with the N++SE heavily doped region, and the Ag positive electrode sequentially passes through a low n-value silicon nitride film, a higher n-value silicon nitride or silicon oxynitride film and a full-surface silicon oxide film, and the Ag positive electrode is connected to the emitter junction region at one end close to the P-type silicon substrate.

[0044] Preferably, an Ag—Al or Ag back electrode is provided on the Al back surface field.

[0045] Preferably, the Local-BSF P++ zone is composed of a plurality of spherical segments rather than conical pits.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The present invention can manufacture the structure on a boron-doped or gallium-doped P-type single crystal silicon, P-type polycrystalline silicon and P-type quasi-single crystal silicon substrate, and deposit thin silicon oxide SiO2, aluminum oxide Al2O3, silicon oxynitride SiO3 on both sides of the silicon substrate from inside to outside. x N y and silicon nitride Si with different n values x N y :H forms a multi-layer composite structure as a dielectric passivation film layer, and forms a new composite dielectric passivation film stack structure on the surface of the silicon wafer; the passivation of the dangling bonds on the silicon surface is achieved through a thermal oxide film on the front, back and surrounding surfaces. The first dense oxide layer SiO2 contains a large amount of oxygen and has stable chemical properties, which can perform good chemical passivation on the dangling bonds on the surface of the silicon wafer.

[0048] The second layer of high refractive index dense silicon nitride or silicon oxynitride film on the front side effectively prevents the subsequent products of sodium ions, -OH and -CH3 groups from migrating into the interior of the battery, blocks the movement and migration of mobile ions under the action of external electric field, temperature and humidity, strengthens the anti-PID effect, and has good anti-PID performance and anti-aging attenuation performance; the second layer of aluminum oxide film on the back side and the periphery has a relatively low growth and annealing temperature and carries a negative charge, that is, after high-temperature heat treatment, the octahedral structure of aluminum atoms in Al2O3 will be converted into a tetrahedral structure to generate interstitial oxygen atoms. The interstitial oxygen atoms capture the valence electrons in P-type silicon to form a fixed negative charge, making the Al2O3 film negatively charged, and generating an interface electric field pointing to the interior of the silicon wafer at the interface, so that the carriers can quickly escape from the interface, reduce the interface recombination rate, and increase the minority carrier lifetime of the silicon wafer, and can perform field passivation on the P-type substrate.

[0049] The third layer fully covers the silicon nitride film Si x N y:H comprehensive optical path matching achieves the best anti-reflection effect, and at the same time can protect the adjacent aluminum oxide film, high refractive index silicon nitride or silicon oxynitride film to prevent excessive reaction corrosion of the slurry; the H passivation effect of this layer after annealing is significant, which once again improves the minority carrier lifetime of the silicon wafer, and can also prevent the subsequent products of Na+, -OH and -CH3 groups from migrating into the battery to a certain extent, avoiding leakage of battery components and power attenuation. Matching the above-mentioned film layers to jointly reduce the CTM of the packaging components, improve the battery light decay and thermal assisted light decay performance, and anti-PID performance. By adopting the stacked composite dielectric passivation film deposition on the PERC structure, the comprehensive utilization rate of passivation and incident light can be effectively enhanced, the short-circuit current and open-circuit voltage of the battery can be increased, and the stability and reliability performance of the anti-light decay and anti-PID of the battery of this structure can be improved.

[0050] 1. Compared with the conventional BSF solar cell production process, the PERC solar cell production process of the present invention adds a plurality of passivation films with different dielectric structures as the front and back passivation layers and the optical receiving layer, which can greatly reduce the recombination rate of the back surface and improve the collection rate of photogenerated carriers; thin silicon oxide SiO2 and aluminum oxide Al2O3 are sequentially deposited on both sides of the silicon substrate from the inside to the outside, the aluminum oxide on the front side is washed off and silicon nitride Si with a higher n value is deposited. x N y or silicon oxynitride SiO x N y , and then deposit low n-value silicon nitride Si on both sides x N y :H stacked structure as a dielectric passivation film layer, forming a new composite dielectric passivation layer stacked structure on the surface of the silicon wafer; by adopting the improved deposition of the stacked dielectric passivation film for the PERC structure, the comprehensive utilization rate of passivation and incident light can be effectively enhanced, the short-circuit current and open-circuit voltage of the battery can be increased, and the anti-light decay and anti-PID stability and reliability performance of the battery of this structure can be improved;

[0051] 2. The passivation of dangling bonds on the silicon surface is achieved through a thermal oxide film on the front, back and surrounding surfaces, which is essentially different from the process in the related patents that uses oxygen ions rich in the Al2O3 film directly in contact with the silicon surface to passivate dangling bonds through subsequent heat treatment. At the same time, the first dense oxide layer SiO2 also contains a certain amount of H, good density and stability, which can passivate the dangling bonds on the silicon wafer surface and improve Voc;

[0052] 3. On the basis of SiO2 thin film passivation, high refractive index dense silicon nitride or silicon oxynitride film, aluminum oxide film layer can not only enhance the passivation effect and improve the minority carrier lifetime, but also prevent the mobile ions in the passivation layer from moving and migrating under the external electric field, temperature and humidity, enhance the anti-PID effect, avoid leakage of different inversion layers in battery components, and cause power attenuation, and have good anti-PID performance and anti-aging attenuation performance;

[0053] 4. Finally, the fully covered low-n silicon nitride film layer can match the optimal optical path difference to achieve optical anti-reflection, and protect the adjacent film layers to prevent the slurry reaction from corroding too many internal cross-sections, and enhance the passivation effect through H passivation during the later high-temperature sintering, further improving the minority carrier life and battery open circuit voltage; at the same time, it can also prevent the subsequent products from migrating into the battery to a certain extent, avoiding leakage of battery components and power attenuation, matching the above film layers to jointly reduce the CTM of the package components, and improve the battery light decay and thermal assisted light decay performance, as well as anti-PID performance;

[0054] 5. Matching silicon oxide SiO2, aluminum oxide Al2O3, high n value silicon nitride Si x N y or silicon oxynitride SiO x N y and low n-value silicon nitride Si x N y :H multi-layer structure can reduce the front light reflection ratio and enhance the back light reflection ratio, ensuring the balanced utilization of short-wave and long-wave light, thereby enhancing the comprehensive utilization rate of incident light and increasing the short-circuit current of the battery;

[0055] 6. The equipment used in the present invention is more than 80% compatible with traditional solar cell equipment, does not require too much new equipment investment, has low process transformation costs, large production capacity, significant performance improvement advantages, and has very good industrial application prospects.

[0056] The back surface passivation layer of aluminum oxide, silicon oxide, silicon oxynitride, silicon nitride with different refractive indices and their stacked structures of the present invention greatly reduces the back surface recombination rate, improves the back reflectivity, and simultaneously reduces the CTM of the component, improves the light decay and thermally assisted light decay performance of the battery, and the anti-PID performance; the structure can be made on boron-doped or gallium-doped P-type single crystal silicon, P-type polycrystalline silicon and P-type quasi-single crystal silicon substrates, and is compatible with the passivation method for manufacturing PERC cells, double-sided PERC+ cells and shingled PERC cells based on the composite dielectric film passivation structure; the preparation process steps and sequence of the stacked structure, the corresponding preparation method and the process parameter range can well complete the battery production. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 It is a schematic diagram of the structure of the composite dielectric passivation layer solar cell of the present invention;

[0058] Figure 2 It is a schematic diagram of the preparation process of the present invention;

[0059] Figure 3 This is a schematic diagram of the conventional battery preparation process;

[0060] Figure 4It is a schematic diagram of the linear grooving structure in the laser grooving of the present invention;

[0061] Figure 5 A schematic diagram of a cross-shaped structure in laser grooving of the present invention;

[0062] Figure 6 It is a schematic diagram of a dash-shaped slotting structure in laser slotting of the present invention;

[0063] Figure 7 It is a schematic diagram of the hexagonal slotting structure in the laser slotting of the present invention;

[0064] Figure 8 It is a schematic diagram of a square slotting structure in laser slotting of the present invention;

[0065] Fig. 9 It is a schematic diagram of the diamond-shaped groove structure in the laser groove of the present invention.

[0066] In the figure: 1 low n-value silicon nitride film, 2 aluminum oxide film, 3 silicon oxide film, 4 P-type silicon substrate, 5 Ag-Al or Ag back electrode, 6 Ag positive electrode, 7 Al back field, 8 Local-BSF P++ region, 9 emitter junction region, 10 N++SE heavily doped region, 11 electrode column, 12 higher n-value silicon nitride or silicon nitride oxide film, 13 spherical notch rather than conical pit. DETAILED DESCRIPTION

[0067] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0068] See also Figure 1-9 , the present invention provides a technical solution:

[0069] A solar cell with a composite dielectric passivation layer structure comprises a P-type silicon substrate 4, an emitter junction region 9 arranged on the upper side of the P-type silicon substrate 4, an N++SE heavily doped region 10 arranged between the emitter junction region 9 and the P-type silicon substrate 4, a silicon oxide film 3 wrapped around the P-type silicon substrate 4, a silicon nitride or silicon oxynitride film 12 with a relatively high n value wrapped around the front side of the silicon oxide film 3, an aluminum oxide film 2 wrapped around the back side of the silicon oxide film 3, and a silicon nitride film 1 with a relatively high n value wrapped around the entire surface of the silicon nitride or silicon oxynitride film 12 and the outer side of the aluminum oxide film 2.

[0070] A Local-BSF P++ region 8 is arranged on the other side of the P-type silicon substrate 4 having an emitter junction region 9, an Al back field 7 is arranged at the bottom of the low-n value silicon nitride film 1 on the entire surface, an Ag-Al back electrode or an Ag back electrode 5 is arranged on the Al back field 7, and an electrode column 11 is arranged on the Al back field 7. The electrode column 11 passes through the low-n value silicon nitride film 1 on the entire surface, the aluminum oxide film 2 on the back and the periphery, and the silicon oxide film 3 in sequence, and the top of the electrode column 11 is connected to the Local-BSF P++ region 8, and the Local-BSF P++ region 8 is composed of multiple spherical segments rather than conical pits 13.

[0071] A P-type silicon substrate 4 is provided with an N++SE heavily doped region 10 on one side thereof and an Ag positive electrode 6 penetrating the composite dielectric passivation film layer is provided. The Ag positive electrode 6 sequentially passes through the low n-value silicon nitride film 1, the higher n-value silicon nitride or silicon nitride oxide film 12, and the silicon oxide film 3 on the entire surface. One end of the Ag positive electrode 6 close to the P-type silicon substrate 4 is connected to the emitter junction region 9.

[0072] A preparation process of a solar cell with a composite dielectric passivation layer structure, wherein a silicon oxide film 3 and an aluminum oxide film 2 are sequentially deposited on the front, back and peripheral surfaces of a P-type silicon substrate, the front aluminum oxide film 2 is washed off and a silicon nitride or silicon nitride oxide film 12 with a higher n value is deposited, and then a silicon nitride film 1 with a low n value is deposited on both sides and the peripheral surface to form a laminated composite dielectric passivation layer, and an N++SE heavily doped region 10 is formed by laser doping on the front side, a Ag positive electrode 6 that penetrates the passivation film layer is matched and printed, and a window is partially opened on the back side for electrode extraction. The specific steps are as follows:

[0073] S1. Remove the damaged layer and make texturing: Pre-clean and make texturing for the P-type silicon substrate 4, remove the damaged layer of 3-5um on the surface of the P-type silicon substrate 4, reduce the recombination rate of photogenerated carriers, and make a velvet surface on the front surface of the P-type silicon substrate 4 to reduce the reflectivity. If the P-type silicon substrate 4 is a polycrystalline silicon wafer, acid texturing is adopted, and the solution used is a mixed solution of nitric acid, hydrofluoric acid and water, nitric acid: hydrofluoric acid: water = 2:1:2-5:1:2; if the P-type silicon substrate 4 is a single crystal silicon wafer, alkali texturing is adopted, and the solvent ratio is NaOH or KOH, isopropanol, single crystal silicon texturing additive and water. The P-type silicon substrate 4 is sequentially subjected to surface cleaning and micro-etching, alkali texturing, water washing tank 1, acid tank, water washing tank 2, alkali washing tank, water washing tank 3, acid tank, water washing tank 4 three chemical reaction tanks and three water washing tanks, and then the P-type silicon substrate 4 is blown dry;

[0074] S2. Diffusion to form a PN junction: Deposit a doping source on the surface of the above-mentioned P-type silicon substrate 4 and perform thermal diffusion to prepare a P-N junction. The doping source is phosphorus oxychloride and oxygen. Under high-temperature diffusion conditions, the heating time is 30 - 60 minutes. Phosphorus oxychloride will decompose, and the free phosphorus and oxygen will enter the surface of the silicon wafer to form a P-N junction; the free chlorine will form chlorine gas and be discharged together with the excess oxygen in the form of chlorine gas. During the diffusion process, POCl3 is carried by N2. Generally, the flow rate of the carrying N2 is 1000 - 2000 sccm, and the time is about 30 minutes. A total of about 20 g of POCl3 can be carried. The O2 flow rate is controlled at 1000 - 3000 sccm, the time is about 40 - 55 minutes, and the temperature is controlled at 830 - 870 °C;

[0075] S3. Laser SE doping: Use a laser with a wavelength of 532 nm to irradiate the diffused P-type silicon substrate 4, and perform local doping diffusion of phosphorus atoms in the surface phosphosilicate glass after diffusion through laser local heating ablation technology. The area ratio of this region is 4.5% - 8.5%, so as to form a selective low sheet resistance doped emitter (SE) on the surface of the P-type silicon substrate 4. The sheet resistance after laser doping is 50 - 90 Ω / sq;

[0076] S4. Etching and backside polishing: Since N-type layers are formed on both the front and back sides of the P-type silicon substrate 4 during the diffusion process and there is phosphosilicate glass on the surface, this process step mainly uses a mixed solution of HF, HNO3, and H2SO4 and the KOH / NaOH solution in the subsequent alkali tank to corrode and remove the backside N-type layer, and remove the phosphosilicate glass on the front side. In this process, the P-type silicon substrate 4 enters three chemical reaction tanks, namely an acidic etching tank, an alkali tank, and an acid pickling tank, in sequence and undergoes chemical reactions, and then the P-type silicon substrate 4 is dried to remove the backside PN junction, the peripheral PN junction, and the phosphosilicate glass layer; and the back surface of the P-type silicon substrate 4 is polished to a thickness of 3 - 8 μm to form a mirror structure and improve the backside light reflectivity;

[0077] S5. Oxidation annealing and silicon oxide deposition: a thin oxidized silicon oxide film 3 is deposited on the front, back and periphery of the P-type silicon substrate 4. The following methods can be used, such as dry oxygen thermal oxidation, ozone oxidation, N2O oxidation, and nitric acid gas oxidation. The thin oxidation annealing process is preferably used. After the above process, the phosphorus content on the surface of the P-type silicon substrate 4 is certain, and the surface concentration of phosphorus is high. High phosphorus will aggravate the recombination of minority carriers, which has an adverse effect on the conversion efficiency of the battery. The unactivated phosphorus can be further activated through the annealing process to reduce the surface concentration of phosphorus, thereby reducing the surface recombination of minority carriers and improving the conversion efficiency of the battery. In addition, during the annealing process, a suitable amount of oxygen is introduced to form a dense 1.5-8nm full-surface covering oxide layer (SiO2 contains H) on the surface of the silicon wafer, and its refractive index is controlled at 1.45-1.65, which can passivate the dangling bonds on the surface of the silicon wafer well: because SiO2 has better matching with Si, it can effectively reduce the interface state density on the Si surface, thereby increasing the chemical passivation effect; Si in SiO2 is a tetrahedral structure, and the source of the negative charge on the surface of Al2O3 is AlO4 in a tetrahedral configuration - , the presence of SiO2 is conducive to the formation of an aluminum oxide layer with a high negative charge density, thereby improving the field passivation effect of Al2O3;

[0078] S6, aluminum oxide deposition: The aluminum oxide film 2, i.e. the second layer of high-density passivation film, uses aluminum-containing precursors (typical aluminum precursors are aluminum chloride, trimethylaluminum, triethylaluminum, dimethylaluminum chloride, aluminum ethoxide, aluminum isopropoxide) to form deposition by atomic layer deposition (ALD), PECVD, CVD, or solid target material is formed by PVD formation and other methods. Its function is to contain a large amount of fixed negative charges, which can not only chemically passivate the dangling bonds on the surface of the silicon wafer, but also have a field passivation effect. Preferably, 2 layers of aluminum oxide film with a film thickness of 3-8nm are grown by atmospheric chemical deposition ALD at 230-280℃, with a refractive index of 1.58-1.73 and a reaction time of 25-35min. It grows one level at the atomic level on the front and back surfaces of the silicon wafer, so that it has good step coverage for different surface undulations;

[0079] S7, removal of aluminum oxide on the front side: The aluminum oxide film 2 diffracted by atomic-level growth to the front side of the P-type silicon substrate 4 is cleaned and removed using a wet chemical solution. HCl reacts with Al2O3 but does not react with SiO2, which has more stable chemical properties. This process can be implemented by equipment such as RENA, SCHMID and RCT. The aluminum oxide film 2 on the front side of the P-type silicon substrate 4 is immersed in an online roller trough device and removed on one side by floating on water or roller with liquid. The P-type silicon substrate 4 is sequentially placed in an acid washing tank with 5%-20% diluted HCl for acid washing, and in a water washing tank with DI water to clean the residual acid on the surface. The two chemical reaction tanks react chemically, and then the P-type silicon substrate 4 is dried to remove the excess 3-8nm of aluminum oxide film 2 on the front side;

[0080] S8, Silicon nitride deposition: Evaporate anti-reflection protective film on the front and back of the silicon wafer. It is recommended to use PECVD silicon nitride film as the capping layer and optical anti-reflection and anti-reflection functional layer (both CVD and PVD can be produced). Other materials with large refractive index, compatible with silicon processing technology, and good interface properties with silicon, as well as visible light transparent dielectric materials, including but not limited to TiO2, SiN x C y or SiN x O y As an alternative, the front and back PECVD low n-value silicon nitride film 1 adopts a 360-480℃ low pressure environment, and applies a radio frequency electric field to the injected ammonia and silane gases to ionize the gases and generate plasma. The high-energy particle flow hits the reactive gas adsorbed on the surface of the silicon wafer, breaking the reactive gas bonding bonds and becoming active substances. These active substances react to form SiN x :H film is applied to the surface of the silicon wafer, thereby achieving the expected capping protection and optical effect. The refractive index of the front high n-value silicon nitride or silicon oxynitride film 12 is controlled at 2.06-2.38, and the film thickness is controlled at 8-60nm; the refractive index of the front low n-value silicon nitride film 1 is controlled at 1.86-2.2, and the film thickness is controlled at 12-72nm; the refractive index of the back and surrounding full surface covered low n-value silicon nitride film 1 is controlled at 1.86-2.36, and the film thickness is controlled at 90-200nm;

[0081] Tubular PECVD is preferred, the high n-value silicon nitride or silicon oxynitride film 12 on the front side and the low n-value silicon nitride film 1 on the front side are coated once, and the front and back sides are coated in batches (the vacuum needs to be broken to take out the film and then turned over during the batch process), and the coating order of the front and back sides can be changed;

[0082] The high refractive index dense silicon nitride or silicon oxynitride film can effectively prevent the subsequent products of sodium ions, -OH and -CH3 groups from migrating into the battery, avoiding leakage of battery components and causing power attenuation, while the low n-value silicon nitride film 1 can prevent the mobile ions in the passivation layer from moving under the external electric field and temperature and humidity to a certain extent, thus enhancing the anti-PID effect;

[0083] S9, laser grooving: Since the laminated film formed by the above process is a dense insulating dielectric film layer, the currently matched front silver paste can penetrate but the back aluminum paste cannot be directly burned through, so it is impossible to form the back P+ contact area and lead the current from the back of the silicon wafer. A 532-1064nm ps or ns laser is used to locally groove the back of the p-type silicon substrate 4 of the above laminated coating. The grooved area accounts for 0.5%-6%. The grooved pattern includes but is not limited to a linear, cross, dash, square, diamond and hexagonal shape. The local laminated film is removed to form an Al back field 7 in the local area and lead the current, as shown in the attached manual. Figure 1 As shown, electrodes of a battery are formed;

[0084] S10, back electrode screen printing: screen printing Ag-Al or Ag back electrode 5 on the back of the solar cell prepared by the above process and drying it, which is consistent with the conventional BSF process;

[0085] S11, aluminum back field screen printing: match the laser slotting pattern in process step S9, screen print thick film aluminum paste on the non-Ag-Al or Ag back electrode 5 area on the back and dry to obtain Al back field 7, with a thickness of 10-30um and a distance of 0.8-1.6mm from the edge;

[0086] S12, positive electrode screen printing: screen printing a proprietary Ag paste on the front of the solar cell made by the above process, the composition of which is different from the conventional one, matching the N++SE heavily doped area 10 on the front of the P-type silicon substrate 4, screen printing the Ag paste positive electrode 6 penetrating the composite passivation film layer and drying it, using the conventional screen printing process;

[0087] S13, sintering: remove organic matter, inorganic adhesive and a small amount of water, anneal and sinter to form a good ohmic contact: the printed battery is quickly dried, sintered and annealed at high temperature (IR heating 180-900°C), so that the Ag positive electrode 6 on the front side penetrates the laminated film and forms an ohmic contact with the emitter junction area 9, and the aluminum paste on the back side is melted and contacted with the P-type silicon substrate 4 to form a P+ back electric field. The back electric field can prevent minority carriers from diffusing to the back surface to participate in recombination, thereby reducing the recombination loss on the back surface and further increasing the opening voltage and current density of the battery;

[0088] S14, LID light decay: Reduce the light-induced decay (LID) of the cell through a light decay furnace or an electric injection furnace: Under strong light conditions, the furnace tube is heated to above 180 degrees, and the furnace processing time is greater than or equal to 2 minutes, which will make the boron and oxygen atoms combine into a steady state and no longer produce defects to capture minority carriers. The LID loss of PERC cells is about 3-6% when they are not treated. After being treated by the LID furnace process, the LID loss will drop to less than 2.5%;

[0089] S15, IV test: The test grading procedure is designed based on the optimal operating voltage, optimal operating current, maximum power, conversion efficiency, open circuit voltage, short circuit current, fill factor, etc. of the PERC battery. The performance parameters of the battery after the process is completed must be measured and graded by precise testing instruments.

[0090] Embodiment 1:

[0091] The present invention comprises the following specific steps:

[0092] (1) using a 40 g / L NaOH solution to remove a 4 μm mechanical damage layer on the surface of the single crystal P-type silicon substrate 4, cleaning the surface of the silicon wafer, and at the same time using a 18 g / L NaOH liquid to anisotropically etch the surface of the silicon wafer to form a 2-3 μm inverted pyramid velvet texture;

[0093] (2) In a diffusion furnace tube, POCl3 liquid source negative pressure diffusion is used to form a PN junction, the diffusion temperature is 830°C, the process time is 55min, and the diffusion square resistance is controlled at 130-150ohm / cm;

[0094] (3) Laser SE doping: On the diffused silicon wafer, the phosphorus atoms on the diffused surface phosphorus silicon glass are laser doped by 5.6% in the main grid and fine grid electrode areas that are subsequently screen-printed, forming a local heavily doped area with a sheet resistance of 70-80 ohm / cm2 in the concentrated diffusion area;

[0095] (4) Using HF:HNO3=35g / L:350g / L, the volumes of each component are HF:55.26L, HNO3:214.78L, DI water:173.80L, H2SO4:80L, the liquid flow rate in the reaction tank is 30L / min, the reaction temperature is 6-8°C, and the mixed solution is used to clean the back junction, and the back of the silicon wafer is polished to 6um to present a mirror structure and remove the peripheral PN junction. The alkaline tank (KOH concentration is 5%) neutralizes the acid and removes the porous silicon, and the mixed solution of HCl, HF (concentration is 5%) and DI water is used to clean the phosphosilicate glass;

[0096] (5) Dry oxygen is introduced into the annealing oxidation furnace to form a thin silicon oxide film 3 on the front and back sides and around the edge of the silicon wafer. The thickness of the silicon oxide is 3 nm and the refractive index is 1.48;

[0097] (6) trimethylaluminum is introduced into an ALD deposition furnace at 250° C. to adsorb and react with OH groups on the surface of the silicon wafer, and the thickness of the generated aluminum oxide film 2 is 5±1 nm;

[0098] (7) Using a roller-type liquid method, 10% dilute HCl was applied to the aluminum oxide film 2 on the front side of the P-type silicon substrate 4 to react for 17 minutes to remove the aluminum oxide film 2, and then DI water was used to clean the residual acid on the surface and dried;

[0099] (8) PECVD deposition of low n-value silicon nitride film 1 on the back: Silane (SiH4) and NH3 (ammonia) are deposited on the back and periphery of the silicon wafer by ionization reaction in a low-pressure 450°C chamber. The PECVD prepared silicon nitride film 1 has a thickness of 135 nm and a refractive index of 2.16.

[0100] (9) PECVD deposition of a low-n value silicon nitride film 1 and a high-n value silicon nitride or silicon oxynitride film 12 on the front side: The high-n value silicon nitride film 12 prepared by PECVD is deposited by ionization reaction of silane (SiH4) and NH3 (ammonia) in a low-pressure 430°C chamber on the front side of the silicon wafer. The thickness of the high-n value silicon nitride film 12 prepared by PECVD is 35 nm, and the refractive index n is: 2.18; the thickness of the low-n value silicon nitride film 1 prepared by PECVD is 45 nm, and the refractive index is: 2.14;

[0101] (10) A 532nm ns laser is used to locally groove the back side of the laminated P-type silicon substrate 4, where the groove area accounts for 3.2% and the groove pattern is a dotted line pattern with a real-dummy ratio of 85%;

[0102] (11) Screen print the Ag-Al back electrode on the back and dry it at 200°C; then screen print the Al paste on the back and dry it at 210°C, with a film thickness of 23um and a distance of 1.0mm from the edge;

[0103] (12) Turning the cell over, screen printing the main grid and the auxiliary grid of the Ag positive electrode 6, and drying at 220°C;

[0104] (13) After the battery cell is transferred to the sintering furnace, the organic matter, inorganic binder and a small amount of water in the slurry are volatilized and discharged, and the battery cell is quickly dried, sintered and annealed in a sintering furnace with a peak setting of 890°C. The positive and back electrodes are sintered once to form good ohmic contacts, and the IV characteristics are tested;

[0105] (14) The cells are passed through a light decay furnace and illuminated by a strong halogen lamp (0.8 Sun) at a temperature of 230°C to reduce the light induced degradation (LID) of the cells.

[0106] (15) Solar cell IV testing and sorting.

[0107] Embodiment 2:

[0108] The present invention comprises the following specific steps:

[0109] (1) using a 30 g / L NaOH solution to remove a 3.5 μm mechanical damage layer on the surface of the single crystal P-type silicon substrate 4, cleaning the surface of the silicon wafer, and at the same time anisotropically etching the surface of the silicon wafer with a 20 g / L NaOH liquid to form a 3-4 μm inverted pyramid velvet texture;

[0110] (2) In a diffusion furnace tube, POCl3 liquid source negative pressure diffusion is used to form a PN junction, the diffusion temperature is 850°C, the process time is 45 minutes, and the diffusion square resistance is controlled at 140-170 ohm / cm;

[0111] (3) Laser SE doping: On the diffused P-type silicon substrate 4, the phosphorus atoms on the diffused surface phosphorus silicon glass are laser doped by 5.2% in the main gate and fine gate electrode areas that are subsequently screen-printed, forming a local heavily doped area with a sheet resistance of 60-70 ohm / cm in the concentrated diffusion area;

[0112] (4) Using HF:HNO3=30g / L:330g / L, the volumes of each component are HF:45.58L, HNO3:184.16L, DI water:183.50L, H2SO4:70L, the liquid flow rate in the reaction tank is 32L / min, the reaction temperature is 6-8°C, and the mixed solution is used to clean the back junction, and the back of the P-type silicon substrate 4 is polished to 4.5um to present a mirror structure and remove the peripheral PN junction. The alkaline tank (NaOH concentration is 6%) neutralizes the acid and removes the porous silicon. The mixed solution of HCl, HF (concentration is 5%) and DI-water is used to clean the phosphosilicate glass and then hot air dry;

[0113] (5) An ozone generator is used to generate a layer of SiO2 with a thickness of 1.5 nm on the back of the P-type silicon substrate 4, and then dry oxygen is introduced into an annealing oxidation furnace to generate a thin layer of silicon oxide film 3 on the front, back and edge of the P-type silicon substrate 4. The thickness of the silicon oxide film 3 is 3.5 nm, and the refractive index is 1.52. At this time, the thickness of the silicon oxide film 3 on the front and the surrounding area is 3.5 nm, but the total thickness of the silicon oxide film 3 on the back is 5.0 nm;

[0114] (6) trimethylaluminum is introduced into an ALD deposition furnace at 230° C. to adsorb and react with OH groups on the surface of the silicon wafer to generate an aluminum oxide film 2 with a thickness of 3-5 nm;

[0115] (7) Using a RENA device, 15% diluted HCl was adsorbed onto the aluminum oxide film 2 on the front side of the P-type silicon substrate 4 by a water float method, and reacted for 12 minutes to remove it, and then the residual acid on the surface was cleaned with DI water and dried;

[0116] (8) PECVD deposition of a low-n value silicon nitride film 1 and a high-n value silicon nitride or silicon oxynitride film on the front side: The high-n value silicon oxynitride film 12 prepared by PECVD is deposited by ionization reaction of silane (SiH4), NH3 (ammonia) and N20 (laughing gas) on the front side of the silicon wafer in a low-pressure 440°C chamber, and the thickness of the film is 20nm, and the refractive index n is: 2.15; The low-n value silicon nitride film 1 prepared by PECVD is deposited by ionization reaction of silane (SiH4) and NH3 (ammonia) on the front side of the silicon wafer in a low-pressure 430°C chamber, and the thickness of the film is 58nm, and the refractive index is: 2.11;

[0117] (9) PECVD deposition of a low-n silicon nitride film 1 on the back side: The silicon nitride film 1 prepared by PECVD is deposited on the back side and around the silicon wafer by ionization reaction of silane (SiH4) and NH3 (ammonia) in a low-pressure 460°C chamber. The thickness of the silicon nitride film 1 is 150 nm and the refractive index is 2.12.

[0118] (10) A 1064 nm ps laser is used to locally groove the back side of the P-type silicon substrate 4 with the laminated coating, the groove area accounts for 2.8%, and the groove pattern is a continuous straight line pattern;

[0119] (11) Screen print the Ag back electrode on the back and dry it at 210°C; then screen print the Al paste on the back and dry it at 210°C, with a film thickness of 20 μm and a distance of 1.5 mm from the edge;

[0120] (12) Turning the cell over, screen printing the main grid and the auxiliary grid of the Ag positive electrode 6, and drying at 220°C;

[0121] (13) After the P-type silicon substrate 4 is conveyed through the sintering furnace, the organic matter, inorganic binder and a small amount of water in the slurry are volatilized and discharged, and the substrate is rapidly dried, sintered and annealed in a sintering furnace with a peak setting of 900° C. The front and back electrodes are both sintered once to form good ohmic contacts, and the IV characteristics are tested;

[0122] (14) The cells are subjected to auxiliary illumination for 1800-2400s at a temperature of 170-200°C and an injection current of 3.5-4A to reduce the light-induced degradation (LID) of the cells.

[0123] (15) Solar cell IV testing and sorting.

[0124] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A process for preparing a composite dielectric passivation layer structure solar cell, characterized in that: Preparing a P-type silicon substrate (4); An N-type emitter junction region (9), a silicon oxide film (3), a relatively high n-value silicon nitride or silicon oxynitride film (12), and a low n-value silicon nitride film (1) are sequentially deposited on the front surface of a P-type silicon substrate (4); a silicon oxide film (3), an aluminum oxide film (2), and a low n-value silicon nitride film (1) are sequentially deposited on the back surface and the periphery to form a full-surface laminated composite dielectric passivation film layer; the refractive index n value of the relatively high n-value silicon nitride or silicon oxynitride film (12) is controlled to be between 2.15 and 2.18, and the refractive index n value of the low n-value silicon nitride film (1) on the front surface is controlled to be between 2.11 and 2.14; The front side of the laminated P-type silicon substrate (4) is laser doped to form an N++SE heavily doped region (10), and a Ag positive electrode (6) that penetrates the composite dielectric passivation film layer is printed and matched, and a window is partially opened on the back side for electrode extraction.

2. The process for preparing a solar cell with a composite dielectric passivation layer structure according to claim 1, characterized in that: Multiple layers of full-surface composite dielectric passivation film layers are sequentially deposited on the front side, back side and periphery of the P-type silicon substrate (4), and specifically include: Oxidation annealing silicon oxide deposition: using any one of dry oxygen thermal oxidation, ozone oxidation, N2O oxidation or nitric acid oxidation processes to form a full-surface silicon oxide film (3) on the front, back and periphery of the P-type silicon substrate (4), and introducing oxygen during the annealing process to fully cover the surface of the P-type silicon substrate (4) to form a 1.5-8nm full-surface silicon oxide film (3), whose refractive index n value is controlled to be 1.4-1.65; Aluminum oxide deposition: using any one of ALD, PECVD, CVD deposition or solid target material PVD formation processes, a layer of 3-30nm thick aluminum oxide film (2) is formed on the front, back and periphery of the P-type silicon substrate (4), and its refractive index n value is controlled at 1.58-1.76, and the generation time is 25-35min. The aluminum oxide film (2) diffracted to the front is washed away by a wet chemical solution; The aluminum oxide film (2) on the front side is removed on one side by an online roller trough type device, and pickled with 5%-20% diluted HCl to remove the aluminum oxide film (2) formed on the front surface of the silicon oxide film (3), and then the residual acid on the surface is cleaned with DI water, and then blown dry with an air knife; Silicon nitride deposition: using a tubular PECVD process, first depositing a silicon nitride or silicon nitride oxide film (12) with a relatively high n value on the front side of a P-type silicon substrate (4), and then generating a layer of a silicon nitride film (1) with a low n value covering the entire surface on the front side, the back side and the periphery of the P-type silicon substrate (4), the temperature of the tubular PECVD process being 360-480° C., injecting ammonia and silane, adding nitrous oxide when depositing the silicon nitride oxide film, and applying a radio frequency electric field; The thickness of the silicon nitride or silicon nitride oxide film (12) with a higher n value on the front side is set to be controlled within a range of 8-60 nm; The thickness of the low n-value silicon nitride film (1) on the front side is set to be controlled within a range of 12-72 nm; The low-n silicon nitride film (1) covering the entire back surface and the surrounding surface is set to have a refractive index n value controlled within a range of 1.86-2.36 and a film thickness controlled within a range of 90-200 nm; The front silicon amide or silicon oxynitride film (12) with a relatively high n value and the front silicon nitride film (1) with a low n value are set to be coated once, and when depositing the silicon oxynitride film, laughing gas is first added and then turned off; The low n-value silicon nitride film (1) on the front and back sides is plated in batches, and the order of the plated in batches is to plate the front side first and then the back side, or to plate the back side first and then the front side. During the process of the plated in batches, the vacuum needs to be broken to take out the film and then turn it over.

3. The process for preparing a solar cell with a composite dielectric passivation layer structure according to claim 1, characterized in that: Preparing a P-type silicon substrate (4), specifically comprising: S1, removing the damaged layer and making a texture: cleaning and making a texture on the P-type silicon substrate (4), removing the damaged layer of 3-5 μm on the surface of the P-type silicon substrate (4), and making a textured surface on the front surface of the P-type silicon substrate (4); S2, diffusion to form PN junction: depositing a doping source on the surface of a P-type silicon substrate (4) and performing thermal diffusion to form a PN junction region, wherein the doping source is phosphorus oxychloride and oxygen, and the heating time is 30-60 minutes; S3, laser SE doping: using a laser with a wavelength of 532 nm to irradiate the diffused P-type silicon substrate (4) to form a localized heavily doped region, wherein the area of ​​the N++SE heavily doped region (10) accounts for 4.5% to 8.5%; S4, etching and backside polishing: the P-type silicon substrate (4) is sequentially etched, cleaned and backside polished, with the backside polishing thickness being 3-8 μm.

4. The process for preparing a composite dielectric passivation layer structure solar cell according to claim 1, characterized in that: Laser grooving: using a 532nm-1064nm ps or ns laser to locally groove the back of the above-mentioned laminated P-type silicon substrate (4), with the grooved area accounting for 0.5%-6%; Back electrode screen printing: screen printing an Ag-Al or Ag back electrode (5) on the back of the P-type silicon substrate (4) prepared above and drying it; Aluminum back field screen printing: corresponding to the local grooved area on the back side, aluminum paste is screen printed on the non-Ag-Al or Ag back electrode (5) area on the back side of the P-type silicon substrate (4) and dried to form an Al back field (7) with a thickness of 10-30 μm and a distance of 0.8-1.6 mm from the edge; Positive electrode screen printing: The front side of the P-type silicon substrate (4) is matched with the N++SE heavily doped region (10), and the Ag positive electrode (6) penetrating the composite passivation film layer is screen printed and dried.

5. The process for preparing a solar cell with a composite dielectric passivation layer structure according to claim 1 or 3, characterized in that: Preparing a P-type silicon substrate (4), further comprising: If the P-type silicon substrate (4) is a polycrystalline cell, acid texturing is used, and the solution used is a mixed solution of nitric acid, hydrofluoric acid and water, with nitric acid: hydrofluoric acid: water = 2:1:2-5:1:2; If the P-type silicon substrate (4) is a single-product battery cell, alkali texturing is adopted, and the solvent ratio is NaOH or KOH, isopropanol, single-product silicon texturing additive and water.

6. The process for preparing a composite dielectric passivation layer structure solar cell according to claim 3, characterized in that: In step S2, phosphorus oxychloride is carried by nitrogen with a nitrogen flow rate of 1000-2000 sccm for 25-35 minutes, an oxygen flow rate of 1000-3000 sccm for 40-55 minutes, and a temperature controlled at 830-870°C.

7. The process for preparing a composite dielectric passivation layer structure solar cell according to claim 3, characterized in that: In step S3, the sheet resistance of the N++SE heavily doped region (10) is 50-90Ω / □.

8. The process for preparing a solar cell with a composite dielectric passivation layer structure according to claim 3, characterized in that: In step S4, the back N-type layer is removed by etching with a mixed solution of HF, HNO3 and H2SO4 and a KOH / NaOH solution in a subsequent alkaline bath, and the phosphosilicate glass on the front is removed, and a 3-8 μm polishing process is performed on the back surface of the P-type silicon substrate (4).

9. The process for preparing a composite dielectric passivation layer structure solar cell according to claim 4, characterized in that: In the laser slotting step, the slotting pattern is any one of a line, a cross, a dash, a square, a diamond and a hexagon.

10. A solar cell with a composite dielectric passivation layer structure, prepared by the preparation process according to any one of claims 1 to 9, characterized in that: It comprises a P-type silicon substrate (4), and a fully-surface deposited silicon oxide film (3) sequentially covering the P-type silicon substrate (4), a front-side silicon nitride or silicon nitride oxide film (12) with a relatively high n value, a back-side and peripheral aluminum oxide film (2), and a fully-surface low-n value silicon nitride film (1); An emitter junction region (9) is arranged on the upper side of the P-type silicon substrate (4), and an N++SE heavily doped region (10) is arranged between the emitter junction region (9) and the P-type silicon substrate (4); The P-type silicon substrate (4) is provided with an emitter junction region (9) and the other side thereof is provided with a Local-BSF P++ region (8); the bottom of the low-n value silicon nitride film (1) is provided with an Al back surface field (7); the Al back surface field (7) is provided with an electrode column (11); the electrode column (11) sequentially passes through the low-n value silicon nitride film (1), the aluminum oxide film (2) on the back and the periphery, and the silicon oxide film (3) on the entire surface; the top of the electrode column (11) is connected to the Local-BSF P++ region (8).

11. A solar cell with a composite dielectric passivation layer structure according to claim 10, characterized in that: A Ag positive electrode (6) penetrating the composite dielectric passivation film layer is arranged on one side of the P-type silicon substrate (4) provided with an N++SE heavily doped region (10); the Ag positive electrode (6) sequentially passes through a low n-value silicon nitride film (1), a relatively high n-value silicon nitride or silicon oxynitride film (12) and a full-surface silicon oxide film (3); and one end of the Ag positive electrode (6) close to the P-type silicon substrate (4) is connected to an emitter junction region (9).

12. A composite dielectric passivation layer structure solar cell according to claim 10, characterized in that: An Ag-Al or Ag back electrode (5) is arranged on the Al back field (7).

13. A solar cell with a composite dielectric passivation layer structure according to claim 10, characterized in that: The Loca1-BSF P++ region (8) is composed of a plurality of spherical segments rather than conical pits (13).

Images