Vertical storage device and method of operating the same

Abstract

The present disclosure provides a vertical memory device and an operation method thereof. An operation method of a memory device is provided, the memory device including a plurality of strings on a substrate, where the plurality of strings include a main string connected to a bit line and a dummy string spaced apart from the bit line, the operation method including: pre-programming the dummy string; and erasing the main string and the dummy string, where pre-programming includes: applying a pre-programming voltage to a word line connected to the dummy string; applying a pass voltage to a ground selection line of a ground selection transistor connected to the dummy string; and applying a common source line voltage to a common source line connected to the dummy string.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0023285, filed on February 27, 2019, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical field

[0003] The inventive concept relates to a vertical memory device and an operating method thereof. Background art

[0004] In recent years, there has been a need for memory devices that are highly integrated and capable of storing a large amount of data. Vertical memory devices have been developed, which include three - dimensionally vertically arranged memory cells to improve integration. Due to the increased integration of memory devices, the memory devices are scaled down, resulting in a change in their structure. It has been found that these structural changes can damage the strings in the memory device and thus damage the data stored in the memory device. Summary of the invention

[0005] According to an exemplary embodiment of the inventive concept, there is provided an operating method of a memory device including a plurality of strings on a substrate, wherein the plurality of strings include a main string connected to a bit line and a dummy string spaced apart from the bit line. The operating method includes: pre - programming the dummy string; and erasing the main string and the dummy string. The pre - programming includes: applying a pre - programming voltage to a word line connected to the dummy string; applying a pass voltage to a ground selection line of a ground selection transistor connected to the dummy string; and applying a common source line voltage to a common source line connected to the dummy string.

[0006] According to another exemplary embodiment of the inventive concept, there is provided a memory device including: a memory cell array including a plurality of strings, each string including a memory cell respectively connected to a word line vertically stacked on a substrate; control logic configured to sequentially perform a pre - programming operation and an erase operation on the plurality of strings, wherein the plurality of strings include a main string connected to a bit line and a dummy string spaced apart from the bit line, and for performing the pre - programming operation, the control logic applies a pre - programming voltage to at least one word line connected to the dummy string, applies a pass voltage to a ground selection line of a ground selection transistor connected to the dummy string, and applies a common source line voltage to a common source line connected to the dummy string.

[0007] According to another exemplary embodiment of the inventive concept, there is provided a memory device including: a memory cell array including a plurality of strings, each string including a memory cell respectively connected to a word line vertically stacked on a substrate; and control logic configured to perform a pre-programming operation on the plurality of strings, wherein the plurality of strings include a main string connected to a bit line and a dummy string spaced apart from the bit line, and the control logic applies a pre-programming voltage to the word line, applies a pass voltage to a ground selection line of a ground selection transistor connected to the dummy string, and applies a first common source line voltage to a common source line connected to the dummy string during the pre-programming operation, and the time of applying the pre-programming voltage to the word line, the time of applying the pass voltage to the ground selection line, and the time of applying the first common source line voltage to the common source line overlap with each other.

[0008] According to another exemplary embodiment of the inventive concept, there is provided an operation method of a memory device including a plurality of strings, wherein the plurality of strings include a first string connected to a first bit line among a plurality of bit lines and a second string not connected to a bit line, and the operation method includes: applying a pre-programming voltage to a word line connected to the second string; applying a pass voltage to a ground selection line of a ground selection transistor connected to the second string; and applying a common source line voltage to a common source line connected to the second string. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features of the inventive concept will be more clearly understood by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings, in which:

[0010] Figure 1 is a block diagram showing a memory device according to an exemplary embodiment of the inventive concept;

[0011] Figure 2A 、 2B and 2C are views for explaining the first memory block shown in Figure 1 according to an exemplary embodiment of the inventive concept;

[0012] Figure 3A is a flowchart showing an operation method of a memory device according to an exemplary embodiment of the inventive concept;

[0013] Figure 3B is a table showing voltage conditions during a pre-programming operation performed by a memory device according to an exemplary embodiment of the inventive concept;

[0014] Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 and Figure 8is a timing diagram of voltages applied to each line during a preprogramming operation and an erase operation performed by a memory device according to an exemplary embodiment of the inventive concept;

[0015] Figure 9 is a cross-sectional view of a memory block included in a memory device according to an exemplary embodiment of the inventive concept;

[0016] Figure 10A 、 10B and 10C are tables showing voltage conditions applied to word lines and virtual word lines when a memory device according to an exemplary embodiment of the inventive concept performs a preprogramming operation;

[0017] Figure 11A and 11B are for explaining according to an exemplary embodiment of the inventive concept Figure 1 a view of the first memory block shown in;

[0018] Figure 12A and 12B are tables showing voltage conditions applied to bit lines and virtual bit lines when a memory device according to an exemplary embodiment of the inventive concept performs a preprogramming operation; and

[0019] Figure 13 is a block diagram showing a case where a memory device according to an exemplary embodiment of the inventive concept is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0020] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. Like reference numerals may refer to like elements in the drawings.

[0021] Figure 1 is a block diagram showing a memory device 100 according to an exemplary embodiment of the inventive concept.

[0022] Referring to Figure 1 , the memory device 100 may include a memory cell array 110, a control logic 120, a voltage generator 130, a row decoder 140, and a page buffer 150. The memory device 100 may also include various other components related to memory operations. For example, the memory device 100 may include a data input / output circuit and an input / output interface.

[0023] The memory cell array 110 includes a plurality of memory cells and may be connected to word lines WL, string selection lines SSL, ground selection lines GSL, a common source line, and bit lines BL. The memory cell array 110 may be connected to the row decoder 140 via the word lines WL, the string selection lines SSL, and the ground selection lines GSL, and may be connected to the page buffer 150 via the bit lines BL.

[0024] For example, the plurality of memory cells included in the memory cell array 110 may be non-volatile memory cells that retain stored data even when their power supply is interrupted. In an exemplary embodiment of the inventive concept, when the memory cells are non-volatile memory cells, the memory device 100 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), etc. Hereinafter, an exemplary embodiment of the inventive concept in which the plurality of memory cells are NAND flash memory cells will be described. However, the inventive concept is not limited thereto.

[0025] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz. For example, each of the memory blocks BLK1 to BLKz may have a three-dimensional structure (or a vertical structure). In an exemplary embodiment of the inventive concept, each of the memory blocks BLK1 to BLKz may include a structure extending in first, second, and third directions. For example, each of the memory blocks BLK1 to BLKz may include a plurality of NAND strings (hereinafter, referred to as "strings") extending in the third direction. The plurality of strings may be spaced apart from each other by a certain distance in the first and second directions. The plurality of strings may include a cell string including a main cell storing data and a dummy string including dummy cells.

[0026] The memory blocks BLK1 to BLKz may be selected by the row decoder 140. For example, the row decoder 140 may select a memory block corresponding to a block address from the memory blocks BLK1 to BLKz. In an exemplary embodiment of the inventive concept, an erase operation may be performed in units of each of the memory blocks BLK1 to BLKz, and a pre-programming operation corresponding to the erase operation may be performed. However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, an erase operation may be performed in units of sub-memory blocks included in a single memory block, and a pre-programming operation corresponding to the erase operation may be performed.

[0027] Each memory cell included in the memory cell array 110 may be a multi-level cell (MLC) storing two or more bits of data. For example, the memory cell may be an MLC storing 2 bits of data. In an exemplary embodiment of the inventive concept, the memory cell may be a triple-level cell (TLC) storing 3 bits of data. However, the inventive concept is not limited thereto. In an exemplary embodiment of the inventive concept, some memory cells included in the memory cell array 110 may be single-level cells (SLCs) storing 1 bit of data, and other memory cells included in the memory cell array 110 may be MLCs.

[0028] The memory blocks BLK1 to BLKz may include SLC blocks including SLCs, MLC blocks including MLCs, or TLC blocks including TLCs. Among the plurality of memory blocks included in the memory cell array 110, some memory blocks may be SLC blocks, while other memory blocks may be MLC blocks or TLC blocks.

[0029] When an erase voltage is applied to the memory cell array 110, a plurality of memory cells may be in an erased state. When a program voltage is applied to the memory cell array 110, the plurality of memory cells may be in a programmed state. For example, when a pre-program voltage is applied to the memory cell array 110, the plurality of memory cells may be in a pre-programmed state. In this case, each memory cell may have an erased state E and at least one programmed state, which is identified according to a threshold voltage (V th ).

[0030] The control logic 120 may output various control signals for programming data into the memory cell array 110 or reading data from the memory cell array 110 based on a command CMD, an address ADDR, and a control signal CTRL sent by the memory controller. For example, the control logic 120 may output a voltage control signal CTRL_vol for controlling the levels of various voltages generated by the voltage generator 130. The control logic 120 may provide a row address X-ADDR to the row decoder 140 and a column address Y-ADDR to the page buffer 150.

[0031] The voltage generator 130 may generate various voltages used in the memory device 100, and may generate, for example, a word line voltage VWL, a string select line voltage VSSL, and a ground select line voltage VGSL. In an exemplary embodiment of the inventive concept, the voltage generator 130 may generate a common source line voltage and a substrate voltage, which will be applied to the substrate on which the memory cell array 110 is formed. In an exemplary embodiment of the inventive concept, the word line voltage VWL may include a pre-program voltage (e.g., Figure 3B Vprepro shown in Figure 3B ), and the ground select line voltage VGSL may include a pass voltage (e.g.,

[0032] Vpass shown in Figure 3B ). In response to the row address X-ADDR, the row decoder 140 may select at least one word line of the selected memory block. In an exemplary embodiment of the inventive concept, during a pre-program operation, the row decoder 140 may apply the pre-program voltage Vprepro as the word line voltage VWL to at least one word line among the word lines WL in response to the row address X-ADDR. During the pre-program operation, the row decoder 140 may apply the pass voltage Vpass as the ground select line voltage VGSL to at least one ground select line among the ground select lines GSL.

[0033] In an exemplary embodiment of the inventive concept, the memory cell array 110 may be connected to a virtual word line, and the row decoder 140 may selectively apply a pre-programming voltage Vprepro to the virtual word line during a pre-programming operation. In an exemplary embodiment of the inventive concept, during the pre-programming operation, the row decoder 140 may provide the pre-programming voltage Vprepro as a word line voltage VWL to the word line (e.g., virtual word line) of a selected memory cell in response to a row address X-ADDR, and may provide a word line pass voltage as the word line voltage VWL to the word line of an unselected memory cell.

[0034] In an exemplary embodiment of the inventive concept, the magnitude of the pre-programming voltage Vprepro may be different from the magnitude of a programming voltage applied to the word line WL to write data to a memory cell. For example, the pre-programming voltage Vprepro may have a level lower than the programming voltage. In an exemplary embodiment of the inventive concept, the memory device 100 may apply a plurality of programming pulses to the word line WL to write data to a memory cell during a programming operation and may apply a pre-programming voltage Vprepro having a single pulse to the word line WL during the pre-programming operation.

[0035] The page buffer 150 may function as a write driver or a sense amplifier. In an exemplary embodiment of the inventive concept, during the pre-programming operation, the page buffer 150 functions as a write driver and applies a bit line programming voltage to at least one of the bit lines BL.

[0036] The control logic 120 may control the voltage generator 130 and the row decoder 140 to perform a pre-programming operation and an erase operation. For example, when performing a pre-programming operation on a virtual string, the control logic 120 may control the voltage generator 130 and the row decoder 140 to apply a pass voltage Vpass to a ground selection line connected to the virtual string. In an exemplary embodiment of the inventive concept, the control logic 120 may control a ground voltage to be applied to a common source line connected to a memory block in which the pre-programming operation is performed.

[0037] During the pre-programming operation, the memory device 100 may perform a pre-programming operation on a virtual string by applying a ground voltage to a common source line, applying a pass voltage Vpass to a ground selection line, and applying a pre-programming voltage Vprepro to a word line. Even when the virtual string is not connected to a bit line, the memory device 100 may pre-program virtual cells in the virtual string. During the pre-programming operation, a threshold voltage distribution of virtual cells included in the virtual string may be shifted in a direction of increasing threshold voltage. The pre-programming operation on the virtual string is performed before or after an erase operation, thereby preventing virtual cells included in the virtual string from being damaged due to repeated erase operations.

[0038] Figures 2A to 2C is a view for illustrating the first memory block shown in Figure 1 the first memory block shown in Figure 2A is Figure 1 a top view of the first memory block shown in Figure 2B shows a cross-section taken along line A-A' shown in Figure 2A the cross-section taken along line A-A' shown in Figure 2C is a circuit diagram showing an equivalent circuit of region B of the memory block showing Figure 2A The memory block BLK1 may be a vertical NAND flash memory, and Figure 1 each of the memory blocks BLK1 to BLKz shown in Figures 2A to 2C may be implemented as shown in

[0039] Referring to Figure 2A , the memory block BLK1 may include word line cut regions WLC spaced apart from each other in a first direction X and extending in a second direction Y. In addition, the memory block BLK1 may include a plurality of vertical holes (e.g., Figure 2B main holes H11, H31, H61, and H81 and dummy holes DH1 in Figure 2B ) disposed between the word line cut regions WLC along the first direction X and the second direction Y. The vertical holes may include: main holes (e.g., Figures 2A to 2C H11, H31, H61, and H81 in

[0040] in which main cells for storing data are formed; and dummy holes DH that constitute dummy cells in which no data is stored. The number of vertical holes included in the memory block BLK1 may vary. In Figure 2A , the dummy holes DH are shown disposed in the central region of the memory block BLK1, but the inventive concept is not limited thereto, and the arrangement of the dummy holes DH may be changed. For example, the dummy holes DH may be disposed on the left or right side of the central region of the memory block BLK1.

[0041] The memory block BLK1 may be connected to bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, and BL8 extending in the second direction Y and spaced apart from each other in the first direction X. In Figure 2A , the memory block BLK1 is connected to eight bit lines, e.g., bit lines BL1 to BL8. However, the inventive concept is not limited thereto, and the number of bit lines may vary.

[0041] In an exemplary embodiment of the inventive concept, main holes may be respectively connected to corresponding bit lines, and a dummy hole DH may be electrically separated from bit lines BL1 to BL8. For example, a vertical hole connected to the first bit line BL1 is a main hole, and a main cell formed in the main hole may perform a data storage function. On the other hand, the dummy hole DH is a vertical hole not connected to the bit lines BL1 to BL8, and a storage cell (in other words, a dummy cell) formed in the dummy hole DH may not perform a data storage function.

[0042] Reference Figure 2B , a ground selection line GSL, a plurality of word lines WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, and a string selection line SSL may be disposed on a substrate SUB. An insulating film IL may be sequentially provided among the substrate SUB, the ground selection line GSL, the word lines WL1 to WL8, and the string selection line SSL. The main holes H11, H31, H61, and H81 and the dummy hole DH1 may extend in a third direction Z through the insulating film IL, the ground selection line GSL, the word lines WL1 to WL8, and the string selection line SSL. In Figure 2B , eight word lines (e.g., word lines WL1 to WL8) are shown, but the inventive concept is not limited thereto, and the number of word lines may vary. For example, surface layers I11, I13, I61, and I81 of the main holes H11, H31, H61, and H81 and a surface layer DI1 of the dummy hole DH1 may include a first type of silicon material and serve as channel regions. The surface layers I11, I13, I61, I81, and DI1 may include p-type silicon. However, the surface layers I11, I13, I61, I81, and DI1 may not be limited to including p-type silicon. For example, the surface layers I11, I13, I61, I81, and DI1 may include an intrinsic semiconductor as a non-conductor. Inner layers S11, S13, S16, and S81 of the main holes H11, H31, H61, and H81 and an inner layer DS1 of the dummy hole DH1 may include an insulating material such as silicon oxide or an air gap.

[0043] Each of the main holes H11, H31, H61, and H81 and each of the plurality of word lines WL1 to WL8 may form a main cell MC. For example, the main hole H31 and the word line WL1 may form a main cell MC. In an exemplary embodiment of the inventive concept, the dummy hole DH1 and each of the plurality of word lines WL1 to WL8 may form a dummy cell DC. For example, the dummy hole DH1 and the word line WL1 may form a dummy cell DC.

[0044] Since the dummy cells DC formed in the dummy holes DH1 are not connected to the bit lines BL1, BL3, BL6, and BL8, the dummy cells DC may not be programmed when voltages are applied to the bit lines BL1, BL3, BL6, and BL8. Accordingly, in the memory device according to an exemplary embodiment of the inventive concept, the dummy cells DC formed in the dummy holes DH1 may be pre-programmed by applying a ground voltage to a common source line formed on a substrate SUB, applying a pass voltage to a ground selection line GSL, and applying a pre-programming voltage to word lines WL1 to WL8. In an exemplary embodiment of the inventive concept, the memory device may pre-program at least some of the dummy cells DC formed in the dummy holes DH1 by selectively applying the pre-programming voltage to at least some of the word lines WL1 to WL8.

[0045] Since the ground voltage is applied to the common source line, the pass voltage is applied to the ground selection line GSL, and the pre-programming voltage is applied to the word lines WL1 to WL8, the main cells MC may also be pre-programmed together with the dummy cells DC.

[0046] Reference Figure 2A and 2C , the memory block BLK1 may include a plurality of cell strings NS41, NS42, and NS43 and NS51, NS52, and NS53, a plurality of dummy strings DS1, DS2, and DS3, a plurality of word lines WL1 to WL8, a plurality of bit lines BL4 and BL5, a plurality of ground selection lines GSL1, GSL2, and GSL3, a plurality of string selection lines SSL1, SSL2, and SSL3, and a common source line CSL. According to an exemplary embodiment of the inventive concept, the number of cell strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines in the memory block BLK1 may vary.

[0047] The cell strings NS41, NS42, and NS43 are disposed between the bit line BL4 and the common source line CSL, and the cell strings NS51, NS52, and NS53 may be disposed between the bit line BL5 and the common source line CSL. The dummy strings DS1, DS2, and DS3 may be connected to the common source line CSL but not to the bit lines.

[0048] Each of the cell strings NS41 to NS43 and NS51 to NS53 may include a string selection transistor SST, a plurality of main cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8, and a ground selection transistor GST, which are connected in series.

[0049] Cell strings commonly connected to a single bit line can form a column. For example, cell strings NS41, NS42, and NS43 commonly connected to bit line BL4 can correspond to a single column, and cell strings NS51, NS52, and NS53 commonly connected to bit line BL5 can correspond to another column.

[0050] Cell strings and dummy strings connected to a single string select line can form a row. For example, cell strings NS41 and NS51 and dummy string DS1 connected to string select line SSL1 can correspond to the first row, cell strings NS42 and NS52 and dummy string DS2 connected to string select line SSL2 can correspond to the second row, and cell strings NS43 and NS53 and dummy string DS3 connected to the third string select line SSL3 can correspond to the third row. In Figure 2C , string select lines SSL1 to SSL3 are shown as different lines, but the inventive concept is not limited thereto. String select lines SSL1 to SSL3 may be connected to each other to form a single string select line.

[0051] String select transistor SST may be connected to a corresponding string select line selected from string select lines SSL1 to SSL3. Main cells MC1 to MC8 may be respectively connected to word lines WL1 to WL8, and dummy cells DC1, DC2, DC3, DC4, DC5, DC6, DC7, and DC8 may be respectively connected to word lines WL1 to WL8.

[0052] Ground select transistor GST may be connected to a corresponding ground select line selected from ground select lines GSL1 to GSL3, and string select transistor SST may be connected to a corresponding bit line selected from bit lines BL1 to BL3. Ground select transistor GST may be connected to common source line CSL. In Figure 2C , ground select lines GSL1 to GSL3 are shown as different lines, but the inventive concept is not limited thereto. Ground select lines GSL1 to GSL3 may be connected to each other to form a single ground select line. Dummy strings DS1, DS2, and DS3 may each be connected to a dummy ground select transistor DGST.

[0053] Figure 3A is a flowchart illustrating an operation method of a memory device according to an exemplary embodiment of the inventive concept. Figure 3B is a table illustrating voltage conditions during a preprogramming operation performed by a memory device according to an exemplary embodiment of the inventive concept.

[0054] Referring to Figure 3A , in operation S10, the memory device (e.g., Figure 1 100 in Figure 1memory blocks (e.g., BLK1 to BLKz) in Figure 1 perform a pre-programming operation on a virtual string (e.g., BLK1 in

[0055] In an exemplary embodiment of the inventive concept, when virtual cells of a virtual string included in memory block BLK1 are pre-programmed, main cells of a main string included in memory block BLK1 may also be pre-programmed. In an exemplary embodiment of the inventive concept, only virtual cells of the virtual string included in memory block BLK1 are pre-programmed, and main cells of the main string included in memory block BLK1 may not be pre-programmed. Operations of selectively pre-programming virtual cells of a virtual string will be described later with reference to Figure 12B description of selectively pre-programming virtual cells of a virtual string.

[0056] Referring to Figure 3A and 3B , to perform the pre-programming operation, the memory device may apply a pre-programming voltage Vprepro to the word line WL. For example, the memory device 100 may apply the pre-programming voltage Vprepro to the word line WL connected to the virtual string on which the pre-programming operation is to be performed.

[0057] The memory device 100 may apply a pass voltage Vpass to the ground selection line GSL connected to the virtual string, and apply a first common source line voltage (e.g., ground voltage Vss) to the common source line CSL. The pass voltage Vpass may be a voltage for turning on a ground selection transistor (e.g., Figure 2C GST in Figure 2B . Thus, since the pass voltage Vpass is applied to the ground selection line GSL, the ground selection transistor GST is turned on, and the ground voltage Vss may be applied to the source of the virtual cell. Although the bit line voltage is not applied to the virtual string because the bit line is not connected to the virtual string, since the ground voltage Vss is applied to the common source line CSL and the pass voltage Vpass is applied to the ground selection line GSL, virtual cells included in the virtual string may be pre-programmed. In this regard, a ground voltage may be applied to the substrate (e.g.,

[0058] Referring to Figure 3A, in operation S20, the memory device 100 may perform an erase operation on a plurality of memory cells including virtual strings that have been pre-programmed thereon. For example, the memory device 100 may perform an erase operation on memory block BLK1 among memory blocks BLK1 to BLKz, and may erase data stored in main cells of cell strings included in memory block BLK1. In an exemplary embodiment of the inventive concept, for example, the memory device 100 may perform an erase operation on a part of memory block BLK1, and data stored in main cells of cell strings included in this part of memory block BLK1 may be erased.

[0059] In operation S30, the memory device 100 may perform an operation of verifying the erase operation. In an exemplary embodiment of the inventive concept, the memory device 100 may perform a verification operation on main cells included in memory block BLK1 on which operations S10 and S20 have been performed. For example, it is verified whether the threshold voltage distribution of main cells included in memory block BLK1 on which operations S10 and S20 have been performed has shifted to an erase verification voltage or lower. In an exemplary embodiment of the inventive concept, the memory device 100 may perform a verification operation on main cells included in this part of memory block BLK1 on which operations S10 and S20 have been performed. When the memory device 100 determines that the erase is not complete, the memory device 100 may perform operation S30 again. After operation S30, the memory device 100 may also perform a programming operation for programming main cells that have had their data erased with new data.

[0060] In an exemplary embodiment of the inventive concept, the memory device 100 may perform operation S20 after operation S10. In an exemplary embodiment of the inventive concept, the memory device 100 may perform operation S10 after sequentially performing operations S20 and S30. When operation S10 is performed after operation S30, in operation S10, only virtual cells of the pre-programmed virtual string are pre-programmed, and the main cells of the main string may not be pre-programmed. When operation S10 is performed after operation S30, the memory device 100 may also further perform a programming operation for programming main cells that have had their data erased with new data after operation S10.

[0061] Exemplary embodiments of the inventive concept have been described, in which operations S10 and S20 are performed in units of memory blocks. However, in the exemplary embodiments of the inventive concept, operations S10 and S20 may be performed in units of sub-memory blocks that are part of a memory block. For example, the memory device 100 may perform a pre-programming operation on a virtual string included in a part (e.g., a sub-memory block) of the memory block BLK1, and in this case, the main cells of the main string included in this part (e.g., the sub-memory block) of the first memory block BLK1 may also be pre-programmed. In the exemplary embodiments of the inventive concept, the memory device 100 may perform an erase operation on this part (e.g., the sub-memory block) of the memory block BLK1.

[0062] The memory device 100 according to an exemplary embodiment of the inventive concept may perform a pre-programming operation (S10) on a virtual string before or after an erase operation (S20), thereby preventing the virtual string from being damaged due to repeated erase operations on virtual cells included in the virtual string.

[0063] Figures 4 to 8 is a timing diagram of voltages applied to each line during a pre-programming operation and an erase operation performed by a memory device according to an exemplary embodiment of the inventive concept. Figures 4 to 8 is for explaining Figure 3A the operations S10 and S20 of

[0064] Referring to Figure 4 , in the pre-programming operation, the memory device (e.g., Figure 1 the memory device 100 in

[0065] A section where a pre-programming voltage Vprepro is applied to a word line WL and a section where a pass voltage Vpass is applied to a ground selection line GSL may overlap. For example, at a time point Tpre when the pre-programming voltage Vprepro is applied to the word line WL, the pass voltage Vpass may be applied to the ground selection line GSL. In an exemplary embodiment of the inventive concept, at a time point Tpf when the word line WL floats at the pre-programming voltage Vprepro, the ground selection line GSL may float at the pass voltage Vpass. In an exemplary embodiment of the inventive concept, a section where the pre-programming voltage Vprepro is applied to the word line WL may match a section where the pass voltage Vpass is applied to the ground selection line GSL. For example, the pre-programming voltage Vprepro and the pass voltage Vpass may be applied simultaneously.

[0066] In an exemplary embodiment of the inventive concept, a section where the pre-programming voltage Vprepro is applied to a word line WL and a section where a first common source line voltage (e.g., a ground voltage Vss) is applied to a common source line CSL may overlap. For example, at a time point Tpre when the pre-programming voltage Vprepro is applied to the word line WL, the ground voltage Vss may be applied to the common source line CSL. In an exemplary embodiment of the inventive concept, at a time point Tpf when the word line WL floats at the pre-programming voltage Vprepro, the common source line CSL may float at the ground voltage Vss. In an exemplary embodiment of the inventive concept, a section where the pre-programming voltage Vprepro is applied to the word line WL may match a section where the ground voltage Vss is applied to the common source line CSL. For example, the pre-programming voltage Vprepro and the ground voltage Vss may be applied simultaneously.

[0067] During an erase operation, the memory device 100 may apply a word line erase voltage Vwers to the word line WL, may apply a ground erase voltage Vgers to the ground selection line GSL, and may apply an erase voltage Vers to the common source line CSL. In this case, the word line erase voltage Vwers may be the ground voltage Vss or may have a level close to the ground voltage Vss. The intensity of the ground erase voltage Vgers may be lower than the intensity of the erase voltage Vers by a certain level. For example, depending on the level of the erase voltage Vers applied to the common source line CSL, the memory device 100 may apply the ground erase voltage Vgers to the ground selection line GSL. During the erase operation performed by the memory device 100, the erase voltage Vers may be applied to the substrate SUB.

[0068] Reference Figure 5, a section where a pre-programming voltage Vprepro is applied to a word line WL and a section where a pass voltage Vpass is applied to a ground selection line GSL may overlap. In an exemplary embodiment of the inventive concept, a time point Tgf at which the ground selection line GSL floats at the pass voltage Vpass may be different from a time point Tpf at which the word line WL floats at the pre-programming voltage Vprepro. For example, the time point Tgf at which the ground selection line GSL floats at the pass voltage Vpass may occur before the time point Tpf at which the word line WL floats at the pre-programming voltage Vprepro. Accordingly, the section where the pass voltage Vpass is applied to the ground selection line GSL may be shorter than the section where the pre-programming voltage Vprepro is applied to the word line WL. In other words, the pass voltage Vpass may be applied for a time shorter than the pre-programming voltage Vprepro. However, in an exemplary embodiment of the inventive concept, the section where the pass voltage Vpass is applied to the ground selection line GSL may be longer than the section where the pre-programming voltage Vprepro is applied to the word line WL. In other words, the pass voltage Vpass may be applied for a time longer than the time for applying the pre-programming voltage Vprepro.

[0069] Reference Figure 6 , a section where a pre-programming voltage Vprepro is applied to a word line WL and a section where a pass voltage Vpass is applied to a ground selection line GSL may overlap. In an exemplary embodiment of the inventive concept, a time point Tpre at which the pre-programming voltage Vprepro is applied to the word line WL may be different from a time point Tgp at which the pass voltage Vpass is applied to the ground selection line GSL. For example, the time point Tpre at which the pre-programming voltage Vprepro is applied to the word line WL may occur before the time point Tgp at which the pass voltage Vpass is applied to the ground selection line GSL. Accordingly, the section where the pass voltage Vpass is applied to the ground selection line GSL may be shorter than the section where the pre-programming voltage Vprepro is applied to the word line WL. However, in an exemplary embodiment of the inventive concept, the section where the pass voltage Vpass is applied to the ground selection line GSL may be longer than the section where the pre-programming voltage Vprepro is applied to the word line WL.

[0070] Reference Figure 7, a section where a pre-programming voltage Vprepro is applied to a section of a word line WL and a section where a first common source line voltage (e.g., a ground voltage Vss) is applied to a common source line CSL may overlap. In an exemplary embodiment of the inventive concept, a time point Tpre at which the pre-programming voltage Vprepro is applied to the word line WL may be different from a time point Tgp at which the ground voltage Vss is applied to the common source line CSL. For example, after the time point Tpre at which the pre-programming voltage Vprepro is applied to the word line WL, the ground voltage Vss may be applied to the common source line CSL, and at the time point Tgp at which a pass voltage Vpass is applied to a ground selection line GSL, the ground voltage Vss may be applied to the common source line CSL.

[0071] In an exemplary embodiment of the inventive concept, a section where the ground voltage Vss is applied to the common source line CSL may be shorter than a section where the pre-programming voltage Vprepro is applied to the word line WL. In other words, the ground voltage Vss may be applied for a time amount shorter than a time amount for applying the pre-programming voltage Vprepro. In an exemplary embodiment of the inventive concept, a section where the ground voltage Vss is applied to the common source line CSL and a section where the pass voltage Vpass is applied to the ground selection line GSL may overlap, e.g., may match each other. For example, the ground voltage Vss and the pass voltage Vpass may be applied for the same time amount. However, in an exemplary embodiment of the inventive concept, a section where the ground voltage Vss is applied to the common source line CSL may be longer than a section where the pre-programming voltage Vprepro is applied to the word line WL.

[0072] In an exemplary embodiment of the inventive concept, a second common source line voltage Vcsl may be applied to the common source line CSL before the ground voltage Vss is applied to the common source line CSL. Applying the second common source line voltage Vcsl to the common source line CSL may prevent any damage to the common source line CSL due to a pre-programming operation when a ground selection transistor connected to the ground selection line GSL is turned off.

[0073] Reference Figure 8, a section where a pre-programming voltage Vprepro is applied to a word line WL and a section where a first common source line voltage (e.g., a ground voltage Vss) is applied to a common source line CSL may overlap. In an exemplary embodiment of the inventive concept, a time point Tpre at which the pre-programming voltage Vprepro is applied to the word line WL may be different from a time point at which the ground voltage Vss is applied to the common source line CSL. For example, after the time point Tpre at which the pre-programming voltage Vprepro is applied to the word line WL, the ground voltage Vss may be applied to the common source line CSL. For example, at the time point Tpre at which the pre-programming voltage Vprepro is applied to the word line WL, the ground voltage Vss may be applied to the common source line CSL, and after a period of time, a second common source line voltage Vcs1 may be applied to the common source line CSL. For example, at a time point Tgf at which a ground selection line GSL is floating, the second common source line voltage Vcsl may be applied to the common source line CSL.

[0074] In an exemplary embodiment of the inventive concept, a section where the ground voltage Vss is applied to the common source line CSL may be shorter than a section where the pre-programming voltage Vprepro is applied to the word line WL. In an exemplary embodiment of the inventive concept, a section where the ground voltage Vss is applied to the common source line CSL and a section where a pass voltage Vpass is applied to a ground selection line GSL may overlap. For example, the pass voltage Vpass and the ground voltage Vss may be applied simultaneously. However, in an exemplary embodiment of the inventive concept, a section where the ground voltage Vss is applied to the common source line CSL may be longer than a section where the pre-programming voltage Vprepro is applied to the word line WL.

[0075] The inventive concept is not limited to the pre-programming operation described in conjunction with Figure 4 and Figure 8 A section where the pre-programming voltage Vprepro is applied to the word line WL, a section where the pass voltage Vpass is applied to the ground selection line GSL, and a section where the ground voltage Vss is applied to the common source line CSL may overlap. To perform the pre-programming operation, in the memory device 100, the time point Tpre at which the pre-programming voltage Vprepro is applied to the word line WL and the length of a section where the pre-programming voltage Vprepro is applied to the word line WL may vary, the time point at which the pass voltage Vpass is applied to the ground selection line GSL and the length of a section where the pass voltage Vpass is applied to the ground selection line GSL may vary, and the time point at which the ground voltage Vss is applied to the common source line CSL and the length of a section where the ground voltage Vss is applied to the common source line CSL may vary.

[0076] Figure 9It is a cross-sectional view of a memory block included in a memory device showing an exemplary embodiment according to the inventive concept. Figure 9 It shows a cross-section taken along Figure 2A the line A-A' shown in. In the embodiment described in conjunction with Figure 9 the description provided in conjunction with Figure 2B can be omitted.

[0077] Referring to Figure 9 , the ground selection line GSL, the virtual word line DWL1, the plurality of word lines WL1 to WL7, and the string selection line SSL may be arranged on the substrate SUB. In an exemplary embodiment of the inventive concept, the virtual word line DWL1 may be arranged adjacent to the ground selection line GSL. Although one virtual word line and seven word lines are shown in Figure 9 , the inventive concept is not limited thereto. The number of virtual word lines and word lines may vary. In an exemplary embodiment of the inventive concept, the virtual word line DWL1 may be arranged adjacent to the string selection line SSL.

[0078] In an exemplary embodiment of the inventive concept, each of the virtual holes DH1 and the plurality of word lines WL1 to WL7 may form a virtual cell DC. For example, the virtual hole DH1 and the word line WL1 may form a virtual cell DC. In an exemplary embodiment of the inventive concept, the virtual hole DH1 and the virtual word line DWL1 may form a virtual cell DCa, and each of the main holes H11, H31, H61, and H81 and the virtual word line DWL1 may form a virtual cell DCb. The virtual cells DC, DCa, and DCb may be memory cells in which no data is written.

[0079] The main cell MC, the virtual cell DCb, the ground selection transistor, and the string selection transistor formed in each of the main holes H11, H31, H61, and H81 may constitute a cell string for each hole. The virtual cells DC and DCa, the ground selection transistor, and the string selection transistor formed in the virtual hole DH1 may constitute a virtual string.

[0080] Since the virtual cells DC and DCa formed in the virtual hole DH1 are not connected to the bit lines BL1, BL3, BL6, and BL8, the virtual cells DC and DCa may not be programmed when a voltage is applied to the bit lines BL1, BL3, BL6, and BL8. Therefore, in the memory device according to an exemplary embodiment of the inventive concept, the virtual cells DC and DCa formed in the virtual hole DH1 may be pre-programmed by applying a ground voltage to the common source line, applying a pass voltage to the ground selection line GSL, and applying a pre-programming voltage to the word lines WL1 to WL7. In this case, a ground voltage may be applied to the substrate SUB.

[0081] In an exemplary embodiment of the inventive concept, a memory device may pre-program at least some of the dummy cells DC and DCa formed in the dummy hole DH1 by selectively applying a pre-program voltage to at least some of the dummy word line DWL1 and the word lines WL1 to WL7. A case of selectively applying the pre-program voltage to the dummy word line DWL1 and some of the word lines WL1 to WL7 will be described in conjunction with Figure 10B and Figure 10C .

[0082] Since a ground voltage is applied to the common source line, a pass voltage is applied to the ground selection line GSL, and a pre-program voltage is applied to the word lines WL1 to WL7, the main cell MC is also pre-programmed together with the dummy cells DC and DCa. In addition, dummy cells DCb formed in the main holes H11, H31, H61, and H81 instead of the dummy hole DH1 may be pre-programmed.

[0083] Figures 10A to 10C is a table showing voltage conditions applied to word lines and dummy word lines when a memory device according to an exemplary embodiment of the inventive concept performs a pre-program operation.

[0084] Referring to Figure 9 and Figure 10A , to perform a pre-program operation (e.g., Figure 3A operation S10), a memory device (e.g., Figure 1 memory device 100) may apply a pre-program voltage to the word line WL and the dummy word line DWL1. In an exemplary embodiment of the inventive concept, the memory device 100 may apply a pre-program voltage Vprepro to all word lines (e.g., first to seventh word lines WL1 to WL7 and dummy word line DWL1) connected to a dummy string to be pre-programmed. In other words, a pre-program operation may be performed on all main cells and dummy cells included in a memory block.

[0085] The memory device 100 may apply a pass voltage to the ground selection line GSL connected to the dummy string and apply a ground voltage to the common source line CSL to perform a pre-program operation. The description provided in conjunction with Figures 4 to 8 may be applied to the time point at which a pass voltage is applied to the ground selection line GSL and the time point at which a ground voltage is applied to the common source line CSL.

[0086] Referring to Figure 9 and Figure 10B, the memory device 100 may apply a pre-programming voltage to the selected virtual word line DWL1 for performing a pre-programming operation, and apply a word line pass voltage Vwp to the unselected word lines. In other words, the memory device 100 may selectively perform a pre-programming operation. In an exemplary embodiment of the inventive concept, the memory device 100 may perform a pre-programming operation on the virtual cells DCa and DCb connected to the virtual word line DWL1, and may not perform a pre-programming operation on the main cell MC. In this case, the level of the word line pass voltage Vwp may be lower than the level of the pre-programming voltage Vprepro.

[0087] However, the memory device 100 according to an exemplary embodiment of the inventive concept may apply the pre-programming voltage Vprepro to the word line WL and apply the word line pass voltage Vwp to the virtual word line DWL1.

[0088] Reference Figure 10C , to perform a pre-programming operation, the memory device 100 may apply the pre-programming voltage Vprepro to the virtual word line DWL1 and some word lines WL, and may apply the word line pass voltage Vwp to other word lines WL, where the other word lines WL are the word lines WL that do not receive the pre-programming voltage Vprepro.

[0089] In an exemplary embodiment of the inventive concept, the memory device 100 may selectively apply the pre-programming voltage Vprepro to the virtual word line DWL1 and the word lines WL that are arranged close to the substrate SUB. In an exemplary embodiment of the inventive concept, the memory device 100 may select the virtual word line DWL1 and the word lines WL1 and WL2 and apply the pre-programming voltage Vprepro thereto. On the other hand, the word line pass voltage Vwp may be applied to the word lines WL3 to WL7 that are arranged farther from the substrate SUB than the word lines WL1 and WL2. In a memory device having a vertical memory cell structure, the memory cells located in the lower layer adjacent to the substrate SUB are more likely to be damaged. Therefore, the memory device 100 may prevent the memory cells from being damaged by performing a pre-programming operation on the memory cells located in the lower layer adjacent to the substrate SUB.

[0090] Reference Figures 10A to 10C , the pre-programming voltage Vprepro is applied to the virtual word line DWL1. However, the inventive concept is not limited thereto. For example, the word line pass voltage Vwp may be applied to the virtual word line DWL1, and the pre-programming voltage Vprepro may be applied to at least some of the word lines WL.

[0091] Figure 11A And 11B is a view for explaining Figure 1 the first memory block shown in Figure 11AYes Figure 1 A top view of the first memory block shown in Figure 11B shows a cross-section taken along line C-C' shown in Figure 11A . In the embodiment described in conjunction with Figure 11B , the corresponding description provided in conjunction with Figure 2B may be omitted. Figure 11B More particularly shows Figure 11A region D.

[0092] Referring to Figure 11A , the memory block BLK1' may include a plurality of vertical holes (e.g., main holes H11, H31, H61, and H81 and dummy hole DH1 in Figure 11B ) arranged along a first direction X and a second direction Y between word line cut regions WLC. The number of vertical holes included in the memory block BLK1' may vary.

[0093] The memory block BLK1' may be connected to bit lines BL1 to BL8 and dummy bit lines DBL extending in the second direction Y and spaced apart from each other in the first direction X. In an exemplary embodiment of the inventive concept, the main holes H11, H31, H61, and H81 may be connected to corresponding bit lines BL1, BL3, BL6, and BL8, respectively, and the dummy hole DH may be connected to the dummy bit line DBL. In the embodiment shown in Figure 1 , the memory block BLK1' includes eight bit lines including bit lines BL1 to BL8 and one dummy bit line including the dummy bit line DBL. However, the inventive concept is not limited thereto, and the number of bit lines and the number of dummy bit lines may vary.

[0094] Referring to Figure 11B , each of the main holes H11, H31, H61, and H81 and each of the word lines WL1 to WL8 may form a main cell MC, and the main holes H11, H31, H61, and H81 may be connected to bit lines BL1, BL3, BL6, and BL8, respectively. The main cell MC, ground selection transistor, and string selection transistor formed in each of the main holes H11, H31, H61, and H81 may constitute one cell string per hole.

[0095] The dummy hole DH1 and each of the word lines WL1 to WL8 may form a dummy cell DC, and the dummy hole DH1 may be connected to the dummy bit line DBL. The dummy cell DC, ground selection transistor, and string selection transistor formed in the dummy hole DH1 may constitute one dummy string.

[0096] The memory device 100 may selectively pre-program the memory cells included in the cell string or dummy string by selectively applying a bit line programming voltage to the bit lines BL1, BL3, BL6, and BL8 and the dummy bit line DBL. This will be described in conjunction with Figure 12Aand Figure 12B Describes a case where a pre-programming operation is selectively performed on a cell string or a dummy string.

[0097] Figure 12A and 12B is a table showing voltage conditions applied to a bit line and a dummy bit line when a pre-programming operation is performed by a memory device according to an exemplary embodiment of the inventive concept. Figure 12A and 12B is a view for explaining a pre-programming operation selectively performed on at least some of a plurality of strings by controlling a bit line voltage.

[0098] Referring to Figure 11B and 12A , during a pre-programming operation, a memory device (e.g., Figure 1 memory device 100) may apply a bit line programming voltage Vbpro to a bit line (BL, e.g., BL1, BL3, BL6, and BL8) and a dummy bit line DBL (e.g., Figure 3A operation S10). Accordingly, a pre-programming operation may be performed on cell strings connected to the bit line BL and formed in main holes H11, H31, H61, and H81 and on dummy strings connected to the dummy bit line DBL and formed in a dummy hole DH1.

[0099] As described above, during a pre-programming operation, the memory device 100 may apply a pre-programming voltage Vprepro to at least some word lines, an enable voltage to a ground selection line GSL connected to a dummy string, and a ground voltage to a common source line CSL. The description provided in conjunction with Figures 4 to 8 may be applied to a time point at which an enable voltage is applied to the ground selection line GSL and a time point at which a ground voltage is applied to the common source line CSL.

[0100] Referring to Figure 11B and 12B , the memory device 100 may selectively perform a pre-programming operation on a dummy string (e.g., a dummy string formed in a dummy hole DH1) among a plurality of strings. The memory device 100 may not perform a pre-programming operation on cell strings (e.g., cell strings formed in main holes H11, H31, H61, and H81). The memory device 100 may apply a bit line programming voltage Vbpro to the dummy bit line DBL and apply a programming inhibit voltage Vbinh to the bit lines BL1, BL3, BL6, and BL8 connected to the cell strings. Once the programming inhibit voltage Vbinh is applied to the bit lines BL1, BL3, BL6, and BL8, even when a pre-programming voltage Vprepro is applied to the word lines, main cells MC connected to the bit lines BL1, BL3, BL6, and BL8 may not be pre-programmed.

[0101] In this case, the level of the programming inhibit voltage Vbinh may be greater than the level of the bit line programming voltage Vbpro. For example, the bit line programming voltage Vbpro may be a ground voltage, and the programming inhibit voltage Vbinh may be a power supply voltage.

[0102] In the embodiment described in conjunction with Figure 12B a pre-programming operation is selectively performed on a virtual string. However, in an exemplary embodiment of the inventive concept, a selective pre-programming operation may be performed on at least some of the cell strings. For example, the memory device 100 may apply the bit line programming voltage Vbpro to at least some of the cell strings.

[0103] The memory device 100 according to an exemplary embodiment of the inventive concept may selectively perform a pre-programming operation on a virtual string in a plurality of strings by applying the bit line programming voltage Vbpro to a virtual bit line DBL. Since data can be written on a main cell MC included in the cell string, a separate programming operation may be performed. On the other hand, since a programming operation of writing data is not performed on a virtual cell DC included in the virtual string, damage to the virtual string may be prevented by performing a separate pre-programming operation on the virtual string before or after an erase operation.

[0104] Figure 13 is a block diagram showing an application of a memory device according to an exemplary embodiment of the inventive concept to a solid state drive (SSD) system 1000.

[0105] Referring to Figure 13 , the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 transmits a signal SIG to the host 1100 and receives a signal SIG from the host 1100 through a signal connector, and receives a power supply PWR through a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. The memory devices 1230, 1240, and 1250 may be flash memory devices. The memory devices 1230, 1240, and 1250 may be connected to the SSD controller 1210 through channels Ch1, Ch2,......Chn. The SSD 1200 may be implemented by the embodiment described above with reference to Figures 1 to 12B Each of the memory devices 1230, 1240, and 1250 includes virtual cells included in a virtual string, and a pre-programming operation may be performed on the virtual string before or after an erase operation. Therefore, damage to the virtual string due to repeated erase operations may be prevented.

[0106] Exemplary embodiments of the inventive concept provide a vertical memory device and an operation method thereof, which can prevent damage to a virtual string due to repeatedly performed erase operations.

[0107] Although the inventive concept has been specifically shown and described with reference to exemplary embodiments of the present invention, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept as set forth in the claims.

Claims

1. A method of operating a memory device, the memory device including a plurality of strings on a substrate, wherein the plurality of strings includes a main string connected to a bit line and a dummy string spaced apart from the bit line, The method of operation includes: Pre-programming the dummy string; and Erasing the main string and the dummy string, wherein the pre-programming includes: Applying a pre-programming voltage to a word line connected to the dummy string; Applying a pass voltage to a ground selection line of a ground selection transistor connected to the dummy string; and Applying a common source line voltage to a common source line connected to the dummy string.

2. The method of operation according to claim 1, wherein, The pre-programming voltage, the pass voltage, and the common source line voltage overlap each other.

3. The method of operation according to claim 2, wherein, The time for applying the pass voltage to the ground selection line is shorter than the time for applying the pre-programming voltage to the word line.

4. The method of operation according to claim 2, wherein, The time for applying the common source line voltage to the common source line is shorter than the time for applying the pre-programming voltage to the word line.

5. The method of operation according to claim 1, wherein, The dummy string is connected to a dummy word line, and The pre-programming further includes applying the pre-programming voltage to the dummy word line.

6. The method of operation according to claim 1, wherein, The dummy string is connected to a plurality of word lines, and Applying the pre-programming voltage includes: Selectively applying the pre-programming voltage to some of the plurality of word lines.

7. The method of operation according to claim 1, wherein, The dummy string is connected to a dummy bit line, and The pre-programming further includes applying a bit line programming voltage to the dummy bit line and applying a programming inhibit voltage to the bit line connected to the main string, wherein the programming inhibit voltage has a level higher than that of the bit line programming voltage.

8. The method of operation according to claim 1, wherein, The erasing is performed after the pre-programming.

9. The method of operation according to claim 1, wherein, The pre-programming is performed after the erasing.

10. A memory device, comprising: A memory cell array including a plurality of strings, each string including a memory cell respectively connected to a word line vertically stacked on a substrate; and Control logic configured to sequentially perform a pre-programming operation and an erasing operation on the plurality of strings, wherein The plurality of strings includes a main string connected to a bit line and a dummy string spaced apart from the bit line, and To perform the pre-programming operation, the control logic applies a pre-programming voltage to a first word line among the word lines connected to the dummy string, applies a pass voltage to a ground selection line of a ground selection transistor connected to the dummy string, and applies a common source line voltage to a common source line connected to the dummy string.

11. The memory device according to claim 10, wherein, The pre-programming voltage has a single pulse.

12. The memory device according to claim 10, wherein, The control logic applies the pre-programming voltage to the first word line connected to the dummy string, and then applies the pass voltage to the ground selection line.

13. The memory device according to claim 10, wherein, the control logic applies the pre-programming voltage to the first word line connected to the virtual string, and then applies the common source line voltage to the common source line.

14. The memory device according to claim 10, wherein, when applying the pass voltage to the ground selection line, the control logic applies the common source line voltage to the common source line.

15. The memory device according to claim 10, wherein the word line is the one closest to the substrate among the word lines connected to the virtual string.

16. The memory device according to claim 10, wherein, the word line includes a virtual word line, and to perform the pre-programming operation, the control logic applies the pre-programming voltage to the virtual word line and applies a word line pass voltage to the word lines other than the virtual word line, wherein the level of the word line pass voltage is lower than the level of the pre-programming voltage.

17. The memory device according to claim 10, wherein, the virtual string is connected to a virtual bit line, and to perform the pre-programming operation, the control logic applies a bit line programming voltage to the virtual bit line and the bit line connected to the main string.

18. The memory device according to claim 10, wherein, the virtual string is connected to a virtual bit line, and to perform a pre-programming operation on the virtual string, the control logic applies a bit line programming voltage to the virtual bit line and applies a programming inhibition voltage to the bit line connected to the main string, wherein the level of the programming inhibition voltage is higher than the level of the bit line programming voltage.

19. A memory device, comprising: a memory cell array including a plurality of strings, each of the strings including memory cells respectively connected to word lines vertically stacked on a substrate; and control logic configured to perform a pre-programming operation on the plurality of strings, wherein the plurality of strings include a main string to which a bit line is connected and a virtual string spaced apart from the bit line, during the pre-programming operation, the control logic applies a pre-programming voltage to the word line connected to the virtual string, applies a pass voltage to the ground selection line of the ground selection transistor connected to the virtual string, and applies a first common source line voltage to the common source line connected to the virtual string, and the time of applying the pre-programming voltage to the word line, the time of applying the pass voltage to the ground selection line, and the time of applying the first common source line voltage to the common source line overlap with each other.

20. The memory device according to claim 19, wherein, the control logic applies the pre-programming voltage to the word line connected to the virtual string, and then applies the pass voltage to the ground selection line.

21. The memory device according to claim 19, wherein, the control logic applies the pre-programming voltage to the word line connected to the virtual string, and then applies the first common source line voltage to the common source line.

22. The memory device according to claim 19, wherein, The control logic applies the second common source line voltage to the common source line connected to the dummy string, where the level of the second common source line voltage is higher than the level of the first common source line voltage, and the time for applying the pre-programming voltage to the word line and the time for applying the second common source line voltage to the common source line overlap with each other.

23. The memory device according to claim 22, wherein, the control logic applies the first common source line voltage to the common source line and then applies the second common source line voltage to the common source line.

24. The memory device according to claim 22, wherein, the control logic applies the second common source line voltage to the common source line and then applies the first common source line voltage to the common source line.

25. The memory device according to claim 22, wherein, the first common source line voltage is a ground voltage.

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