Semiconductor structure and method for manufacturing the same

Abstract

The embodiment of the present invention relates to a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises: a first semiconductor unit and a first TSV structure located in the first semiconductor unit, wherein the first TSV structure is exposed on the top surface of the first semiconductor unit; an interlayer bonding layer located on the top surface of the first semiconductor unit, wherein the interlayer bonding layer has an interconnection structure, wherein the interconnection structure comprises at least one conductive layer, wherein the interconnection structure has a top and a bottom opposite to the top, and wherein the first TSV structure is in contact with the bottom of the interconnection structure; and a second semiconductor unit located on the surface of the interlayer bonding layer, wherein the second semiconductor unit and the first semiconductor unit are located on opposite sides of the interlayer bonding layer, wherein the second semiconductor unit has a second TSV structure, and wherein the second TSV structure is in contact with the top of the interconnection structure. The semiconductor structure provided by the embodiment of the present invention has a thin overall thickness, and is conducive to reducing the resistance value of the semiconductor structure and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of integrated circuit design and manufacturing, in the field of packaging technology, the ordinary 2DIC packaging structure will bring about the problem of too long lines, resulting in reduced circuit operation speed and increased power consumption, and the 3D packaging structure came into being. The 3D packaging structure can effectively reduce the length of the line, increase the operation speed, and reduce power consumption.

[0003] In the 3D packaging structure, multiple chips are placed in the vertical direction to reduce the planar area of ​​the chip, and the multi-layer chips (die) or wafers can be interconnected between different layers through the TSV (Through-Silicon Via) structure. The functions of the TSV structure mainly include: on the one hand, the upper chip or wafer is interconnected with the lower chip or wafer through the TSV structure; on the other hand, since the thermal conductivity of the material of the TSV structure is usually higher than that of semiconductor materials such as silicon, the TSV structure is set in the 3D packaging structure for example, heat dissipation of the circuit.

[0004] However, the performance of existing packaging structures with TSVs still needs to be improved. Summary of the invention

[0005] The technical problem solved by the embodiments of the present invention is to provide a semiconductor structure and a manufacturing method thereof, to provide a brand-new semiconductor structure, and to improve the performance of the semiconductor structure.

[0006] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including: a first semiconductor unit and a first TSV structure located in the first semiconductor unit, the first TSV structure is exposed on the top surface of the first semiconductor unit; an interlayer bonding layer located on the top surface of the first semiconductor unit, the interlayer bonding layer has an interconnection structure, the interconnection structure includes at least one conductive layer, the interconnection structure has a top and a bottom opposite to the top, and the first TSV structure is in contact with the bottom of the interconnection structure; a second semiconductor unit located on the surface of the interlayer bonding layer, the second semiconductor unit and the first semiconductor unit are respectively located on opposite sides of the interlayer bonding layer, the second semiconductor unit has a second TSV structure, and the second TSV structure is in contact with the top of the interconnection structure.

[0007] An embodiment of the present invention also provides a method for manufacturing a semiconductor structure, comprising: providing a first semiconductor unit, wherein the first semiconductor unit has a first TSV structure, and the first TSV structure is exposed on the top surface of the first semiconductor unit; providing a second semiconductor unit; forming an interlayer bonding layer, wherein an interconnection structure is formed in the interlayer bonding layer, wherein the interconnection structure comprises at least one conductive layer, wherein the interconnection structure has a top and a bottom opposite to the top, and the first semiconductor unit and the second semiconductor unit are respectively located on opposite surfaces of the interlayer bonding layer, and the first TSV structure is in contact with the bottom of the interconnection structure; forming a second TSV structure that passes through the second semiconductor unit, and the second TSV structure is also in contact with the top of the interconnection structure.

[0008] Compared with the prior art, the technical solution provided by the embodiment of the present invention has the following advantages:

[0009] An embodiment of the present invention provides a semiconductor structure with superior structural performance, wherein a first semiconductor unit has a first TSV structure, a second semiconductor unit has a second TSV structure, and an interlayer bonding layer is provided between the second semiconductor unit and the first semiconductor unit, wherein the interlayer bonding layer has an interconnection structure including at least one conductive layer; wherein the bottom end of the interconnection structure contacts the first TSV structure, and the top end of the interconnection structure contacts the second TSV structure. In the embodiment of the present invention, the first TSV structure and the second TSV structure are electrically connected by the interconnection structure including the conductive layer, which is beneficial to reducing the equivalent resistance value between the first TSV structure and the second TSV structure, and reducing the overall thickness of the semiconductor structure.

[0010] In addition, in the direction from the first semiconductor unit to the second semiconductor unit, the thickness of the interconnect structure is in the range of 0.4 μm to 10 μm, which is beneficial to reduce the thickness of the semiconductor structure while ensuring good electrical connection performance between the first TSV structure and the second TSV structure.

[0011] In addition, the interconnect structure includes not only the bottom conductive layer but also the top conductive layer and the middle interconnect structure. By properly setting the number of conductive layers of the interconnect structure, the requirements of different lengths of the second TSV structure can be met.

[0012] In addition, in the direction from the first semiconductor unit to the second semiconductor unit, the thickness of the interlayer bonding layer is equal to the thickness of the interconnect structure, which minimizes the thickness of the interlayer bonding layer and is conducive to further reducing the thickness of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0014] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present invention;

[0015] Figure 2 A schematic cross-sectional view of another semiconductor structure provided by an embodiment of the present invention;

[0016] Figure 3 A schematic cross-sectional structure diagram of another semiconductor structure provided by an embodiment of the present invention;

[0017] Figure 4 A schematic cross-sectional view of a semiconductor structure provided by another embodiment of the present invention;

[0018] Figures 5 to 7 A local cross-sectional SEM comparison diagram of the semiconductor structure provided by an embodiment of the present invention and a conventional semiconductor structure;

[0019] Figures 8 to 10 A schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention;

[0020] Figures 11 to 13 A schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0021] From the background technology, it can be known that the performance of the packaging structure with TSV in the prior art needs to be improved, wherein the 3D semiconductor structure can be a single wafer or a single chip, or a stacked structure of wafers and chips, a stacked structure of wafers and wafers, or a stacked structure of chips and chips.

[0022] Taking the 3D packaging structure as a stacked structure of chips as an example, the lower chip has a first TSV structure, the upper chip has a second TSV structure, and a solder ball (bump) or a copper pillar (Pillar) is arranged between the top of the first TSV structure and the bottom of the second TSV structure, and the electrical connection between the first TSV structure and the second TSV structure is achieved through the solder ball or the copper pillar.

[0023] However, due to the limitation of the solder ball and copper pillar formation process, the thickness of the solder ball or copper pillar is relatively thick along the chip stacking direction, and a relatively thick dielectric structure layer is correspondingly formed around the solder ball or copper pillar, and the thickness of the dielectric structure layer is usually above 10μm. When the electrical connection is achieved by using solder balls or copper pillars, the distance between the first TSV structure and the second TSV structure is long, which not only causes a large resistance value of the package structure, but also causes the overall thickness of the package structure to be relatively thick.

[0024] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, which electrically connects a first TSV structure and a second TSV structure through an interconnection structure. Compared with solder balls or copper pillars, the vertical thickness of the interconnection structure is smaller, which is beneficial for reducing the overall thickness of the semiconductor structure and reducing the resistance value between the first TSV structure and the second TSV structure, thereby reducing the resistance value of the semiconductor structure.

[0025] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can be implemented.

[0026] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present invention.

[0027] A first semiconductor unit 10 and a first TSV structure 101 located in the first semiconductor unit 10, wherein the first TSV structure 101 is exposed on the top surface of the first semiconductor unit 10; an interlayer bonding layer 20 located on the top surface of the first semiconductor unit 10, wherein the interlayer bonding layer 20 has an interconnection structure 30, wherein the interconnection structure 30 includes at least one conductive layer, wherein the interconnection structure 30 has a top and a bottom opposite to the top, and the first TSV structure 101 is in contact with the bottom of the interconnection structure 30; a second semiconductor unit 40 located on the surface of the interlayer bonding layer 20, wherein the second semiconductor unit 40 and the first semiconductor unit 10 are respectively located on opposite sides of the interlayer bonding layer 20, wherein the second semiconductor unit 40 has a second TSV structure 102, and wherein the second TSV structure 102 is in contact with the top of the interconnection structure 30.

[0028] The semiconductor structure provided by this embodiment will be described in detail below with reference to the accompanying drawings.

[0029] In this embodiment, the semiconductor structure is a 3D semiconductor structure, for example, it may include a DRAM chip, and may also include a DRAM chip and a logic chip. The first TSV structure 101 in the upper layer and the second TSV structure 102 in the lower layer are electrically connected via an interconnection structure 30 including a conductive layer, which replaces the solution of using solder balls or copper pillars for electrical connection in the prior art. Since the thickness of the interconnection structure 30 including the conductive layer can be set to be relatively small, the vertical distance between the first TSV structure 101 and the second TSV structure 102 in this embodiment is small, which is not only conducive to reducing the resistance value between the first TSV structure 101 and the second TSV structure 102, but also conducive to reducing the overall thickness of the semiconductor structure.

[0030] The first semiconductor unit 10 includes a first wafer or a first chip, and the second semiconductor unit 40 includes a first wafer or a second chip.

[0031] Among them, the main difference between a wafer and a chip is that a wafer can be made using integrated circuit manufacturing technology. For example, NMOS devices, PMOS devices, CMOS devices, etc. are formed on a substrate through deposition, etching, doping and other processes, and a dielectric layer, an interconnection structure, and pads electrically connected to the interconnection structure are formed on the device to form multiple chips in the wafer; after the wafer is cut, several chips are formed.

[0032] The chip may be an active component, a passive component, a micro-electromechanical system or an optical component. Specifically, according to the functional type, the chip may be a storage chip, a communication chip, a processing chip, a flash memory chip, a logic chip or a specific function chip. For example, the processing chip may be an image sensor chip, a temperature sensor chip or a pressure sensor chip, etc. The specific function chip may be a chip developed for certain specific functions, such as a Wifi chip, a Bluetooth chip or a power management chip, etc.

[0033] In this embodiment, taking the first semiconductor unit 10 as a first chip and the second semiconductor unit 40 as a second chip as an example, the types of the first chip and the second chip may be the same or different.

[0034] The first semiconductor unit 10 includes a first substrate 11 and a first functional stack 12 located on the surface of the first substrate 11, wherein the surface of the first functional stack 12 is the top surface of the first semiconductor unit 10. In this embodiment, the first TSV structure 101 penetrates the first substrate 11 and the first functional stack 12.

[0035] In this embodiment, the first substrate 11 is a silicon substrate. In other embodiments, the first substrate may also be a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V substrate, or a sapphire substrate. The first functional stack 12 includes at least one dielectric layer and an interconnection layer located in the dielectric layer, and the first functional stack 12 also has a gate structure of an NMOS transistor, a PMOS transistor, or a CMOS transistor.

[0036] The second semiconductor unit 40 includes a second substrate 41 and a second functional stack 42 located on the surface of the second substrate 41. The second substrate 41 faces the first semiconductor unit 10. For the detailed description of the second substrate 41 and the second functional stack 42, reference can be made to the detailed description of the first substrate 11 and the second functional stack 12.

[0037] In this embodiment, the second TSV structure 102 is exposed on the top surface of the second semiconductor unit 40 , that is, the second functional stack 42 exposes the second TSV structure 102 , so as to facilitate electrical connection between the second TSV structure 102 and other semiconductor units located thereon.

[0038] The interlayer bonding layer 20 has the function of providing a spatial position for setting an interconnection structure 30 that electrically connects the first TSV structure 101 and the second TSV structure 102. The material of the interlayer bonding layer 20 is a dielectric material. In this embodiment, the material of the interlayer bonding layer is an organic dielectric material. In other embodiments, the material of the interlayer bonding layer can also be an inorganic dielectric material.

[0039] The interconnection structure 30 includes: a bottom conductive layer, the bottom conductive layer is located on the top surface of the first semiconductor unit 10, the bottom conductive layer has a first front side and a first back side opposite to the first front side, and the first back side of the bottom conductive layer is in contact with the first TSV structure 101. The bottom end of the interconnection structure 30 is flush with the back side of the interlayer bonding layer 20.

[0040] Compared with solder balls or copper pillars, the thickness of the layered bottom conductive layer can be set smaller, so the vertical distance between the first TSV structure 101 and the second TSV structure 102 is correspondingly smaller, and the thickness of the corresponding interlayer bonding layer 20 is correspondingly smaller, which is beneficial to reduce the overall thickness of the semiconductor structure and reduce the resistance value between the first TSV structure 101 and the second TSV structure 102. The bottom conductive layer can be manufactured by a redistribution layer (RDL) process.

[0041] In this embodiment, taking the interconnect structure 30 including a single conductive layer as an example, the interconnect structure 30 is the bottom conductive layer 30. Accordingly, the second TSV structure 102 is in contact with the first front side of the bottom conductive layer 30.

[0042] In the direction from the first semiconductor unit 10 to the second semiconductor unit 40, the thickness of the interconnection structure 30 is the distance between the top of the interconnection structure 30 and the bottom of the interconnection structure 30. In the direction from the first semiconductor unit 10 to the second semiconductor unit 40, the thickness of the interconnection structure 30 should not be too small or too large. If the thickness of the interconnection structure 30 is too small, the thickness uniformity of the interconnection structure 30 is relatively poor, which may easily cause the electrical connection performance between the first TSV structure 101 and the second TSV structure 102 to be weak; if the thickness of the interconnection structure 30 is too large, it is not conducive to reducing the overall thickness of the semiconductor structure.

[0043] In this embodiment, in the direction from the first semiconductor unit 10 to the second semiconductor unit 40, the thickness of the interconnection structure 30 is in the range of 0.4 μm to 10 μm, for example, 1 μm, 3 μm, 5.5 μm, 7 μm or 9.5 μm. When the interconnection structure 30 includes a single conductive layer, the thickness of the bottom conductive layer is in the range of 0.4 μm to 10 μm.

[0044] In this embodiment, in the direction from the first semiconductor unit 10 to the second semiconductor unit 40, the thickness of the interlayer bonding layer 20 is greater than the thickness of the interconnection structure 30. Accordingly, the second TSV structure 102 is also located within a partial thickness of the interlayer bonding layer 20, which is beneficial to improving the bonding force between the second semiconductor unit 40 and the interlayer bonding layer 20 and improving the reliability of the semiconductor structure.

[0045] Figure 2 is a schematic diagram of a cross-sectional structure of another semiconductor structure. In other embodiments, Figure 2 As shown, in the direction from the first semiconductor unit 10 to the second semiconductor unit 40, the thickness of the interlayer bonding layer 20 can also be equal to the thickness of the interconnection structure 30. Accordingly, the top of the interconnection structure 30 is flush with the surface of the interlayer bonding layer 20, and the second TSV structure 102 is not arranged in the interlayer bonding layer 20.

[0046] In this embodiment, the interconnection structure 30 includes a single conductive layer as an example. In other embodiments, the interconnection structure may also include at least two conductive layers.

[0047] Figure 3 This is a schematic diagram of the cross-sectional structure of another semiconductor structure.

[0048] like Figure 3As shown, the interconnection structure 30 includes, in addition to the bottom conductive layer 31, a top conductive layer 32, wherein the top conductive layer 32 has a second front side and a second back side opposite to the second front side, wherein the second back side is opposite to the first front side of the bottom conductive layer 31, and the second front side of the top conductive layer 32 is in contact with the second TSV structure 102; and an intermediate interconnection structure electrically connecting the first front side of the bottom conductive layer 31 and the second back side.

[0049] The second front surface of the top conductive layer 32 is the top of the interconnect structure 30. Taking the example that the second front surface of the top conductive layer 32 is located in the interlayer bonding layer 20, in other embodiments, the second front surface of the top conductive layer can also be flush with the surface of the interlayer bonding layer, and the interlayer bonding layer exposes the second front surface of the top conductive layer.

[0050] The intermediate interconnection structure includes: a conductive plug 33, one end of which is in contact with the first front side of the bottom conductive layer 31, and the other end of which is in contact with the second back side of the top conductive layer 32. It should be noted that, in other embodiments, the intermediate interconnection structure may also include: at least one intermediate conductive layer; and conductive plugs electrically connecting the bottom conductive layer with the intermediate conductive layer and electrically connecting the intermediate conductive layer with the top conductive layer.

[0051] By reasonably setting the number of conductive layers in the interconnect structure 30, the length of the second TSV structure 102 in contact with the top of the interconnect structure 30 can be set more flexibly. For example, by reasonably increasing the number of conductive layers in the interconnect structure 30, the length of the second TSV structure 102 is relatively short, which is conducive to reducing the difficulty of the formation process of the second TSV structure 102.

[0052] In addition, by reasonably setting the number of layers and position distribution of the conductive layers in the interconnect structure 30, different signal distribution and arrangement requirements can be met, thereby meeting different design requirements or electrical signal connection requirements.

[0053] It should also be noted that for the sake of convenience of illustration, only two first TSV structures 101 and two second TSV structures 102 are shown. In other embodiments, the number of first TSV structures in the semiconductor structure can be any number, the number of second TSV structures can also be any number, and the number of second TSV structures is the same as the number of first TSV structures.

[0054] In this embodiment, when the number of the second TSV structures is at least two, in the direction from the first semiconductor unit to the second semiconductor unit, the lengths of all the second TSV structures are the same, and accordingly, the number of conductive layers in each interconnect structure is the same.

[0055] In this embodiment, a semiconductor structure including two layers of semiconductor units is taken as an example. In the actual process, the number of layers of semiconductor units in the semiconductor structure can be set according to actual needs. The multiple layers of semiconductor units are stacked in the vertical direction, and any one layer of semiconductor units serves as the second semiconductor unit of the next layer and the first semiconductor unit of the previous layer.

[0056] Another embodiment of the present invention further provides a semiconductor structure. Different from the previous embodiment, in this embodiment, the number of second TSV structures is two or more than two, and in the direction from the first semiconductor unit to the second semiconductor unit, the lengths of all the second TSV structures are not exactly the same. Accordingly, the number of conductive layers in all the interconnect structures is not exactly the same. Figure 4 A schematic cross-sectional view of a semiconductor structure provided in accordance with another embodiment of the present invention.

[0057] refer to Figure 4 The semiconductor structure includes: a first semiconductor unit 200 and a first TSV structure 201 located in the first semiconductor unit 200; an interlayer bonding layer 203, wherein the interlayer bonding layer 203 has an interconnection structure, wherein the interconnection structure includes at least one conductive layer, wherein the interconnection structure has a top and a bottom opposite to the top, and the first TSV structure 201 is in contact with the bottom of the interconnection structure; a second semiconductor unit 205 located on the surface of the interlayer bonding layer 203, wherein the second semiconductor unit 205 and the first semiconductor unit 200 are respectively located on opposite sides of the interlayer bonding layer 203, wherein the second semiconductor unit 205 has a second TSV structure 206, and the second TSV structure 206 is also in contact with the top of the interconnection structure 204.

[0058] The semiconductor structure provided in this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that the parts that are the same as or corresponding to the previous embodiment will not be described in detail below.

[0059] The first semiconductor unit 200 includes a first substrate 21 and a first functional stack 22 located on the surface of the first substrate 21, wherein the surface of the first functional stack 22 is the top surface of the first semiconductor unit 200. In this embodiment, the first TSV structure 201 penetrates the first substrate 21 and the first functional stack 22.

[0060] The second semiconductor unit 205 includes a second substrate 51 and a second functional stack 52 located on a surface of the second substrate 51. The second substrate 51 faces the first semiconductor unit 200.

[0061] For detailed description of the second semiconductor unit 205 and the first semiconductor unit 200, please refer to the corresponding description of the above-mentioned embodiment, which will not be repeated here. In this embodiment, the number of the second TSV structures 206 is two or more, and the lengths of all the second TSV structures 206 in the direction from the first semiconductor unit 200 to the second semiconductor unit 205 are not exactly the same; the number of conductive layers in all the interconnect structures is not exactly the same. For the convenience of illustration, Figure 4 Only two second TSV structures 206 are shown.

[0062] The interconnect structure includes: a first interconnect structure (not labeled) and a second interconnect structure 204 , and the number of conductive layers in the first interconnect structure is different from the number of conductive layers in the second interconnect structure 204 .

[0063] The first interconnect structure includes: a bottom conductive layer 214, wherein the bottom conductive layer 214 is located on the top surface of the first semiconductor unit 200, wherein the bottom conductive layer 214 has a first front side and a first back side opposite to the first front side, and the first back side of the bottom conductive layer 214 is in contact with the first TSV structure 201, and the first front side of the bottom conductive layer 214 is in contact with the second TSV structure 206.

[0064] The second interconnect structure 204 includes: a bottom conductive layer 214, wherein the bottom conductive layer 214 is located on the top surface of the first semiconductor unit 200, wherein the bottom conductive layer 214 has a first front side and a first back side opposite to the first front side, and the first back side of the bottom conductive layer 214 is in contact with the first TSV structure 201; a top conductive layer 224, wherein the top conductive layer 224 has a second front side and a second back side opposite to the second front side, wherein the second back side is opposite to the first front side, and the second front side of the top conductive layer 224 is in contact with the second TSV structure 206; and an intermediate interconnect structure electrically connecting the first front side and the second back side.

[0065] The bottom conductive layer 214 in the first interconnect structure and the bottom conductive layer 214 in the second interconnect structure 204 are in the same layer, and are separated from each other.

[0066] In this embodiment, the intermediate interconnect structure includes: a conductive plug 234, one end of the conductive plug 234 contacts the first front surface of the bottom conductive layer 214, and the other end of the conductive plug 234 contacts the second back surface. In other embodiments, the intermediate interconnect structure may further include at least one intermediate conductive layer.

[0067] In the semiconductor structure provided in this embodiment, by properly arranging the number of conductive layers in different interconnect structures, the second TSV structures 206 with different lengths can all be electrically connected to the corresponding first TSV structures 201 .

[0068] It should be noted that, in this embodiment, the semiconductor structure includes two layers of semiconductor units as an example. In other embodiments, the number of layers of semiconductor units included in the semiconductor structure can be reasonably set according to actual needs, and interlayer bonding layers are provided between adjacent layers of semiconductor units.

[0069] Figures 5 to 7 The SEM (scanning electron microscope) comparison diagram of the local cross section of the semiconductor structure provided by the embodiment of the present invention and the existing semiconductor structure is taken as an example of a semiconductor structure including a DRAM chip.

[0070] Figure 5 In the figure, the left figure shows a partial cross-sectional SEM schematic diagram of a semiconductor structure composed of four DRAM chips and a single logic chip in the prior art, and the right figure shows a partial cross-sectional SEM schematic diagram of a semiconductor structure composed of four DRAM chips and a single logic chip provided by an embodiment of the present invention. The semiconductor structure in the right figure includes: a first semiconductor unit 500 and a first TSV structure 501 located in the first semiconductor unit 500; an interlayer bonding layer 503, wherein the interlayer bonding layer 503 has an interconnection structure (not shown); a second semiconductor unit 505 and a second TSV structure 506 located in the second semiconductor unit 505. Among them, taking the DRAM chip thickness of the prior art and the embodiment of the present invention as 100μm, the distance between adjacent layers of DRAM chips in the prior art is 50μm; the thickness of the semiconductor structure provided by the embodiment of the present invention is 200μm thinner than that of the prior art, which can save the thickness of two DRAM chips.

[0071] Figure 6 In the figure, the left figure shows a partial cross-sectional SEM schematic diagram of a semiconductor structure composed of four DRAM chips, and the right figure is a partial cross-sectional SEM schematic diagram of a semiconductor structure composed of four DRAM chips provided in an embodiment of the present invention. The semiconductor structure in the right figure includes: a first semiconductor unit 600 and a first TSV structure 601 located in the first semiconductor unit 600; an interlayer bonding layer 603, wherein the interlayer bonding layer 603 has an interconnection structure (not shown); a second semiconductor unit 605 and a second TSV structure 606 located in the second semiconductor unit 605. For example, the thickness of the DRAM chips in the prior art and the embodiment of the present invention is 60 μm, and the distance between adjacent layers of DRAM chips in the prior art is 20 μm; the thickness of the semiconductor structure provided in the embodiment of the present invention is 60 μm thinner than that in the prior art, and the thickness of one DRAM chip can be saved.

[0072] Figure 7 In the figure, the left figure shows a partial cross-sectional SEM schematic diagram of a semiconductor structure composed of 8 DRAM chips and a single logic chip, and the right figure shows a partial cross-sectional SEM schematic diagram of a semiconductor structure composed of 8 DRAM chips and a single logic chip provided by an embodiment of the present invention. The semiconductor structure in the right figure includes: a first semiconductor unit 700 and a first TSV structure 701 located in the first semiconductor unit 700; an interlayer bonding layer 703, wherein the interlayer bonding layer 703 has an interconnection structure (not shown); a second semiconductor unit 705 and a second TSV structure 706 located in the second semiconductor unit 705. Among them, taking the DRAM chip thickness of both the existing and the embodiment of the present invention as 60μm, the distance between adjacent layers of DRAM chips in the existing is 17μm; the thickness of the semiconductor structure provided by the embodiment of the present invention is 136μm thinner than the existing one, which can save the thickness of 2 DRAM chips.

[0073] Correspondingly, an embodiment of the present invention also provides a method for manufacturing a semiconductor structure, which can be used to manufacture the above-mentioned semiconductor structure, including: providing a first semiconductor unit, wherein the first semiconductor unit has a first TSV structure, and the first TSV structure is exposed on the top surface of the first semiconductor unit; providing a second semiconductor unit; forming an interlayer bonding layer, wherein an interconnection structure is formed in the interlayer bonding layer, wherein the interconnection structure includes at least one conductive layer, wherein the interconnection structure has a top and a bottom opposite to the top, and the first semiconductor unit and the second semiconductor unit are respectively located on the surfaces opposite to the interlayer bonding layer, and the first TSV structure is in contact with the bottom of the interconnection structure; forming a second TSV structure that penetrates the second semiconductor unit, and the second TSV structure is also in contact with the top of the interconnection structure. The following will be described in detail with reference to the accompanying drawings.

[0074] It should be noted that the following description will be made by taking the case where the number of the second TSV structures is two and the lengths of each second TSV structure are different as an example. In other embodiments, the number of the second TSV structures may be any number and the lengths of each second TSV structure may be the same.

[0075] Figures 8 to 10 A schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present invention.

[0076] refer to Figure 8, providing a first semiconductor unit 200, wherein the first semiconductor unit 200 has a first TSV structure 201, and the first TSV structure 201 is exposed on the top surface of the first semiconductor unit 200; forming an interlayer bonding layer 203 on the top surface of the first semiconductor unit 200, wherein an interconnection structure is formed in the interlayer bonding layer 203, wherein the interconnection structure includes at least one conductive layer, wherein the interconnection structure has a top end and a bottom end opposite to the top end, and the first TSV structure 201 is in contact with the bottom end of the interconnection structure.

[0077] In this embodiment, the top of the interconnect structure is located in the interlayer bonding layer 203 , and the first TSV structure 201 penetrates the first semiconductor unit 200 .

[0078] One of the interconnect structures only includes the bottom conductive layer 214 contacting the first TSV structure 201 ; the other interconnect structure includes: the bottom conductive layer 214 , a top conductive layer 224 located on the bottom conductive layer 214 , and a conductive plug 234 .

[0079] For the description of the first semiconductor unit 200 and the interconnection structure, please refer to the description of the above embodiments, which will not be repeated here. In other embodiments, the interconnection structure may be only a single conductive layer, or the number of conductive layers of each interconnection structure may be the same.

[0080] refer to Fig. 9 , provide a second semiconductor unit 205; bond the second semiconductor unit 205 to the surface of the interlayer bonding layer 203.

[0081] For the corresponding description of the second semiconductor unit 205 , reference may be made to the corresponding description of the aforementioned embodiment, which will not be repeated here.

[0082] After the second semiconductor unit 205 is bonded to the surface of the inter-layer bonding layer 203 , the first semiconductor unit 200 and the second semiconductor unit 205 are respectively located on opposite surfaces of the inter-layer bonding layer 203 .

[0083] The second semiconductor unit 205 is bonded to the surface of the interlayer bonding layer 203 by one or more of direct bonding (also called melt bonding), adhesive layer bonding, metal diffusion bonding or eutectic bonding.

[0084] refer to Fig.10 A second TSV hole 216 is formed in the second semiconductor unit 205 and a partial thickness of the interlayer bonding layer 203, and the second TSV hole 216 exposes the top of the interconnection structure.

[0085] In this embodiment, the second semiconductor unit 205 and the interlayer bonding layer 203 are etched by an etching process until the top of the interconnect structure is exposed to form a second TSV hole 216. Specifically, one second TSV hole 216 exposes the surface of the bottom conductive layer 213, and the other second TSV hole 216 exposes the surface of the top conductive layer 223.

[0086] During the etching process, the bottom conductive layer 213 and the top conductive layer 223 in different interconnect structures are respectively used as etching stop layers.

[0087] In this embodiment, deep reactive ion etching (DRIE) is used for etching. In other embodiments, Bosh etching process can also be used for etching.

[0088] refer to Figure 4 , the second TSV hole 216 is filled with a conductive material (refer to Fig.10 ) to form the second TSV structure 206.

[0089] In this embodiment, an electroplating process is used to form a conductive material that fills the second TSV hole 216. After the electroplating process is completed, the top surface of the second semiconductor unit 205 is chemically mechanically polished to remove the conductive material formed by electroplating on the top of the second semiconductor unit 205.

[0090] It should be noted that, in other embodiments, the interlayer bonding layer may also expose the top of the interconnect structure. Accordingly, the method for forming the second TSV structure includes: forming the second TSV structure after bonding the second semiconductor unit to the surface of the interlayer bonding layer; or forming the second TSV structure before bonding the second semiconductor unit to the interlayer bonding layer.

[0091] Subsequent process steps also include: bonding a semiconductor unit on the second semiconductor unit 205, and providing an interlayer bonding layer between the second semiconductor unit 205 and the semiconductor unit; stacking a plurality of semiconductor units in a direction perpendicular to the surface of the second semiconductor unit 205 according to actual process requirements; and then performing cutting processing.

[0092] Another embodiment of the present invention further provides a method for manufacturing a semiconductor structure. Different from the previous embodiment, in this embodiment, after forming an interlayer bonding layer on the bottom surface of the second semiconductor unit, the interlayer bonding layer is bonded to the top surface of the first semiconductor unit. This will be described in detail below with reference to the accompanying drawings.

[0093] Figures 11 to 13A schematic cross-sectional structure diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by another embodiment of the present invention.

[0094] refer to Fig.11 , providing a second semiconductor unit 305; forming an interlayer bonding layer 303 on the bottom surface of the second semiconductor unit 305.

[0095] The interconnect structure has a top end and a bottom end opposite to the top end, wherein an end of the interconnect structure close to the second semiconductor unit 305 is the top end, and an end of the interconnect structure away from the second semiconductor unit 305 is the bottom end.

[0096] In this embodiment, the top of the interconnection structure is located in the interlayer bonding layer 303. One of the interconnection structures only includes the bottom conductive layer 314, and the bottom of the interlayer bonding layer 303 exposes the surface of the bottom conductive layer 314. The other interconnection structure includes: the bottom conductive layer 314, the top conductive layer 324 located on the bottom conductive layer 314, and the conductive plug 334.

[0097] For the corresponding description of the interconnection structure, reference may be made to the corresponding description of the aforementioned embodiment, which will not be repeated here.

[0098] refer to Fig.12 , providing a first semiconductor unit 300, wherein the first semiconductor unit 300 has a first TSV structure 301, and the first TSV structure 301 is exposed on the top surface of the first semiconductor unit 300; bonding the interlayer bonding layer 303 to the top surface of the first semiconductor unit 300.

[0099] In this embodiment, a direct bonding process is used to bond the interlayer bonding layer 303 to the top surface of the first semiconductor unit 300. In other embodiments, the bonding process may also be metal diffusion bonding or eutectic bonding.

[0100] The first TSV structure 301 is in contact with the bottom conductive layer 314 .

[0101] refer to Fig.13 , forming a second TSV structure 306 , wherein the second TSV structure 306 penetrates the second semiconductor unit 305 and is electrically connected to the top of the interconnection structure.

[0102] Regarding the process steps for forming the second TSV structure 306 , reference may be made to the corresponding description of the aforementioned embodiment, which will not be described in detail herein.

[0103] In this embodiment, a second TSV structure 306 is in contact with the bottom conductive layer 314 , and another second TSV structure 306 is in contact with the top conductive layer 314 .

[0104] It should be noted that, in this embodiment, the second TSV structure 306 is formed after the interlayer bonding layer 303 is bonded to the top surface of the first semiconductor unit 300. In other embodiments, the second TSV structure may be formed after the interlayer bonding layer is formed on the bottom surface of the second semiconductor unit and before the interlayer bonding layer is bonded to the top surface of the first semiconductor unit.

[0105] Those skilled in the art will appreciate that the above embodiments are specific examples of the present invention, and in practical applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention, and therefore the scope of protection of the present invention shall be subject to the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A first semiconductor unit and a first TSV structure located in the first semiconductor unit, wherein the first TSV structure is exposed on a top surface of the first semiconductor unit; An interlayer bonding layer is located on the top surface of the first semiconductor unit, wherein the interlayer bonding layer has an interconnection structure, wherein the interconnection structure includes at least one conductive layer, wherein the interconnection structure has a top end and a bottom end opposite to the top end, and the first TSV structure is in contact with the bottom end of the interconnection structure; A second semiconductor unit located on the surface of the inter-layer bonding layer, the second semiconductor unit and the first semiconductor unit are respectively located on two opposite sides of the inter-layer bonding layer, the second semiconductor unit has a second TSV structure, and the second TSV structure is in contact with the top of the interconnect structure; Wherein, in a direction from the first semiconductor unit to the second semiconductor unit, the thickness of the interlayer bonding layer is greater than the thickness of the interconnect structure; and the second TSV structure is also located in a partial thickness of the interlayer bonding layer.

2. The semiconductor structure according to claim 1, wherein: In a direction from the first semiconductor unit to the second semiconductor unit, a thickness of the interconnection structure is in a range of 0.4 μm to 10 μm.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The interconnect structure includes: a bottom conductive layer, the bottom conductive layer is located on the top surface of the first semiconductor unit, the bottom conductive layer has a first front side and a first back side opposite to the first front side, and the first back side of the bottom conductive layer contacts the first TSV structure.

4. The semiconductor structure according to claim 3, characterized in that A first front side of the bottom conductive layer contacts the second TSV structure.

5. The semiconductor structure according to claim 3, wherein: The interconnect structure also includes: a top conductive layer, the top conductive layer having a second front side and a second back side opposite to the second front side, wherein the second back side is opposite to the first front side, and the second front side of the top conductive layer is in contact with the second TSV structure; and an intermediate interconnect structure electrically connecting the first front side and the second back side.

6. The semiconductor structure according to claim 5, characterized in that The intermediate interconnection structure includes a conductive plug, one end of which contacts the first front side of the bottom conductive layer, and the other end of which contacts the second back side.

7. The semiconductor structure according to claim 5, characterized in that The intermediate interconnect structure further includes at least one intermediate conductive layer.

8. The semiconductor structure according to claim 1, wherein: The second TSV structure is exposed on a top surface of the second semiconductor unit.

9. The semiconductor structure according to claim 1, wherein: The first semiconductor unit includes a first wafer or a first chip; the second semiconductor unit includes a second wafer or a second chip.

10. The semiconductor structure according to claim 1, wherein: The number of the second TSV structures is two or more, and in the direction from the first semiconductor unit to the second semiconductor unit, the lengths of all the second TSV structures are not completely the same; the number of conductive layers in all the interconnect structures is not completely the same.

11. A method for manufacturing a semiconductor structure, characterized in that: Providing a first semiconductor unit, wherein the first semiconductor unit has a first TSV structure therein, and the first TSV structure is exposed on a top surface of the first semiconductor unit; providing a second semiconductor unit; Forming an interlayer bonding layer, wherein an interconnection structure is formed in the interlayer bonding layer, wherein the interconnection structure includes at least one conductive layer, wherein the interconnection structure has a top end and a bottom end opposite to the top end, and the first semiconductor unit and the second semiconductor unit are respectively located on opposite surfaces of the interlayer bonding layer, and the first TSV structure is in contact with the bottom end of the interconnection structure; forming a second TSV structure penetrating the second semiconductor unit, wherein the second TSV structure is also in contact with a top end of the interconnect structure; Wherein, in a direction from the first semiconductor unit to the second semiconductor unit, the thickness of the interlayer bonding layer is greater than the thickness of the interconnect structure; and the second TSV structure is also located in a partial thickness of the interlayer bonding layer.

12. The manufacturing method according to claim 11, characterized in that: The first semiconductor unit and the second semiconductor unit are respectively located on opposite surfaces of the interlayer bonding layer, and the forming steps include: forming the interlayer bonding layer on the top surface of the first semiconductor unit; The second semiconductor unit is bonded to the surface of the interlayer bonding layer.

13. The manufacturing method according to claim 12, characterized in that: The process steps for forming the second TSV structure include: after bonding the second semiconductor unit to the surface of the interlayer bonding layer, forming a second TSV hole in the second semiconductor unit and a partial thickness of the interlayer bonding layer, wherein the second TSV hole exposes the top of the interconnect structure; and filling the second TSV hole with a conductive material to form the second TSV structure.

14. The manufacturing method according to claim 11, characterized in that: The first semiconductor unit and the second semiconductor unit are respectively located on opposite surfaces of the interlayer bonding layer, and the forming steps include: forming the interlayer bonding layer on the bottom surface of the second semiconductor unit; The interlayer bonding layer is bonded to the top surface of the first semiconductor unit.

15. The manufacturing method according to claim 14, characterized in that: The method for forming the second TSV structure includes: forming the second TSV structure after forming the interlayer bonding layer and before bonding the interlayer bonding layer to the top surface of the first semiconductor unit; or forming the second TSV structure after bonding the interlayer bonding layer to the top surface of the first semiconductor unit.

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