Operational amplifier

Abstract

The present disclosure provides an operational amplifier, which includes a current mirror circuit, an input and gain stage circuit, an output stage circuit, a bias compensation circuit, and a control circuit. The current mirror circuit generates a bias current. The input and gain stage circuit is coupled to the current mirror circuit, and the input and gain stage circuit generates a gain bias according to a differential input signal and the bias current. The output stage circuit is coupled to the current mirror circuit and the input and gain stage circuit, and the output stage circuit generates an output signal according to the bias current and the gain bias. The bias compensation circuit is connected in parallel with the output stage circuit, and the bias compensation circuit adjusts the gain bias generated by the input and gain stage circuit, so that the operational amplifier has a switchable bandwidth.

Description

Technical Field

[0001] The present invention relates to an operational amplifier, and in particular to an operational amplifier with switchable bandwidth. Background Art

[0002] An operational amplifier generally has a fixed bandwidth. An operational amplifier with a fixed bandwidth cannot meet the application requirements of different bandwidths. For different bandwidth application requirements, it is necessary to redesign the operational amplifier, which is inconvenient for product development.

[0003] Furthermore, if the operational amplifier is designed to have switchable bandwidth, the stability problem of the operational amplifier needs to be further considered. If the operational amplifier becomes unstable, the range of the actually switchable bandwidth will also be limited. Further, designing the operational amplifier to have switchable bandwidth also needs to consider its circuit area. If the operational amplifier occupies too large a circuit area, it will be difficult to meet the current requirements for thin, light, short, and small products. Therefore, when designing an operational amplifier with switchable bandwidth, it is necessary to simultaneously consider the good stability and small circuit area of the operational amplifier, which is a better circuit design. Summary of the Invention

[0004] The present disclosure provides an operational amplifier, including a current mirror circuit, an input and gain stage circuit, an output stage circuit, a bias compensation circuit, and a control circuit. The current mirror circuit is used to generate a bias current. The input and gain stage circuit is coupled to the current mirror circuit, and the input and gain stage circuit is used to generate a gain bias according to a differential input signal and the bias current. The output stage circuit is coupled to the current mirror circuit and the input and gain stage circuit, and the output stage circuit is used to generate an output signal according to the bias current and the gain bias. The bias compensation circuit is connected in parallel with the output stage circuit, and the bias compensation circuit is used to adjust the gain bias. The bias compensation circuit includes a plurality of first N-type transistors, a plurality of first switches, a plurality of first P-type transistors, and a plurality of second switches. The plurality of first N-type transistors are connected in parallel with each other. Each first switch is coupled to the control terminal of each first N-type transistor. The plurality of first P-type transistors are connected in parallel with each other and the plurality of first P-type transistors are connected in parallel with the plurality of first N-type transistors. Each second switch is coupled to the control terminal of each first P-type transistor. The control circuit is used to control the first switch and the second switch to be conductive or cutoff respectively, so as to change the parallel number between the first N-type transistors and the parallel number between the first P-type transistors, so as to adjust the aforementioned gain bias. Description of the Drawings

[0005] Figure 1 It is a block diagram of an embodiment of the operational amplifier according to the present disclosure.

[0006] Figure 2 For Figure 1 a circuit diagram of an embodiment of the operational amplifier.

[0007] Figure 3 For Figure 2 a circuit diagram of an embodiment of a bias compensation circuit for an operational amplifier.

[0008] Figure 4 For Figure 2 a circuit diagram of another embodiment of a bias compensation circuit for an operational amplifier.

[0009] Figure 5 For Figure 2 a circuit diagram of an embodiment of an input transistor of a current mirror circuit.

[0010] Figure 6 For Figure 2 a circuit diagram of an embodiment of an output transistor of a current mirror circuit.

[0011] Figure 7 a circuit diagram of an embodiment of a switch of the present disclosure.

[0012] Description of reference numerals:

[0013] 1 Operational amplifier

[0014] 11 Current mirror circuit

[0015] M1 Equivalent input transistor

[0016] M2 Equivalent output transistor

[0017] M11 - M13 Input transistors

[0018] M21 - M23 Output transistors

[0019] S71 - S73 Fifth switch

[0020] S81 - S83 Sixth switch

[0021] 12 Input and gain stage circuit

[0022] 121 Gain circuit

[0023] 122 Gain circuit

[0024] 13 Output stage circuit

[0025] MN2 Second N-type transistor

[0026] MP2 Second P-type transistor

[0027] 14 Bias compensation circuit

[0028] MN1 Equivalent first N-type transistor

[0029] MN11 - MN13 First N - type transistor

[0030] S11 - S13 First switch

[0031] S21 - S23 Second switch

[0032] MP1 Equivalent first P - type transistor

[0033] MP11 - MP13 First P - type transistor

[0034] R1 Equivalent resistance

[0035] R11 - R13 Resistors

[0036] R2 Equivalent resistance

[0037] R21 - R23 Resistors

[0038] C1 Equivalent capacitance

[0039] C11 - C13 Capacitances

[0040] C2 Equivalent capacitance

[0041] C21 - C23 Capacitances

[0042] S31 - S33 Third switch

[0043] S41 - S43 Fourth switch

[0044] S51 - S53 Fourth switch

[0045] S61 - S63 Third switch

[0046] 15 Control circuit

[0047] I1 Reference current

[0048] I2 Bias current

[0049] IN1 Differential input terminal

[0050] IN2 Differential input terminal

[0051] N1 Node

[0052] N2 Node

[0053] N3 Connection point

[0054] OUT Output terminal

[0055] C Control terminal

[0056] CB Control terminal

[0057] G gate terminal

[0058] D drain terminal

[0059] S source terminal Detailed implementation manners

[0060] Please refer to Figure 1 and Figure 2 , Figure 1 which is a block diagram of an embodiment of the operational amplifier 1 according to the present disclosure. Figure 2 It is Figure 1 a circuit diagram of an embodiment of the operational amplifier. The operational amplifier 1 includes a current mirror circuit 11, an input and gain stage circuit 12, an output stage circuit 13, a bias compensation circuit 14, and a control circuit 15. Among them, the output stage circuit 13 is coupled to the input and gain stage circuit 12, the current mirror circuit 11 is coupled to the input and gain stage circuit 12 and the output stage circuit 13, the bias compensation circuit 14 is connected in parallel with the output stage circuit 13, and the control circuit 15 is coupled to the bias compensation circuit 14.

[0061] As Figure 2 shown, the current mirror circuit 11 is used to provide a bias current I2, and the input and gain stage circuit 12 and the output stage circuit 13 operate according to the bias current I2 generated by the current mirror circuit 11. The input and gain stage circuit 12 has a differential input terminal IN1, IN2 at both ends. The input and gain stage circuit 12 receives a differential input signal. The input and gain stage circuit 12 generates a gain bias at nodes N1, N2 between the input and gain stage circuit 12 and the output stage circuit 13 according to the gain generated by its circuit configuration with the bias current I2. The output stage circuit 13 then amplifies the differential input signal according to the bias current I2 and the aforementioned gain bias to generate an output signal at the output terminal OUT.

[0062] The bias compensation circuit 14 is controlled by the control circuit 15. The bias compensation circuit 14 can change the gain bias generated by the input and gain stage circuit 12 at nodes N1, N2, so that the output stage circuit 13 generates an output signal according to different gain biases, that is, the operational amplifier 1 has switchable different bandwidths, and the operational amplifier 1 can support high-frequency or low-frequency applications.

[0063] Specifically, please refer to Figure 2 and Figure 3 , the bias compensation circuit 14 includes a plurality of first N-type transistors MN11, MN12, MN13, a plurality of first P-type transistors MP11, MP12, MP13, a plurality of first switches S11, S12, S13, and a plurality of second switches S21, S22, S23. Among them, Figure 2For example, the bias compensation circuit 14 includes equivalent first N-type transistors MN1 and equivalent first P-type transistors MP1 to represent the first N-type transistors MN11, MN12, MN13 and the first P-type transistors MP11, MP12, MP13 respectively, and Figure 3 For example, the bias compensation circuit 14 includes three first N-type transistors MN11, MN12, and MN13 and three first P-type transistors MP11, MP12, and MP13. However, the present disclosure is not limited thereto, and the bias compensation circuit 14 may also include other numbers of N-type transistors and P-type transistors.

[0064] In one embodiment, the first N-type transistors MN11, MN12, MN13 and the plurality of first P-type transistors MP11, MP12, MP13 may be referred to as a mesh of head-to-tail connected transistors. As Figure 2 and Figure 3 shown, the first N-type transistors MN11, MN12, MN13 are coupled between the node N1 and the node N2. The first N-type transistors MN11, MN12, MN13 are in parallel with each other, and each of the first switches S11, S12, S13 is coupled to the control terminal of each of the first N-type transistors MN11, MN12, MN13. That is, the first switch S11 is coupled to the control terminal of the first N-type transistor MN11, the first switch S12 is coupled to the control terminal of the first N-type transistor MN12, and the first switch S13 is coupled to the control terminal of the first N-type transistor MN13. The first switches S11, S12, S13 are controlled by the control circuit 15, and the control circuit 15 can control the first switches S11, S12, S13 to be turned on or off respectively to change the number of transistors in parallel between the first N-type transistors MN11, MN12, MN13, so that the equivalent first N-type transistor MN1 has different aspect ratios (W / L ratio), that is, the equivalent first N-type transistor MN1 has switchable dimensions.

[0065] For example, when the control circuit 15 controls the first switch S11 to conduct and the first switches S12 and S13 to cut off, the first N-type transistor MN11 is conducting while the first N-type transistors MN12 and MN13 are cut off, and the number of transistors connected in parallel among the first N-type transistors MN11, MN12, and MN13 is one; when the control circuit 15 controls the first switch S11 to cut off and the first switches S12 and S13 to conduct, the first N-type transistor MN11 is cut off while the first N-type transistors MN12 and MN13 are conducting, and the number of transistors connected in parallel among the first N-type transistors MN11, MN12, and MN13 is two; when the control circuit 15 controls the first switches S11, S12, and S13 to all conduct, the first N-type transistors MN11, MN12, and MN13 are all conducting, and the number of transistors connected in parallel among the first N-type transistors MN11, MN12, and MN13 is three; and so on for the rest, which will not be elaborated here. When the number of conducting first N-type transistors MN11, MN12, and MN13 is larger, the equivalent first N-type transistor MN1 has a larger size.

[0066] Furthermore, the first P-type transistors MP11, MP12, and MP13 are coupled between the node N1 and the node N2. The first P-type transistors MP11, MP12, and MP13 are connected in parallel with each other, and the first P-type transistors MP11, MP12, and MP13 are also connected in parallel with the first N-type transistors MN11, MN12, and MN13. The second switches S21, S22, and S23 are respectively coupled to the control terminals of the first P-type transistors MP11, MP12, and MP13, that is, the second switch S21 is coupled to the control terminal of the first P-type transistor MP11, the second switch S22 is coupled to the control terminal of the first P-type transistor MP12, and the second switch S23 is coupled to the control terminal of the first P-type transistor MP13. The second switches S21, S22, and S23 are controlled by the control circuit 15, and the control circuit 15 can respectively control the second switches S21, S22, and S23 to conduct or cut off, so as to change the number of transistors connected in parallel among the first P-type transistors MP11, MP12, and MP13, and make the equivalent first P-type transistor MP1 have different aspect ratios (W / L ratio), that is, the equivalent first P-type transistor MP1 has a switchable size.

[0067] For example, when the control circuit 15 controls the second switch S21 to conduct and the second switches S22 and S23 to cut off, the first P-type transistor MP11 conducts while the first P-type transistors MP12 and MP13 cut off, and the number of parallel-connected transistors among the first P-type transistors MP11, MP12, and MP13 is one; when the control circuit 15 controls the second switch S21 to cut off and the second switches S22 and S23 to conduct, the first P-type transistor MP11 cuts off while the first P-type transistors MP12 and MP13 conduct, and the number of parallel-connected transistors among the first P-type transistors MP11, MP12, and MP13 is two; when the control circuit 15 controls the second switches S21, S22, and S23 to all conduct, the first P-type transistors MP11, MP12, and MP13 all conduct, and the number of parallel-connected transistors among the first P-type transistors MP11, MP12, and MP13 is three; and so on for the rest, which will not be elaborated here. When the number of conducting first P-type transistors MP11, MP12, and MP13 is larger, the equivalent first P-type transistor MP1 has a larger size.

[0068] Based on this, according to the different sizes of the equivalent first N-type transistor MN1 and the first P-type transistor MP1, the bias compensation circuit 14 can switch and change the gain bias generated by the input and the gain stage circuit 12, so that the operational amplifier 1 generates a corresponding output signal according to different gain biases. In other words, according to different gain biases, the poles of the operational amplifier 1 move and it has different operating bandwidths. Among them, if the sizes of the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 are larger, the operating bandwidth of the operational amplifier 1 tends to be higher frequency; if the sizes of the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 are smaller, the operating bandwidth of the operational amplifier 1 tends to be lower frequency. Thus, the operational amplifier 1 can support high-frequency or low-frequency applications. When the operational amplifier 1 is intended to be used in a high-frequency environment, the control circuit 15 can control a larger number (e.g., three) of the first switches S11, S12, and S13 to conduct and control a larger number (e.g., three) of the second switches S21, S22, and S23 to conduct, so that the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 have larger sizes, that is, the operating bandwidth of the operational amplifier 1 is higher, and the operational amplifier 1 can achieve high speed; conversely, when the operational amplifier 1 is intended to be used in a low-frequency environment, the control circuit 15 can control a smaller number (e.g., one) of the first switches S11, S12, and S13 to conduct and control a smaller number (e.g., one) of the second switches S21, S22, and S23 to conduct, so that the equivalent first N-type transistor MN1 and the equivalent first P-type transistor MP1 have smaller sizes, that is, the operating bandwidth of the operational amplifier 1 is lower, and the operational amplifier 1 can achieve power saving.

[0069] In one embodiment, as Figure 2 shown, the input and gain stage circuit 12 further includes gain circuits 121 and 122. The gain circuits 121 and 122 are respectively connected to nodes N1 and N2, and the gain circuits 121 and 122 are coupled to the bias compensation circuit 14 via nodes N1 and N2. Furthermore, taking the first N-type transistors MN11, MN12, MN13 and the first P-type transistors MP11, MP12, MP13 as MOSFETs as an example, as Figure 2 and Figure 3 shown, the drain terminals and source terminals of the first N-type transistors MN11, MN12, MN13 are respectively connected to nodes N1 and N2. The first N-type transistors MN11, MN12, MN13 are connected in parallel with each other. The source terminals and drain terminals of the first P-type transistors MP11, MP12, MP13 are respectively connected to nodes N1 and N2. The first P-type transistors MP11, MP12, MP13 are connected in parallel with each other, and the switches S11 - S13, S21 - S23 are respectively connected to the gate terminals of the first P-type transistors MP11, MP12, MP13 and the first P-type transistors MP11, MP12, MP13.

[0070] In one embodiment, as Figure 2 shown, the output stage circuit 13 includes a second N-type transistor MN2 and a second P-type transistor MP2. The control terminal of the second P-type transistor MP2 (taking the second N-type transistor MN2 and the second P-type transistor MP2 as MOSFETs as an example, the control terminal is the gate terminal) is coupled to node N1, and the control terminal of the second P-type transistor MP2 is coupled to the source terminals of the first P-type transistors MP11, MP12, MP13 and the drain terminals of the first N-type transistors MN11, MN12, MN13 via node N1; the control terminal of the second N-type transistor MN2 is coupled to node N2, and the control terminal of the second N-type transistor MN2 is coupled to the drain terminals of the first P-type transistors MP11, MP12, MP13 and the source terminals of the first N-type transistors MN11, MN12, MN13 via node N2. Furthermore, the connection point N3 between the control terminal of the second N-type transistor MN2 and the control terminal of the second P-type transistor MP2 serves as the output terminal OUT of the operational amplifier 1, that is, the connection point N3 generates the aforementioned output signal.

[0071] In one embodiment, please refer to Figure 2 and Figure 4 in combination. The bias compensation circuit 14 further includes a resistor array formed by a plurality of resistors R11 - R13, R21 - R23, a capacitor array formed by a plurality of capacitors C11 - C13, C21 - C23, and a plurality of third switches S31 - S33, S61 - S63 and a plurality of fourth switches S41 - S43, S51 - S53. Among them, Figure 2Taking the example that the equivalent resistor array is represented by equivalent resistors R1 and R2 and the equivalent capacitor array is represented by equivalent capacitors C1 and C2, and Figure 4 taking the example that the bias compensation circuit 14 includes six resistors R11 - R13, R21 - R23 and corresponding six switches S31 - S33, S61 - S63, and six capacitors C11 - C13, C21 - C23 and corresponding six switches S41 - S43, S51 - S53. However, the present invention is not limited thereto, and the resistor array and the capacitor array may respectively include other numbers of resistors and capacitors.

[0072] As Figure 2 and Figure 4 shown, the resistor array and the capacitor array are coupled between node N1 and node N2, that is, the resistor array and the capacitor array are coupled between the control terminal of the second P-type transistor MP2 and the control terminal of the second N-type transistor MN2, and the resistor array and the capacitor array are connected in parallel to the first N-type transistors MN11 - MN13 and the first P-type transistors MP11 - MP13. Further, as Figure 4 shown, the resistors R11, R12, R13 and the third switches S31, S32, S33, and the capacitors C11, C12, C13 and the fourth switches S41, S42, S43 are coupled between node N1 and the output terminal OUT; the capacitors C21, C22, C23 and the fourth switches S51, S52, S53, and the resistors R21, R22, R23 and the third switches S61, S62, S63 are coupled between the output terminal OUT and node N2. Among them, the resistors R11, R12, R13 are connected in parallel with each other, and the resistors R11, R12, R13 are respectively connected in series to the third switches S31, S32, S33; the capacitors C11, C12, C13 are connected in parallel with each other, and the capacitors C11, C12, C13 are respectively connected in series to the fourth switches S41, S42, S43; the capacitors C21, C22, C23 are connected in parallel with each other, and the capacitors C21, C22, C23 are respectively connected in series to the fourth switches S51, S52, S53; the resistors R21, R22, R23 are connected in parallel with each other, and the resistors R21, R22, R23 are respectively connected in series to the third switches S61, S62, S63.

[0073] Based on this, the control circuit 15 can respectively control the third switches S31, S32, and S33 to be turned on or off to change the number of parallel resistances among the resistors R11, R12, and R13, and the control circuit 15 can respectively control the fourth switches S41, S42, and S43 to be turned on or off to change the number of parallel capacitances among the capacitors C11, C12, and C13. Moreover, the control circuit 15 can respectively control the third switches S61, S62, and S63 to be turned on or off to change the number of parallel resistances among the resistors R21, R22, and R23, and the control circuit 15 can respectively control the fourth switches S51, S52, and S53 to be turned on or off to change the number of parallel capacitances among the capacitors C21, C22, and C23. The control circuit 15 can switch the gain bias voltages of the nodes N1 and N2 by changing the aforementioned number of parallel resistances and the number of parallel capacitances, so that the output stage circuit 13 generates corresponding output signals according to different gain bias voltages, that is, the operational amplifier 1 has different operating bandwidths.

[0074] For example, if the operational amplifier 1 is to operate in a high-frequency application, the control circuit 15 can control a larger number (e.g., three) of the third switches S31, S32, and S33 to be turned on and control a larger number (e.g., three) of the third switches S61, S62, and S63 to be turned on. Moreover, the control circuit 15 controls a smaller number (e.g., one) of the fourth switches S41, S42, and S43 to be turned on and controls a smaller number (e.g., one) of the fourth switches S51, S52, and S53 to be turned on, so that there are smaller resistance values and capacitance values between the nodes N1 and N2. Conversely, if the operational amplifier 1 is to operate in a low-frequency application, the control circuit 15 can control a smaller number (e.g., one) of the third switches S31, S32, and S33 to be turned on and control a smaller number (e.g., one) of the third switches S61, S62, and S63 to be turned on. Moreover, the control circuit 15 controls a larger number (e.g., three) of the fourth switches S41, S42, and S43 to be turned on and controls a larger number (e.g., three) of the fourth switches S51, S52, and S53 to be turned on, so that there are larger resistance values and capacitance values between the nodes N1 and N2. Based on this, the different resistance values of the resistor array and the different capacitance values of the capacitor array between the nodes N1 and N2 can be matched with the different transistor sizes of the equivalent first N-type transistor MN1 and the different transistor sizes of the equivalent first P-type transistor MP1, so that the operational amplifier 1 has corresponding operating bandwidths to meet the products of its applications.

[0075] In an embodiment, the current mirror circuit 11 generates a bias current I2 with a switchable current magnitude. As Figure 2 、 Figure 5 and Figure 6As shown, the current mirror circuit 11 includes a plurality of input transistors M11, M12, M13, a plurality of fifth switches S71, S72, S73, a plurality of output transistors M21, M22, M23, and a plurality of sixth switches S81, S82, S83. Among them, Figure 2 the input transistors M11, M12, M13 are represented by an equivalent input transistor M1, and the output transistors M21, M22, M23 are represented by an equivalent output transistor M2; and, Figure 5 and Figure 6 taking the current mirror circuit 11 including three input transistors M11 - M13 and three output transistors M21 - M23 as an example, however, the present disclosure is not limited thereto, and the current mirror circuit 11 may include other numbers of input transistors and output transistors.

[0076] Taking the input transistors M11, M12, M13 and the output transistors M21, M22, M23 as MOSFETs as an example, the gate terminals G of each of the input transistors M11, M12, M13 are connected to the drain terminals D, and the input transistors M11, M12, M13 are in parallel with each other, that is, the drain terminals D of the input transistors M11, M12, M13 are connected to each other and the source terminals S of the input transistors M11, M12, M13 are connected to each other, and the gate terminals G of the input transistors M11, M12, M13 are respectively coupled to the fifth switches S71, S72, S73. The output transistors M21, M22, M23 are in parallel with each other, that is, the drain terminals D of the output transistors M21, M22, M23 are connected to each other and the source terminals S of the output transistors M21, M22, M23 are connected to each other, and the gate terminals G of the output transistors M21, M22, M23 are respectively coupled to the sixth switches S81, S82, S83.

[0077] Please refer to Figure 2 、 Figure 5 and Figure 6, the input transistors M11 - M13 receive a reference current I1, and the output transistors M21 - M23 generate a bias current I2 as a mirror current in proportion to the reference current I1 (where the ratio of the bias current I2 to the reference current I1 is equal to the ratio of the aspect ratio of the equivalent output transistor M2 to the aspect ratio of the equivalent input transistor M1). Thus, the control circuit 15 can control the fifth switches S71, S72, S73 and the sixth switches S81, S82, S83 to be turned on or off respectively. When the fifth switches S71, S72, S73 are turned on, the input transistors M11, M12, M13 are turned on, and when the fifth switches S71, S72, S73 are turned off, the input transistors M11, M12, M13 are turned off; when the sixth switches S81, S82, S83 are turned on, the output transistors M21, M22, M23 are turned on, and when the sixth switches S81, S82, S83 are turned off, the output transistors M21, M22, M23 are turned off. According to the on or off state of the input transistors M11, M12, M13, the control circuit 15 can control the number of transistors in parallel between the input transistors M11, M12, M13, so that the equivalent input transistor M1 has different aspect ratios; according to the on or off state of the output transistors M21, M22, M23, the control circuit 15 can control the number of transistors in parallel between the output transistors M21, M22, M23, so that the equivalent output transistor M2 has different aspect ratios; thus, according to the different aspect ratios of the equivalent input transistor M1 and the equivalent output transistor M2, the current mirror circuit 11 can generate bias currents I2 with different current magnitudes, that is, the control circuit 15 can control the switches S71, S72, S73, S81, S82, S83 to be turned on or off to switch the current magnitude of the bias current I2.

[0078] For example, taking the case where the input transistors M11, M12, M13 and the output transistors M21, M22, M23 all have the same parameter K value, if the control circuit 15 controls the switches S71, S81, S83 to be turned on and the switches S72, S73, S82 to be turned off, then the input transistor M11 and the output transistors M21, M23 are turned on and the input transistors M12, M13 and the output transistor M22 are turned off. The number of transistors in parallel (n) between the input transistors M11, M12, M13 is one, and the number of transistors in parallel (m) between the output transistors M21, M22, M23 is two. The bias current I2 is twice the reference current I1 (m / n is 2); if the control circuit 15 controls the switches S71, S72, S73, S81, S83 to be turned on and the switch S82 to be turned off, then the input transistors M11, M12, M13 and the output transistors M21, M23 are turned on and the output transistor M22 is turned off. The number of transistors in parallel (n) between the input transistors M11, M12, M13 is three, and the number of transistors in parallel (m) between the output transistors M21, M22, M23 is two. The bias current I2 is 2 / 3 times the reference current I1 (m / n is 2 / 3). The rest can be deduced by analogy and will not be elaborated here.

[0079] Based on this, if the operational amplifier 1 is to operate in a high-frequency application, the control circuit 15 can control the current mirror circuit 11 to generate a larger bias current I2. If the operational amplifier 1 is to operate in a low-frequency application, the control circuit 15 can control the current mirror circuit 11 to generate a smaller bias current I2, so that the operational amplifier 1 has different operating bandwidths, and the operational amplifier 1 can support high-frequency or low-frequency applications simultaneously. In one embodiment, the input transistors M11, M12, M13 and the output transistors M21, M22, M23 can be N-type MOSFETs or P-type MOSFETs.

[0080] Please refer to Figure 7 , Figure 7 is a circuit diagram of an embodiment of the switches S11 - S13, S21 - S23, S31 - S33, S41 - S43, S51 - S53, S61 - S63, S71 - S73, S81 - S83 of the present disclosure. The switches S11 - S13, S21 - S23, S31 - S33, S41 - S43, S51 - S53, S61 - S63, S71 - S73, S81 - S83 can include PMOS transistors and NMOS transistors. The PMOS transistors and NMOS transistors each include two control terminals C, CB, and the two control terminals C, CB respectively receive two control signals that are opposite to each other. The two control signals that are opposite to each other can control the PMOS transistor or the NMOS transistor to be turned on.

[0081] In summary, according to an embodiment of the operational amplifier of the present disclosure, the operational amplifier has a switchable bandwidth, can meet the product application requirements of different bandwidths, and has good stability (unit gain stable). Furthermore, switching the bias current of the operational amplifier through the current mirror circuit has the advantages of simple design and easy circuit layout, and the design of matching the transistor elements connected in series with the head and tail and switching the resistor and capacitor enables the operational amplifier to have a relatively large switchable bandwidth range. The operational amplifier can be applied to a wide range of different applications from low current and low bandwidth to high current and high bandwidth.

[0082] Although the present disclosure has been disclosed above by way of examples, it is not intended to limit the present disclosure. Any person skilled in the art within the scope of the present disclosure may make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to what is defined by the claims.

Claims

1. An operational amplifier, comprising: A current mirror circuit for generating a bias current; An input and gain stage circuit coupled to the current mirror circuit for generating a gain bias according to an input signal and the bias current; An output stage circuit coupled to the current mirror circuit and the input and gain stage circuit for generating an output signal according to the bias current and the gain bias; A bias compensation circuit connected in parallel with the output stage circuit for adjusting the gain bias, comprising: A plurality of first N-type transistors connected in parallel with each other; A plurality of first switches, each first switch being coupled to the control terminal of each first N-type transistor; A plurality of first P-type transistors connected in parallel with the plurality of first N-type transistors and connected in parallel with each other; And A plurality of second switches, each second switch being coupled to the control terminal of each first P-type transistor; And A control circuit for controlling the first switches and the second switches to be conductive or non-conductive respectively, so as to change the number of parallel connections between the first N-type transistors and the number of parallel connections between the first P-type transistors, thereby adjusting the gain bias.

2. The operational amplifier according to claim 1, wherein the bias compensation circuit further comprises: A plurality of resistors connected in parallel with each other; A plurality of capacitors connected in series with the plurality of resistors and connected in parallel with each other; A plurality of third switches, each third switch being connected in series with each resistor; and A plurality of fourth switches, each fourth switch being connected in series with each capacitor; Wherein, The control circuit further controls the third switches and the fourth switches to be conductive or non-conductive respectively, so as to change the number of parallel connections between the resistors and the number of parallel connections between the capacitors, thereby adjusting the gain bias.

3. The operational amplifier according to claim 2, wherein the output stage circuit comprises a second N-type transistor and a second P-type transistor connected in series, wherein the resistors, the third switches, the capacitors and the fourth switches are coupled between the gate terminals of the second P-type transistor and the second N-type transistor and connected in parallel with the first N-type transistors and the first P-type transistors.

4. The operational amplifier according to claim 3, wherein an output signal is generated at a connection point between the second N-type transistor and the second P-type transistor, wherein a part of the resistors, a part of the third switches, a part of the capacitors and a part of the fourth switches are connected in series between the gate terminal of the second P-type transistor and the connection point, and another part of the resistors, another part of the third switches, another part of the capacitors and another part of the fourth switches are connected in series between the gate terminal of the second N-type transistor and the connection point.

5. The operational amplifier according to claim 3 or 4, wherein the first N-type transistors and the first P-type transistors are coupled between the gate terminal of the second N-type transistor and the gate terminal of the second P-type transistor.

6. The operational amplifier according to claim 1, wherein the current mirror circuit generates the bias current with a switchable current magnitude.

7. The operational amplifier according to claim 6, wherein the current mirror circuit comprises: A plurality of input transistors, which are connected in parallel with each other, and each of the input transistors is used to receive a reference current; and A plurality of fifth switches, each of the fifth switches being coupled to the gate terminal of each of the input transistors; Wherein, The control circuit further controls the fifth switches to be turned on or off to change the number of input transistors connected in parallel to change the bias current.

8. The operational amplifier according to claim 7, wherein the current mirror circuit further comprises: A plurality of output transistors, which are connected in parallel with each other, and the output transistors are used to output the bias current; and A plurality of sixth switches, each of the sixth switches being coupled to the gate terminal of each of the output transistors; Wherein, The control circuit further controls the sixth switches to be turned on or off to change the number of output transistors connected in parallel to change the bias current.

9. The operational amplifier according to claim 1, wherein the bias compensation circuit and the output stage circuit are coupled to each other at two nodes and are connected in parallel, and the control circuit controls the bias compensation circuit to change the voltage levels of the two nodes to adjust the gain bias.

10. The operational amplifier according to claim 1, wherein the input signal is a differential input signal.

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