Dynamic enhancement loop response after recovery from a fault condition

Abstract

The present disclosure relates to dynamically enhancing loop response after recovery from a fault condition. A method for dynamically enhancing loop response after recovery from a fault condition includes detecting a fault condition in response to a programmed output voltage of a pulse width modulation (PWM) converter decreasing below an input voltage of the PWM converter. In response to detecting the fault condition, sampling a peak voltage at an end of at least one clock cycle of a plurality of clock cycles of the PWM converter, wherein the peak voltage is proportional to a sensed current conducted through a transistor. Pre-setting an error output of an error amplifier to an error value determined from the peak voltage. Controlling a PWM driver with the error value to drive the transistor. In response to the input voltage increasing above the programmed output voltage, charging an output load to the programmed output voltage with the transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to pulse width modulation (PWM) converters, and more particularly, to enhancing the loop response of a PWM converter in response to recovery from a fault condition. BACKGROUND

[0002] Current mode PWM converters can enter various limiting conditions outside of normal operation. It is generally desirable for the converter to enter and exit these limiting conditions slowly, and preferably have a predictable and controlled amount of disturbance, or no disturbance at all, at its output. These limiting conditions can include voltage differentials, current limits, etc., which cause one of the state variables of the converter to saturate.

[0003] A voltage differential condition is defined as a condition where the input voltage of the converter decreases below its programmed output voltage. During a voltage differential condition, the duty cycle of the converter can saturate to a 100% duty cycle. The voltage differential condition in turn causes other state variables (or nodes) within its controller to become saturated. Recovery from the saturated state can be slow, and thus can induce undesirable large transients at the output of the converter. SUMMARY

[0004] According to one aspect of the present invention, a method for dynamically enhancing loop response after recovery from a fault condition is provided, comprising:

[0005] detecting a fault condition in response to a programmed output voltage of a pulse width modulation (PWM) converter decreasing below an input voltage of the PWM converter;

[0006] sampling a peak voltage at an end of at least one clock cycle of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor;

[0007] presetting an error output of an error amplifier to an error value determined from the peak voltage, controlling a PWM driver to drive the transistor with the error value; and

[0008] charging an output load to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.

[0009] According to one or more embodiments, the peak voltage is increased by a compensation ramp voltage when the fault condition is a voltage differential condition.

[0010] According to one or more embodiments, the fault condition is a voltage differential condition detected without activating the PWM driver for a predetermined number of the plurality of clock cycles.

[0011] According to one or more embodiments, the fault condition is a current limit condition detected by comparing the sensed current to a current limit.

[0012] According to one or more embodiments, the peak voltage is determined for each of the plurality of clock cycles.

[0013] According to one or more embodiments, determining the error value includes driving the peak voltage on a terminal of an offset resistor, the error value increased by a voltage offset determined by the offset resistor and a compensation resistor, wherein the offset resistor is connected in series with the compensation resistor and the compensation resistor is connected to the error output.

[0014] According to one or more embodiments, the voltage offset is greater than an input reference offset of a PWM comparator configured to receive the error output of the error amplifier.

[0015] According to one or more embodiments, the transistor is a high-side transistor connected between the input voltage and the output load.

[0016] According to a second aspect of the present invention, there is provided an apparatus comprising:

[0017] a fault detector configured to detect a fault condition in response to a programmed output voltage of a pulse width modulated (PWM) converter decreasing below an input voltage of the PWM converter;

[0018] a sampling circuit connected to a fault detector output of the fault detector, the fault detector configured to enable the sampling circuit in response to the fault condition, the sampling circuit coupled to a current sense output of a current sensor configured to sense a sensed current conducted through a transistor, wherein the sampling circuit samples a peak voltage at an end of at least one of a plurality of clock cycles of the PWM converter, and the peak voltage is proportional to the sensed current; and

[0019] an offset circuit connected between a sampling output of the sampling circuit and an error output of an error amplifier, wherein the offset circuit is configured to preset the error output to an error value determined by the peak voltage, a PWM driver configured to drive the transistor in response to the error value, and the transistor configured to charge an output load to the programmed output voltage in response to the input voltage increasing above the programmed output voltage.

[0020] According to one or more embodiments, further comprising a ramp output of a ramp generator connected to the current sense output when the fault condition is a differential pressure condition.

[0021] According to one or more embodiments, the fault detector comprises a differential pressure detector configured to reset in response to a change in the PWM driver and indicate the fault condition on the fault detector output in response to a predetermined number of the plurality of clock cycles elapsing without the fault detector resetting.

[0022] According to one or more embodiments, the fault detector comprises a differential pressure detector configured to indicate the fault condition on the fault detector output in response to an input of the error amplifier decreasing to less than a threshold value.

[0023] According to one or more embodiments, the fault detector comprises a current limit comprising a current limit comparator configured to indicate the fault condition in response to the current sense output increasing above a threshold value.

[0024] According to one or more embodiments, the offset circuit comprises an offset resistor connected in series with a compensation resistor, and the compensation resistor is connected to the error output.

[0025] According to one or more embodiments, an offset resistor and the compensation resistor form a voltage offset, and the error value is equal to the peak voltage plus the voltage offset.

[0026] According to one or more embodiments, the voltage offset is greater than an input reference offset of a PWM comparator configured to receive the error output of the error amplifier.

[0027] According to a third aspect of the present invention, there is provided an apparatus comprising:

[0028] a fault detector configured to detect a fault condition of a pulse width modulated (PWM) converter;

[0029] a sampling circuit connected to a fault detector output of the fault detector, the fault detector configured to enable the sampling circuit in response to the fault condition, the sampling circuit coupled to a current sense output of a current sensor configured to sense a sense current conducted through a high side transistor, wherein the sampling circuit samples a peak voltage; and

[0030] an offset resistor connected between a sampling output of the sampling circuit and a terminal of a compensation capacitor, a compensation resistor connected between the terminal and an error output of an error amplifier, wherein the error output is preset to an error value determined by a peak voltage proportional to the sense current, and a voltage offset is formed between the offset resistor and the compensation resistor, a PWM driver configured to drive the high-side transistor in response to the error value, and the high-side transistor is configured to charge an output load to the programmed output voltage in response to the input voltage increasing above the programmed output voltage.

[0031] According to one or more embodiments, the fault detector includes a differential pressure detector configured to reset in response to a change in the PWM driver, and indicate the fault condition on the fault detector output in response to a predetermined number of the plurality of clock cycles elapsing without the fault detector resetting.

[0032] According to one or more embodiments, the fault detector includes a differential pressure detector configured to indicate the fault condition on the fault detector output in response to an input of the error amplifier decreasing below a threshold value.

[0033] According to one or more embodiments, the fault detector includes a current limit including a current limit comparator configured to indicate the fault condition in response to the current sense output increasing above a threshold value. BRIEF DESCRIPTION OF DRAWINGS

[0034] The present disclosure is illustrated by way of example and not limitation in the figures of which like references indicate similar elements. Elements in the figures are shown for simplicity and clarity and have not necessarily been drawn to scale.

[0035] Figure 1 schematic diagram of an example embodiment of a PWM converter.

[0036] Figure 2 schematic diagram of an example embodiment of a PWM converter without a dynamic boost loop response. Figure 1 graphical view of voltage waveforms of an example embodiment.

[0037] Figure 3 schematic diagram of an example embodiment of a PWM converter with a dynamic boost loop response according to the present disclosure. Figure 1 graphical view of voltage waveforms of an example embodiment.

[0038] Figure 4 schematic diagram of a preset circuit interfacing elements of an example embodiment. Figure 1 schematic diagram of a preset circuit interfacing elements of an example embodiment.

[0039] Figure 5 A schematic diagram of a PWM converter with preset circuitry for recovery from a differential pressure fault, according to example embodiments of the disclosure.

[0040] Figure 6 A schematic diagram of a PWM converter with preset circuitry for recovery from a current limit fault, according to example embodiments of the disclosure.

[0041] Figure 7 A schematic diagram of a sampling circuit, according to example embodiments of the disclosure.

[0042] Figure 8 A schematic diagram of a differential pressure detector, according to example embodiments of the disclosure.

[0043] Figure 9 A flowchart representation of a method for dynamically enhancing loop response after recovery from a fault condition, according to example embodiments of the disclosure. DETAILED DESCRIPTION

[0044] The embodiments described herein provide a method and apparatus for preventing overshoot of the output of a PWM converter during recovery from a fault condition. The overshoot is avoided by predictively determining the error output level of the error amplifier to speed recovery from the fault condition. More specifically, the output of the error amplifier that is prone to saturation during the fault condition is dynamically preset to a state (e.g., voltage level) that is closest to the state that the error amplifier will be in after recovery from the fault condition. In one embodiment, the state is preset for each cycle of the PWM converter during the existence of the fault condition, so recovery from the fault does not depend on the length of time that the PWM converter spends in the fault condition. The value of the state is dynamically determined according to other conditions of the PWM power stage that are not prone to saturation during the fault condition.

[0045] Figure 1 An example embodiment 10 of a PWM converter configured as a current mode buck converter is shown. In example embodiment 10, an input voltage (Vin) is driven on input 12. The input voltage is referenced to ground 14 and converted to an output voltage (Vout) on output 16 by delivering a series of energy packets controlled by a PWM drive signal 20. The PWM drive signal 20 drives a PWM driver 22, which drives a P-channel field effect transistor (PFET) gate 24 in a PFET 26 (e.g., "high side transistor"), thereby increasing the output voltage 16. The PWM driver also drives an N-channel field effect transistor (NFET) gate 28 in a NFET 30 (e.g., "low side transistor"), thereby decreasing the output voltage.

[0046] PFET 26 and NFET 30 are both connected to node 32, where current is sourced or sunk through inductor 34 connected between node 32 and output 16. Capacitor 36 is connected between output 16 and ground 14. Inductor 34 and capacitor 36 form a load for embodiment 10 of the PWM converter. Resistors 38 and 40 form a resistive voltage divider that determines feedback voltage 42 used as part of a control loop for the PWM converter. Current sensor 46 determines current sensor output 48 with current detector 44. In one example embodiment, current detector 44 is one leg of a current mirror. In another example embodiment, current detector 44 is a Hall effect sensor.

[0047] Feedback voltage 42 is compared to reference voltage (Vref) 50 by error amplifier 52 to determine error output 54 (Veamp). In one example embodiment, error amplifier 52 is an operational transconductance amplifier (OTA). Error output 54 is applied across compensation resistor 56 in series with compensation capacitor 58. Compensation capacitor 58 is between compensation node 60 and ground 14. In one embodiment, error output 54 is also applied across additional capacitor 62 connected to ground 14.

[0048] PWM comparator 64 compares ramp voltage (Vramp) 66 to error voltage 54. Sense current 68 (Isns) derived from current sensor output 48 is combined with ramp current (Iramp) 70 by sense resistor 72 to form ramp voltage 66. Ramp current 70 is derived from ramp generator 74. Ramp generator 74 is controlled by feedback voltage 42, output 80 of PWM comparator 64, and clock 82 to determine ramp duration and amplitude. Clock 82 sets bistable device (e.g., flip-flop) 84 to drive PWM drive signal 20 high. Output 80 of PWM comparator 64 resets bistable device 84 to drive PWM drive signal 20 low.

[0049] In one embodiment, preset circuit 86 drives compensation node 60 and thus presets error output 54 to a voltage determined by the peak voltage of the PWM converter. In one embodiment, the peak voltage is determined by sampling the peak of ramp voltage 66 occurring at the end of one clock cycle of clock 82. In another embodiment, the peak voltage is determined by sampling the peak of ramp voltage 66 occurring at the end of each clock cycle of clock 82. Preset circuit 86 is activated by enable signal 88, which is activated upon detection of a fault condition (e.g., a differential voltage condition or a current limit condition).

[0050] A differential voltage condition in a buck converter is defined as a condition where the input voltage (Vin) of the converter drops below the programmed output voltage (Vout). As shown in FIG. 1, the output voltage (Vout) is determined by the voltage across inductor 34 and capacitor 36. The output voltage (Vout) is also determined by the voltage across resistors 38 and 40.Figure 1 The current-mode converter shown in FIG. 1 is expected to continue operating during a pressure differential condition, where the output of the converter closely tracks the input voltage. During the pressure differential condition, the error amplifier 52 becomes saturated. The error amplifier 52 is part of the control loop of the converter, thus lengthening the time to recover from the pressure differential condition. As the feedback voltage 42 decreases to a level that forces the error output 54 to reach a maximum level, the error amplifier saturates, driving the output 80 of the PWM comparator 64 toward the ground voltage, preventing the bistable device 84 from resetting, and forcing the high-side transistor 26 to reach 100% duty cycle (e.g., to remain in the "on" state).

[0051] Figure 2 With continued reference to Figure 1 , the voltage waveforms are shown without a dynamic boost loop response. Figure 1 The example embodiment of the error amplifier 52 in FIG. 1 is implemented as an OTA with a fixed transconductance gain (Gm) that has a limited output current capability and a high output impedance. When the pressure differential condition ends, the current-mode buck converter is expected to return to normal operation (e.g., the input voltage returns to a value higher than the programmed output voltage). If the input voltage rises quickly over time (e.g., with a high dv / dt), the output of the converter can overshoot significantly. Specifically, the input voltage at time 90 is higher than the output voltage at time 92, the duty cycle 94 of the PWM driver 22 is less than 100%, and the error output 54 is low at time 96 (i.e., the error amplifier 52 is not saturated). At time 100, the input voltage is equal to the output voltage, so further decreases in the input voltage will result in a pressure differential condition. As shown at time 102, the output voltage is equal to the input voltage as the input voltage continues to decrease below the programmed output voltage. When the feedback voltage 42 decreases below the reference voltage 50, the error amplifier 52 saturates, and the error output reaches a maximum value at time 104. At time 104, the duty cycle 94 is also maximized, thus holding the high-side transistor 26 in the "on" state, and thus equalizing the output voltage to the input voltage. The "programmed output voltage" is the desired output voltage, as compared to the "output voltage," which is the actual voltage obtained at the output 16 of the converter.

[0052] At time 105, when the input voltage increases to equal the programmed output voltage, the error output 54 decreases (or slews) at a slow rate due to the high impedance and fixed Gm of the error amplifier 52. Thus, the error amplifier 52 slews the voltage on the compensation node 60 at a constant rate at time 106, insufficient to prevent the excessive duty cycle in the time interval 108. Accordingly, during the time interval 108, the output voltage overshoots the programmed output voltage by an overshoot value 110. Eventually, the input voltage returns to the high level at time 112, and the output voltage returns to the programmed output voltage at time 114 when the error output slews down to a steady value at time 116. As shown for the differential voltage condition, similar behavior of the converter also occurs during the current limit condition.

[0053] In contrast, Figure 2 Figure 3 Referring to Figure 1 a voltage waveform with a dynamically enhanced loop response is shown. In one embodiment, the preset circuit 86 samples the peak voltage 120 in the ramp voltage 66 at the end of a clock cycle of the clock 82 to determine the peak voltage 120. The preset circuit 86 drives the compensation node 60 to the peak voltage 120, which is increased by a voltage offset 122. Accordingly, at time 124, the error amplifier 52 remains unsaturated, and the duty cycle 126 remains less than 100%.

[0054] Figure 4 an example embodiment 130 of the preset circuit 86 interfacing with the elements of embodiment 10 of Figure 1 Referring to Figure 1 , Figure 3 and Figure 4 , the preset circuit 86 samples the peak voltage 120 in the ramp voltage 66. The offset resistor 134 forms the offset voltage 122. Specifically, the error value (Veamp) on the error output 54 is made equal to the peak voltage 120, plus the bias current 136 of the error amplifier multiplied by the value of the compensation resistor 56, plus the value of the offset resistor 134. The bias current 136 is the maximum output current of the error amplifier 52. The sampling circuit 132 samples the peak voltage 120 and applies the peak voltage 120 to the offset resistor 134 at the output 133. In one embodiment, the offset voltage 122 exceeds the input reference offset 138 (shown symbolically at input 140) of the PWM comparator 64. The offset voltage 122 is important to avoid switching the PWM comparator 64 during the differential voltage condition. Typically, the input reference offset 138 of the PWM comparator 64 is small, so the effect of the voltage offset 122 on the output voltage of the PWM converter is negligible after the differential voltage condition ends.

[0055] Figure 5 ​An example embodiment 150 is shown configured to respond to a pressure differential condition of the PWM converter. Corresponding to the pressure differential condition, the pressure differential detector 152 asserts the enable signal 88 when the PWM comparator remains low for a predetermined period of time. In another embodiment, the enable signal 88 is determined by comparing the input of the error amplifier to a threshold. For example, the enable signal 88 is asserted when the feedback voltage 42 falls below the reference voltage 50 as determined by a comparator with hysteresis.

[0056] Figure 6 An example embodiment 160 is shown configured to respond to a current limit condition of the PWM converter. The current limit comparator 162 compares the voltage produced at the mirror sense current output 164 by the mirror sense current flowing through the sense resistor 163 to a threshold (not shown). When the mirror sense current rises above the threshold, the current limit comparator 162 determines the enable signal 88, where the enable signal 88 enables the sampling circuit 167 for sampling the voltage at the mirror sense current output 164. The current sensor 166 produces the mirror sense current at the mirror sense current output, which is mirrored by the sense current 68 provided at the sense current output 48.

[0057] Figure 7 An example embodiment 132 is shown for use within the preset circuit 86 of Figure 1 , Figure 4 and Figure 5 . Figure 6 The sampling circuit 167 of the example embodiment 160 is the same as the sampling circuit 132, but the sense input 164 of the circuit 167 replaces the sense input 66 of the circuit 132. The sampling circuit 132 includes a first switch 170 that samples the ramp voltage 66 onto a first capacitor 172, and a second switch 174 that samples the sampled voltage from the first capacitor 172 onto a second capacitor 176. The sampled voltage on the second capacitor 176 is received at an input 178, and an amplifier 180 amplifies the sampled voltage. The amplifier 180 has a low output impedance. The amplifier 180 is configured as a unity gain amplifier with a feedback back to the input of the amplifier 180. The output 182 of the amplifier 180 is delivered to the output 133 through a third switch 184. A logic circuit 186 activates a first switch control 188 in response to the enable signal 88 being active and after detecting the end of a clock cycle of the clock 82. The first switch control 188 is inverted by an inverter 190 to form a second switch control 192 and a third switch control 194. The first switch control 188, the second switch control 192, and the third switch control 194 activate the first switch 172, the second switch 174, and the third switch 184, respectively. The sampling circuit 132 is also referred to as a "sample and hold" circuit.

[0058] Figure 8 An example embodiment 160 is shown configured to respond to a current limit condition of the PWM converter. The current limit comparator 162 compares the voltage produced at the mirror sense current output 164 by the mirror sense current flowing through the sense resistor 163 to a threshold (not shown). When the mirror sense current rises above the threshold, the current limit comparator 162 determines the enable signal 88, where the enable signal 88 enables the sampling circuit 167 for sampling the voltage at the mirror sense current output 164. The current sensor 166 produces the mirror sense current at the mirror sense current output, which is mirrored by the sense current 68 provided at the sense current output 48.Figure 5 An example embodiment of the pressure differential detector 152 is shown. The pressure differential detector 152 resets the flip-flop 200 through the output 80 of the PWM comparator 64. During a pressure differential condition, the output 80 is in a low state, so the flip-flop has exited the reset state. The clock 82 transfers the data input 202 to the output of the flip-flop 200. The output of the flip-flop 200 is delayed through a series of inverters 204, 206, 208, and 210 to enable an AND gate 212 in alignment with the high state of the clock 82, and to enable a counter 214. Each transition of the clock 82 will cause a rising edge transition on the output of the AND gate 212. The rising edge transition on the output of the AND gate 212 will similarly cause a rising edge transition on the output of an AND gate 216, thereby advancing the count of the counter 214. When the counter 214 has reached a desired value corresponding to a predetermined time period or delay, a NAND gate 218 will activate the enable signal 88 through an inverter 219, and disable the AND gate 216 from advancing the count of the counter 214. It should be appreciated that other example embodiments of the sample circuit 132 and the pressure differential detector 152 can be used with the invention disclosed herein.

[0059] Figure 9 An example embodiment 220 of a method for dynamically enhancing loop response after recovery from a fault condition is shown. At 222, a fault condition of a PWM converter is detected when a programmed output voltage decreases below an input voltage of the PWM converter. At 224, a peak voltage 120 of the PWM converter is sampled. At 226, an error output 54 of an error amplifier 52 is preset to an error value determined from the sampled peak voltage. At 228, an output load (34 and 36) is charged to the programmed output voltage with the transistor when the input voltage increases above the programmed output voltage.

[0060] As should be appreciated, the disclosed embodiments include at least the following. In one embodiment, a method for dynamically enhancing loop response after recovery from a fault condition includes detecting a fault condition in response to a programmed output voltage of a PWM converter decreasing below an input voltage of the PWM converter. In response to detecting the fault condition, a peak voltage at an end of at least one clock cycle of the PWM converter is sampled, where the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined from the peak voltage. A PWM driver is controlled with the error value to drive the transistor. In response to the input voltage increasing above the programmed output voltage, an output load is charged to the programmed output voltage with the transistor.

[0061] In another embodiment, an apparatus includes a fault detector configured to detect a fault condition in response to a programmed output voltage of a PWM converter decreasing below an input voltage of the PWM converter. A sampling circuit is connected to a fault detector output of the fault detector, the fault detector configured to enable the sampling circuit in response to the fault condition. The sampling circuit is coupled to a current sense output of a current sensor configured to sense a sense current conducted through a transistor, wherein the sampling circuit samples a peak voltage at an end of at least one clock cycle of the PWM converter, and the peak voltage is proportional to the sense current. An offset circuit is connected between a sampling output of the sampling circuit and an error output of an error amplifier, wherein the offset circuit is configured to preset the error output to an error value determined by the peak voltage. A PWM driver is configured to drive the transistor in response to the error value, and the transistor is configured to charge an output load to the programmed output voltage in response to the input voltage increasing above the programmed output voltage.

[0062] In another embodiment, an apparatus includes a fault detector configured to detect a fault condition in a PWM converter. A sampling circuit is connected to a fault detector output of the fault detector, the fault detector configured to enable the sampling circuit in response to the fault condition. The sampling circuit is coupled to a current sense output of a current sensor configured to sense a sense current conducted through a high-side transistor, wherein the sampling circuit samples a peak voltage. An offset resistor is connected between a sampling output of the sampling circuit and a terminal of a compensation capacitor. A compensation resistor is connected between the terminal and an error output of an error amplifier, wherein the error output is preset to an error value determined by the peak voltage proportional to the sense current, and a voltage offset is formed between the offset resistor and the compensation resistor. A PWM driver is configured to drive the high-side transistor in response to the error value, and the high-side transistor is configured to charge an output load to a programmed output voltage in response to the input voltage increasing above the programmed output voltage.

[0063] While the application herein is described with reference to particular embodiments, various modifications and changes can be made without departing from the scope of the application as set forth in the claims that follow. The specification and drawings should thus be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the application. It is not intended that any benefit, advantage or solution to the problems herein described be understood as a key, essential or indispensable feature or element of any or all of the claims.

[0064] Unless otherwise stated, the terms "first" and "second" are used to arbitrarily distinguish terms that describe elements. Thus, these terms are not necessarily intended to indicate a chronological order or other priority.

Claims

1. A method for dynamically enhancing loop response after recovery from a fault condition, characterized by, comprising: detecting a fault condition in response to a programmed input voltage of a pulse width modulated (PWM) converter decreasing below an output voltage of the PWM converter; sampling a peak voltage at an end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sense current conducted through a transistor, the peak voltage is increased by a voltage offset; presetting an error output of an error amplifier to an error value determined from the peak voltage, the error value is used to control a PWM driver to drive the transistor; and charging an output load to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.

2. The method of claim 1, wherein, the peak voltage is increased by a compensation ramp voltage when the fault condition is a differential voltage condition.

3. The method of claim 1, wherein, the fault condition is a differential voltage condition detected without activating the PWM driver for a predetermined number of the plurality of clock cycles.

4. The method of claim 1, wherein, the fault condition is a current limit condition detected by comparing the sense current to a current limit.

5. The method of claim 1, wherein, the peak voltage is determined for each of the clock cycles.

6. The method of claim 1, wherein, determining the error value includes driving the peak voltage across a offset resistor, the error value is increased by a voltage offset determined by the offset resistor and a compensation resistor, wherein the offset resistor is connected in series with the compensation resistor, and the compensation resistor is connected to the error output.

7. The method of claim 6, wherein, the voltage offset is greater than an input reference offset of a PWM comparator configured to receive the error output of the error amplifier.

8. The method of claim 1, wherein, the transistor is a high side transistor connected between the input voltage and the output load.

9. A device for dynamically enhancing loop response after recovery from a fault condition, characterized in that, comprising: a fault detector configured to detect a fault condition in response to a programmed input voltage of a pulse width modulated (PWM) converter decreasing below an output voltage of the PWM converter; a sampling circuit connected to a fault detector output of the fault detector, the fault detector configured to enable the sampling circuit in response to the fault condition, the sampling circuit coupled to a current sense output of a current sensor configured to sense a sense current conducted through a transistor, wherein the sampling circuit samples a peak voltage at an end of at least one of a plurality of clock cycles of the PWM converter, and the peak voltage is proportional to the sense current, the peak voltage is increased by a voltage offset; and an offset circuit connected between a sampling output of the sampling circuit and an error output of an error amplifier, wherein the offset circuit is configured to preset the error output to an error value determined from the peak voltage, a PWM driver is configured to drive the transistor in response to the error value, and the transistor is configured to charge an output load to the programmed output voltage in response to the input voltage increasing above the programmed output voltage.

10. A device for dynamically enhancing loop response after recovery from a fault condition, characterized in that, comprising: a fault detector configured to detect a fault condition of a pulse width modulation (PWM) converter; a sampling circuit connected to a fault detector output of the fault detector, the fault detector configured to enable the sampling circuit in response to the fault condition, the sampling circuit coupled to a current sense output of a current sensor, the current sensor configured to sense a sense current conducted through a high side transistor, wherein the sampling circuit samples a peak voltage, the peak voltage increased by a voltage offset; and an offset resistor connected between a sampling output of the sampling circuit and one end of a compensation capacitor, a compensation resistor connected between the end and an error output of an error amplifier, wherein the error output is preset to an error value determined by the peak voltage proportional to the sense current, and a voltage offset is formed between the offset resistor and the compensation resistor, a PWM driver configured to drive the high side transistor in response to the error value, and the high side transistor configured to charge an output load to a programmed output voltage in response to an input voltage increased above the programmed output voltage.

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