Different size coplanar bump contacts

Abstract

Embodiments of the present disclosure relate to coplanar bump contacts of different sizes. The present disclosure relates to a die including a first contact (e.g., a ring-shaped contact) having a first shape and a second contact (e.g., a post-shaped contact) having a second shape different from the first shape. The first contact has an opening extending through a central region of a surface of the first contact. A first solder portion is coupled to the surface of the first contact, and the first solder portion has the first shape. A second solder portion is coupled to the surface of the second contact, and the second solder portion has the second shape. The first solder portion and the second solder portion have respective points that are furthest from a substrate of the die. The respective points of the first solder portion and the second solder portion are coplanar with each other, such that a footprint height of the die remains consistent when coupled to a PCB or electronic assembly.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to conductive contacts and structures on a die surface. BACKGROUND

[0002] Generally, semiconductor device packages, such as chip scale packages or wafer level chip scale packages (WLCSPs), contain semiconductor devices, semiconductor wafers, or integrated circuit dies. These can be sensors configured to detect any number of quantities or qualities or controllers for controlling various other electronic components. For example, such semiconductor device packages can detect light, temperature, sound, pressure, stress, strain, or any other quantity or quality.

[0003] Semiconductor device packages can be formed utilizing flip chip technology, where a semiconductor die is flipped by a pick and place machine and then mounted to a printed circuit board (PCB) by the pick and place machine after flipping. The semiconductor die can be coupled to the PCB by solder balls. These solder balls are generally the same size and have no variation in shape or size. However, as semiconductor device packages become more advanced to perform increasingly complex functions, various different sizes of solder bumps are needed to couple the semiconductor die to the printed circuit board or to mount the semiconductor die within the semiconductor device package.

[0004] A significant challenge in forming different various sizes of solder bumps is achieving coplanarity between the different various sizes of solder bumps. If the different various sizes of solder bumps are not coplanar to each other at a point furthest from the die substrate, then the semiconductor die can be at an angle or functional electrical connections can not be formed within the semiconductor device package.

[0005] Another significant challenge in manufacturing increasingly advanced semiconductor device packages is forming the solder bumps to form electrical connections that are robust enough to withstand stresses and strains that the semiconductor device package can be exposed to, thereby reducing the likelihood of the solder components breaking or failing. For example, if the solder components are not robust enough, then the solder components can break or break off during shipping of these conventional semiconductor device packages due to vibrational stresses during shipping of these conventional semiconductor device packages, thereby causing the semiconductor device package to no longer function when the semiconductor device package is transported or moved.

[0006] In conventional semiconductor dies that use different sized solder bumps, the different sized solder bumps are not substantially coplanar with each other. This non-coplanarity between the different sized solder bumps causes the semiconductor die to be at an angle with respect to the surface to which the semiconductor die is coupled. This can cause other components to become misaligned within the semiconductor device package, where the dies are part of the increasing functionality being accomplished in complex electronic devices. The angle can cause electrical connections within the semiconductor device package or electronic device to be more prone to breaking and failure, thus also reducing the useful life of the semiconductor device package and electronic device.

[0007] To avoid the coplanarity issues of different various sized solder components discussed directly above, conventional semiconductor dies typically include solder bumps that are all the same size and made of the same amount of solder, such that the solder bumps also all have the same volume. SUMMARY

[0008] Embodiments of the present disclosure overcome significant challenges associated with coplanarity issues between various different sized and shaped solder components to form electrical connections discussed above. One significant challenge is forming different various sized solder components that have a point that is coplanar with each other that is furthest from a substrate of a semiconductor die. This coplanarity allows the semiconductor die in a semiconductor device package to be non-angled within the semiconductor device package and allows each electrical connection to be formed with higher reliability when forming the semiconductor device package. This higher reliability improves the overall yield of usable semiconductor device packages when positioning semiconductor dies within semiconductor device packages with different various sized solder components.

[0009] In one embodiment, the semiconductor die has some contacts that are ring-shaped contacts, with an opening extending through a central region of each of the ring-shaped contacts. By ring-shaped is meant that an outer shape surrounds an inner shape (e.g., an outer circle having a first diameter surrounds an inner circle having a second diameter that is less than the first diameter). The ring-shaped contacts allow ring-shaped solder components to be formed on surfaces of the ring-shaped contacts. Some other contacts of the semiconductor die have a different shape (e.g., a columnar shape) than the ring-shaped contacts, and solder bumps are formed on surfaces of these differently shaped contacts. However, the solder bumps on these differently shaped contacts and the ring-shaped solder components on the ring-shaped contacts have points that are farthest from a substrate of the semiconductor die, such that these points are all coplanar with each other. This coplanarity means that when the semiconductor die is mounted to a surface of, for example, a PCB, the semiconductor die is substantially parallel to the surface of the PCB, rather than angled with respect to the surface of the PCB. In other words, the standoff height between the semiconductor die and the surface of the PCB is substantially the same at each point along the surface of the PCB, for example, when the semiconductor die is coupled to the surface of the PCB. This allows for more robust electrical connections to be formed between the PCB and the semiconductor die, where the electrical connections are exposed to a greater amount of stress or strain relative to other electrical connections between the PCB and the semiconductor die.

[0010] The coplanarity between the differently sized solder components discussed above also reduces the likelihood that electrical connections do not form between the PCB and the semiconductor die. For example, if the differently sized solder components are not substantially coplanar with each other, then some electrical connections between the PCB and the semiconductor die can be less reliable in transmitting electrical signals to the semiconductor die through the PCB and the solder components. BRIEF DESCRIPTION OF DRAWINGS

[0011] For a better understanding of the embodiments, reference will now be made, by way of example, to the accompanying drawings. In the drawings, like reference numerals identify like elements or acts, unless the context dictates otherwise. The sizes and relative proportions of the elements in the drawings are not necessarily drawn to scale. For example, some of the elements can be exaggerated and positioned to improve drawing legibility.

[0012] FIG. 1A is a cross-sectional view of a die embodiment taken along line 1A-1A in FIG. 1B ;

[0013] FIG. 1B is a bottom view of a die embodiment in FIG. 1A ;

[0014] FIG. 1C is a perspective view of an embodiment of surfaces of first and second contacts of a die in FIGS. 1A-1B ;

[0015] FIG. 1D is FIGS. 1A-1C a perspective view of an embodiment of a die having a first contact and a second contact of a surface of the die covered by a conductive material;

[0016] FIG. 2 is including FIGS. 1A-1D a cross-sectional view of an embodiment of a package of an embodiment of a die as shown;

[0017] FIGS. 3A-3I shows an embodiment of a method of manufacturing FIGS. 1A-1D an embodiment of a die as shown;

[0018] FIGS. 4A-4B shows steps of an alternative embodiment of a method of manufacturing FIGS. 1A-1D an embodiment of a die as shown; and

[0019] FIGS. 5A-5B shows steps of an alternative embodiment of a method of manufacturing FIGS. 1A-1D an embodiment of a die as shown. DETAILED DESCRIPTION

[0020] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the disclosure. However, one skilled in the art will understand that the disclosure can be practiced without these specific details. In other instances, well-known structures associated with electronic components and semiconductor fabrication techniques have not been described in detail in order to avoid unnecessarily obscuring the description of embodiments of the disclosure.

[0021] Unless the context requires otherwise, throughout the present specification and claims, the word “comprise” and variations thereof (such as “comprises” and “comprising”) are to be construed in an open, inclusive sense, that is as “including, but not limited to.”

[0022] Use of ordinal terms such as first, second, and third, etc. does not necessarily denote an ordinal sense, but can simply distinguish actions or structures from one another.

[0023] Reference throughout this specification to “one embodiment” and “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0024] Based on the orientation of the components in the following discussion of the figures in the present disclosure, the terms "left," "right," "top," and "bottom" are used solely for discussion purposes. These terms do not limit the possible positions of the components expressly disclosed, implicitly disclosed, or inherently disclosed in the present disclosure.

[0025] The term "substantially" is used to account for minor variations that can exist when the package is manufactured in the real world, as nothing can be made exactly equal or exactly the same. In other words, substantially means that there can be some minor variations in actual practice, while still being within acceptable tolerances.

[0026] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the content clearly dictates otherwise.

[0027] While various embodiments are illustrated and described with respect to semiconductor dies and semiconductor packages, it will be readily apparent to those having ordinary skill in the art that the embodiments of the present disclosure are not limited to this context. In various embodiments, the structures, devices, methods, etc. described herein can be implemented in or otherwise used in connection with any suitable type or form of semiconductor die or package, and can be manufactured utilizing any suitable semiconductor die and package technology, as desired.

[0028] FIGS. 1A-1D Referring to die 100 in accordance with embodiments disclosed herein, there are different sized solder contacts that protrude outwardly from substrate 102 of die 100 to the same height. FIG. 1A is a cross-sectional view of die 100, which can be used in a variety of different applications. For example, die 100 can be a sensor (e.g., a pressure sensor, a temperature sensor, a vibration sensor, a MEMS sensor, etc.), an integrated circuit (e.g., an application specific integrated circuit (ASIC), a substrate with active components inside, etc.), or some other type of die or integrated circuit. Die 100 includes substrate 102, first contact pad 104, second contact pad 106, first non-conductive layer 108, second non-conductive layer 110, first conductive layer 112, second conductive layer 113, first conductive structure 114, second conductive structure 116, first solder component 118, and second solder component 120.

[0029] First conductive structure 114 has a ring shape, and first solder component 118 is located on first conductive structure 114. First solder component 118 has a ring shape. The ring includes an outer surface 138, which can be referred to as a first arc or circular wall, that is concentric with an inner surface 140, which can be referred to as a second arc or circular wall. The center of first conductive structure 114 is open at opening 144, i.e., does not include conductive material. When die 100 is viewed in a bottom view, first circular wall 138 surrounds second circular wall 140, which can be seen in FIGS. 1B-1DThe first conductive structure includes a surface 142 extending from the outer surface 138 to the inner surface 140. The surface 142 is transverse to the outer surface 138 and the inner surface 140. The surface 142 has an annular shape and surrounds the opening 144.

[0030] The edge 143 at the end of the outer surface 138 surrounds the edge 145 at the end of the inner surface 140, and the surface 142 of the conductive material of the conductive structure 114 extends between the edge 143, the edge 145, i.e., the conductive material of the conductive structure 114 extends between the edge 143, the edge 145. The edge 143, the edge 145 are substantially circular. However, in some embodiments, the edge 143, the edge 145 can have different shapes from each other or similar shapes to each other. For example, the edge 143 can be a square shape, and the edge 145 can be an oval shape, such that the opening 144 is an oval shape. Alternatively, the edge 143 can be rectangular, and can surround the edge 145 which can have a circular shape, such that the opening 144 has a circular shape. In other words, the edge 143, the edge 145 can be some other combination of outer and inner shapes.

[0031] The second conductive structure 116 is a cylindrical conductive structure, and the second solder component 120 is a solder ball on the second conductive structure 116. The second solder component 120 can have a semi-spherical shape. The first solder component 118 and the second solder component 120 each have a point that is farthest from the substrate 102, and are substantially coplanar with each other. These points of the solder components 118, 120 are along a representative dashed line 121 that extends across the solder components 118, 120. This coplanarity between the solder components 118, 120 takes advantage of the different shapes and sizes of the conductive structures 114, 116 and the solder components 118, 120, which will be discussed in more detail later herein.

[0032] The substrate 102 has a first surface 122 and a second surface 124 opposite the first surface 122. The first surface 122 can be referred to as a passive surface, an outer surface, or some other language or reference to a surface of the substrate 102. The second surface 124 can be referred to as an active surface on which active components reside, a mounting surface, a contact surface, or some other language or reference to a surface of the substrate 102. The second surface 124 provides a platform on which the non-conductive layer 108, the non-conductive layer 110, the conductive layer 112, the conductive layer 113, the conductive structure 114, the conductive structure 116, and the solder members 118, 120 are formed, respectively. In some embodiments, the substrate 102 can be a semiconductor material, a silicon material, a dielectric material, or some other substrate material or combination of substrate materials. In some embodiments, the substrate 102 can be made of multiple layers of semiconductor material, multiple layers of silicon material, multiple layers of dielectric material, or some other combination of multiple layers of substrate material. For example, in some embodiments, the substrate 102 can be made of a stack of various material combinations, such as semiconductor material, dielectric material, silicon material, conductive material, passivation material, re-passivation material, or some other combination of materials or substrate materials.

[0033] The first contact pad 104 is on the second surface 124 of the substrate 102. The first contact pad 104 provides electrical connections to electrical components within the substrate 102. While these electrical components are not shown for simplicity and brevity, these electrical components can be electrical vias, conductive layers, transistors, sources, gates, drains, or some other electrical component or combination of electrical components within the substrate 102. The first contact pad 104 has a dimension dl that extends between opposite ends 125 of the first contact pad 104. The first contact pad 104 can be one of a plurality of first contact pads 104 on the second surface 124.

[0034] The second contact pad 106 is on the second surface 124 of the substrate 102 and provides electrical connections to electrical components within the substrate 102 in the same manner as the first contact pad 104 discussed earlier. The second contact pad 106 is spaced apart from the first contact pad 114 and has a second dimension d2 that extends between opposite ends 127 of the second contact pad 106. The second dimension d2 is less than the first dimension dl. The second contact pad 106 can be one of a plurality of second contact pads 106 on the second surface 124.

[0035] The first non-conductive layer 108 is on the second surface 124 of the substrate 102. The first non-conductive layer 108 covers the end 125 of the first contact pad 104 and the end 127 of the second contact pad 106, respectively. The first non-conductive layer 108 is between the first contact pad 104 and the second contact pad 106 to electrically isolate the first contact pad 104 from the second contact pad 106. The first non-conductive layer 108 reduces the likelihood of electrical cross-talk between the first contact pad 104 and the second contact pad 106. Electrical cross-talk is the direct transfer of a signal from the first contact pad 104 to the second contact pad 106, and vice versa.

[0036] The second non-conductive layer 110 is on the first non-conductive layer 108, and a portion 128 of the second non-conductive layer 110 is on the surface 130 of the first contact pad 104. The portion 128 is aligned with the center of the surface 130 of the first contact pad 104, and can have a substantially circular shape, which can be seen in FIGS. 1B-1D In some embodiments, the portion 128 can have a substantially square shape, a substantially rectangular shape, a substantially oval shape, or some other shape or combination of shapes.

[0037] The first non-conductive layer 108 and the second non-conductive layer 110 can be a dielectric material, a passivation material, a re-passivation material, an insulating material, or some other non-conductive material or combination of non-conductive materials.

[0038] The first conductive layer 112 extends through the second non-conductive layer 110 to the surface 130 of the first contact pad 104. The first conductive layer 112 is directly on and coupled to the surface 130 of the first contact pad 104. The first conductive layer 112 is between the portion 128 of the second non-conductive layer 110 and the rest of the second non-conductive layer 110, such that the portion 128 is isolated, spaced apart, and separated from the second portion 129 of the second non-conductive layer 110. The first conductive layer 112 has a substantially annular shape, such that the first conductive layer 112 surrounds the portion 128 of the second non-conductive layer 110. The first conductive layer 110 covers a side surface 132 of the portion 128 of the second non-conductive layer 110, and the first conductive layer 110 covers a side surface 134 that is part of the second portion 129 of the second non-conductive layer 110. The side surface 134 surrounds the side surface 132 of the portion 128. The side surfaces 132, 134 are transverse to the second surface 124. The first conductive layer 112 can be a copper material, a gold material, a silver material, an alloy material, or some other conductive material or combination of conductive materials.

[0039] The second conductive layer 113 extends through the second non-conductive layer 110 to the surface 131 of the second contact pad 106. The second conductive layer 113 is directly on and coupled to the surface 131 of the second contact pad 106. The second conductive layer 113 covers the side surface 136 of the second non-conductive layer 110. The second conductive layer 113 and the side surface 136 have a substantially circular shape, which can be seen in FIGS. 1B-1D . The side surface 136 is transverse to the second surface 124 of the substrate 102. In some embodiments, the side surface 136 can have a substantially rectangular shape, a substantially square shape, a substantially oval shape, or some other shape or combination of shapes.

[0040] The first conductive structure 114 is on and coupled to the first conductive layer 112. When viewed in the bottom view shown in FIG. 1B , the first conductive structure 114 and the first conductive layer 112 have substantially the same shape.

[0041] The first conductive structure 114 also includes an opening that extends into the first conductive structure 114 and exposes a surface 146 of the portion 128 of the second non-conductive layer 110. The opening 144 extends completely through the first conductive structure 114 to the surface 146 of the portion 128. The opening 144 is surrounded by the inner surface 140 of the first conductive structure 114. The opening 144 is surrounded by the inner surface 140 of the first conductive structure 114 and the surface 146 of the portion 128 of the second non-conductive layer 110. The opening 144 has a substantially circular shape, which can be seen in FIGS. 1B-1D . In some embodiments, the opening 144 can have a substantially rectangular shape, a substantially square shape, a substantially oval shape, or some other shape or combination of shapes.

[0042] The first conductive structure 114 has a dimension d3 that extends from the surface 146 of the portion 128 of the second non-conductive layer 110 to the surface 142 of the first conductive structure 114.

[0043] The second conductive structure 116 has an outer surface 148 and a surface 150 that is transverse to the outer surface 148. The surface 150 is transverse to the outer surface 148, which can be seen in FIG. 1C . The second conductive structure 116 covers the second conductive layer 113.

[0044] The second conductive structure has a dimension d4 that extends from the surface 152 of the second portion 129 of the second non-conductive layer 110. The dimension d4 is substantially equal to the dimension d3.

[0045] The first solder component 118 is on and coupled to a surface 142 of the first conductive structure 114. The first solder component 118 has substantially the same shape as the first conductive structure 114 and the first conductive layer 112 as set forth earlier. The first solder component 118 includes a dimension d5 extending from the surface 142 to a point of the first solder component 118 furthest from the surface 142 of the first conductive structure 114.

[0046] The second solder component 120 is on and coupled to a surface 150 of the second conductive structure 116. The second solder component 120 is the solder ball set forth earlier. The second solder component 120 includes a dimension d6 extending from the surface 150 to a point of the second solder component 120 furthest from the surface 150 of the second conductive structure 116. The dimension d6 is substantially equal to the dimension d5.

[0047] In view of the earlier discussion, the first conductive structure 114 and the first solder component 118 will have substantially the same shape as the first conductive layer 112. For example, if the first conductive layer 112 has a substantially circular ring shape, then the first conductive structure 114 and the first solder component will have the substantially circular ring shape of the first conductive layer 112.

[0048] In view of the earlier discussion, the second conductive structure 116 and the second solder component 120 will have substantially the same shape as the second conductive layer 113. For example, if the second conductive layer 113 has a substantially circular shape, then the second conductive structure 116 and the second solder component 120 will have the substantially circular shape of the second conductive layer 113.

[0049] In view of the earlier discussion with respect to the dimensions d3, d4, d5, d6 of the conductive structures 114, 116 and the solder components 118, 120, the sum of the dimensions d3 and d5 is substantially equal to the sum of the dimensions d4 and d6. These sums being equal to each other allows each of the solder components 118, 120 to have a respective point furthest from the surface 124 of the substrate 102 to be substantially coplanar with each other.

[0050] The die 100 includes a sidewall 154 that can be made of the substrate 102, the first non-conductive layer 108, and the second non-conductive layer 110. The conductive layers 104, 106, 112, 113 are spaced inwardly from the sidewall 154 to avoid exposing conductive features (e.g., electrical active components and passive components such as resistors, transistors, etc.) within the die 100.

[0051] FIG. 1B is FIG. 1A A bottom view of the die 100 is shown. FIG. 1BThe substantially annular shape of the first conductive structures 114 and the substantially circular shape of the second conductive structures 116 are illustrated.

[0052] The dimension d7 of the first solder component 118 is substantially equal to the dimension dl. The dimension d7 is a diameter of the first solder component 118. In some embodiments, the dimension d7 can be less than the dimension dl.

[0053] The dimension d8 of the second solder component 120 is substantially equal to the dimension d2. The dimension d8 is a diameter of the second solder component 120. In some other embodiments, the dimension d8 can be greater than, substantially equal to, or less than the dimension d2.

[0054] The dimension d9 of the first conductive structures 114 is less than the dimension d7 and the dimension dl. The dimension d9 is a diameter of the first conductive structures 114. In some embodiments, the dimension d9 can be substantially equal to or greater than the dimension dl.

[0055] The dimension d 10 of the second conductive structures 116 is less than the dimension d8 and the dimension d2. The dimension d 10 is a diameter of the second conductive structures 116. In some embodiments, the dimension d 10 may be substantially equal to or greater than the dimension d2.

[0056] FIGS. 1C-1D is a magnified perspective view of one of the first conductive structures 114 and one of the second conductive structures 116 on the second surface 124 of the substrate 102.

[0057] FIG. 2 is a package 200 containing FIGS. 1A-1D the embodiment of the die 100 shown. The die 100 can be attached to an electrical component 202 using flip chip technology. For example, the flip chip technology can utilize a pick-and-place machine that picks up the die 100, flips the die, and then positions the die 100 onto the electrical component 202, which can be an application specific integrated circuit (ASIC), a printed circuit board (PCB), a semiconductor chip, or some other electrical component.

[0058] The electrical component 202 includes a substrate 204 having a first surface 206 and a second surface 208 opposite the first surface 206. A first non-conductive layer 210, a plurality of first conductive layers 212, and a plurality of second conductive layers 214 are located on the first surface 206. The substrate 204 can be a silicon material, a semiconductor material, or another substrate material or combination of substrate materials.

[0059] Each of the first solder components 118 of the die 100 is coupled to a corresponding one of the first conductive layers 212. Each of the second solder components 120 of the die 100 is coupled to a corresponding one of the second conductive layers 214.

[0060] The electrical assembly 202 also includes a second non-conductive layer 216 on the second surface 208 of the substrate 204, a plurality of third conductive layers 218, and a third non-conductive layer 220. The second non-conductive layer 216 surrounds each of the third conductive layers 218. The third non-conductive layer 220 is on the second non-conductive layer 216 and can be on and partially cover a surface 222 of the third conductive layers 218. The third non-conductive layer 220 has openings 224 that expose the surface 222 of the third conductive layers 218.

[0061] The plurality of vias 224 are in the substrate 204 and extend through the substrate 204 from the first surface 206 to the second surface 208. Some of the vias 224 couple each of the first conductive layers 212 to one of the third conductive layers 218, and some of the vias 224 couple each of the second conductive layers 214 to one of the third conductive layers 218. The first conductive layers 212, the second conductive layers 214, and the vias 224 form electrical connections that allow signals to be communicated to and from the die 100 to external electrical assemblies outside of the package 200. The plurality of vias 224 can be through-silicon vias (TSVs).

[0062] The first non-conductive layer 210 can be an insulating material, a dielectric material, or some other non-conductive material or combination of non-conductive materials. The first conductive layers 212 and the second conductive layers 214 can be made of a copper material, a gold material, a silver material, an alloy material, or some other conductive material or combination of conductive materials. The first conductive layers 212 and the second conductive layers 214 can be referred to as electrical contacts, electrical pads, electrical contact pads, or some other language or reference to the conductive layers.

[0063] The electrical assembly 202 can be a printed circuit board (PCB), an application-specific integrated circuit (ASIC) die, a controller die, or some other electrical assembly to which the die 100 is coupled.

[0064] The first epoxy 226 fills the openings 144 of the first conductive structures 114 and the gaps between the first conductive structures 114 and the second conductive structures 116 and separates the first conductive structures 114 and the second conductive structures 116. The first epoxy 226 electrically isolates each of the first conductive structures 114 and the second conductive structures 116 from each other to avoid electrical cross-talk between the conductive structures 114, 116. Electrical cross-talk refers to signals passing directly between the first conductive structures 114 and the second conductive structures 116 from each other. The first epoxy 226 is on the second non-conductive layer 110. The first epoxy 226 partially covers the sidewalls 154 of the die 100. The first epoxy 226 includes a sloped surface 228. In some embodiments, the surface 228 can be curved in a concave or convex manner instead of being sloped as shown. FIG. 2 The first epoxy 226 can be referred to as a bottom fill epoxy that is partially positioned between the electrical components 202 and the die 100.

[0065] The second epoxy 230 is on and covers the second surface 124 of the die 100 and covers the remaining sidewalls 154 that are not covered by the first epoxy 226. The second epoxy 230 helps to protect the die 100 from external stresses and forces that can cause the die to fail if applied directly to the die 100. For example, the die 100 is dropped, the die 100 is pressed upon, or other stresses or external forces.

[0066] The first conductive layer 212, the second conductive layer 214, the third conductive layer 218, and the via 224 can be made of a conductive material, such as a copper material, a gold material, an alloy material, or some other conductive material or combination of conductive materials.

[0067] The first non-conductive layer 210, the second non-conductive layer 216, and the third non-conductive layer 220 can be a passivation material, a re-passivation material, an insulating material, a dielectric material, or some other non-conductive material or combination of non-conductive materials.

[0068] The first epoxy 226 and the second epoxy 230 can be a molding compound material, an insulating material, a resin material, or some other non-conductive material or combination of non-conductive materials. In some embodiments, the first epoxy 226 can alternatively be an adhesive, a glue, a die attach film (DAF), or some other coupling material or combination of coupling materials. In some embodiments, the second epoxy 230 can not be present and there can only be the first epoxy covering and filling the space between the electrical components 202 and the die 100.

[0069] In general, conventional semiconductor dies can include a plurality of conductive structures that protrude outward from a surface of the conventional semiconductor die, and a plurality of solder bumps are coupled to the surface of the conductive structures. These conventional conductive structures all have the same size, profile, and overall shape, and these conventional solder bumps also have the same size, profile, and overall shape. These conventional conductive structures and conventional solder bumps generally allow for a consistent footprint height, i.e., a distance between the conventional semiconductor die and a PCB or ASIC die to which the conventional semiconductor die is coupled, that remains consistent along the conventional semiconductor die when coupled to the PCB or ASIC. FIGS. 1A-1D The illustrated embodiment of the die 100 of the present disclosure has a first conductive structure 114 that is substantially ring-shaped and a second conductive structure 116 that is substantially circular (e.g., cylindrical). The die 100 also includes a first solder component 118 coupled to the first conductive structure 114 and a second solder component 120 coupled to the second conductive structure 116. The first solder component 118 has a ring shape, and the second solder structure 120 is a solder bump. These different sized conductive structures 114, 116 and solder components 118, 120 allow for a consistent footprint height between the die 100 and a PCB or ASIC die to which the die 100 is coupled to remain consistent along the die 100 when coupled to the PCB.

[0070] However, unlike conventional semiconductor dies, the first conductive structure 114 and the first solder component 118 of the die 100 allow for a greater amount of solder to be coupled to the PCB when compared to the second conductive structure 116 and the second solder component 120 of the die 100. This greater contact formed between the first conductive structure 114, the first solder component 118, and the PCB when compared to the second conductive structure 116 and the second solder component 120 allows for a stronger adhesive bond between the PCB and the die 100 at the location of the first conductive structure 114. The greater contact formed by the first conductive structure 114 and the first solder component 118 also provides for greater or stronger electrical communication when compared to the second conductive structure 116 and the second solder component 120. Thus, the first conductive structure 114 can be formed in selected locations on the die 100 that are exposed to greater stresses and strains where electrical communication can need to be stronger, or both, so that the useful life of the die 100 is increased in use. For example, at the corners of the die 100 or near the edges of the die 100, die flexing or bending due to expansion and contraction can be more likely to cause solder cracks at these locations. Thus, the first conductive structure 114 can be located at the corners of the die 100, while the second conductive structure 116 can be positioned closer to the center of the die 100.

[0071] Unlike conventional semiconductor dies having the same solder bumps and conductive structures, the conductive structures 114, the first solder component 118, and the second solder component 120 on the conductive structures 116 of the die 100 have different sizes, shapes, and profiles relative to one another. However, similar to the conventional solder bumps in conventional semiconductor dies having points that are farthest from the conventional semiconductor dies that are all coplanar with one another, the first solder component 118 and the second solder component 120 have points that are farthest from the substrate 102 of the die 100 such that the points are all coplanar with one another along the line 121, which can be seen in FIG. 1A FIG. 1. Thus, when the solder components 118, 120 are coupled to a PCB or ASIC die, the standoff height between the die 100 and the PCB or ASIC die is consistent, and the die 100 is not angled relative to the PCB or ASIC.

[0072] Generally, a certain alternative conventional semiconductor die has a plurality of conventional first conductive structures that are different in size and shape than a plurality of conventional second conductive structures, compared to those discussed directly above. The conventional first conductive structures and the conventional second conductive structures generally do not have openings extending through them, but are each cylindrical in shape. The conventional first conductive structures are generally larger than the conventional second conductive structures. Conventional first solder components are coupled to the conventional first conductive structures, and the conventional first solder components are generally larger than conventional second solder components coupled to the conventional second conductive structures. However, the conventional first solder components and the conventional second solder components are generally both solder bumps. These conventional solder structures and conventional solder components of the alternative conventional semiconductor die generally have a relatively large amount of variation between respective points of the conventional solder components that need to be coplanar with one another relative to the solder components 118, 120 of the die 100.

[0073] Unlike the alternative conventional semiconductor die, the first solder component 118 having a ring shape and the second solder component 120 that can be a solder bump and have a semi-spherical shape have points that are farthest from the substrate 102 such that the points are coplanar along the line 121, as shown in FIG. 1A Thus, when the die 100 is coupled to a PCB, the standoff height of the die 100 is consistent. In other words, the die 100 is not angled relative to a surface of the PCB to which the die 100 is coupled with the first solder component 118 and the second solder component 120. Thus, when compared to the die 100 coupled to a PCB or ASIC die, the variation of the conventional solder components of the alternative conventional semiconductor die results in a less consistent standoff height when the alternative conventional semiconductor die is coupled to a PCB or ASIC die.

[0074] FIGS. 3A-3H is to manufacture FIGS. 1A-1Dvarious cross-sectional views of steps of the method of the die 100 shown. For brevity and simplicity, features similar to those described above with respect to the formation of the first and second conductive layers 306, 308 will not be described in detail. FIGS. 1A-1D features similar to those described above with respect to the formation of the first and second conductive layers 306, 308 will not be described in detail. FIGS. 3A-3H features in FIGS. 1-3 will not be described in detail.

[0075] FIG. 3A is a cross-sectional view of a wafer 300 having a first surface 302 and a second surface 304 opposite the first surface 302. A plurality of first conductive layers 306 and a plurality of second conductive layers 308 are formed on the first surface 302 of the wafer 300. The first and second conductive layers 306, 308 can be formed by a sputtering technique, a photoresist patterning technique, a vapor deposition technique, an etching technique, or some other technique or combination of techniques to form and pattern layers of conductive material.

[0076] For example, the conductive layers 306, 308 can be formed by sputtering conductive material over the first surface 302 to cover the first surface 302. After sputtering, a photoresist material is formed over the conductive material and is patterned to have openings at locations where the conductive material is to be removed. A chemical etchant is then applied to the patterned photoresist layer and the chemical etchant enters the openings in the patterned photoresist to remove portions of the conductive material exposed by the openings. This patterns the conductive material to form the conductive layers 306, 308. Once the conductive layers 306, 308 are formed, the patterned photoresist material is removed, thereby exposing the first and second conductive layers 306, 308. The first conductive layers 306 correspond to the first contact pads 104 in the die 100. The second conductive layers 308 correspond to the second contact pads 106 of the die 100.

[0077] Once the first and second conductive layers 306, 308 are formed, a first non- conductive layer 310 is formed on the first surface 302 of the wafer 300 and on the ends of the first and second conductive layers 306, 308. The first non-conductive layer 310 is formed in a similar manner as discussed above with respect to the formation of the first and second conductive layers 306, 308. However, unlike the formation of the first and second conductive layers 306, 308, a chemical etchant is applied that is configured to remove portions of the first non-conductive layer 310 and not the first and second conductive layers 306, 308. The first non-conductive layer 310 corresponds to the first non-conductive layer 108 of the die 100, as FIGS. 1A-1D shown.

[0078] Once the first non-conductive layer 310 is formed and patterned, a second non-conductive layer 312 is formed. The second non-conductive layer 312 is formed in a similar manner as discussed earlier with respect to the formation of the first and second conductive layers 306 and 308. However, unlike the formation of the first and second conductive layers 306 and 308, a chemical etchant is applied that is configured to remove portions of the second non-conductive layer 312, but not the first and second conductive layers 306 and 308. The second non-conductive layer 312 includes a plurality of first portions 314 and second portions 316. Each first portion is centered over each second conductive layer 308. The first portions 314 have a substantially circular shape, which can be seen in FIG. 3B .

[0079] When the chemical etchant is applied to the second non-conductive layer 312 to remove portions of the second non-conductive layer 312, a plurality of first openings 318 and a plurality of second openings 320 are formed. These portions are selectively removed by using a temporary photoresist layer that is formed on the second non-conductive layer 312 and is patterned, such that the chemical etchant forms the first and second openings 318 and 320. The temporary photoresist is then removed after the first and second openings 318 and 320 are formed.

[0080] Each first portion 314 is surrounded by a corresponding one of the first openings 318 that has an annular shape. The second portions 316 of the second non-conductive layer 312 make up a majority of the second non-conductive layer 312 and surround the first openings 318 and the first portions 314. The second non-conductive layer 312 will form the second non-conductive layer 110 of the die 100. The first portions 314 correspond to the first portions 128 of the second non-conductive layer 110, and the second portions 316 correspond to the second portions 129 of the second non-conductive layer 110, as shown in FIGS. 1A-1D . Each of the first openings 318 exposes a corresponding one of the first conductive layers 306. Each of the second openings 320 exposes a corresponding one of the second conductive layers 308.

[0081] The plurality of second openings 320 extend into the second portions 316 of the second non-conductive layer 312. The second openings 320 have a substantially circular shape, which can be seen in FIG. 3B . Each of the second openings 320 exposes a corresponding one of the conductive layers 308.

[0082] FIG. 3Bis a top view of wafer 300 with first conductive layer 306, second conductive layer 308, first non-conductive layer 310, and second non-conductive layer 312 on the wafer. The top view of wafer 300 shows first portion 314 having a substantially circular shape, first opening 318 having a substantially annular shape, and second opening 320 having a substantially circular shape. In some embodiments, the annular shape of first opening 318 can be substantially rectangular, square, oval, or some other shape. In some embodiments, first portion can be substantially rectangular, square, oval, or some other shape or combination of shapes. In some embodiments, second opening 320 can be substantially square, rectangular, square, triangular, or some other shape or combination of shapes.

[0083] After first conductive layer 306, second conductive layer 308, first non-conductive layer 310, and second non-conductive layer 312 are formed on wafer 300, third conductive layer 321 is formed on wafer 300 as seen in FIG. 3C . Third conductive layer 321 is formed in a similar manner as discussed with respect to the formation of first conductive layer 306 and second conductive layer 308. However, unlike the formation of first conductive layer 306 and second conductive layer 308, in which conductive material is patterned to form first conductive layer 306 and second conductive layer 308, third conductive layer 321 is sputtered onto second non-conductive layer 312 and is not patterned. Third conductive layer 321 covers first portion 314 and second portion 316 of second non-conductive layer 312 and partially fills first opening 318 and second opening 320 in second non-conductive layer 312.

[0084] After third conductive layer 321 is formed on wafer 300 as shown in FIG. 3C , first temporary layer 322 is formed on third conductive layer 321 in a similar manner as discussed above with respect to first non-conductive layer 310 as shown in FIG. 3D . First temporary layer 322 has a surface 323 facing away from wafer 300. First temporary layer 322 can be a photoresist material, an insulating material, a dielectric material, or some other non-conductive material.

[0085] Multiple first openings 324 are formed in a first temporary layer 322. Each opening in the first temporary layer 322 is aligned with a corresponding opening in one of the first openings 318 in the second non-conductive layer 312. The first openings 324 may be formed in a manner similar to the first openings 318 and 320 in the second non-conductive layer 312. Alternatively, the first openings 324 may be formed by drilling, etching, or some other forming technique capable of forming openings in the temporary layer 322. Each opening in the first temporary layer 324 exposes a portion of a third conductive layer 321, which is located within each opening in the first openings 318 in the second non-conductive layer 312. The first openings 324 in the first temporary layer 322 have a substantially annular shape similar to the first openings 318 in the second non-conductive layer 312.

[0086] Multiple second openings 326 are formed in the first temporary layer 322. Each of the second openings 326 in the first temporary layer 322 is aligned with a corresponding opening in one of the second openings 320 in the second non-conductive layer 312. The second openings may be formed in a manner similar to the first openings 318 and 320 in the second non-conductive layer 312. Alternatively, similar to the first opening 324, the second openings 326 may be formed by drilling, etching, or some other forming technique capable of forming openings in the temporary layer 322. Each of the second openings 326 in the first temporary layer 322 exposes a portion of the third conductive layer 321 aligned with each opening in the second opening 320 in the second non-conductive layer 312. The second openings 326 in the first temporary layer 322 have a generally circular shape similar to the second openings 320 in the second non-conductive layer 312.

[0087] like FIG. 3D As shown, after the first temporary layer 322 is formed and patterned to have a first opening 324 and a second opening 326, conductive material is formed in the first opening 324 and the second opening 326 in the first temporary layer 322, as... FIG. 3E As shown, a first conductive structure 328 is formed in the first opening 324, and a second conductive structure 330 is formed in the second opening 326. The first conductive structure 328 corresponds to the first conductive structure 114 in the die 100, and the second conductive structure 330 corresponds to the second conductive structure 116 in the die 100.

[0088] The conductive material forming the first and second conductive structures 328, 330 can be formed through an electroplating technique. In this electroplating technique, the third conductive layer 321 is a seed layer to which the conductive material is attracted, and the first temporary layer 322 is a photoresist layer. In this electroplating technique, the first temporary layer 322 having the openings 324, 326 is used as a guide to position the conductive material on the third conductive layer 321 to form the first and second conductive structures 328, 330. When the electroplating technique is utilized, the wafer 300 having the first temporary layer 322 with the openings 324, 326 is placed in a liquid solution that includes the conductive material. An electrical current is passed through the liquid solution, causing the conductive material to be attracted to the third conductive layer 321. The conductive material then accumulates in the openings 324, 326 and on the third conductive layer 321, which results in the formation of the conductive structures 328, 330.

[0089] After the conductive structures 328, 330 are formed as shown in FIG. 3E , a solder material is formed in the openings 324, 326 and on the conductive structures 328, 330 to form first and second solder features 332, 334 as shown in FIG. 3F . The solder material is deposited into the openings 324, 326. The first solder features 332 each have a surface 333 within one of the first openings 324 and below the surface 323 of the first temporary layer 322 based on the orientation shown in FIG. 3F . The second solder features 334 each have a surface 335 within one of the second openings 326 and below the surface 323 of the first temporary layer 322 based on the orientation shown in FIG. 3F . The solder material can be deposited utilizing an injection technique, such as an injection molding solder (IMS) technique.

[0090] The amount of solder placed in the first openings 324 can be different than the amount of solder placed in the second openings 326. The amount or volume of solder in the first openings relative to the second openings can be selected based on a consideration of the soldering adhesion between the solder and the first and second conductive structures 328, 330 and the dimensions (e.g., height, base, width, length, etc.) of the first and second conductive structures 328, 330 and other factors. This selection of the volume of solder placed on the first conductive structures 328 relative to the volume of solder placed on the second conductive structures 330 allows for the first and second solder features 114, 116 in FIG. 1A to have points furthest from the substrate 102 of the die 100 along the line 121 that are coplanar with each other as will be discussed in detail with respect to FIG. 3H .

[0091] In some embodiments, the solder material can be formed by overfilling the openings 324, 326 such that excess solder material is located on the surface 323 of the first temporary layer 322. The excess solder material on the surface 323 is then removed with a squeegee or some other mechanism that removes excess solder. If this overfill technique is used to form the solder features 332, 334, the surfaces 333, 335 of the solder features 332, 334 are coplanar or flush with the surface 323 of the first temporary layer 322.

[0092] After the solder material is formed in the openings 324, 326 and on the conductive structures 328, 330, the solder material is allowed to solidify. Each of the first solder features 332 has a substantially annular shape of the first openings 318. Each of the second solder features 334 has a substantially circular shape that is the same as the second openings 320. In other words, the second solder features 334 have a substantially cylindrical shape.

[0093] After the first solder features 332 and the second solder features 334 are solidified and hardened as shown in FIG. 3F , the first temporary layer 322 is removed and the third conductive layer 321 is patterned as shown in FIG. 3G . The first temporary layer 322 can be removed and the third conductive layer 321 can be patterned at the same time using the same technique. For example, the first temporary layer 322 and the third conductive layer 321 can be removed using chemical etching, a water jet removal technique, a drilling technique, or some other removal technique or combination of removal techniques. Alternatively, the first temporary layer 322 can be removed first by one of the techniques listed above, and then after the first temporary layer 322 has been removed, the third conductive layer 321 can be patterned using one of the techniques listed above.

[0094] After the solder features 332, 334 are formed, the first temporary layer 322 is removed and the third conductive layer 321 is patterned as shown in FIG. 3G , the solder features 332, 334 are reflowed to form a plurality of annular solder features 336 and a plurality of solder balls 338 as shown in FIG. 3I . Each of the plurality of annular solder features 336 is located on one of the first conductive structures 328, and each of the plurality of solder balls 338 is located on one of the second conductive structures 330. The annular solder features 336 correspond to the first solder features 118 of the die 100, and the solder balls 338 correspond to the second solder features 120 of the die 100 as shown in FIG. 1AThe solder features 332, 334 can be reflowed in a reflow oven at a peak temperature between 245°C and 265°C. This reflow process rounds the solder features 332, 334 so that they have a semi-spherical shape in cross-section, as shown in FIG. 3G

[0095] After the ring-shaped solder features 336 and solder balls 338 are formed by the reflow process shown, FIG. 3H FIGS. 3A-3H The wafer 300 and the various components formed on the wafer 300 shown are singulated by a singulation tool 340 into individual dies 100, as shown in FIG. 1A

[0096] FIGS. 4A-4B Some steps in an alternative method of manufacturing the die 100 shown are illustrated. For simplicity and brevity, only the differences between this alternative manufacturing method and the manufacturing method in FIG. 1A FIGS. 4A-4B FIGS. 3A-3I

[0097] This alternative manufacturing method is the same as the manufacturing method in FIGS. 3A-3I except that in this alternative method of manufacturing the die 100, the conductive structures 328, 330 are not formed simultaneously in the same step as in FIG. 3E Instead, as shown in FIGS. 3D-3F a plurality of first conductive structures 342 and first solder features 344 are formed in a similar manner as the second conductive structures 330; and after these first conductive structures 342 and first solder features 344 are formed, a second temporary layer 346 is formed on the third conductive layer 321 and is patterned with substantially ring-shaped openings 348. This second temporary layer 346 is formed and patterned with the openings 348 in a similar manner as the first temporary layer 322, as discussed above in the method shown in FIGS. 3A-3I The second temporary layer 346 can be a photoresist material, an insulating material, a dielectric material, or some other non-conductive material. The second temporary layer 346 covers a surface 350 of the first solder features 344 on the first conductive structures 342. The openings 348 expose the third conductive layer 321, and then an electroplating process is completed to form second conductive structures 352 in the same manner as the electroplating step discussed with respect to FIG. 3E After the second conductive structures 352 are formed, in a similar manner as the first conductive structures 328 and first solder features 332 discussed above with respect to FIGS. 3D-3F a plurality of second solder features 354 are formed in the openings 348 and on the second conductive structures 352.

[0098] FIGS. 5A-5B Some steps in an alternative method of manufacturing the die 100 are illustrated.​​​​​​FIG. 5A The solder material 354, 356 is formed on the conductive structures 358, 360 by overfilling the openings in the temporary layer 362 such that excess solder material is on a surface 364 of the temporary layer 362. The excess solder material on the surface 364 is then removed with a squeegee or some other mechanism to remove the excess solder from the surface 364. When this overfill technique is used to form the solder features 354, 356, the surface 366 of the solder feature 354, the surface 368 of the solder feature 358 are coplanar or flush with the surface 364 of the temporary layer 362, as shown. FIG. 5A FIG. 5B The result after the temporary layer 362 is removed is shown. The temporary layer 362 can be removed with a chemical etch, a water jet removal technique, a drilling technique, or some other removal technique or combination of removal techniques. The temporary layer 362 can be a photoresist material, an insulating material, a dielectric material, or some other non-conductive material. Otherwise, this alternative method of fabricating the die 100 is similar to the method of fabricating the die 100 discussed with respect to FIGS. 3A-3I

[0099] Generally, the conventional method of forming an alternative conventional semiconductor die having a conventional first conductive structure that is larger than a conventional second conductive structure is more expensive than the method of forming the die 100 disclosed in FIGS. 3A-3I In the conventional method, the conventional first conductive structure and the conventional first solder feature coupled to the first conductive structure are formed with a first conventional photoresist layer that is patterned with openings to form the conventional first conductive structure and the conventional first solder feature. After the conventional first conductive structure and the conventional first solder feature are formed, the first conventional photoresist layer is removed and a second conventional photoresist layer is formed with openings and covers the conventional first conductive structure and the conventional first solder feature. The conventional second conductive structure and the conventional second solder feature are then formed with the openings in the second conventional photoresist layer.

[0100] However, unlike the conventional method of forming an alternative conventional semiconductor die having conductive structures of different sizes, the openings 324, 326 in the first temporary layer 322 are formed simultaneously, which is more efficient than the conventional method of forming the alternative conventional semiconductor die. FIGS. 3A-3I ​​The method of forming the die 100 in FIG. 1 forms the first and second conductive structures 328, 330. Then, after the conductive structures 328, 330 are formed, the first and second solder components 332, 334 are simultaneously formed on the conductive structures 328, 330. By simultaneously forming the first and second conductive structures 328, 330 and simultaneously forming the first and second solder components 332, 334, the number of steps to form the die 100 is significantly reduced when compared to the method of forming an alternative conventional semiconductor die, and the cost to form the die 100 is lower than the cost to form the alternative conventional semiconductor die.

[0101] Unlike the conventional method of forming an alternative conventional semiconductor die, because the portion of the first temporary layer 322 is on the first portion 314 of the second non-conductive layer 312, less conductive material is used to form the first conductive structure 328 relative to the formation of a conventional first conductive structure. Thus, this generally reduces the cost to manufacture the die 100 relative to the alternative conventional semiconductor die.

[0102] However, like the conventional method of forming an alternative conventional semiconductor die with different sized conductive structures, the techniques of forming the first and second conductive structures 328, 330 and the first and second solder components 332, 334 are relatively similar to each other, thereby allowing machines used to form the alternative conventional semiconductor die to be easily reconfigured or reprogrammed to form the die 100 in FIG. 1. FIG. 1A

[0103] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. The terms used in the following claims should not be construed to limit the claims present application to the particular embodiments disclosed in the specification and claims. The scope of the claims should be construed in accordance with the entire specification, including the claims, presented herein. Accordingly, the claims are not limited to the embodiments described herein, but rather the full scope of the claims is to be afforded the broadest interpretation under the law.​

Claims

1. A device comprising: a substrate having a first surface; a ring-shaped conductive structure on the substrate, the ring-shaped conductive structure extending outward from the substrate, the ring-shaped conductive structure comprising: a second surface facing away from the substrate; an opening extending toward the substrate; an inner sidewall surrounding the opening; an outer sidewall surrounding the opening, the inner sidewall, and the second surface; and a first diameter, the first diameter being an outer diameter; and a column-shaped conductive structure on the substrate, the column-shaped conductive structure extending outward from the substrate, the column-shaped conductive structure being spaced apart from the ring-shaped conductive structure, and the column-shaped conductive structure comprising a second diameter, the second diameter being less than the first diameter; wherein a first soldering component is on the ring-shaped conductive structure, a second soldering component is on the column-shaped conductive structure, the first soldering component and the second soldering component each have a point that is furthest from the substrate, and the points and a mounting plane parallel to the substrate are substantially coplanar.

2. The device of claim 1, wherein the second surface of the ring-shaped conductive structure extends between the inner sidewall and the outer sidewall, and separates the inner sidewall and the outer sidewall.

3. The device of claim 1, wherein the first soldering component is a ring-shaped soldering component on the second surface of the ring-shaped conductive structure.

4. The device of claim 1, wherein the column-shaped conductive structure comprises: a third surface facing away from the substrate; and an outer sidewall surrounding the third surface.

5. The device of claim 4, wherein: the ring-shaped conductive structure has a first dimension extending between the first surface and the second surface; and the column-shaped conductive structure has a second dimension extending between the first surface and the third surface, the second dimension being substantially equal to the first dimension.

6. The device of claim 4, wherein the substrate further comprises: a first contact pad on the first surface of the substrate, the first contact pad having a fourth surface, the fourth surface having a first area, the first contact pad being coupled to the ring-shaped conductive structure; and a second contact pad on the first surface of the substrate, the second contact pad having a fifth surface, the fifth surface having a second area, the second contact pad being coupled to the column-shaped conductive structure.

7. The device of claim 1, wherein the opening exposes a non-conductive layer on the first surface of the substrate.

8. The device of claim 1, wherein the opening exposes a contact pad of the substrate.

9. A device comprising: a die comprising: a substrate having a first surface; a ring-shaped first conductive structure on the first surface, the first conductive structure extending away from the first surface and comprising: a second surface spaced apart from the first surface by a first dimension extending between the first surface and the second surface; an opening in the first conductive structure; a first wall surrounding the opening; and a first diameter, the first diameter being an outer diameter; and a second conductive structure on the first surface, the second conductive structure extending away from the first surface and comprising: a third surface spaced apart from the first surface by a second dimension extending between the first surface and the third surface; and a second diameter, the second diameter being less than the first diameter. a second electrically conductive structure that is cylindrical on the first surface, the second electrically conductive structure extending away from the first surface and including: a third surface spaced apart from the first surface by a second dimension extending between the first surface and the third surface, the second dimension substantially equal to the first dimension; and a second diameter that is less than the first diameter; wherein a first solder component is on the second surface of the first electrically conductive structure, a second solder component is on the third surface of the second electrically conductive structure, the first solder component and the second solder component each have a point that is furthest from the substrate, and the points and a mounting plane parallel to the substrate are substantially coplanar.

10. The device of claim 9, wherein the second surface is substantially annular.

11. The device of claim 9, wherein the third surface is substantially circular.

12. The device of claim 9, wherein: the first solder component includes: a first point that is furthest from the second surface; and a third dimension that extends from the second surface to the first point; the second solder component includes: a second point that is furthest from the third surface; and a fourth dimension that extends from the third surface to the second point, the fourth dimension substantially equal to the third dimension.

13. The device of claim 12, further comprising: an electrical component including: a first contact having a fourth surface, the fourth surface having a first area, the first contact coupled to the first solder component; and a second contact having a fifth surface, the fifth surface having a second area, the second contact coupled to the second solder component, the second area less than the first area.

14. The device of claim 9, wherein the die further includes: a first contact pad on the first surface of the substrate, the first contact pad having a fourth surface, the fourth surface having a first area, the first contact pad coupled to the first electrically conductive structure; and a second contact pad on the first surface of the substrate, the second contact pad having a fifth surface, the fifth surface having a second area, the second contact pad coupled to the second electrically conductive structure, the second area less than the first area.

15. A method comprising: forming an annular electrically conductive structure having a first diameter on a first contact pad of a substrate, the first diameter being an outer diameter, by: forming a first electrically conductive material on the first contact pad, the first electrically conductive material including an outer wall and an inner wall surrounding an opening; forming a cylindrical electrically conductive structure having a second diameter on a second contact pad of the substrate, the second diameter less than the first diameter, by: forming a second electrically conductive material on the second contact pad; forming a first solder material on the annular electrically conductive structure, the first solder material being annular; and forming a second solder material on the cylindrical electrically conductive structure, the second solder material being substantially hemispherical; ​ wherein the first solder material and the second solder material each have a point that is furthest from the substrate, and the point and a mounting plane parallel to the substrate are substantially coplanar.

16. The method of claim 15, wherein forming the ring-shaped conductive structure on the first contact pad of the substrate further comprises: forming a photoresist material having a first opening, the first opening exposing a conductive layer, the conductive layer coupled to the first contact pad of the substrate; and forming the first conductive material, the first conductive material partially filling the first opening.

17. The method of claim 16, wherein forming the first solder material on the annular conductive structure further comprises: forming the first solder material on the first conductive material in the first opening.

18. The method of claim 15, further comprising: coupling the first solder material to a contact of an electrical component; and forming a molding compound on the substrate and the electrical component, the molding compound surrounding the substrate.

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