Layout pattern for magnetoresistive random access memory

Abstract

A layout pattern of a magnetoresistive random access memory is disclosed. The layout pattern includes first and second diffusion regions extending along a first direction on a substrate, a first contact plug extending along a second direction from the first diffusion region to the second diffusion region on the substrate, first and second gate patterns extending along the second direction on one side of the first contact plug, and third and fourth gate patterns extending along the second direction on the other side of the first contact plug.

Description

TECHNICAL FIELD

[0001] The present application relates to a layout pattern of a magnetoresistive random access memory. BACKGROUND

[0002] It is known that the magnetoresistance (MR) effect is an effect in which the resistance of a material changes with an applied magnetic field. The physical quantity is defined as the difference in resistance with and without a magnetic field divided by the original resistance, which represents the rate of change in resistance. At present, the magnetoresistance effect has been successfully applied in the production of hard disks, and has important commercial application value. In addition, using the characteristic that the giant magnetoresistance material has different resistance values in different magnetization states, a magnetic random access memory (MRAM) can also be made, which has the advantage of being able to continue to retain stored data without power.

[0003] The above-mentioned magnetoresistance effect is also applied in the field of magnetic field sensors, for example, an electronic compass component for mobile phones equipped with a global positioning system (GPS) to provide the user with information about the direction of movement. At present, there are various magnetic field sensing technologies on the market, such as anisotropic magnetoresistance (AMR) sensing elements, giant magnetoresistance (GMR) sensing elements, magnetic tunneling junction (MTJ) sensing elements, etc. However, the disadvantages of the above-mentioned prior art usually include: occupying a large chip area, expensive manufacturing process, high power consumption, insufficient sensitivity, and being easily affected by temperature changes, etc., and it is necessary to further improve. SUMMARY

[0004] An embodiment of the present application discloses a layout pattern of a magnetoresistive random access memory, which mainly comprises a first diffusion region and a second diffusion region extending along a first direction on a substrate, a first contact plug extending from the first diffusion region to the second diffusion region along a second direction on the substrate, a first gate pattern and a second gate pattern extending along the second direction on one side of the first contact plug, and a third gate pattern and a fourth gate pattern extending along the second direction on the other side of the first contact plug. BRIEF DESCRIPTION OF DRAWINGS

[0005] Fig. 1 A layout diagram of an MRAM element of an embodiment of the present application;

[0006] Fig. 2 A layout diagram of an MRAM element of an embodiment of the present application;

[0007] Fig. 3 Layout of an MRAM element according to an embodiment of the present application.

[0008] Main element symbol explanation

[0009] 12: substrate

[0010] 14: diffusion region

[0011] 16: diffusion region

[0012] 18: diffusion region

[0013] 20: diffusion region

[0014] 22: gate pattern

[0015] 24: gate pattern

[0016] 26: gate pattern

[0017] 28: gate pattern

[0018] 30: shallow trench isolation

[0019] 32: source region

[0020] 34: source region

[0021] 36: source region

[0022] 38: source region

[0023] 42: drain region

[0024] 44: drain region

[0025] 46: drain region

[0026] 48: drain region

[0027] 52: source region

[0028] 54: source region

[0029] 56: source region

[0030] 58: source region

[0031] 62: drain region

[0032] 64: drain region

[0033] 66: drain region

[0034] 68: drain region

[0035] 72: source region

[0036] 74: source region

[0037] 76: source region

[0038] 78: source region

[0039] 82: contact plug

[0040] 84: contact plug

[0041] 86: contact plug

[0042] 92: contact plug

[0043] 94: contact plug

[0044] 96: contact plug

[0045] 98: contact plug

[0046] 102: metal pattern

[0047] 104: metal pattern

[0048] 106: metal pattern DETAILED DESCRIPTION

[0049] Certain terms are used throughout the description and claims which have particular meanings that, unless otherwise expressly provided, are taken in their broadest sense and are not to be interpreted under the doctrine of equivalents. In the description and claims, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Also, the term "comprising" is used in the description and claims to mean "including but not limited to". Furthermore, the term "or" is used in the description and claims in the inclusive sense, i.e., the term "or" is the logical disjunction meaning any one of the terms or combinations of terms. The term "connected" or "coupled" as used in the description and claims includes any connection or coupling, either direct or indirect, between any two elements.

[0050] Reference will now be made to the drawings, wherein Figs. 1-2 , Figs. 1-2 is a schematic diagram of a physical layout of an MRAM element according to an embodiment of the present application. As shown in Fig. 1 , the MRAM element according to the present application is primarily provided with a substrate 12 composed of a semiconductor material selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc.

[0051] The plurality of diffusion regions, such as diffusion regions 14, 16, 18, 20, are formed on the substrate 12 along a first direction, such as the X direction, the plurality of gate patterns, such as gate patterns 22, 24, 26, 28, are formed on the substrate 12 and the gate patterns 22, 24, 26, 28 along a second direction, such as the Y direction, source regions 32, 34, 36, 38, 52, 54, 56, 58, 72, 74, 76, 78 and drain regions 42, 44, 46, 48, 62, 64, 66, 68 are formed on the diffusion regions 14, 16, 18, 20 on both sides of the gate patterns 22, 24, 26, 28, respectively, and a plurality of contact plugs 82, 84, 86, 92, 94, 96, 98 are formed on both sides of the gate patterns 22, 24, 26, 28 and extend from one diffusion region 14, 18 to another diffusion region 16, 20 or are formed directly on the source regions 32, 34, 36, 38, 52, 54, 56, 58, 72, 74, 76, 78 and the drain regions 42, 44, 46, 48, 62, 64, 66, 68. A shallow trench isolation (STI) 30 formed of silicon oxide is formed on the substrate 12 around the diffusion regions 14, 16, 18, 20.

[0052] In the present embodiment, the diffusion regions 14, 16, 18, 20 can include N-type or P-type dopants, the gate patterns 22, 24, 26, 28 can include gate structures or gate patterns formed of polysilicon material or metal, the source regions and the drain regions can include N-type or P-type dopants according to the type of transistors, and the contact plugs 82, 84, 86, 92, 94, 96, 98 can be formed according to a single damascene or a dual damascene manufacturing process, wherein the contact plugs 82, 84, 86, 92, 94, 96, 98 can further include a barrier layer and / or a metal layer, wherein the barrier layer can be selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride, and tungsten nitride, and the metal layer can be selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum, and copper, but is not limited thereto.

[0053] In detail, the source regions and the drain regions include source region 32 disposed on diffusion region 14 to the left of gate pattern 22, source region 34 disposed on diffusion region 16 to the left of gate pattern 22, source region 36 disposed on diffusion region 18 to the left of gate pattern 22, source region 38 disposed on diffusion region 20 to the left of gate pattern 22, drain region 42 disposed on diffusion region 14 between gate patterns 22 and 24, drain region 44 disposed on diffusion region 16 between gate patterns 22 and 24, drain region 46 disposed on diffusion region 18 between gate patterns 22 and 24, drain region 48 disposed on diffusion region 20 between gate patterns 22 and 24, source region 52 disposed on diffusion region 14 between gate patterns 24 and 26, source region 54 disposed on diffusion region 16 between gate patterns 24 and 26, source region 56 disposed on diffusion region 18 between gate patterns 24 and 26, source region 58 disposed on diffusion region 20 between gate patterns 24 and 26, drain region 62 disposed on diffusion region 14 between gate patterns 26 and 28, drain region 64 disposed on diffusion region 16 between gate patterns 26 and 28, drain region 66 disposed on diffusion region 18 between gate patterns 26 and 28, drain region 68 disposed on diffusion region 20 between gate patterns 26 and 28, source region 72 disposed on diffusion region 14 to the right of gate pattern 28, source region 74 disposed on diffusion region 16 to the right of gate pattern 28, source region 76 disposed on diffusion region 18 to the right of gate pattern 28, and source region 78 disposed on diffusion region 20 to the right of gate pattern 28.

[0054] The contact plugs include contact plugs 82, 84, 86 extending from diffusion region 14 through shallow trench isolation 30 to diffusion region 16 along the second direction (e.g., the Y direction), contact plugs 92, 94, 96 extending from diffusion region 18 through shallow trench isolation 30 to diffusion region 20, and contact plugs 98 disposed on each of drain regions 42, 44, 46, 48, 62, 64, 66, 68, wherein contact plugs 82, 84, 86 are connected from the bottom side of diffusion region 14 to the top side of diffusion region 16 without extending beyond the top side of diffusion region 14 and the bottom side of diffusion region 16, and similarly, contact plugs 92, 94, 96 are connected from the bottom side of diffusion region 18 to the top side of diffusion region 20 without extending beyond the top side of diffusion region 18 and the bottom side of diffusion region 20. In this embodiment, contact plugs 82, 84, 86 that cross diffusion regions 14, 16 and contact plugs 92, 94, 96 that cross diffusion regions 18, 20 each include a rectangular shape as viewed from the top, and each of contact plugs 98 disposed on drain regions 42, 44, 46, 48, 62, 64, 66, 68 includes a square shape.

[0055] As shown in FIG. 1, the semiconductor device 10 includes a substrate 12, a gate pattern 22, a gate pattern 24, a gate pattern 26, a gate pattern 28, a shallow trench isolation 30, a diffusion region 14, a diffusion region 16, a diffusion region 18, a diffusion region 20, a source region 32, a source region 34, a source region 36, a source region 38, a drain region 42, a drain region 44, a drain region 46, a drain region 48, a source region 52, a source region 54, a source region 56, a source region 58, a drain region 62, a drain region 64, a drain region 66, a drain region 68, a source region 72, a source region 74, a source region 76, a source region 78, a contact plug 82, a contact plug 84, a contact plug 86, a contact plug 92, a contact plug 94, a contact plug 96, and a contact plug 98. Fig. 2As shown, the MRAM element further comprises a plurality of first layer metal patterns (Ml) disposed on the substrate 12 and overlapping the gate patterns 22, 24, 26, 28 and the contact plugs 82, 84, 86, 92, 94, 96. The first layer metal patterns comprise a metal pattern 102 extending along a first direction, such as the X direction, between the diffusion regions 14, 16 and overlapping and connecting the underlying contact plugs 82, 84, 86 and the source regions 32, 34, 52, 54, 72, 74. A metal pattern 104 also extends along the X direction between the diffusion regions 18, 20 and overlapping and connecting the underlying contact plugs 92, 94, 96 and the source regions 36, 38, 56, 58, 76, 78. A metal pattern 106 overlaps and connects the underlying contact plugs 98 and the drain regions 42, 44, 46, 48, 62, 64, 66, 68.

[0056] From a top view perspective, the metal patterns 102, 104 of the first layer metal patterns preferably appear as rectangles, such as rectangles, extending along the Y direction and overlapping the contact plugs 82, 84, 86, 92, 94, 96 and connecting the source regions 32, 34, 36, 38, 52, 54, 56, 58, 72, 74, 76, 78. The metal pattern 106 comprises a square overlapping and connecting the underlying drain regions 42, 44, 46, 48, 62, 64, 66, 68. It is noted that the metal patterns 102, 104 of the first layer metal patterns are also connected to a source line (SL) and transmit signals through the source line SL.

[0057] The MRAM element further comprises a plurality of first layer contact hole patterns (Vl) disposed on the first layer metal patterns Ml and a plurality of second layer metal patterns (M2) disposed on the substrate 12 and overlapping the first layer metal patterns and the first layer contact hole patterns. The MRAM element further comprises a plurality of magnetic tunnel junctions (MTJ) disposed on the second layer metal patterns and connected to the underlying second layer metal patterns and the underlying drain regions. Since the MTJs are disposed on the second layer metal patterns, the MTJs can be considered as third layer metal patterns (M3). For simplicity, the first layer contact hole patterns, the second layer metal patterns and the MTJs on the substrate 12 are not shown in the figures.

[0058] In the present embodiment, each MTJ preferably comprises, from bottom to top, a bottom electrode, a pinned layer, a barrier layer, a free layer, and a top electrode disposed on the second metal pattern. In the present embodiment, the bottom electrode and the top electrode preferably comprise a conductive material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al). The pinned layer can comprise a ferromagnetic material such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), cobalt (Co), etc. In addition, the pinned layer can also be composed of an antiferromagnetic (AFM) material such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), nickel oxide (NiO), etc. to fix or limit the direction of the magnetic moment of the adjacent layer. The barrier layer can be composed of an insulating material comprising an oxide such as aluminum oxide (AlO x ) or magnesium oxide (MgO), but is not limited thereto. The free layer can be composed of a ferromagnetic material such as iron, cobalt, nickel, or an alloy thereof such as cobalt-iron-boron (CoFeB), but is not limited thereto. Among them, the magnetization direction of the free layer will be "free" to change under the influence of an external magnetic field.

[0059] Please continue to refer to Fig. 3 , Fig. 3 Another embodiment of the present application is disclosed. As shown in Fig. 3 , the present application can reduce the area of the storage cell region of the entire MRAM element, including reducing the diffusion region and / or the metal pattern such as the first metal pattern Ml. Overall, compared to the metal pattern 106 of the square shape of the overlapping drain region 42, 44, 46, 48, 62, 64, 66, 68 in the foregoing embodiment, the present application can slightly adjust the size of each metal pattern 106 to be approximately rectangular in the top view and the left and right sides of each metal pattern 106 are preferably more overlapping than the gate pattern 22, 24, 26, 28 in the foregoing embodiment.

[0060] In summary, compared to the layout pattern of the prior art MRAM element in which the first layer metal pattern M1 spans and covers most of the diffusion regions including the source region and the drain region, the present application provides a larger process window for the subsequent first layer metal pattern M1 by the contact plugs 82, 84, 86 simultaneously spanning the source regions 32, 34, 52, 54, 72, 74 on the diffusion regions 14, 16 and / or the contact plugs 92, 94, 96 simultaneously spanning the source regions 36, 38, 56, 58, 76, 78 on the diffusion regions 18, 20, so that the first layer metal pattern does not need to occupy an excessively large area to affect the operation of the element.

[0061] The above description is only the preferred embodiment of the present application, and any equivalent changes and modifications made according to the claims of the present application should be within the scope of the present application.

Claims

1. A layout pattern of a magnetoresistive random access memory, characterized by, Comprising: a first diffusion region and a second diffusion region, extending along a first direction on a substrate; a first contact plug, extending from the first diffusion region to the second diffusion region on the substrate along a second direction perpendicular to the first direction; a first gate pattern and a second gate pattern, extending along the second direction on one side of the first contact plug; a third gate pattern and a fourth gate pattern, extending along the second direction on another side of the first contact plug; a second contact plug, disposed only on the first diffusion region and between the first gate pattern and the second gate pattern, wherein the first contact plug comprises an oblong according to a top view angle and the second contact plug comprises a square according to the top view angle; and a first metal pattern, extending along the first direction between the first diffusion region and the second diffusion region.

2. The layout pattern of a magnetoresistive random access memory as claimed in claim 1, further comprising: a first drain region disposed on the first diffusion region between the first gate pattern and the second gate pattern; a first source region disposed on the first diffusion region between the second gate pattern and the third gate pattern; a second drain region disposed on the second diffusion region between the first gate pattern and the second gate pattern; and a second source region disposed on the second diffusion region between the second gate pattern and the third gate pattern.

3. The layout pattern of a magnetoresistive random access memory as claimed in claim 2, wherein the first contact plug is disposed on the first source region and the second source region.

4. The layout pattern of a magnetoresistive random access memory as claimed in claim 2, further comprising: the second contact plug disposed on the first drain region; and a third contact plug disposed on the second drain region.

5. The layout pattern of a magnetoresistive random access memory as claimed in claim 4, further comprising: a first metal pattern extending along the first direction between the first diffusion region and the second diffusion region; a second metal pattern overlapping the second contact plug; and a third metal pattern overlapping the third contact plug.

6. The layout pattern of a magnetoresistive random access memory as claimed in claim 5, wherein the first metal pattern overlaps the first gate pattern, the second gate pattern, the third gate pattern, the fourth gate pattern, and the first contact plug.

7. The layout pattern of a magnetoresistive random access memory as claimed in claim 5, wherein the first metal pattern comprises an oblong according to a top view angle.

8. The layout pattern of a magnetoresistive random access memory as claimed in claim 5, wherein the second metal pattern comprises a square according to a top view angle.

9. The layout pattern of a magnetoresistive random access memory as claimed in claim 5, wherein the second metal pattern comprises an oblong according to a top view angle. ​ ​

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