adjusting the DFT coefficients to compensate for frequency offset during the sounding sequence used for fractional time determination

Abstract

The receiver includes a first discrete Fourier transform (DFT) block that performs a first single tone DFT on the positive tones associated with the probe sequence. A second DFT block performs a second single tone DFT on the negative tones associated with the probe sequence. A DFT coefficient generation block generates first DFT coefficients based on the nominal frequency of the positive tones and an estimated frequency offset between the transmitter frequency and the receiver frequency. The DFT coefficient generation block generates second DFT coefficients based on the nominal frequency of the negative tones and the estimated frequency offset. Multipliers in the DFT blocks multiply the I and Q values of the probe sequence with the coefficients. Accumulators in the DFT modules accumulate the multiplier outputs. An arctangent function receives the average accumulated values from the first and second DFT blocks and provides first and second phase values used to calculate the fractional timing.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to communication systems, and more specifically to radio frequency (RF) apparatuses and related methods for distance measurement between wireless nodes. BACKGROUND

[0002] Distances between wireless nodes can be determined using packet switching in a short-range radio frequency communication system (e.g., conforming to Bluetooth™, Bluetooth™ Low Energy (BLE), Zigbee™, or other network protocol standards) using phase measurements or time-based distance measurements. Accurate distance measurements are very useful in short-range wireless technologies, can be used to improve positioning capabilities of devices, enhance security, and otherwise provide more diverse short-range wireless Internet of Things (IoT) applications. Local oscillators used in the wireless nodes are independent of each other, and distance measurements are affected by frequency offsets of the oscillators in the wireless nodes. Accordingly, improved techniques for distance measurement that take into account frequency offsets are desirable. SUMMARY

[0003] Accordingly, in one embodiment, a receiver includes a first discrete Fourier transform (DFT) block. The first DFT block includes a first complex multiplier coupled to receive an imaginary part of a received signal, a real part of the received signal, and a first complex DFT coefficient. A first accumulator is coupled to a real part output of the first complex multiplier and provides a first accumulated real part value. A second accumulator receives an imaginary part output of the first complex multiplier and provides a first accumulated imaginary part value. A DFT coefficient generation function generates the first complex DFT coefficient based in part on one or more estimated frequency offsets between a transmitter frequency and a receiver frequency, and provides the first DFT coefficient to the first complex multiplier.

[0004] In an embodiment, an arctangent function receives an average of the first accumulated real part values and an average of the first accumulated imaginary part values and provides a first phase value.

[0005] In an embodiment, a second DFT block includes a second complex multiplier coupled to receive an imaginary part of a received signal, a real part of the received signal, and a second complex DFT coefficient. A third accumulator is coupled to a real part output of the second complex multiplier and provides a second accumulated real part value. A fourth accumulator receives an imaginary part output of the second complex multiplier and provides a second accumulated imaginary part value. A DFT coefficient generation function generates the second complex DFT coefficient based in part on the one or more estimated frequency offsets. An arctangent function receives an average of the second accumulated real part values and an average of the second accumulated imaginary part values and provides a second phase value.

[0006] In another embodiment, a method for determining fractional timing includes receiving, at a receiving device, a probe sequence of alternating ones and zeros from a transmitting device. First coefficients used by first complex multipliers of a first discrete Fourier transform (DFT) block are based in part on a frequency offset estimate of a frequency offset between a first frequency associated with the transmitting device and a second frequency associated with the receiving device. The DFT block provides a first DFT output. Second coefficients used by second complex multipliers of a second DFT block are based in part on the frequency offset estimate. The second DFT block provides a second DFT output. A first phase based on the first DFT output and a second phase based on the second DFT output are determined. The phases are used to determine fractional timing.

[0007] In another embodiment, a receiver includes a first discrete Fourier transform (DFT) block that performs a first single-tone DFT on positive tones associated with a probe sequence. A second DFT block performs a second single-tone DFT on negative tones associated with the probe sequence. DFT coefficient generation circuitry generates first DFT coefficients based on a nominal frequency of the positive tones and one or more frequency offset estimates between a transmitter frequency and a receiver frequency, and provides the first DFT coefficients to the first DFT block. The DFT coefficient generation circuitry also generates second DFT coefficients based on a nominal frequency of the negative tones and the frequency offset estimates, and provides the second DFT coefficients to the second DFT block. BRIEF DESCRIPTION OF DRAWINGS

[0008] The present application can be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.

[0009] Figure 1 A wireless communication system is shown that includes a first communication device that is communicatively coupled with a second communication device, the first communication device having a transmitter and a receiver, the second communication device having a transmitter and a receiver.

[0010] Figure 2 A form of distance measurement known as round trip time (RTT) that involves exchanging packets between two communication devices is shown.

[0011] Figure 3 A time error that can be determined and corrected using fractional timing is shown.

[0012] Figure 4 A probe sequence of alternating ones and zeros that is being provided to a receiver is shown that produces tone outputs that are used to determine fractional timing.

[0013] Figure 5 A receiver in accordance with an embodiment is shown.

[0014] Figure 6Additional details of embodiments of a discrete Fourier transform (DFT) block are shown.

[0015] Figure 7 A timing diagram related to transmission of a probe sequence is shown.

[0016] Figure 8 A flowchart of operations of an embodiment that compensates for frequency offset during a probe sequence by adjusting a local oscillator or digital mixer based on an estimated frequency error is shown.

[0017] Figure 9 An embodiment that compensates for frequency offset between a transmitting and receiving device during a fractional timing measurement by adjusting DFT coefficients based on an estimated frequency offset is shown.

[0018] Figure 10 Additional details related to a DFT block are shown.

[0019] Figure 11 A flowchart of operations in a receiver that compensates for frequency offset during a fractional measurement made during a probe sequence by adjusting DFT coefficients based on an estimated frequency offset is shown.

[0020] The use of the same reference numbers in different drawings indicates similar or identical items. DETAILED DESCRIPTION

[0021] REFERENCE Figure 1 An embodiment of a wireless communication system 100 includes a communication device 102 (including a transmitter 104 and a receiver 106) and a communication device 112 (including a transmitter 114 and a receiver 116). A distance D separates the communication device 102 from the communication device 112. Although the communication device 102 and the communication device 112 are shown as each including only one antenna, in other embodiments, the communication device 102 and the communication device 112 each include multiple antennas. In an embodiment, the wireless communication system 100 conforms to a BLE communication protocol designed for low-power and low-latency applications. However, in other embodiments, the wireless communication system 100 conforms to other communication protocols (e.g., classic Bluetooth, Zigbee, or other short-range radio frequency protocol standards). Local oscillators 105 and 115 provide signals used in the transceiver functions of the communication device 102 and the communication device 112, respectively. Data processing circuits 107 and 138 are coupled to memories 103 and 136, respectively. The operation of the data processing circuits will be described further herein. Note that the transmitter and receiver in each communication device share the data processing circuit.

[0022] Figure 2 A form of distance measurement known as round trip time (RTT) is shown, which involves an initiator device 202 (e.g.,Figure 1 The communication device 102 in FIG. 1 and the reflector device 212 (eg, Figure 1 Packets are exchanged between initiator 202 and reactant 212 (reactant device 112 in the example). There is a time offset Δ seconds between initiator 202 and reactant 212. At initiator time t1, reactant time is t1 + Δ. At time t1, the initiator sends a packet (symbol s1) to the reactant. Symbol s1 arrives at the reactant at reactant time t2 + Δ. The time it takes for the initiator device 202 to travel to the reactant device 212 is called the time of flight (ToF). Forward ToF 214 = t2 + Δ – t1. At time t3 + Δ, reactant 212 sends symbol s2 to initiator 202, which receives s2 at time t4. Reverse ToF = t4 – (t3 + Δ). Round-trip ToF = (t2 - t1) + (t4 - t3). For round-trip time calculation, the clock offset Δ cancels each other out. By exchanging symbols or packets that include the local times of sending and receiving the symbol or packet, a rough round-trip time can be determined. The one-way flight time and distance can be determined by dividing the round-trip time by 2. Figure 1 The distance D shown is determined by (one-way ToF) × c, where c is the speed of light.

[0023] In the embodiment, the target resolution of the distance measurement is 0.5 m. That is, the goal is to determine the distance to within 0.5 m. Since radio waves travel at the speed of light c (3x10 8 m / s) propagation, this means the ToF target resolution is (0.5m / c), or 1.6ns. The resolution depends on the sampling frequency, and even at a high sampling frequency, the difference between the active edge of the sampling clock and the start of the incoming symbol will produce further error in the round-trip measurement. Figure 3 The error is shown in FIG. 3 . The initiator device 302 sends a symbol s1 to the reacter 312. The symbol s1 arrives at the reacter 312 after a time period which is a ToF. The fractional time T of the reacter FRAC_R Reflects the difference from the start of the incoming symbol (s1) at the reacting side at 314 to the local sampling instant 315 of the reacting side device 312. The fractional component T of the initiator FRAC_I Indicates the difference between the start of reception of the incoming symbol (s2) at 317 in the initiator and the local sampling instant 319 of the initiator device 302. The coarse time is combined with the fractional time to determine the total ToF and make the distance measurement more precise. Specifically:

[0024]

[0025] Note that the fractional time is added to the difference in coarse time.

[0026] One method of performing fractional RTT measurements is to use a probe sequence. Figure 4 A probe sequence of alternating 1s and Os being provided to the transmitter 404 is shown, as well as the power spectrum of the TX signal after frequency shift keying (FSK) modulation. This results in tone output including tones at fc-fo and fc+fo. When BLE is run at 1 Mbps, the tones fc+fo and fc-fo are at +500 kHz and -500 kHz, respectively, at baseband in the receiver 416. The frequency fo is half the symbol rate due to the periodicity of the symbol rate alternating between 1 and 0. When BLE is run at 2 Mbps, the tones at baseband in the receiver are ±1 MHz. By measuring the phase difference of the two tones at the receiver, a fractional RTT time can be obtained, and thus an improved RTT resolution.

[0027] Figure 5 A block diagram of an embodiment of a receiver 500 included in the wireless communication device 112 or the wireless communication device 102 that uses the two tones fc+fo and fc-fo from a probe sequence to provide fractional timing measurements is shown. The receiver improves fractional timing measurements by accounting for the frequency offset between the transmitter and the receiver. An antenna 501 provides an RF signal to a passive network (PN) 503, which provides impedance matching, filtering, and electrostatic discharge protection. A low noise amplifier (LNA) 505 amplifies the signal from the passive network 503 without substantially degrading the signal-to-noise ratio and provides the amplified RF signal to a mixer 507. The mixer 507 performs frequency conversion or shifting of the RF signal using a local oscillator (LO) signal provided by a frequency synthesizer block 509. In an embodiment, the frequency synthesizer uses a fractional-N phase-locked loop (PLL) for implementation. In one mode of operation, the receiver 500 is configured as a low intermediate frequency (LIF receiver) and converts the RF signal to a low intermediate frequency (e.g., 100 to 200 kHz) to avoid DC offset and 1 / f noise problems of ZIF receivers.

[0028] The mixer 507 provides the converted output signal as a set of two signals (one in-phase (I) signal and one quadrature (Q) signal) to a programmable gain amplifier (PGA) 508. The I and Q signals are analog time-domain signals. In at least one embodiment of the receiver 500, an analog amplifier 508 and filter (not shown separately) provide amplified and filtered versions of the I and Q signals to an analog-to-digital converter (ADC) 510, which converts these versions of the I and Q signals to digital I and Q signals. An exemplary embodiment of the ADC 510 uses various signal conversion techniques (e.g., delta-sigma (or sigma-delta) analog-to-digital conversion). In an embodiment, the ADC block 510 also includes a decimator. The ADC 510 provides the digital I and Q signals to a digital filter 511, which provides digital filtering of the digital I and Q signals and provides the filtered I and Q signals to a digital mixer 515. The digital mixer 515 converts the IF signals to baseband and provides the baseband signals to a filter 517. In an embodiment, the filter 517 includes a decimator, channel filter, and sample rate converter, not shown separately. The filter 517 provides the filtered baseband signals to a demodulator 518. The demodulator 518 performs demodulation on the digital I and Q signals to retrieve or extract information (e.g., a data signal modulated by, for example, a transmitter (not shown) and provided as an RF signal to the antenna 501). The demodulator 518 provides the demodulated data to a data processing circuit 519, which corresponds to the data processing circuits 107 and 138 in Figure 1 In an embodiment, the data processing circuit 519 performs various functions (e.g., logical, arithmetic, etc.). For example, the data processing circuit 519 uses the demodulated data in a program, routine, or algorithm (whether in software, firmware, hardware, or a combination thereof) to perform desired control or data processing tasks. In an embodiment, the data processing circuit includes a processor (e.g., a microcontroller) and software and / or firmware that performs the required functions. Note that the functions described thus far in the path between the antenna 501 and the data processing circuit 519 are well known in the art. Figure 5

[0029] Figure 5 ​Embodiments of the receiver shown in the middle also include circuitry that provides more accurate RTT measurements. In embodiments, the goal of the RTT measurement method is to achieve 0.5m resolution, which requires measuring the round trip time with an uncertainty of 1.6ns. One way to achieve this resolution is to use a coarse RTT measurement and then use an optional fine RTT measurement. The optional fine RTT measurement performs a single bin DFT at the positive frequency, a single bin DFT at the negative frequency, and compares the phases of the two DFT calculations to make a fractional time measurement. Thus, the probe sequence (101010...) can be used to provide a fractional time estimate that is combined with the coarse RTT measurement to obtain a more accurate RTT measurement.

[0030] The fractional time measurement performs a single bin DFT, where one DFT is centered at a +500kHz tone and another DFT is centered at a -500kHz tone (or centered at ±1MHz tones) that are embedded in the probe sequence. As described further herein, the fractional time measurement determines the phase difference between the two tones and uses the phase difference to determine the fractional timing. The use of the fractional time measurement improves the resolution of the RTT, thus making the distance measurement more accurate.

[0031] The frequency offset represents the difference in frequency between the clock signal used in the transmitting device and the clock signal used in the receiving device. The clock signal can be based on a local oscillator or other clock generation logic used in the respective device. While the fractional time measurement improves the accuracy, the frequency offset between the transmitter and receiver during the probe sequence can cause an error in the fractional RTT measurement based on the + / - 500KHz tones or ±1MHz tones. If the frequency offset is close to 15KHz, the error can be very large. Even if the frequency offset is small, simulations have shown that the RTT error doubles (delay from 3ns to 6ns per measurement) when the frequency offset is 5kHz. Thus, embodiments herein compensate for the frequency offset to provide a more accurate fractional timing value for the RTT measurement.

[0032] Still referring to Figure 5 The digital filter 517 after the digital mixer 515 provides complex discrete Fourier transform (DFT) blocks 531 and 533. The DFT block 531 performs a single bin DFT at +500kHz, while the DFT block 533 performs a single bin DFT centered at -500kHz to obtain complex numbers. The complex number signal information from each of the two DFT blocks is provided to an arctangent function 535. The arctangent function 535 determines the phase based on the complex numbers provided for the positive tone and the negative tone. The fractional timing calculation block then uses these phases to provide a fractional timing value that can be combined with the coarse RTT measurement. The +500KHz and -500KHz tones that result from transmitting the 101010 probe sequence follow the phase and time relationship shown below:

[0033]

[0034]

[0035] Thus,

[0036] (or for 2MHz BLE, )

[0037] A DFT is performed on the filter output to obtain signal information at the two tones. Figure 6 Additional details of an embodiment of the DFT block 531 are shown. The digital filter 517 provides a memory 601 that provides the I and Q values to the DFT block 531 in sequence through an input scaling block 603. A multiplexer circuit 602 allows the memory 601 to be bypassed, sending the output of the digital filter 517 directly to the DFT input scaling block 603. The DFT block 533 is identical and also receives scaled I and Q values from the memory 601 through an input scaling block 603. The DFT input scaling block 603 scales the input I, Q signals to avoid saturation of large signals and to reduce quantization effects for small signals. A complex multiplier 613 receives a rotation factor WN(n) 604 and provides a complex multiplication result to accumulators 605 and 607, one for the real part and the other for the imaginary part of the DFT. The two complex numbers WN(n) provided to the multiplier provide the real and imaginary parts of WN(n). The DFT block 533 receives WN(n) values corresponding to other frequencies of interest (e.g., -500 kHz or -1 MHz). In embodiments, the DFT blocks 531 and 533 are each formed from dedicated DFT circuitry. In other embodiments, a programmed processor logic can be used to perform some or all of the multiplication and addition, or any suitable combination of programmed processor logic and dedicated logic can be used.

[0038] The rotation factor is based in part on the center frequency of the bin (e.g., 500 kHz), the oversampling rate (OSR), and the length of the probe sequence. The oversampling rate (OSR) refers to the ratio of the sampling rate of the system to the symbol rate of the PHY. For example, the OSR can be 4 to 7 or some other appropriate number depending on the frequency of the signal being sampled and the frequency of the sampling clock. In an embodiment, the DFT block 533 accumulates values from 64 symbols (M = 64) of the probe sequence for the signal tone DFT computation, and the total samples N = OSR*M. For BLE 1 MHz, the ±500 kHz tone is at DFT bin k = M / 2. For BLE 2M, the ±1000 kHz tone is also at DFT bin k = M / 2. The rotation factor provided to the complex multiplier corresponds to the +500 kHz tone for one DFT and the -500 kHz tone for the other DFT. For the +500 kHz tone:

[0039] where fs is the sampling frequency.

[0040] For the -500 kHz tone:

[0041]

[0042] In an embodiment, the rotation factor is computed in the data processing circuit 519 (see Figure 5 ), another processing unit, or pre-computed and stored in non-volatile memory (NVM) for use by the complex multiplier. Accumulators 605 and 607 of the real and imaginary parts of the multiplication result accumulate the results for the samples of the 64 symbols from the probe sequence. Average blocks 609 and 611 average the accumulated values and provide their average values to the DFT output scaling block 615. The DFT output scaling block 615 scales the accumulator output to maximize the resolution of small signals and avoid saturation of large signals that exceed the bit width of downstream circuitry. The DFT output scaling block 615 provides its output to the arctangent function 535. The arctangent function 535 produces phase values (φ and ) based on the accumulated real and imaginary parts of the DFT output. As described above, the fractional timing computation block 537 computes the fractional timing t frac from the difference of the two phases. In an embodiment, this computation is implemented in software or firmware running on the data processing circuit 519 or another processor in the receiver.

[0043] Thus, the two tones discovered at baseband can be used to determine fractional timing. However, the frequency offset between the initiator and the responder causes inaccuracies in the fractional timing estimate. Embodiments described herein compensate for the frequency offset during the probe sequence, so the fractional timing estimate is more accurate. Embodiments utilize a frequency offset estimate and adjust the digital mixer 515 or mixer 507 based on the estimated timing offset to increase the accuracy of the fractional timing estimate.

[0044] Figure 7 A timing diagram is shown that illustrates transmission of a probe sequence from an initiator (transmitting device) to a responder (receiving device), and vice versa. The transmission includes a preamble 701, a 32-bit synchronization word 703 (e.g., a PN sequence pn[31:0]), and a 96-bit probe sequence 705. In an embodiment, the preamble is an 8-bit sequence of alternating 1s and Os. The PN sequence is a 32-bit pseudo-noise sequence, also known as a pseudo-random binary sequence (PRBS), that is known to both the initiator and the responder. In an embodiment, the end of the synchronization word marks the beginning of the probe sequence. Figure 5 The receiver 500 in the responder 500 detects reception of the PN sequence (or other synchronization word), e.g., using a demodulator 518 (or other circuitry), and asserts a frame detect signal at 707 that indicates detection of the reception of the PN sequence, which also marks the beginning of the probe sequence. A frequency offset estimator 521 produces a frequency offset estimate based on the preamble, the PN sequence, or both.

[0045] Referring back to Figure 5 , a coordinate rotation digital computer (CORDIC) 520 receives the I and Q values from the filter 517. Generally, the CORDIC implements known techniques to perform calculations that include trigonometric functions and complex multiplications without using multipliers. The operations used by the CORDIC are addition, subtraction, shifting, and table lookup operations. In other embodiments, a digital signal processor executing firmware is used. In at least one embodiment, the CORDIC 520 receives filtered versions of I and Q from the digital filter 517 and converts the digital I and Q signals from Cartesian representation to polar representation by performing an arctangent operation. The polar representation includes a phase and an amplitude. The phase is provided to a frequency offset estimator (FOE) 521 that provides an estimate of the frequency offset between a clock signal associated with the initiator (e.g., a local oscillator) and a clock signal associated with the responder (e.g., a local oscillator).

[0046] In at least one embodiment, the frequency offset estimator (FOE) 521 receives the phase value from the CORDIC 520 and provides a frequency offset estimate to a frequency offset correction circuit 522. The frequency offset estimator 521 produces the frequency offset estimate f EST (i.e., ). For example, the frequency offset estimator 521 distinguishes the phase output of the CORDIC by computing the discrete-time phase difference value (e.g., f X ). The frequency offset estimator 521 subtracts from the incoming discrete-time phase difference value a value corresponding to an expected phase difference value pre-determined and stored in memory, accumulates the error, and divides by a predetermined number of symbols (e.g., N symbols, 8 < N < 32) to form an estimate of the frequency error. The expected phase difference value is based on the expected frequency of the transmitted signal. For example, in BLE, the expected frequency is based on the specified frequency deviation f DEV (e.g., ±250 kHz) of the physical layer, which determines the frequency of the transmitted signal.

[0047] For example, for frequency shift keying, when transmitting a “1”, the transmitter transmits a radio frequency tone at f RF +f DEV , and when transmitting a “0”, the transmitter transmits a tone at f RF -f DEV . In an exemplary embodiment that uses the eight symbols of the preamble to estimate the frequency error, expected values x1, x2, x3, -x1, -x2, -x3 corresponding to the expected instantaneous frequency deviation (i.e., phase difference over a symbol) are stored in memory. The values of x1, x2, and x3 vary with the system BT parameters (e.g., bandwidth x bit time = 0.5), which determines the impact of transmitter pulse shaping and receiver filtering bandwidth. In at least one embodiment, the impact of filtering in the receiver and transmitter pulse shaping from a bit can impact subsequent bits, which is known as inter-symbol interference (ISI). If consecutive symbols contain a relatively long “1”, then a full frequency deviation (e.g., x1) is expected. If consecutive symbols alternate between “1” and “0”, then the expected frequency deviation is less than the full frequency deviation (e.g., ±x3) due to the impact of filtering. Each expected value corresponds to a different three-bit data pattern (i.e., b n , b n-1 , and b n-2 ). Exemplary values of x1, x2, and x3 correspond to expected deviations f DEV of 250 kHz, 173 kHz, and 92 kHz, respectively, after receiver filtering. The expected deviation will vary depending on the filtering characteristics implemented in the receiver. If consecutive symbols contain a relatively long “1”, then a full frequency deviation (e.g., 250 kHz) is expected, and assuming an exemplary transmitter has a 50 kHz offset, then the frequency of the transmitted signal is f RF +f DEV + 50 kHz. Thus, the frequency offset estimator 521 will compute the average frequency offset value as follows:

[0048]

[0049] For a 32-bit PN sequence, the sum of the actual (f X ) and expected (f expected ) values will of course be different.

[0050] The frequency offset estimator 521 provides a frequency offset estimate to a frequency offset correction circuit 522. A gain circuit 523 in the frequency offset correction circuit 522 receives the frequency offset estimate. The gain circuit 523 scales the frequency offset estimate according to an AFC gain value 524 and provides the scaled value to a shifter circuit 525. The AFC gain scales the frequency estimate to the resolution used by the digital mixer. The shifter circuit scales the scaled version of the frequency offset estimate according to a high or low gear setting. In the case of the high gear setting, the scaled frequency offset is provided without any adjustment to an accumulator 527. In the case of the low gear setting, a digital shift of, for example, 8 bits (equivalent to dividing by 256) is used to reduce the scaled frequency offset from the gain circuit 523. Other shift values (more than two gears) can of course be used as needed by a particular implementation. The embodiment combines the AFC gain function with a gear shift. The AGC gain is typically used to scale the gain while the gear shift is used to select how much of the frequency estimate should be used for frequency offset compensation. The output of the shifter circuit 525 is provided to the accumulator 527 which stores the accumulated value in a register 529 and periodically provides the accumulated scaled value as a frequency offset correction signal 541 to a de-multiplexer circuit 543. In an embodiment, the gear shift can be bypassed by scaling (or not scaling) the high and low gears the same. The de-multiplexer circuit 543 provides the frequency offset correction signal 541 to either a sum circuit 545 or a sum circuit 547 which act as adjustment circuits to adjust the frequency used by the mixer 507 provided by either the digital mixer 515 or the frequency synthesizer 509. The sum circuit 545 adds the nominal digital mixer frequency (digmixfreq) 546 to the frequency offset correction signal and provides the adjusted frequency to the digital mixer 515 for use in converting the intermediate frequency signal to baseband. Alternatively, the de-multiplexer circuit 543 provides the frequency offset correction signal to the sum circuit 547 which combines the frequency offset correction signal with a reference frequency control signal 549 and provides the combined control signal to control the frequency synthesizer 509, for example, through a delta-sigma modulator used to control the feedback divider of a fractional-N PLL implementation local oscillator function. The adjusted frequency of the LO signal provided by the frequency synthesizer block 509 is provided as the LO signal used by the mixer 507 to convert the RF signal to an intermediate frequency signal. Note that in at least one embodiment, both mixers are adjusted based on the frequency offset correction signal.

[0051] Referring againFigure 7 and Figure 5Once the frame detect signal is asserted at 707, the frame detect signal is delayed for a predetermined amount of time until 709 to allow for AFC setup. In an embodiment, the delay is 8 symbol periods. The frequency offset estimator 521 estimates the frequency error based on the received preamble and sync word (or just the sync word). A high speed mode setting will be applied to produce a first frequency offset correction at 711 to adjust the mixer 507 or 515 at the beginning of the probe sequence to compensate for the frequency offset. The AFC high speed mode adjustment attempts to fully correct the frequency offset. The high speed mode setting corrects the frequency offset faster but can cause transients in the signal. Once the delayed frame detect is asserted at 709, the multiplexer 551 selects the low speed mode control signal to provide the frequency offset estimate divided by the frequency to the accumulator 527, which in turn provides the frequency offset correction signal at 715, 717, and 719 to continue the frequency adjustment during the probe sequence. The frequency adjustments at 711, 715, 717, and 719 are maintained until the next frequency adjustment occurs. There is one output for the accumulator 527 for each input to the frequency offset correction circuit 522. The goal is to reference the frequency estimate back to the digmixfreq 546. Assume the current frequency offset correction 541 is at -10 kHz and the transmitter is shifting, and the new frequency offset estimate is +20 kHz. The new frequency offset estimate is based on the adjusted digmixfreq 548 (the digmixfreq 546 adjusted by the frequency offset correction 541), so +20 kHz is relative to the adjusted digmixfreq 548, which means the adjusted digmixfreq 548 should be increased by +20 kHz. Thus, the accumulator 527 adds the -10 kHz offset correction in register 529 to the new +20 kHz offset estimate to cause the next frequency offset correction 541 to increase the baseline digmixfreq 546 by +10 kHz to increase the adjusted digmixfreq 548 by 20 kHz. If the transmitter frequency remains the same after the -10 kHz correction instead of increasing, then the new frequency offset estimate will be 0 (assuming perfect correction). After the frame detect delay assertion, the gear setting is switched from high speed to low speed, and the receiver 500 continues to gradually perform the frequency correction during the probe sequence. This improves the probe sequence measurement performance when there is a frequency offset. The lower gear setting gradually corrects the offset and limits the disturbance to the I and Q signals. The frequency adjustment operates to center the tones around DC in the baseband, so the DFT performed at ±500 kHz provides as accurate data as possible for the phase compensation. For example, if the frequency offset without offset compensation causes the tones to be at +490 kHz and -510 kHz, the frequency adjustment centers the tones that are, for example, 1000 kHz apart around DC (0 Hz) to provide higher DFT accuracy, since the DFT is configured for the nominal values of the positive and negative tones.Note that due to normal limitations of circuitry and its operation, centering the tone around DC can not be perfect, so some error can remain even after compensation.

[0052] Figure 8 A flowchart showing the operation of an embodiment that compensates for frequency offset during a probe sequence by adjusting a local oscillator or digital mixer based on an estimated frequency error. The flow shows the operation of control logic and other circuitry in the receiver 500. The control logic can be implemented as digital logic, as firmware as part of a programmed microcontroller, or as any suitable combination of digital, programmable logic, firmware, and / or higher level software. At 802, in response to the frame detect signal being low, the frequency adjustment is set to high speed. At 804, the receiving device receives a first sequence. In embodiments, the sequence includes a preamble and a PN sequence. At 806, the receiver looks for a frame detect indicating that the sync word reception is complete. At 808, a frequency offset estimator estimates the frequency offset based on the first sequence of the preamble and / or PN sequence (or a portion thereof). At 810, the receiver begins receiving a probe sequence formed of alternating ones and zeros. In embodiments, the probe sequence is 96 symbols in length. At 812, frequency adjustment based on the high speed setting is made at the end of the sync word to compensate and attempt to remove any frequency offset between the transmitting device and the receiving device. At 814, the flow waits for the frame detect delay to be asserted. Once the frame detect delay is asserted, the frequency adjustment is set to low speed at 816. In embodiments, the DFT is delayed until the frame detect delay is asserted. In embodiments, the DFT is performed on 64 bits, which occurs at 820. During the DFT is performed, the frequency offset compensation continues. At 822, if the frequency adjustment is ready, then at 824 the frequency adjustment is applied to the local oscillator provided by the fractional-N PLL or to the digital frequency control signal of the digital mixer. At 826, the control logic checks to see if the DFT computation 820 of the probe sequence is complete. When the probe sequence is complete or the number of bits of the probe sequence (M) required for the DFT has been processed, at 828 the averaged real and imaginary parts from the DFT are provided to an arctangent function after scaling, which determines the phase at 830. At 832, the fractional timing is determined based on the phase difference. Assuming that the fractional timing is determined first in the responder, the responder provides the fractional timing information to the transmitter, so the transmitter can determine the RTT measurement as described above.

[0053] Thus, Figure 5 to Figure 8 The embodiment shown in FIG. 6 describes a method that improves the fractional timing measurement of an RTT measurement by compensating for frequency offset between a transmitting device and a receiving device during a fractional timing measurement of a probe sequence by adjusting a local oscillator or a frequency used by a digital mixer based on an estimated frequency offset.

[0054] Figure 9 An embodiment of another method of compensating for frequency offset between a transmitting device and a receiving device during fractional timing measurements is shown. The receiver 900 includes a signal path from an antenna 501 to a data processing circuit 519, which is connected to Figure 5 The paths shown are identical. However, the frequency of the signal provided by frequency synthesizer block 509 to mixer 507 and the frequency control signal (DIGMIXFREQ) that controls the frequency used by digital mixer 515 are not adjusted based on the frequency offset estimate. Instead, receiver 900 compensates for the estimated frequency offset by adjusting the DFT coefficients used by both DFTs for positive and negative tones (e.g., + / - 500 kHz) based on the frequency offset.

[0055] Still refer to Figure 9 The filtered I and Q digital values ​​from filter 517 are provided to CORDIC 920. Frequency offset estimator (FOE) 921 receives the phase value from CORDIC 920 and generates a frequency offset estimate. The functions of CORDIC 920 and FOE 921 are as described earlier. Figure 5 As described in the description of CORDIC 520 and FOE 521 in

[15] , note that in embodiments, the FOE output is accumulated, scaled, and / or averaged. In embodiments, the DFT calculation utilizes an M = 64-bit probing sequence for the signal tone DFT calculation (M = 64). The total number of samples N = OSR * M. For BLE 1 MHz, the ±500 kHz tones are located at tone number k = M / 2. For BLE 2 MHz, the ±1000 kHz tones are also located at tone number k = M / 2.

[0056] The DFT coefficient calculation block 930 receives the frequency offset estimate and generates DFT coefficients adjusted from the nominal settings of positive and negative frequencies (e.g., + / - 500kHz).

[0057] +500kHz tone by To adjust:

[0058]

[0059] in ,in is estimated from the PN[31:0] sequence, and Δf is the frequency offset estimate.

[0060] For a -500kHz tone:

[0061]

[0062] The DFT coefficient calculation block 930 functionality can be implemented as a programmed microcontroller unit (MCU) or other processor, as dedicated logic, or as any appropriate combination of digital, programmable logic, firmware, and software. Individual logic in the DFT coefficient calculation block 930 can be dedicated to calculating the coefficients for each DFT. While shown with rotation factors for tones at + / - 500 kHz, the rotation factors are set according to the detected tones. Thus, for example, for 2 MHz BLE, the nominal tones to detect are at + / - 1 MHz.

[0063] The DFT calculation block 930 provides the adjusted rotation factors WN(n) to complex DFT blocks 931 and 933. The adjustment of the rotation factors ensures that the DFT bins are centered at the appropriate frequencies given the estimated frequency offset. For example, if the frequency offset causes tones at +490 kHz and -510 kHz, the DFT coefficients are adjusted so that the bins of the single tone DFT blocks 931 and 933 are centered at +490 kHz and -510 kHz, respectively. The arctangent function block 935 receives the output of the DFT blocks and provides the phase used by the fractional timing calculation block 937 to calculate the fractional timing as described previously.

[0064] Figure 10 Additional details of an embodiment of the DFT block 931 (or 933) are shown. Since these blocks are identical except that they receive different rotation factors, only one block is shown. The digital filter 517 provides a memory 1001 that provides the I and Q values to the DFT block 931 (and DFT block 933) in turn through an input scaling block 1003. A multiplexer circuit 1002 allows the memory 1001 to be bypassed, sending the output of the digital filter 517 directly to the DFT input scaling block 1003. The DFT input scaling block 1003 scales the incoming I, Q signals to avoid saturation of large signals and to reduce quantization effects for small signals. A complex multiplier 903 receives the adjusted complex rotation factor WN(n) 1006 from the memory 1001 as well as the I(n) and Q(n) values for the 64 symbols of the probe sequence and provides a complex multiplication result that is accumulated in two accumulators 1005 and 1007, one for the real part of the DFT and the other for the imaginary part. Average blocks 1009 and 1011 average the accumulated values and provide their average to a DFT output scaling block 1015. The DFT output scaling block 1015 scales the accumulator output to maximize resolution for small signals and to avoid saturation of large signals beyond the bit width of downstream circuitry. The DFT 931 (and 933) provide their results to the arctangent function 935, which then produces a phase value for the adjusted frequency based on the real and imaginary parts of the accumulated DFT values and Fractional timing Based on the difference in the two phases: where the adjusted phase represents a phase calculated using the adjusted rotation factor. While a nominal ±500 kHz tone has been described for a 1 MHz BLE embodiment, the tone depends on the frequency used in a particular embodiment.

[0065] Thus, the two tones at baseband during the probe sequence can be used to determine fractional timing based on the phases of the two tones. Compensation for the frequency offset between the transmitter and receiver yields a more accurate fractional timing result. Figure 11A flowchart illustrates the operations in a receiver for compensating for the frequency offset estimated during a 1, 0, 1, 0, ... sounding sequence. This flowchart illustrates the operation of control logic and other circuitry. The control logic can be implemented as digital logic, as firmware as part of a programmed microcontroller, or as any suitable combination of digital logic, programmable logic, firmware, or software. At 1102, a receiving device receives a first sequence. In an embodiment, the sequence includes a preamble and a PN sequence. At 1104, a frequency offset estimator estimates the frequency offset based on at least the PN[31:0] sequence. At 1106, the MCU or other logic adjusts the rotation factors of the two-tone DFTs based on the estimated error offset. For example, the DFTs can be adjusted based on the frequency offset estimates to process tones at +490 kHz and -510 kHz, rather than the nominal ±500 kHz. At 1108, the receiver receives a sounding sequence consisting of alternating 1s and 0s. In an embodiment, the sounding sequence is 96 symbols long, but this length is exemplary, and other sounding sequence lengths may be used in different embodiments. The number of bits in the sounding sequence used for the DFT (e.g., 64 or 96 bits) may also vary between embodiments. The DFT logic performs single-tone DFTs at the adjusted positive and negative frequencies, which are adjusted based on the frequency offset estimate, and an accumulator accumulates the complex results from the multiplier. At 1112, the control logic checks whether the DFT has completed the required number of sounding sequence samples. If not, it checks at 1114 whether a new frequency offset estimate is available. Frequency offset estimates are available periodically during the sounding sequence. If no new frequency offset estimate is available, the process returns to receiving the sounding sequence at 1108 and performing the DFT at 1110. If a new frequency offset estimate is available, the process returns to 1106 to adjust the rotation factors of both DFTs to more accurately compensate for the current frequency offset estimate. In such embodiments, frequency offset estimation continues during the sounding sequence, resulting in a change in Δf in φ(n) during the sounding sequence. In at least one embodiment where the frequency offset continues during the sounding sequence and Δf changes during the sounding sequence, the frequency offset estimate is scaled, for example using high / low gear as described above, to adjust Δf. In another embodiment, frequency adjustment is performed based on at least a portion of the first sequence (e.g., the sync word) to eliminate any frequency offset between the transmitting and receiving devices, and no additional frequency offset determination is performed during the sounding sequence. In such an embodiment, the frequency offset estimation does not continue during the sounding sequence, resulting in Δf in φ(n) being fixed during the sounding sequence based on one or more frequency offset estimates (made based on the first sequence). In either case, a DFT is performed on the positive and negative frequency tones until the sounding sequence is complete or the number of samples in the sounding sequence required for the DFT has been processed.Once the DFT is completed, the averaged (and scaled) real and imaginary parts from the DFT are provided to an arctangent function, which computes the phase in 1116. In 1120, the fractional time is computed based on the provided phase difference. Assuming the fractional timing is determined first in the responder, the responder provides the fractional timing information to the transmitter, so the transmitter can determine the RTT measurement as described above.

[0066] Thus, a receiver that compensates for frequency offset between a transmitter and a receiver using an estimated frequency offset during a sounding sequence has been described. The description of the application set forth herein is illustrative, and is not intended to limit the scope of the application as set forth in the following claims. Other variations and modifications can be made based on the description set forth herein, without departing from the scope of the application as set forth in the following claims.

Claims

1. A receiver comprising: a first discrete Fourier transform (DFT) block, the first DFT block comprising: a first complex multiplier coupled to receive an imaginary part of a received signal and a real part of the received signal and to receive a first complex DFT coefficient; and a first accumulator receiving a real part output of the first complex multiplier and providing a first accumulated real part value; a second accumulator receiving an imaginary part output of the first complex multiplier and providing a first accumulated imaginary part value; and a DFT coefficient generation function to generate the first complex DFT coefficient based in part on one or more estimated frequency offsets between a transmitter frequency and a receiver frequency and to provide the first complex DFT coefficient to the first complex multiplier.

2. The receiver of claim 1, further comprising: an arctangent function coupled to receive an average of the first accumulated real part value and an average of the first accumulated imaginary part value and to provide a first phase value.

3. The receiver of claim 2, further comprising: a second DFT block, the second DFT block comprising: a second complex multiplier coupled to receive an imaginary part of a received signal and a real part of the received signal and to receive a second complex DFT coefficient; and a third accumulator receiving a real part output of the second complex multiplier and providing a second accumulated real part value; a fourth accumulator receiving an imaginary part output of the second complex multiplier and providing a second accumulated imaginary part value, wherein the DFT coefficient generation function is to generate the second complex DFT coefficient based in part on the one or more estimated frequency offsets; and wherein the arctangent function is coupled to receive an average of the second accumulated real part value and an average of the second accumulated imaginary part value and to provide a second phase value.

4. The receiver of any one of claims 1 to 3, wherein, The received signal is a probe sequence generated with an alternating 1 and 0 pattern.

5. The receiver of claim 4, wherein, The estimated frequency offsets are generated at least in part using sequences received prior to the probe sequence.

6. The receiver of claim 3, further comprising: fractional timing logic to determine a fractional timing value based on a difference between the first phase value and the second phase value.

7. The receiver of claim 4, wherein, The first DFT block performs a first single tone DFT on a positive tone associated with the probe sequence and the second DFT block performs a second single tone DFT on a negative tone associated with the probe sequence.

8. The receiver of claim 7, wherein, The positive tone is nominally 500 kHz or 1000 kHz and the negative tone is nominally -500 kHz or -1000 kHz.

9. The receiver of claim 7, wherein, The first DFT coefficient is generated by adjusting a nominal first coefficient of a nominal frequency of the positive tone by Φn, where where Δf is the frequency offset estimate and OSR is the over-sampling rate.

10. The receiver of claim 9, wherein, The second DFT coefficient is generated by adjusting a nominal second coefficient of the nominal frequency of the negative sound by Φn, where .

11. A method for determining fractional timing in a receiver, comprising: receiving, at a receiving device, a probe sequence of alternating 1s and 0s from a transmitting device; generating a first coefficient for use by a first complex multiplier of a first discrete Fourier transform (DFT) block, the first coefficient based in part on a frequency offset estimate of a frequency offset between a first frequency associated with the transmitting device and a second frequency associated with the receiving device; providing a first DFT output from the first DFT block; based in part on the frequency offset estimate, generating a second coefficient for use by a second complex multiplier of a second DFT block; providing a second DFT output from the second DFT block; and and determining a first phase based on the first DFT output and a second phase based on the second DFT output.

12. The method of claim 11, further comprising: accumulating a first real part and a first imaginary part provided by the first complex multiplier to produce an accumulated first real part and an accumulated first imaginary part; and providing an average of the accumulated first real part and an average of the accumulated first imaginary part to an arctangent function for producing the first phase.

13. The method of claim 12, further comprising: accumulating a second real part and a second imaginary part provided by the second complex multiplier to produce an accumulated second real part and an accumulated second imaginary part; and providing an average of the accumulated second real part and an average of the accumulated second imaginary part to the arctangent function for producing the second phase.

14. The method of any of claims 11 to 13, further comprising: determining a fractional timing value based on a difference between the first phase and the second phase.

15. The method of any one of claims 11 to 13, wherein, the first DFT and the second DFT are single tone DFTs.

16. The method of any of claims 11 to 13, further comprising producing the frequency offset estimate based at least in part on a sequence received prior to the sounding sequence.

17. The method of any of claims 11 to 13, further comprising: during the sounding sequence, producing one or more additional frequency offset estimates; based in part on the one or more additional frequency offset estimates, producing additional first coefficients for the first DFT block; and based in part on the one or more additional frequency offset estimates, producing additional second coefficients for the second DFT block.

18. The method of any of claims 11 to 13, wherein the first coefficients are based on a first nominal value of a positive frequency adjusted by the frequency offset estimate; and wherein the second coefficients are based on a second nominal value of a negative frequency adjusted by the frequency offset estimate.

19. A receiver, comprising: a first discrete Fourier transform (DFT) block to perform a first single tone DFT on a positive tone associated with a sounding sequence; a second DFT block to perform a second single tone DFT on a negative tone associated with the sounding sequence; a DFT coefficient generation block to generate first DFT coefficients based on a nominal frequency of the positive tone and one or more frequency offset estimates between a transmitter frequency and a receiver frequency, and provide the first DFT coefficients to the first DFT block, and to generate second DFT coefficients based on a nominal frequency of the negative tone and the one or more frequency offset estimates, and provide the second DFT coefficients to the second DFT block.

20. The receiver of claim 19, the first DFT block comprises, wherein, a first complex multiplier coupled to receive an imaginary part of the sounding sequence and a real part of the sounding sequence and to receive the first DFT coefficients; and a first accumulator to receive real part outputs of the first complex multiplier and to provide a first accumulated real part value; ​ ​ a second accumulator receiving imaginary part outputs of the first complex multiplier and providing a first accumulated imaginary value; and wherein the second DFT block comprises, a second complex multiplier coupled to receive an imaginary part of the sounding sequence and a real part of the sounding sequence and to receive the second DFT coefficient; a third accumulator coupled to real part outputs of the second complex multiplier and providing a second accumulated real value; a fourth accumulator receiving imaginary part outputs of the second complex multiplier and providing a second accumulated imaginary value; an arctangent function coupled to receive an average of the first accumulated real value and an average of the first accumulated imaginary value and an average of the second accumulated real value and an average of the second accumulated imaginary value and to provide a first phase value and a second phase value for fractional timing calculation.

Images