Circuit board and method for manufacturing the same

Abstract

The present invention provides a circuit board and a manufacturing method thereof. After the first circuit layer is completed, the circuit board first arranges a conductive bump on the first circuit layer, covers the first circuit layer with a first dielectric layer but exposes the conductive bump, arranges a second dielectric layer on the first dielectric layer, and has a second dielectric layer opening formed by a photolithography process to expose the conductive bump. Finally, the second circuit layer is completed on the surface of the second dielectric layer and in the second dielectric layer opening. The second circuit layer is electrically connected to the first circuit layer through the conductive bump in the second dielectric layer opening. Since the surface roughness of the second dielectric layer and the second dielectric layer opening is low, it is not easy to form a small gap with the second circuit layer, so the second circuit layer can be closely attached, which is more conducive to improving the bonding force between the fine circuit and the surface of the dielectric layer.

Description

Technical Field

[0001] The present invention relates to a circuit board and a manufacturing method thereof, in particular to a multi-layer circuit board and a layer-adding manufacturing method thereof. Background Art

[0002] See also FIG. 4A to FIG. 4G The existing circuit board circuit layer production method generally includes the following steps: Figure 4A As shown, a first circuit layer 42 is completed on a substrate 41, and a dielectric layer 43 is laminated on the substrate 41 and the first circuit layer 42 to cover the first circuit layer 42; Figure 4B As shown, the dielectric layer 43 is laser drilled to form a blind hole 430 for connecting to the surface of the first circuit layer; Figure 4C As shown, the dielectric layer 43 is subjected to a desmear process to remove the smear remaining after laser drilling; Figure 4D As shown, a conductive material layer 44a is formed in the dielectric layer 43 and the blind hole 430 after the desmear process is completed; Figure 4E As shown, a patterned photoresist layer 45 is disposed on the conductive material layer 44a; Figure 4F As shown, a second circuit layer 44 is formed on the conductive material layer 44a and in the blind hole 430; Figure 4G As shown, the patterned photoresist layer 45 is finally removed, and copper etching is performed to separate the circuits and complete the second circuit layer 44.

[0003] However, if Figure 4B and Figure 4C As shown, some smear will remain in the blind hole 430 after laser drilling. When the smear removal process is used to remove the smear at the bottom of the hole, the surface 431 of the dielectric layer 43 will also be corroded. Therefore, the roughness of the dielectric layer surface 431' after the smear removal process will be too high, and its roughness (Ra) is about 0.2~0.3μm. The multiple dielectric layer surfaces 431' with high roughness make it easy to form a tiny gap between the conductive material layer 44a attached thereto as the seed layer of the second circuit layer 44 and the second circuit layer 44, and there is a risk of further cracks in subsequent processes or use; in addition, when the second circuit layer 44 includes a fine line, that is, a circuit structure with a line pitch or blind hole diameter of less than 10μm, the multiple surfaces with high roughness are not conducive to the formation of fine lines in the second circuit layer 44, resulting in poor reliability of the fine lines and increased signal loss; in addition, as Figure 4C As shown, the desmear will corrode the sidewall of the blind hole 430 , so that the glass fiber 432 of the dielectric layer is exposed from the sidewall of the blind hole 430 , increasing the risk of the conductive anodic filament (CAF) leakage phenomenon and reducing the reliability of the blind hole 430 .

[0004] Furthermore, 5G mobile communication (5th Generation Mobile Communication) is one of the trend technologies that has been booming in recent years, and its characteristics are high-speed, low-latency wireless communication transmission. In order to achieve communication technology that meets 5G specifications, one of the technical focuses that the existing technology must overcome is to achieve high-quality electrical signals with higher frequencies and lower noise influence. However, due to the high roughness of the surface of the dielectric material and the exposure of glass fibers in the blind holes, the circuit quality of the circuit board is unstable, which is prone to noise or signal loss, especially in the thin line part where the risk is higher.

[0005] In summary, the existing method for manufacturing build-up layers of circuit boards must be further improved. Summary of the invention

[0006] In view of the problems that the existing circuit layer manufacturing method makes the roughness on the dielectric layer and in the blind hole too high, resulting in unstable circuit attachment structure and exposure of glass fibers in the dielectric material layer, the present invention provides a circuit board and a manufacturing method thereof, the manufacturing method comprising: providing a substrate; completing a first circuit layer on the substrate; forming a conductive bump on the first circuit layer; arranging a first dielectric layer on the substrate, the first dielectric layer covering the first circuit layer and exposing the conductive bump; arranging a second dielectric layer on the first dielectric layer, the second dielectric layer having a second dielectric layer opening, the second dielectric layer opening being formed by a photolithography process and arranged corresponding to the conductive bump, so that the conductive bump is exposed in the second dielectric layer opening; and completing a second circuit layer on the second dielectric layer and in the second dielectric layer opening, so that the second circuit layer is electrically connected to the conductive bump, and is electrically connected to the first circuit layer through the conductive bump.

[0007] In one embodiment of the present invention, the manufacturing method includes: setting a first photoresist layer on the substrate, the first photoresist layer having a first photoresist layer opening to expose a portion of the first circuit layer; forming the conductive bump in the first photoresist layer opening; and removing the first photoresist layer.

[0008] In one embodiment of the present invention, the manufacturing method includes: disposing a first dielectric layer on the substrate so that the first dielectric layer covers the first circuit layer and the conductive bump; performing a thinning process on the first dielectric layer so that the first dielectric layer exposed the conductive bump.

[0009] In one embodiment of the present invention, the manufacturing method includes: setting a seed layer on the second dielectric layer and in the second dielectric layer opening; setting a second photoresist layer on the seed layer, the second photoresist layer having at least one second photoresist layer opening exposing a portion of the seed layer and the second dielectric layer opening; forming the second circuit layer on the portion of the seed layer in the at least one second photoresist layer opening and in the second dielectric layer opening; removing the second photoresist layer, and etching the second circuit layer and the seed layer to separate the circuits to complete the second circuit layer.

[0010] In one embodiment of the present invention, the manufacturing method includes: disposing a second dielectric layer on the first dielectric layer so that the second dielectric layer covers the first dielectric layer and the conductive bump; performing a photolithography process on the second dielectric layer to form the second dielectric layer opening and a patterned groove.

[0011] In one embodiment of the present invention, the manufacturing method includes: forming the second circuit layer in the second dielectric layer opening and in the patterned groove of the second dielectric layer.

[0012] In one embodiment of the present invention, the circuit board includes a fine circuit arrangement area and a thick circuit arrangement area which do not overlap each other; and the second dielectric layer is arranged in the fine circuit arrangement area.

[0013] In one embodiment of the present invention, the manufacturing method further includes: completing a third circuit layer in the coarse circuit setting area on the first dielectric layer; setting a third dielectric layer on the first dielectric layer, so that the third dielectric layer covers the second dielectric layer and the second circuit layer in the fine circuit setting area, the first dielectric layer and the third circuit layer in the coarse circuit setting area, and completing a fourth circuit layer on the third dielectric layer.

[0014] The present invention also provides a circuit board, comprising a first circuit layer, a conductive bump, a first dielectric layer, a second dielectric layer and a second circuit layer. The conductive bump is arranged on the first circuit layer; the first dielectric layer covers the first circuit layer and exposes the conductive bump; the second dielectric layer is arranged on the first dielectric layer and has a second dielectric layer opening, the second dielectric layer opening is arranged corresponding to the conductive bump, so that the conductive bump is exposed in the second dielectric layer opening; the second circuit layer is arranged on the second dielectric layer and in the second dielectric layer opening to electrically connect the conductive bump, and electrically connect the first circuit layer through the conductive bump.

[0015] In one embodiment of the present invention, the circuit board includes a thin circuit setting area and a thick circuit setting area which do not overlap each other; the second dielectric layer is arranged in the thin circuit setting area. Further, the circuit board also includes a third circuit layer, which is arranged in the thick circuit setting area on the first dielectric layer.

[0016] In one embodiment of the present invention, the circuit board further includes a third dielectric layer and a fourth circuit layer, the third dielectric layer is arranged on the second dielectric layer and the second circuit layer in the fine circuit setting area, on the first dielectric layer and the third circuit layer in the thick circuit setting area, and the fourth circuit layer is arranged on the third dielectric layer.

[0017] In one embodiment of the present invention, the first circuit layer is disposed on a substrate, or the first circuit layer is embedded in the first dielectric layer.

[0018] In one embodiment of the present invention, the second circuit layer is buried in the second dielectric layer.

[0019] The circuit board manufacturing method of the present invention forms a conductive bump on the first circuit layer at the position where the conducting column connecting another circuit layer is to be arranged after completing a first circuit layer on the substrate surface, then arranges the first dielectric layer on the substrate, the first dielectric layer must expose the conductive bump, then arranges a second dielectric layer on the first dielectric layer, the second dielectric layer opening of the second dielectric layer exposes the conductive bump, and finally completes the second circuit layer on the second dielectric layer and in the second dielectric layer opening. The second circuit layer in the second dielectric layer opening is electrically connected to the first circuit layer through the conductive bump exposed at the bottom of the second dielectric layer opening.

[0020] In the circuit board of the present invention, there are two dielectric layers between the first circuit layer and the second circuit layer, and the second circuit layer is formed in the second dielectric layer above and its second dielectric layer opening, and the first circuit layer is electrically connected through the conductive bump in the second dielectric layer opening. Since the second dielectric layer opening is formed by the photolithography process, the inner wall of the second dielectric layer opening and the surface of the second dielectric layer are smoother than the surface of the dielectric material after the desmear process. The roughness (Ra) of the surfaces of the multiple second dielectric layers is about 0.02 to 0.05 μm, which is only one tenth of the surface of the dielectric layer after the desmear process. Therefore, when the conductive material used as the seed layer is set on the second dielectric layer, it can be tightly attached without easily generating tiny gaps; the upper surface of the seed layer is therefore smoother, which is conducive to the attachment of fine circuits to the seed layer.

[0021] Furthermore, as described above, the roughness of the surfaces of the plurality of second dielectric layers in the process of the present invention is only one tenth of that of the surfaces of the dielectric materials that have undergone the desmearing process in the known technology, while avoiding the risk of glass fibers being exposed in the conductive blind holes of the dielectric materials that have undergone the desmearing process, and can effectively improve the quality of the lines set on its surface and in the openings of the second dielectric layer. Therefore, as a circuit board in 5G mobile communications, it can effectively reduce the signal loss of high-frequency signals in the circuits, improve the signal quality, and make the signal quality meet the specifications required for 5G mobile communications. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1A to 1M It is a schematic diagram of a process of the circuit board manufacturing method of the present invention.

[0023] FIG. 2A to FIG. 2D It is a schematic flow chart of a first embodiment of a method for manufacturing a circuit board according to the present invention.

[0024] FIG. 3A to FIG. 3C It is a flow chart of a second embodiment of the circuit board manufacturing method of the present invention.

[0025] FIG. 4A to FIG. 4G The present invention is a flow chart of a method for manufacturing a build-up layer circuit in the prior art. DETAILED DESCRIPTION

[0026] See also Figures 1A to 1M As shown, the present invention provides a circuit board 10 and a manufacturing method thereof, the manufacturing method of the circuit board 10 comprises the following steps: providing a substrate 11; completing a first circuit layer 12 on the substrate 11; forming a conductive bump 13 on the first circuit layer 12; disposing a first dielectric layer 14 on the substrate 11, the first dielectric layer 14 covering the first circuit layer 12 and exposing the conductive bump 13; disposing a second dielectric layer 15 on the first dielectric layer 14, the second dielectric layer 15 having a second dielectric layer opening 151, wherein the second dielectric layer opening 151 is formed by a photolithography process and is arranged corresponding to the conductive bump 13, so that the conductive bump 13 is exposed in the second dielectric layer opening 151; and completing a second circuit layer 16 on the second dielectric layer 15 and in the second dielectric layer opening 151, so that the second circuit layer 16 is connected to the conductive bump 13, and is electrically connected to the first circuit layer 12 through the conductive bump 13.

[0027] The detailed process of the above steps will be further described below.

[0028] like Figure 1A As shown, the first circuit layer 12 is firstly completed on a substrate 11 .

[0029] See also Figures 1B to 1D The step of forming a conductive bump 13 on the first circuit layer 12 includes the following sub-steps: Figure 1B As shown, a first photoresist layer 11a is provided on the substrate 11; Figure 1C As shown, the first photoresist layer 11a is patterned to form a first photoresist layer opening 11b to expose a portion of the first circuit layer 12; Figure 1D As shown, the conductive bump 13 is formed in the first photoresist layer opening 11 b . This step can be completed by electroplating process, and the first photoresist layer 11 a is removed to complete the conductive bump 13 on the first circuit layer 12 .

[0030] See also Figure 1E to Figure 1F As shown, the step of disposing the first dielectric layer 14 on the substrate 11 so that the first dielectric layer 14 covers the first circuit layer 12 and exposes the conductive bump 13 includes the following sub-steps: Figure 1E As shown, a first dielectric layer 14 is disposed on the substrate 11 so that the first dielectric layer 14 covers the first circuit layer 12 and the conductive bump 13; Figure 1F As shown, a thinning process is performed on the first dielectric layer 14 so that the conductive bump 13 is exposed from the thinned first dielectric layer 14 .

[0031] Preferably, the thinning process of the first dielectric layer 14 is, for example, a plasma process using a fluorine-containing gas (CF 4 or SF 4 ), a desmear process, a physical or chemical polishing process, etc.

[0032] See also Figure 1G to Figure 1H As shown, a second dielectric layer 15 is disposed on the first dielectric layer 14, and the second dielectric layer 15 has a second dielectric layer opening 151. The second dielectric layer opening 151 is formed by a photolithography process and corresponds to the conductive bump 13. The step of exposing the conductive bump 13 in the second dielectric layer opening 151 includes the following sub-steps: Figure 1G As shown, a second dielectric layer 15 is disposed on the first dielectric layer 14 so that the second dielectric layer 15 covers the first dielectric layer 14 and the exposed conductive bumps 13; Figure 1H As shown, a photolithography process is performed on the second dielectric layer 15 to form the second dielectric layer opening 151 .

[0033] See also Figures 1I to 1M As shown, the step of completing a second circuit layer 16 on the second dielectric layer 15 and in the second dielectric layer opening 151 so that the second circuit layer 16 is electrically connected to the first circuit layer 12 through the conductive bump 13 includes the following steps: Fig. 1I As shown, a sub-layer 16a is disposed on the second dielectric layer 15 and in the second dielectric layer opening 151; Figure 1J As shown, a second photoresist layer 15a is disposed on the seed layer 16a, and the second photoresist layer 15a has at least one second photoresist layer opening 15b to expose a portion of the seed layer 16a and the second dielectric layer opening 151; Figure 1K As shown, the second circuit layer 16 is formed on the seed layer 16a in the at least one second photoresist layer opening 15b and in the second dielectric layer opening 151. This step can be completed by electroplating or copper deposition processes; Figure 1LAs shown, the second photoresist layer 15 a is removed, and the second circuit layer 16 and the seed layer 16 a are etched to separate circuits, so as to complete the second circuit layer 16 .

[0034] At this point, the circuit board 10 of the present invention has completed the production of the first circuit layer 12 and the second circuit layer 16. From the above process, it can be seen that no matter what process the first dielectric layer 14 is thinned by or what its roughness is, since the second dielectric layer 15 is also covered thereon, and the second dielectric layer opening 151 for conduction is formed in the second dielectric layer 15 by a photolithography process, the seed layer 16a will not be directly disposed on the first dielectric layer 14, but on the second dielectric layer 15 with a lower roughness. It is not easy to form a gap between the seed layer 16a and the second dielectric layer 15 with a lower roughness, and they can be stably combined. Correspondingly, the surface of the seed layer 16a with a lower roughness is also conducive to the adhesion of the second circuit layer 16.

[0035] See also Figure 1L As shown, a circuit board 10 is completed by the manufacturing method of the present invention, and the circuit board 10 includes the first circuit layer 12, the conductive bump 13, the first dielectric layer 14, the second dielectric layer 15 and the second circuit layer 16. The conductive bump 13 is arranged on the first circuit layer 12; the first dielectric layer 14 covers the first circuit layer 12 and exposes the conductive bump 13; the second dielectric layer 15 is arranged on the first dielectric layer 14 and has a second dielectric layer opening 151, and the second dielectric layer opening 151 is arranged corresponding to the conductive bump 13 so that the conductive bump 13 is exposed in the second dielectric layer opening 151; the second circuit layer 16 is arranged on the second dielectric layer 15 and in the second dielectric layer opening 151, and is electrically connected to the first circuit layer 12 through the conductive bump 13.

[0036] The circuit board 10 may include the substrate 11, that is, the first circuit layer 12 after completion is a surface circuit layer disposed on the substrate 11. Figure 1M As shown, in another embodiment, the first circuit layer 12 may also be an embedded circuit layer, that is, after the circuit board 10 completes the circuit and build-up circuit manufacturing, the substrate 11 is further peeled off so that the first circuit layer 12 is directly embedded in the first dielectric layer 14 .

[0037] Preferably, the first dielectric layer 14 is made of a material such as ABF (Ajinomoto Build-up Film) or PP (Prepreg), BCB (Benzocylobuthene), BT (Bismaleimide Triazine), liquid crystal polymer, PI (Poly-imide), acrylic resin, polyurethane resin, epoxy resin, phenolic resin and other organic substances and talcum powder, barium sulfate, silicon dioxide, glass fiber and other inorganic substances and other additives. The second dielectric layer 15 is a photosensitive dielectric layer, and its material is made of a material such as BCB (Benzocylobuthene), BT (Bismaleimide Triazine), liquid crystal polymer, PI (Poly-imide), acrylic resin, polyurethane resin, epoxy resin, polyethylene ether, polytetrafluoroethylene (Poly (phenylene ether)), aromatic nylon (Aramide) and other additives.

[0038] See also FIG. 2A to FIG. 2B As shown, in a first embodiment of the present invention, the surface of the second dielectric layer 15 further has a patterned groove 152, and the step of disposing a second dielectric layer 15 on the first dielectric layer 14 includes the following sub-steps: Figure 2A As shown, the second dielectric layer 15 is disposed on the first dielectric layer 14 so that the second dielectric layer 15 covers the first dielectric layer 14 and the exposed conductive bumps 13; Figure 2B As shown, a photolithography process is performed on the second dielectric layer 15 to form the second dielectric layer opening 151 and the patterned groove 152 .

[0039] Please read further Figure 2C to Figure 2D As shown, in the first embodiment, the step of completing the second circuit layer 16 on the second dielectric layer 15 and in the second dielectric layer opening 151 so that the second circuit layer 16 is electrically connected to the first circuit layer 12 through the conductive bump 13 includes the following steps: forming the second circuit layer 16 in the second dielectric layer opening 151 of the second dielectric layer 15 and in the patterned groove 152. In more detail, as Figure 2C As shown, the second circuit layer 16 is formed on the surface of the second dielectric layer 15, in the second dielectric layer opening 151 and the patterned groove 152. This step can be completed by using a process such as copper deposition; Figure 2D As shown, the surface portion of the second circuit layer 16 is removed to complete the second circuit layer 16 in the second dielectric layer opening 151 and the patterned groove 152. The step of removing the surface portion of the second circuit layer 16 can use any metal thinning process such as grinding and etching to thin the second circuit layer 16.

[0040] In this embodiment, the second circuit layer 16 is an embedded circuit layer. In the photolithography process of the second dielectric layer 15, the second dielectric layer opening 151 and the patterned groove 152 with different depths are formed by different exposure and development, and the pattern of the second circuit layer 16 is completed by configuring the patterned groove 152. Then, the second circuit layer 16 is directly formed in the second dielectric layer opening 151 and the patterned groove 152, so that the second circuit layer 16 embedded in the second dielectric layer 15 is completed.

[0041] See also Figure 3A Figure 3B As shown, in a preferred embodiment of the present invention, the circuit board 10 includes a fine line setting area 10A and a thick line setting area 10B which do not overlap each other; and the second dielectric layer 15 is disposed in the fine line setting area 10A.

[0042] In this embodiment, when the second dielectric layer 15 and the second circuit layer 16 thereon are completed in the fine circuit setting area 10A, the following steps are further included: Figure 3C As shown, a third circuit layer 17 is completed in the coarse circuit setting area 10B on the first dielectric layer 14, and a third dielectric layer 18 is set on the fine circuit setting area 10A and the coarse circuit setting area 10B on the first dielectric layer 14, so that the third dielectric layer 18 covers the second dielectric layer 15 and the second circuit layer 16 in the fine circuit setting area 10A, the first dielectric layer 14 and the third circuit layer 17 in the coarse circuit setting area 10B; and a fourth circuit layer 19 is completed on the third dielectric layer 18.

[0043] In this embodiment, the circuit board 10 includes a thin circuit area 10A and a thick circuit area 10B that do not overlap each other; the second dielectric layer 15 is disposed in the thin circuit area 10A. Further, the circuit board 10 also includes the third circuit layer 17, which is disposed in the thick circuit area 10B on the first dielectric layer 14.

[0044] See also Figure 3C As shown, in this embodiment, the circuit board 10 further includes the third dielectric layer 18 and the fourth circuit layer 19, the third dielectric layer 18 is arranged on the second dielectric layer 15 and the second circuit layer 16 in the fine circuit setting area 10A, and on the first dielectric layer 14 and the third circuit layer 17 in the thick circuit setting area 10B, and the fourth circuit layer 19 is arranged on the third dielectric layer 18.

[0045] In this embodiment, a second dielectric layer 15 is further provided only in the fine line setting area 10A of the circuit board 10 and a second circuit layer 16 of fine lines is provided thereon. The fine lines, for example, refer to line spacing or the aperture of the second dielectric layer opening 151 being less than 10 μm. Further, a third circuit layer 17 can be provided in the coarse line setting area 10B of the first dielectric layer 14, and a third dielectric layer 18 can be provided on the fine line setting area 10A and the coarse line setting area 10B of the entire circuit board 10, and a fourth circuit layer 19 on the third dielectric layer 18. The fourth circuit layer 19 can also be provided in a general circuit layer adding process, which is not described in detail in the present invention. In this way, the third dielectric layer 18 will directly contact and adhere to the first dielectric layer 14 in the coarse line setting area 10B. Since the first dielectric layer 14 has a surface with a higher roughness, there is a better interlayer bonding force between the first dielectric layer 14 and the third dielectric layer 18, making the circuit board 10 more stable as a whole.

[0046] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as above by the embodiments, it is not used to limit the present invention. Any technician familiar with the profession can make some changes or modify the technical contents disclosed above into equivalent embodiments of equivalent changes without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A method for manufacturing a circuit board, characterized in that: include: providing a substrate; completing a first circuit layer on the substrate; forming a conductive bump on the first circuit layer; Disposing a first dielectric layer on the substrate, the first dielectric layer covers the first circuit layer and exposes the conductive bump; A second dielectric layer is disposed on the first dielectric layer, the second dielectric layer having a second dielectric layer opening and a second dielectric layer surface, the second dielectric layer opening is formed by a photolithography process and is disposed corresponding to the conductive bump so that the conductive bump is exposed in the second dielectric layer opening; A second circuit layer is completed on the surface of the second dielectric layer and in the opening of the second dielectric layer, so that the second circuit layer is electrically connected to the conductive bump and is electrically connected to the first circuit layer through the conductive bump; Disposing a sublayer on the surface of the second dielectric layer and in the opening of the second dielectric layer; Disposing a second photoresist layer on the seed layer, wherein the second photoresist layer has at least one second photoresist layer opening to expose a portion of the seed layer and the second dielectric layer opening; forming the second circuit layer in the second photoresist layer opening and the second dielectric layer opening; as well as removing the second photoresist layer, and etching the second circuit layer and the seed layer to separate the circuits, thereby completing the second circuit layer; The surface roughness of the second dielectric layer surface and the second dielectric layer opening is lower than the surface roughness of the first dielectric layer.

2. The method for manufacturing a circuit board according to claim 1, wherein: include: A first photoresist layer is disposed on the substrate, wherein the first photoresist layer has a first photoresist layer opening to expose a portion of the first circuit layer; forming the conductive bump in the first photoresist layer opening; as well as The first photoresist layer is removed.

3. The method for manufacturing a circuit board according to claim 1, wherein: include: Disposing the first dielectric layer on the substrate so that the first dielectric layer covers the first circuit layer and the conductive bump; A thinning process is performed on the first dielectric layer to expose the conductive bump from the first dielectric layer.

4. The method for manufacturing a circuit board according to claim 1, wherein: Also includes: Disposing the second dielectric layer on the first dielectric layer so that the second dielectric layer covers the first dielectric layer and the conductive bump; A photolithography process is performed on the second dielectric layer to form the second dielectric layer opening and a patterned groove.

5. The method for manufacturing a circuit board according to claim 4, characterized in that: include: The second circuit layer is formed in the second dielectric layer opening of the second dielectric layer and in the patterned groove.

6. The method for manufacturing a circuit board according to claim 1, wherein: The circuit board comprises a thin circuit setting area and a thick circuit setting area which do not overlap each other; and the second dielectric layer is arranged in the thin circuit setting area.

7. The method for manufacturing a circuit board according to claim 6, wherein: Further comprising the following steps: completing a third circuit layer in the rough circuit setting area on the first dielectric layer; A third dielectric layer is set in the fine line setting area and the thick line setting area on the first dielectric layer, so that the third dielectric layer covers the second dielectric layer and the second circuit layer in the fine line setting area, the first dielectric layer and the third circuit layer in the thick line setting area, and a fourth circuit layer is completed on the third dielectric layer.

8. A circuit board, characterized in that: Include: a first circuit layer; A conductive bump is disposed on the first circuit layer; a first dielectric layer covering the first circuit layer and exposing the conductive bump; A second dielectric layer, disposed on the first dielectric layer and having a second dielectric layer opening and a second dielectric layer surface, wherein the second dielectric layer opening is disposed corresponding to the conductive bump so that the conductive bump is exposed in the second dielectric layer opening; A sub-layer is separately disposed on the surface of the second dielectric layer and in the opening of the second dielectric layer; A second circuit layer is disposed on the seed layer, and the seed layer in the opening of the second dielectric layer is electrically connected to the conductive bump, and is electrically connected to the first circuit layer through the conductive bump; The surface roughness of the second dielectric layer surface and the second dielectric layer opening is lower than the surface roughness of the first dielectric layer.

9. The circuit board according to claim 8, characterized in that: The circuit board includes a thin circuit arrangement area and a thick circuit arrangement area which do not overlap each other; The second dielectric layer is disposed in the fine line arrangement area; wherein the circuit board further comprises: A third circuit layer is arranged in the rough circuit arrangement area on the first dielectric layer.

10. The circuit board according to claim 9, characterized in that: The board also includes: a third dielectric layer, disposed on the second dielectric layer and the second circuit layer in the fine circuit setting area, and on the first dielectric layer and the third circuit layer in the thick circuit setting area; A fourth circuit layer is disposed on the third dielectric layer.

11. The circuit board according to claim 8, characterized in that: The first circuit layer is arranged on a substrate, or the first circuit layer is buried in the first dielectric layer.

12. The circuit board according to claim 8, characterized in that: The second circuit layer is buried in the second dielectric layer.

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