Fan-out packaging structure and packaging method for embedded sensor or display chip

Abstract

The present invention discloses a fan-out package structure and a packaging method for embedding a sensor or display chip, and relates to the field of semiconductor processing technology. The method comprises the following steps: 1) making a chip-level package; 2) making a fan-out package; 3) adhering and assembling a plurality of chip-level packages to a first glass carrier; 4) processing a second mold resin layer on the outside of each fan-out package, making a plurality of third RDL layers corresponding to each fan-out package on the second mold resin layer, providing a third copper bump at the contact point of the top third RDL layer, and implanting solder balls at the third copper bump to obtain an initial product; and 5) separating the first glass carrier and then cutting the initial product into individual chips. The present invention embeds a plurality of chip-level packages in the mold resin. Because the coplanarity of the plurality of chip-level packages is not changed by subsequent processes, and because multiple chips are encapsulated in the same package, the volume of the system can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor processing technology, and in particular to a fan-out packaging structure embedded with a sensor or display chip and a packaging method thereof. Background Art

[0002] The current packaging method for multi-chip sensors or displays primarily involves encapsulating a single sensor or display chip in a chip-scale package. The chip's top surface is covered with protective glass, and the chip has TSVs (transistor-strip-vibration) to route signals from the upper layer to the lower layer. The lower surface of the chip has RDLs and tin-copper bumps. The chip-scale package is then stacked on a fan-out package that houses a controller or processor. Multiple stacked packages are then soldered to a circuit board.

[0003] Display chips contain light-emitting chips for red, green, and blue (RGB) pixels. Each emits three types of light to the screen, which are then blended to create images of various colors. These three different light-emitting chips have their own driver and control chips. Optical lenses in front of each light-emitting chip focus the light pixels on the screen. Coplanarity between the light-emitting chips is crucial. Good coplanarity ensures that the three color pixels overlap correctly, resulting in clear images. Poor coplanarity prevents the three color pixels from overlapping correctly, resulting in incorrect blended colors and blurry images. Image sensor chips also face similar issues.

[0004] The packaging of the front sensor or display is independent of the three colors, so it is difficult to control the coplanarity, resulting in low product yield. Summary of the Invention

[0005] The purpose of the present invention is to provide a fan-out packaging structure and packaging method for an embedded sensor or display chip, and to solve the following technical problems:

[0006] How to encapsulate multiple sensor or display chips in the same package and reduce the size of the system.

[0007] The purpose of the present invention can be achieved through the following technical solutions:

[0008] A packaging method for embedding a sensor or display chip includes the following steps:

[0009] Step 1: Making a chip-scale package: Apply glue to specific locations on the wafer surface, then flip-chip the wafer onto one side of a third glass carrier. Apply protective tape to the other side of the third glass carrier to protect it from scratches during the manufacturing process.

[0010] TSVs are fabricated on the side of the wafer to serve as signal connections between the top and bottom surfaces of the chip. Several fourth RDL layers are then fabricated on the side of the wafer away from the third glass carrier. Finally, tin-copper bumps are electroplated at the topmost RDL layer contacts.

[0011] Then remove the protective tape and cut the wafer and the third glass carrier into individual pieces to obtain chip-scale packaging, and there is glass protection on the sensor or display chip;

[0012] Step 2: Making a fan-out package: Apply adhesive to the upper side of the second glass carrier to form a second adhesive layer, make the first-side tin-copper contacts and several first RDL layers on the upper side of the second adhesive layer, set several copper pillars on the upper side of the top first RDL layer, adhere the chip body, i.e. the driver chip or control chip of the sensor or display, on the upper side of the top first RDL layer, set the first copper bump on the upper side of the chip body, and cast a first molding resin layer on the upper side of the first RDL layer to wrap around the copper pillars and the outside of the chip body;

[0013] Step 3: Grinding the first die resin layer to expose the copper pillars and the first copper bumps to a designed thickness, wherein the exposed thickness is adjusted by adjusting the thickness of the first die resin layer;

[0014] Step 4: A plurality of second RDL layers are formed on the upper side of the first molding resin layer. The uppermost second RDL layer is the second surface contact, and a second copper bump is provided on the upper side of the second surface contact at the uppermost second RDL layer contact. The second adhesive layer is then debonded, and the first RDL layer is separated from the second glass carrier. The glass carrier is removed and the chips are cut into individual pieces to obtain a fan-out package.

[0015] Step 5: Assemble the chip-scale package and the fan-out package: Attach the third glass of several chip-scale packages to the first glass carrier through the first adhesive layer. The thickness of the first glass carrier is standard. Because several chip-scale packages are on the same plane, they have good coplanarity. After assembly, the tin-copper bumps of the chip-scale package are distributed upward. Align the tin-copper contacts on the first side of the fan-out package with the tin-copper bumps of the chip-scale package and solder them to form electrical conduction. After assembly, the second copper bumps of the contacts on the second side of the fan-out package are facing upward.

[0016] Step 6: Process a second mold resin layer on the outside of each fan-out package, grind the second mold resin layer, expose the second copper bump of the second surface contact of the fan-out package to the designed thickness, and make several third RDL layers on the side of the second mold resin layer and corresponding to the upper side of each fan-out package. The third copper bump is set at the contact of the top third RDL layer, and solder balls are planted on the third copper bump to obtain the initial product;

[0017] Step 7: Debonding the first adhesive layer, removing the first glass carrier, and cutting the initial product into individual pieces, wherein the initial product includes a plurality of assembled chip-scale packages and fan-out packages. After being cut into individual pieces, each piece contains three sets of assembled chip-scale packages and fan-out packages. After completing the process of embedding the chip-scale package in the fan-out package, the plurality of chip-scale packages are embedded in a molding resin. The coplanarity of the plurality of chip-scale packages will not be changed by subsequent processes.

[0018] The present invention also discloses a fan-out packaging structure for embedding a sensor or display chip, comprising a first glass carrier, with a plurality of chip-scale packages adhered to the upper side of the first glass carrier via a first adhesive layer. After processing, the first adhesive layer is dissociated, the first glass carrier is removed, and fan-out packages are mounted on the upper sides of the plurality of chip-scale packages. A second molding resin layer covering the outer sides of the plurality of first adhesive layers and the plurality of chip-scale packages is provided on the upper side of the first glass carrier.

[0019] The upper side of the chip-scale package is provided with upwardly distributed tin-copper bumps;

[0020] The fan-out package is provided with a second surface contact and a first surface tin-copper contact on the upper and lower sides respectively. The first surface tin-copper contact is electrically connected to the tin-copper bump of the chip-scale package by welding. The upper side of the second surface contact is provided with a plurality of second copper bumps extending to the upper side of the second molding resin layer.

[0021] A third RDL layer connected to the second copper bump is provided on the upper side of the second molding resin layer. A plurality of third copper bumps are provided on the uppermost side of the third RDL layer. Solder balls are planted outside the plurality of third copper bumps.

[0022] As a further solution of the present invention: the chip-scale packaging includes a third glass carrier, a flip-chip wafer is adhered to the upper side of the third glass carrier, and TSV (through silicon via) is made on the back side of the wafer to serve as a signal connection between the upper and lower surfaces of the chip, and several fourth RDL layers are provided on the side of the wafer away from the third glass carrier, and tin-copper bumps are provided on the uppermost side of the several fourth RDL layers.

[0023] As a further solution of the present invention: the third glass carrier in the chip-level package is affixed with a protective tape on the side away from the wafer during processing to protect the third glass carrier from being scratched during the process. After processing, the protective tape is removed, and the thickness of the third glass carrier adopts a standard thickness.

[0024] As a further solution of the present invention: the fan-out package includes several first RDL layers arranged on the upper side of the tin-copper contact on the first side, several copper pillars are arranged on the upper side of the uppermost first RDL layer, and the lowermost first RDL layer is provided with tin-copper bumps for welding with the chip-level package. Several copper pillars constitute an installation area, and the installation area is provided with a chip body adhered to the uppermost first RDL layer.

[0025] As a further solution of the present invention: a plurality of first copper bumps distributed upward are provided on the side surface of the chip body.

[0026] As a further solution of the present invention: a first mold resin layer covering the outside of the chip body and several copper pillars is provided on the upper side of the first RDL layer, and several of the copper pillars and several first copper bumps all extend to the outside of the first mold resin layer. When the mold is filled with resin to form the chip body, the chip body is covered to the outside of the several copper pillars and several first copper bumps, and the surface is then polished until the several copper pillars and the first copper bumps are exposed to the designed thickness.

[0027] As a further solution of the present invention: before processing, the first RDL layer is adhered to the upper side of the second glass carrier through a second adhesive layer. After processing, the second adhesive layer is dissociated, and the first RDL layer is separated from the second glass carrier.

[0028] As a further solution of the present invention: the thickness of the second adhesive layer is uniformly arranged on the upper side of the second glass carrier.

[0029] As a further solution of the present invention: a plurality of second RDL layers covering a plurality of copper pillars and a plurality of first copper bumps are provided on the upper side of the first molding resin layer, and a plurality of second copper bumps are provided on the upper side of the topmost second RDL layer.

[0030] As a further solution of the present invention: the first RDL layer, the second RDL layer, the third RDL layer and the fourth RDL layer are all plural layers.

[0031] As a further solution of the present invention: the chip-level packages and fan-out packages are of the same number, and both the chip-level packages and the fan-out packages are plural.

[0032] Beneficial effects of the present invention:

[0033] The present invention embeds multiple chip-scale packages in a molding resin. Because the coplanarity of the multiple chip-scale packages is not affected by subsequent manufacturing processes, and because multiple chips are encapsulated in the same package, the system size can be reduced.

[0034] During chip-level packaging processing, a protective tape is attached to the side of the first glass carrier away from the wafer to protect the third glass carrier from being scratched during the process. The third glass carrier can also protect the sensor or display chip on the upper side. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The present invention will be further described below with reference to the accompanying drawings.

[0036] Figure 1 This is a schematic diagram of the finished product of the chip package in the present invention;

[0037] Figure 2 is a cross-sectional view of the fan-out package of the present invention;

[0038] Figure 3 is an assembly flow chart of the fan-out package in the present invention;

[0039] Figure 4 It is a schematic diagram of a semi-finished product of chip packaging in the present invention.

[0040] In the figure: 1. First glass carrier; 2. First adhesive layer; 3. Chip-scale packaging; 4. Fan-out packaging; 41. First RDL layer; 42. Wafer body; 43. Copper pillar; 44. Second RDL layer; 45. First copper bump; 46. Second glass carrier; 47. Second adhesive layer; 48. First mold resin layer; 49. Second copper bump; 5. Second mold resin layer; 6. Third RDL layer; 7. Third copper bump. DETAILED DESCRIPTION

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0042] See also Figure 1-Figure 4 As shown, the present invention is a fan-out packaging structure for embedding a sensor or display chip, comprising a first glass carrier 1, to the upper side of which a plurality of chip-scale packages 3 are adhered via a first adhesive layer 2. After processing, the first adhesive layer 2 is dissociated, the first glass carrier 1 is removed, and fan-out packages 4 are mounted on the upper sides of the plurality of chip-scale packages 3. A second molding resin layer 5 covering the outer sides of the plurality of first adhesive layers 2 and the plurality of chip-scale packages 3 is provided on the upper side of the first glass carrier 1;

[0043] The upper side of the chip-scale package 3 is provided with upwardly distributed tin-copper bumps;

[0044] The upper and lower sides of the fan-out package 4 are respectively provided with second-side contacts and first-side tin-copper contacts. The first-side tin-copper contacts are electrically connected to the tin-copper bumps of the chip-scale package 3 by welding. The upper side of the second-side contacts is provided with a plurality of second copper bumps 49 extending to the upper side of the second molding resin layer 5.

[0045] A third RDL layer 6 connected to the second copper bumps 49 is provided on the upper side of the second molding resin layer 5 . A plurality of third copper bumps 7 are provided on the uppermost side of the third RDL layer 6 . Solder balls are planted outside the plurality of third copper bumps 7 .

[0046] The chip-scale package 3 includes a third glass carrier, a flip-chip wafer is adhered to the upper side of the third glass carrier, and TSVs are made on the back of the wafer to serve as signal connections between the upper and lower surfaces of the chip. Several fourth RDL layers are provided on the side of the wafer away from the third glass carrier, and tin-copper bumps are provided on the uppermost side of the several fourth RDL layers.

[0047] The third glass carrier in the chip-scale package 3 is located on a side away from the wafer. During processing, a protective tape is attached to the side of the third glass carrier to prevent the glass carrier from being scratched during the manufacturing process. The protective tape is removed after processing.

[0048] See also Figure 2 As shown, the fan-out package 4 includes several first RDL layers 41 arranged on the upper side of the first-side tin-copper contact, several copper pillars 43 are arranged on the upper side of the uppermost first RDL layer 41, and the lowermost first RDL layer 41 is provided with tin-copper bumps for welding with the chip-level package 3. Several copper pillars 43 constitute a mounting area, and the mounting area is provided with a chip body 42 adhered to the uppermost first RDL layer 41.

[0049] A plurality of first copper bumps 45 distributed upward are provided on the side surface of the chip body 42 .

[0050] A first molding resin layer 48 covering the outside of the chip body 42 and several copper pillars 43 is provided on the upper side of the first RDL layer 41. Several copper pillars 43 and several first copper bumps 45 all extend to the outside of the first molding resin layer 48. When the molding resin is poured to form the chip body 42, the chip body 42 is covered to the outside of the several copper pillars 43 and several first copper bumps 45, and the surface is then polished until the several copper pillars 43 and the first copper bumps 45 are exposed to the designed thickness.

[0051] Before processing, the first RDL layer 41 is adhered to the upper side of the second glass carrier 46 through the second adhesive layer 47. The thickness of the second adhesive layer 47 is uniformly set on the upper side of the second glass carrier 46. After processing, the second adhesive layer 47 dissociates, and the first RDL layer 41 is separated from the second glass carrier 46.

[0052] A plurality of second RDL layers 44 covering the copper pillars 43 and the first copper bumps 45 are provided on the upper side of the first molding resin layer 48 . A plurality of second copper bumps 49 are provided on the uppermost second RDL layer 44 .

[0053] The first RDL layer 41 , the second RDL layer 44 , the third RDL layer 6 , and the fourth RDL layer are all plural layers.

[0054] The number of chip-scale packages 3 and fan-out packages 4 is the same, and both the chip-scale packages 3 and the fan-out packages 4 are plural.

[0055] The packaging method of the embedded sensor or display chip includes the following steps:

[0056] Step 1: Fabricating Chip-Scale Package 3: Apply glue to specific locations on the wafer surface, then flip-chip-mount the wafer onto one side of a third glass carrier. Apply protective tape to the other side of the third glass carrier to prevent scratches during the manufacturing process.

[0057] TSVs are fabricated on the side of the wafer to serve as signal connections between the top and bottom surfaces of the chip. Several fourth RDL layers are then fabricated on the side of the wafer away from the third glass carrier. Finally, tin-copper bumps are electroplated at the topmost RDL layer contacts.

[0058] Then remove the protective tape and cut the wafer and the third glass carrier into individual pieces to obtain chip-scale package 3, and there is glass protection on the sensor or display chip;

[0059] Step 2: Fabricating a fan-out package 4: Apply adhesive to the upper side of a second glass carrier 46 to form a second adhesive layer 47. A first-side tin-copper contact and several first RDL layers 41 are fabricated on the upper side of the second adhesive layer 47. Several copper pillars 43 are disposed on the upper side of the topmost first RDL layer 41. A chip body 42, i.e., a driver chip or control chip for a sensor or display, is adhered to the upper side of the topmost first RDL layer 41. First copper bumps 45 are disposed on the upper side of the chip body 42. A first molding resin layer 48 is molded and poured on the upper side of the first RDL layer 41 to wrap around the copper pillars 43 and the chip body 42.

[0060] Step 3: Grinding the first mold resin layer 48 to expose the copper pillars 43 and the first copper bumps 45 to a designed thickness. The exposed thickness is adjusted by adjusting the thickness of the first mold resin layer 48;

[0061] Step 4: Form several second RDL layers 44 on the upper side of the first molding resin layer 48. The uppermost second RDL layer 44 is the second surface contact, and a second copper bump 49 is provided on the upper side of the second surface contact at the uppermost second RDL layer 44 contact. Then, the second adhesive layer 47 is dissociated, and the first RDL layer 41 is separated from the second glass carrier 46. The glass carrier is removed and the chip is cut into individual pieces to obtain a fan-out package 4.

[0062] Step 5: Assemble the chip-scale package 3 and the fan-out package 4: Attach the third glass of several chip-scale packages 3 to the first glass carrier 1 via the first adhesive layer 2. Because the several chip-scale packages 3 are on the same plane, they have good coplanarity. After assembly, the tin-copper bumps of the chip-scale package 3 are distributed upward. The tin-copper contacts on the first side of the fan-out package 4 are aligned with the tin-copper bumps of the chip-scale package 3 and soldered to form electrical conduction. After assembly, the second copper bumps 49 of the contacts on the second side of the fan-out package 4 are facing upward.

[0063] Step 6: Process the second mold resin layer 5 on the outside of each fan-out package 4, and grind the second mold resin layer 5 to expose the second copper bump 49 of the second surface contact of the fan-out package 4 to the designed thickness. Make several third RDL layers 6 on the side of the second mold resin layer 5 and on the upper side of each fan-out package 4. Set the third copper bump 7 at the contact of the top third RDL layer 6, and plant solder balls at the third copper bump 7 to obtain the initial product.

[0064] Step 7: Debond the first adhesive layer 2, remove the first glass carrier 1, cut the initial product into individual pieces, and complete the process of embedding the chip-scale package 3 in the fan-out package 4. The plurality of chip-scale packages 3 are embedded in the molding resin. Preferably, a single initial product is provided with three sets of connected chip-scale packages 3 and fan-out packages 4. The coplanarity of the plurality of chip-scale packages 3 will not be changed by subsequent processes.

[0065] The above is a detailed description of an embodiment of the present invention. However, the content described is only a preferred embodiment of the present invention and should not be considered to limit the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. A fan-out packaging method for embedded sensors or display chips, characterized in that: The following steps are involved: Step 1: making a chip-scale package (3) and processing tin-copper bumps on the upper side of the chip-scale package (3); Step 2: making a fan-out package (4), and processing a second surface contact and a first surface tin-copper contact on the upper and lower sides of the fan-out package (4), respectively, and processing a second copper bump (49) on the upper side of the second surface contact; Step 3: Attach and assemble a plurality of chip-scale packages (3) to the first glass carrier (1), align the first-side tin-copper contacts of each fan-out package (4) with the corresponding tin-copper bumps of the chip-scale package (3), and weld them to form electrical conduction; Step 4: Processing a second mold resin layer (5) on the outer sides of each chip-level package (3) and fan-out package (4), and making a plurality of third RDL layers (6) corresponding to each fan-out package (4) on the second mold resin layer (5); Step 5: Separate the first glass carrier (1), and then cut the plurality of chip-scale packages (3) and fan-out packages (4) into a single unit. The single unit contains three sets of assembled chip-scale packages (3) and fan-out packages (4). After completing the process of embedding the chip-scale package (3) in the fan-out package (4), the plurality of chip-scale packages (3) are embedded in the molding resin.

2. The fan-out packaging method for an embedded sensor or display chip according to claim 1, characterized in that: In the fourth step, a third copper bump (7) is provided at the contact point of the uppermost third RDL layer (6), and a solder ball is planted at the third copper bump (7).

3. The fan-out packaging method for an embedded sensor or display chip according to claim 1, characterized in that: The processing method of the fan-out package (4) comprises the following steps: B1: Applying adhesive on the upper side of the second glass carrier (46) to form a second adhesive layer (47); B2: a first-side tin-copper contact and a plurality of first RDL layers (41) are formed on the upper side of the second adhesive layer (47), a plurality of copper pillars (43) are provided on the upper side of the uppermost first RDL layer (41), and a chip body (42) is adhered to the upper side of the uppermost first RDL layer (41); B3: A first molding resin layer (48) is molded on the upper side of the first RDL layer (41) to wrap around the copper pillar (43) and the outer side of the chip body (42); B4: a plurality of second RDL layers (44) are formed on the upper side of the first die resin layer (48), the uppermost second RDL layer (44) being the second surface contact, and a second copper bump (49) located on the upper side of the second surface contact is provided at the uppermost second RDL layer (44) contact; B5: Debonding the second adhesive layer (47), separating the first RDL layer (41) from the second glass carrier (46), removing the glass carrier, and cutting into individual pieces.

4. A fan-out packaging structure of a fan-out packaging method for embedding a sensor or display chip according to any one of claims 1 to 3, comprising a plurality of chip-level packages (3) and a plurality of fan-out packages (4), characterized in that: The upper side of the chip-scale package (3) is provided with upwardly distributed tin-copper bumps; The upper and lower sides of the fan-out package (4) are respectively provided with a second surface contact and a first surface tin-copper contact, and the first surface tin-copper contact is electrically connected to the tin-copper bump of the chip-level package (3) by welding; A second compression mold resin layer (5) is provided on the outer sides of the plurality of chip-scale packages (3) and the plurality of outer fan-out packages (4), and a plurality of second copper bumps (49) extending to the upper side of the second compression mold resin layer (5) are provided on the upper side of the second surface contacts; A third RDL layer (6) connected to the second copper bump (49) is provided on the upper side of the second die-cast resin layer (5); a plurality of third copper bumps (7) are provided on the uppermost side of the third RDL layer (6); and solder balls are planted outside the plurality of third copper bumps (7).

5. The fan-out packaging structure for an embedded sensor or display chip according to claim 4, characterized in that: The fan-out package (4) comprises a plurality of first RDL layers (41) arranged on the upper side of the first-side tin-copper contact, a plurality of copper pillars (43) are arranged on the upper side of the uppermost first RDL layer (41), a tin-copper bump is arranged on the lowermost first RDL layer (41), and a chip body (42) adhered to the uppermost first RDL layer (41) is arranged between the plurality of copper pillars (43).

6. The fan-out packaging structure for an embedded sensor or display chip according to claim 5, characterized in that: A plurality of first copper bumps (45) distributed upwards are provided on the side surface of the chip body (42).

7. The fan-out packaging structure for an embedded sensor or display chip according to claim 6, wherein: A first die-cast resin layer (48) covering the outside of the chip body (42) and the plurality of copper pillars (43) is provided on the upper side of the first RDL layer (41), and the plurality of copper pillars (43) and the plurality of first copper bumps (45) all extend to the outside of the first die-cast resin layer (48).

8. The fan-out packaging structure for an embedded sensor or display chip according to claim 7, wherein: A plurality of second RDL layers (44) covering the outside of a plurality of copper pillars (43) and a plurality of first copper bumps (45) are provided on the upper side of the first die resin layer (48), and a plurality of second copper bumps (49) are provided on the upper side of the uppermost second RDL layer (44).

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