Prevention of discharge in power switches in power converters

Abstract

A power converter includes a controller for controlling a synchronous rectifier (SR) switch. The controller includes a request control circuit and a discharge prevention circuit. The request control circuit is configured to generate a request signal in response to the output of the power converter. The request control circuit generates a secondary control signal to control the SR switch. The discharge prevention circuit is configured to prevent the discharge of parasitic capacitance of the power switch caused by the activating of the SR switch. The discharge prevention circuit further generates a prevention signal to: disable the control of the synchronous rectifier switch by the secondary control signal when the period of the request signal is greater than a first time threshold; and enable the control of the synchronous rectifier switch by the secondary control signal when the period of the request signal is less than a second time threshold.

Description

[0001] Background Information

[0002] Technical fields of publicly available content

[0003] The present invention relates generally to power converters, and more specifically to methods for preventing the discharge of parasitic capacitance of power switches caused by the switching on of synchronous rectifier switches. Background Technology

[0004] Electronic devices (such as cell phones, tablets, laptops, etc.) operate using electricity. Switch-mode power supplies are commonly used to power many of today's electronic devices because of their high efficiency, small size, and light weight. Conventional wall outlets provide high-voltage alternating current (AC). In a switching power supply, a switch-mode power converter transforms the high-voltage AC input into a well-regulated direct current (DC) output to the load through energy transfer elements. During operation, switches are turned on and off to provide the desired output by changing the duty cycle (typically the ratio of the switch's on time to the total switching cycle), changing the switching frequency, or changing the number of on / off pulses per unit time of the switch in the switch-mode power converter.

[0005] A switch-mode power converter may include a clamping circuit coupled across the primary winding of an energy transfer element to prevent damage to the switch. Typically, this clamping circuit includes passive components such as diodes, resistors, or capacitors. Generally, passive components can store or maintain energy in the form of voltage or current. Active components can generate energy in the form of voltage or current. One embodiment of an active component may be a transistor. Attached Figure Description

[0006] Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein, unless otherwise stated, the same reference numerals refer to the same parts in all the various views.

[0007] Figure 1 An embodiment of a power converter having active clamping, a first controller, and a second controller, according to some embodiments of the present disclosure, is illustrated.

[0008] Figure 2 An embodiment of a power converter according to some embodiments of the present disclosure is illustrated, wherein the parasitic capacitance of the power switch is discharged due to the switching on of the synchronous rectifier.

[0009] Figure 3 Timing diagrams illustrating some embodiments of this disclosure are shown, illustrating secondary control signals, clamping voltages, drain-source voltages, primary currents, and secondary currents.

[0010] Figure 4 Examples of implementation schemes based on this disclosure are provided, such as... Figure 1 An embodiment of the anti-discharge circuit shown is illustrated.

[0011] Figure 5 Examples of some implementation schemes based on this disclosure are illustrated. Figure 4 An embodiment of the state machine diagram for an anti-discharge circuit.

[0012] Figure 6 A flowchart illustrating some embodiments of the present disclosure is provided, illustrating the prevention of discharge of power switches.

[0013] In all the views of the accompanying drawings, corresponding reference characters indicate corresponding parts. Those skilled in the art will understand that the elements in the drawings are illustrated for simplicity and clarity and are not necessarily drawn to scale. For example, the dimensions of some elements in the drawings may be exaggerated relative to other elements to aid in understanding the various embodiments of the invention. Furthermore, common but easily understood elements that are useful or necessary in commercially viable embodiments are generally not described to facilitate viewing of these embodiments of the invention with less hindrance. Detailed Implementation

[0014] This document describes embodiments of a controller for preventing discharge of power switches caused by the switching on of a synchronous rectifier. Numerous specific details are set forth in the following description to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the specific details are not required to practice the invention. In other instances, well-known materials or methods have not been described in detail to avoid obscuring the invention.

[0015] Throughout this specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean that a specific feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases "one embodiment," "an embodiment," "one example," or "an example" appearing in various places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. Specific features, structures, or characteristics can be included in integrated circuits, electronic circuits, combinational logic circuits, or other suitable components that provide the described functionality. Additionally, it should be understood that the accompanying drawings are for illustrative purposes to those skilled in the art and are not necessarily drawn to scale.

[0016] Power converters—such as flyback converters with active clamping circuitry—can provide high efficiency because they achieve zero-voltage switching on the power switch. Active clamping circuitry serves several purposes: limiting the voltage across the drain of the power switch and recovering energy back into the output instead of dissipating it. Each time the power switch is turned off, the clamping capacitor of the active clamping driver is charged. For flyback converters with synchronous rectifier (SR) switches, the SR switch is turned on to charge the output capacitor once the power switch is turned off. The on-time of the SR switch corresponds to a secondary current greater than zero. The on-time varies in response to the load.

[0017] Under light or no-load conditions, the clamping capacitor can be charged to a voltage less than the reflected voltage of the secondary winding. After the power switch is turned off, energy is transferred from the primary winding to the secondary winding. To avoid noise that could cause the SR switch to turn off unexpectedly, the SR switch is typically turned on for at least a minimum on-time. When the secondary current decreases below zero, an undesirable operation occurs, in which the output capacitor discharges and begins to charge the secondary winding. Turning off the SR switch will then cause energy to be transferred from the secondary winding back to the primary winding, which may cause the drain voltage to drop below ground. This disclosure includes circuit systems that prevent undesirable conditions from occurring by disabling control of the SR switch under light or no-load conditions. In other words, the SR switch is not allowed to be turned on under light or no-load conditions.

[0018] For example, Figure 1A diagram illustrating an example power converter 100 according to the teachings of this disclosure is provided. The power converter 100 includes an example active clamping circuit 104, a first controller 120, and a second controller 121. The illustrated embodiment of the power converter 100 includes an energy transfer element 106, a primary winding 108 of the energy transfer element 106, a secondary winding 110 of the energy transfer element 106, an input return line 111, a power switch S1 112, an active clamping circuit 104, an SR switch 114, and an output capacitor C. O 116 and output return line 117. The active clamping circuit 104 is shown as including clamping capacitor C. CL 122, active clamp switch 123 (represented as a transistor with associated anti-parallel diodes) and diodes 124 and 125.

[0019] The first controller 120 is shown as including a clamping control circuit 131 and an adjustment control circuit 133. The parasitic capacitance C is represented by a dashed line. P1 127 is shown to represent all capacitors coupled to power switch S1 112, and may include the inherent capacitance within energy transfer element 106, the inherent internal capacitance of power switch S1 112, and / or discrete capacitors. Figure 1 The input voltage V is also shown. IN 102. Output voltage V O 138. Output current I O 107. Drive signal U D 128. Clamp enable signal U EN 130. Clamping drive signal U CD 132. Clamping voltage V CL 136. Primary voltage V P 137. Current sensing signal; 129. Feedback signal U FB 139. Secondary control signal U SR 140. Request signal U REQ 141. Clamping current I CL 142. Drain voltage V D 143. Switching current I D 144 and enable signal U ESR 145.

[0020] In the illustrated embodiment, power converter 100 is shown with a flyback topology. Furthermore, the input and output currents of power converter 100 are isolated, such that input loop 111 is current-isolated from output loop 117. Because the input and output of power converter 100 are current-isolated, there is no direct current (DC) path across the isolation barrier of energy transfer element TI 106, or between the primary winding 108 and the secondary winding 110, or between input loop 111 and output loop 117. It should be understood that other known topologies and configurations of power converters may also benefit from the teachings of this disclosure.

[0021] Power converter 100 takes unregulated input V IN 102 provides output power to load 118. In one embodiment, the input voltage V IN 102 is the rectified and filtered AC line voltage. In another implementation, the input voltage V IN 102 is the DC input voltage. Input voltage V IN 102 is coupled to energy transfer element 106. In some embodiments, energy transfer element 106 may be a coupling inductor, transformer, or inductor. An example energy transfer element 106 is shown as comprising two windings: a primary winding 108 and a secondary winding 110. When power switch S1 112 is turned on, the primary voltage V P 137 is basically equal to the input voltage V IN The negative sum of 102, or mathematically: V P =-V IN .

[0022] When power switch S1 112 is open, the primary voltage V P 137 is essentially equal to the reflected output voltage of the secondary winding 110. The primary winding 108 of the energy transfer element is further coupled to power switch S1 112, and power switch S1 112 is further coupled to the input loop 111. The voltage at the drain of power switch S1 112 is denoted as the drain voltage V. D 143, which is also the parasitic capacitance C P1 The voltage across 127.

[0023] An active clamping circuit 104 is coupled in parallel to the primary winding 108. The active clamping circuit 104 is shown as including a clamping capacitor C. CL 122. The clamping capacitor is coupled to the active clamping switch 123, diodes 124 and 125. Diode 124 is coupled to the clamping capacitor C. CLOne end of 122. The active clamp switch 123 is illustrated as a transistor having a body diode (anti-parallel diode). As shown, the active clamp switch 123 is shown as a metal-oxide-semiconductor field-effect transistor (MOSFET), but it should be understood that other transistors may be used. It should be understood that the active clamp switch 123 may also be in a cascode configuration, where a low-voltage transistor is coupled to a high-voltage junction field-effect transistor (JFET). The JFET transistor may include gallium nitride (GaN) or silicon carbide (SiC) materials.

[0024] The active clamp switch 123 is coupled so that the drain of the transistor is coupled to the clamp capacitor C. CL 122, while the source of the active clamp switch 123 is coupled to the anode of diode 125. The cathode of diode 124 is coupled to the clamping capacitor C. CL 122.

[0025] Clamping capacitor C CL The voltage across 122 is labeled as the clamping capacitor voltage V. CL Furthermore, the current in the clamping circuit is labeled as the clamping current I. CL 142.

[0026] The active clamping circuit 104 limits the maximum voltage on the power switch S1 112. Furthermore, control of the active clamping switch 123 within the active clamping circuit 104 facilitates zero-voltage switching of the power switch S1 112. Additionally, the active clamping circuit 104 can reduce the root-mean-square (RMS) current in the power converter 100. Diodes 124 and 125 can be used to control the flow to the clamping capacitor C. CL Clamping current I of 122 CL 142.

[0027] The active clamping circuit 104 is coupled to receive the clamping drive signal U from the first controller 120. CD 132. The active clamp switch 123 is controlled to turn on to inject current into the primary winding 108. The active clamp switch 123 is turned on for a first duration before the power switch S1 112 turns on. In other words, the active clamp switch 123 is not turned on for the entire duration during which the power switch S1 112 is turned off. At or near the beginning of the off time of the power switch S1 112, the diode 124 conducts the charge associated with the uncoupled inductor of the power converter 100. In one embodiment, when the drain voltage V D When the voltage is increased to a sufficiently high level to forward bias the diode 124 of the active clamping circuit 104, diode 124 conducts. Drain voltage V D143 is increased at or near the start of the off-time of power switch S1 112. Diode 125 blocks charge conduction associated with the uncoupled inductor. Charge from the uncoupled inductor is transferred to clamping capacitor C via diode 124. CL 122 and is stored. Diode 124 essentially stops conducting after the net charge associated with the uncoupled inductor of power converter 100 has been transferred.

[0028] The active clamp switch 123 remains open until near the end of the off-time of the power switch S1 112. It should be understood that in other embodiments, a non-active clamp—such as a resistor-clamp-diode (RCD)—may be used instead of the active clamp switch 123. Once it is determined that the power switch should be turned on, the active clamp switch 123 is turned on for a first duration. The turning on of the active clamp switch 123 occurs before the power switch S1 112 is turned on, near the end of the off-time of the power switch S1 112. The transistor of the active clamp switch 123 is turned on such that the net charge previously transferred to the clamp capacitor C1 144 associated with the uncoupled circuit is transferred to the primary winding 108. Thus, the energy associated with the uncoupled inductor is returned to the system instead of dissipated. In one embodiment, the uncoupled inductor represents the leakage inductance of the energy transfer element 106. The active clamp switch 123 is controlled so that the leaked energy is reset and returned to the power converter instead of being dissipated.

[0029] The secondary winding 110 is coupled to the SR switch 114. Output capacitor C O 116 is shown as coupled to SR switch 114 and output return line 117. The power converter 100 also includes circuitry for regulating the output, which in one embodiment may be an output voltage V. O 138. Output current I O 107 or a combination of both. The feedback signal U represents the output of the power converter 100. FB 139 is provided to the second controller 121.

[0030] The second controller 121 is coupled to receive a feedback signal U representing the output of the power converter 100. FB 139 and outputs secondary control signal U SR 140 and request signal U REQ 141. Secondary drive signal U SR 126 is received by SR switch 114 and controls the switching of SR switch 114 on and off. Request signal U REQ 141 represents a request to turn on power switch S1 112. Request signal U REQ 141 may include a response to feedback signal U FBThe request event generated by 139. In one embodiment, the request signal U REQ 141 may include a feedback signal U FB A request event generated by comparing 139 with the target value. Request signal U REQ 141 can be a rectangular pulse waveform that jumps to a logic high value and quickly returns to a logic low value. The logic high pulse can be referred to as a request event.

[0031] The first controller 120 is coupled to receive a request signal U via communication link 146 (shown as a dashed line). REQ 141, and output clamping drive signal U CD 132 and drive signal U D 128. The first controller 120 will drive signal U D 128 provides power switch S1 112 with various switching parameters to control the transfer of energy through energy transfer element 106 from the input of power converter 100 to the output of power converter 100. Examples of these parameters include switching frequency (or switching period), duty cycle, on-time and off-time, or changing the number of pulses per unit time of power switch S1 112. Additionally, power switch S1 112 can be controlled to have a fixed switching frequency or a variable switching frequency. In one embodiment of variable switching frequency control, the switching frequency can be reduced for light load conditions or no load conditions.

[0032] The second controller 121 and the first controller 120 can communicate via communication link 146. In the illustrated embodiment, the second controller 121 is coupled to the secondary side of the power converter 100 and references output loop 117, while the first controller 120 is coupled to the primary side of the power converter 100 and references input loop 111. Regulation control 133 references input loop 111. In embodiments, the first controller 120 and the second controller 121 are current-isolated from each other, and communication link 146 uses inductive coupling (such as a transformer or coupling inductor), optocoupler, capacitive coupling, or other devices that maintain isolation to provide current isolation. However, it should be understood that in some embodiments, the second controller 121 is not current-isolated from the first controller 120.

[0033] In one embodiment, the first controller 120 and the second controller 121 may be formed as part of an integrated circuit, which is manufactured as a hybrid integrated circuit or a monolithic integrated circuit. In one embodiment, the power switch S1 112 may also be integrated with the first controller 120 and the second controller 121 in a single integrated circuit package. Alternatively, in one embodiment, the first controller 120 and the second controller 121 may be formed as separate integrated circuits. The power switch S1 112 may also be integrated with the first controller 120 in the same integrated circuit or may be formed on its own integrated circuit. Furthermore, it should be understood that the first controller 120, the second controller 121, and the power switch S1 112 need not be included in a single package, but may be implemented in separate controller packages or a combination of / separate packages.

[0034] Generally, it is understood that a closed switch can conduct current and is considered to be conducting, while an open switch cannot conduct current and is considered to be open. In one embodiment, the power switch S1 112 can be a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a bipolar junction transistor (BJT), a SiC-based transistor, a GaN-based transistor, or an insulated-gate bipolar transistor (IGBT).

[0035] The first controller 120 includes a clamping control circuit 131 and an adjustment control circuit 133. As shown, the adjustment control circuit 133 is coupled to receive a request signal U. REQ 141 and output drive signal U D 128 and clamp enable signal U EN 130, drive signal U D 128 controls the switching of power switch S1 112. In one embodiment, the clamp enable signal U EN 130 can represent when the power switch S1 112 will be enabled (or turned on). Or in other words, the clamp enable signal U EN 130 can represent the determination of turning on the power switch S1 112. Or in other words, the clamp enable signal U. EN 130 indicates that the active clamp switch 123 can be turned on.

[0036] Clamp control circuit 131 is coupled to receive clamp enable signal U EN 130 and output clamping drive signal U CD 132. Clamping Driver U CD 132 controls various switching parameters of the active clamp switch 123, such as the on-time or off-time of the active clamp switch 123. In one embodiment, the clamp drive signal U CD132 is a rectangular pulse waveform with varying durations of logic high and logic low segments. The logic high segment corresponds to the active clamp switch 123 being turned on, and the logic low segment corresponds to the active clamp switch 123 being turned off.

[0037] In one embodiment, the clamping control circuit 131 uses a clamping drive signal U CD 132 controls the amount of current supplied to the primary winding 108 so that the net charge associated with the uncoupled inductor is transferred to the primary winding 108.

[0038] The adjustment control circuit 133 is also coupled to receive the clamping drive signal U. CD 132 and output drive signal U D 128. As shown, the regulating control circuit 133 is also coupled to receive the switching current I representing the power switch S1 112. D The current sensing signal 129 of 144. In an embodiment, the regulating control circuit 133 adjusts the clamping drive signal U. CD 132 indicates that the active clamp switch 123 has been turned off, after which the power switch S1 112 is turned on. In other words, the control circuit adjusts the clamp drive signal U... CD The drive signal U is output after the trailing edge of the 132. D 128 turns on power switch S1 112. Furthermore, the regulating control circuit 133 turns on power switch S1 112 only after a second duration has elapsed since the active clamp switch 123 has been turned off. This second duration can be selected to provide a drain voltage V before power switch S1 112 is turned on. D 143 drops to essentially zero within sufficient time (or in other words, provides enough time for the parasitic capacitance C to decrease). P1 Sufficient time is allowed for 127 to fully discharge into the primary winding 108, which allows for zero-voltage switching of the power switch S1 112. In one embodiment, when the switching current I provided by the current sensing signal 129... D When the current limit is reached, the regulating control circuit 133 can turn off the power switch S1112.

[0039] The second controller 121 is configured to output a secondary control signal U. SR 140 controls SR switch 114 and generates request signal U REQ 141 turns on power switch S1 114. The second controller 121 includes an anti-discharge circuit 134 and a request control circuit 135. The request control circuit 135 is coupled to receive feedback signal U. FB 139 and generates a request signal U when the output of the power converter (i.e., output voltage, output current, or a combination of both) drops below the regulation value. REQ141. The generated request signal U REQ The period of 141 can vary depending on load conditions. For example, under full load, the request signal U... REQ The period of 141 will be relative to the request signal U under light load or no load conditions. REQ The period of 141 is shorter.

[0040] To detect and prevent energy transfer from the secondary winding to the primary winding under light or no-load conditions, the anti-discharge circuit 134 is coupled to receive the request signal U. REQ 141 and generate an enable signal U ESR 145 controls the enable switch 109. The enable switch 109 can also be called a prevent switch. Enable signal U ESR 145 can also be called a prevent signal, which prevents the secondary control signal from controlling the SR switch by controlling the prevent switch. When the enable signal U... ESR When logic 145 is high, enable switch 109 closes and the secondary control signal U... SR 140 can control SR switch 114. When the enable signal U... ESR When logic 145 is low, enable switch 109 is turned off and secondary control signal U is prevented from being activated. SR 140 turns on SR switch 114. The anti-discharge circuit 134 responds to the request signal U. REQ An enable signal U is generated when the period of 141 is greater than the first timing threshold. ESR The logic is low at 145, and an enable signal U is generated in response to a request signal period less than the second timing threshold. ESR Logic high 145. In one embodiment, the first timing threshold can be in the range of 1 millisecond. In one embodiment, the second timing threshold can be in the range of 2 milliseconds.

[0041] If in Figure 2 As explained in the text, preventing the SR switch 114 from being turned on eliminates the capacitance C. P1 127 can cause a drain voltage V D 143 temporarily drops below ground level.

[0042] Figure 2 An embodiment of a power converter according to the teachings of this disclosure is illustrated, wherein the parasitic capacitance of the power switch discharges due to the shutdown of the synchronous rectifier. It should be understood that... Figure 2 The signal mentioned could be Figure 1 One embodiment of the signal, and the similarly named and numbered elements mentioned below are coupled and function in a manner similar to that described above.

[0043] Example power converter 200 illustrates the output capacitor C of power switch S1 212. P1 The discharge of capacitor 227 can occur under light load or no load conditions. During light load or no load conditions, the clamped capacitor C... CL 222 is not fully charged and can cause improper operation of the entire power converter 200. In one embodiment, clamping capacitor C CL 222 discharges to zero volts. The effect is that after power switch S1 212 is turned off, most of the energy is instead used to clamp capacitor C. CL 222 charges instead of being transferred from the primary winding 108 to the secondary winding 210. As a result, if the change in the polarity of the voltage across the secondary winding 210 is not detected, the second controller 221 may be unable to turn on the SR switch 214.

[0044] In another embodiment, clamping capacitor C CL 222 can have a voltage, but not high enough for normal operation. After power switch S1 212 is turned off, some energy is used to clamp capacitor C. CL 222 is charged, and most of the energy is transferred from the primary winding 208 to the secondary winding 210. The second controller correctly detects the polarity of the voltage across the secondary winding 210. The second controller 221 outputs a secondary control signal U during the minimum on-time. SR 240. When energy is transferred, the output capacitor C... O 216 passes through the secondary current I when SR switch 214 is turned on. S 248 is charged. Due to the minimum on-time of SR switch 214, with the secondary current I... S 248 decreases, secondary current I S 248 can reach negative values ​​and the output capacitor C O 216 will begin discharging and charging the secondary winding 210. When SR switch 214 is turned off, energy is transferred from the secondary winding 210 back to the primary winding 208. Discharge current I DIS 256 represents the drain voltage V D 156. Why is the parasitic capacitance C of power switch S1 212 affected? P1 227 discharges and can briefly drop to zero. The second controller 221 is designed to disallow the secondary control signal U. SR 240 responds to request signal U REQ 241. The SR switch 214 is controlled to prevent the discharge of the parasitic capacitance of the power switch caused by the minimum on-time of the SR switch 214.

[0045] Figure 3A timing diagram illustrating the teachings of this disclosure is shown, illustrating the secondary control signal, clamp voltage, drain voltage, primary current in the primary winding, and secondary current. It should be understood that... Figure 3 The signal mentioned could be Figure 1 One embodiment of the signal, and the similarly named and numbered elements mentioned below are coupled and function in a manner similar to that described above.

[0046] The first timing diagram illustrates the secondary control signal U. SR 340. The second timing diagram illustrates the clamping voltage V. CL 335. The third timing diagram illustrates the drain voltage V. D 343. The fourth timing diagram illustrates the primary current I. P 349. The fifth timing diagram illustrates the secondary current I. S 348 Enable Signal U CE 468.

[0047] exist Figure 3 In this embodiment, the power converter is under light load or no load conditions. Before time t1, the power switch is turned off, causing the drain voltage V... D 343 is a non-zero value. Clamping voltage V CL 336 is a non-zero value and decreases linearly. Secondary control signal U SR 340 is a logic low. Primary current I P 349 is zero because energy is transferred to the secondary winding. Secondary current I S 348 is zero.

[0048] At time t1, the power switch is turned on, as indicated by the drain voltage V at zero. D The secondary control signal U is marked as 343. SR 340 is a logic low because the SR switch is off. Primary current I P The voltage starts to rise at 349 because the primary winding is being charged. Clamping voltage V CL 336 at zero volts. Secondary current I S 348 is at zero.

[0049] At time t2, the power switch is turned off, as indicated by the non-zero drain voltage V. D As indicated by 343. Clamping capacitor voltage V CL 336 rises from zero to a non-zero value. As previously mentioned, the second controller did not detect a change in the polarity of the voltage across the secondary winding, and the secondary control signal U... SR 340 did not transition to logic high. Therefore, the secondary current I... S 348 is zero.

[0050] At time t3, the power switch is turned on, as indicated by the drain voltage V at zero. D The secondary control signal U is marked as 343. SR 340 is a logic low because the SR switch is off. Primary current I P The voltage starts to rise at 349 because the primary winding is being charged. Clamping voltage V CL 336 is at a non-zero value. Secondary current I S 348 is at zero.

[0051] At time t4, the power switch is turned off, as indicated by the drain voltage V. D The sharp increase marked in 343. Clamping voltage V CL 336 rises due to the drain voltage charging the clamping capacitor. Primary current I P 349 becomes zero because energy is transferred from the primary winding to the secondary winding. Secondary current I S 348 rose.

[0052] At time t5, the drain voltage V DS 343 is a non-zero value with zero slope. Secondary control signal U SR 340 transitions to logic high, which activates the synchronous rectifier. Secondary current I... S 348 begins to decrease towards zero. Clamping voltage V CL 336 is a non-zero value. Primary current I P 349 is zero.

[0053] At time t6, the secondary current I S 348 is a negative value. The output capacitor begins to discharge and charges the secondary winding. Secondary control signal U SR A transition from logic low to 340 can cause the parasitic capacitance of the power switch to discharge. Primary current I P 349 is zero. Clamping voltage V CL 336 is a non-zero value.

[0054] At the time intervals between t6 and t7, the drain voltage V D 343 drops to zero – caused by energy transfer from the secondary winding to the primary winding. Secondary control signal U SR 340 is logic low. Clamp voltage V CL 336 is a non-zero value. Primary current I P 349 is zero. Secondary current I S 348 is a negative value.

[0055] At time t7, the drain voltage V D 343 rises sharply. Clamping voltage VCL 336 is a non-zero value. Secondary control signal U SR 340 is a logic low. Primary current I P 349 is zero. Secondary current I S 348 is zero.

[0056] After time t7, the secondary control signal U SR 340 is logic low. Clamp voltage V CL 336 decreases linearly. Drain voltage V D 343 oscillates, but above zero. Primary current I P 349 is zero. Secondary current I S 348 is zero.

[0057] Figure 4 Examples of teachings based on this disclosure are provided. Figure 1 An embodiment of the disable circuit shown is illustrated. It should be understood that... Figure 4 The signal mentioned could be Figure 1 One embodiment of the signal, and the similarly named and numbered elements mentioned below are coupled and function in a manner similar to that described above.

[0058] The anti-discharge circuit 434 is coupled to receive the request signal U. REQ 441 and generate an enable signal U ESR 445 controls the enable switch, which allows the secondary control signal to control the SR switch. The discharge prevention circuit 434 determines the request signal U. REQ Whether the period of 441 is greater than a timing threshold, which indicates whether the power converter is under light load or no load conditions, is checked. The discharge prevention circuit 434 disables the enable switch until the request signal U is received. REQ Continuous operation of 441 below a second time threshold indicates that the power converter is no longer under light load or no load conditions. The anti-discharge circuit 434 includes a state machine 450, a first timer 451, and a second timer 452.

[0059] The first timer 451 is coupled to receive the request signal U. REQ 441 and in response to request signal U REQ The period of timer 441 is greater than the time threshold of the first timer 451, thus generating a light load signal ULL 453. The second timer 452 is coupled to receive the request signal U. REQ 441 and in response to request signal U REQ The period of 441 is less than the second time threshold, thus generating an inverted light load signal. 455. State machine 450 is coupled to receive request signal U.REQ 441. Light load signal ULL 453. 453. Inverted light load signal 455, and generate an enable signal U. ESR 445. State machine 450 includes multiple states to determine whether the enable switch is open or closed. The default state of the state machine is the normal operation state. The second state is the light load operation state, during which the enable signal is in the first state. In one embodiment, the first state of the enable signal may be logic low. The third state is the reset count state. The fourth state is the detection state. The explanation of each state is described below.

[0060] During operation, the default state of state machine 450 is the normal operating state. State machine 450 is configured to respond to inverted light load signals. 455 remains in normal operating condition. Therefore, state machine 450 generates an enable signal U. ESR 445's second state. In one embodiment, the enable signal U ESR The second state of the 445 can be logic high. The first state of the ULL453 for the light load signal can be logic low. Inverted light load signal. The first state of the 455 timer is logic high. In normal operation, the enable switch is closed, which allows the secondary control signal to control the SR switch.

[0061] State machine 450 is further configured to transition to a light-load operating state in response to a second state of the light-load signal ULL 453. The second state of the light-load signal ULL 453 can be logic high. Enable signal U... ESR The second state of the 445 can be logic low. Inverted light load signal. The second state of the 455 can be logic low. Secondary control signals are not allowed to control the SR switch.

[0062] State machine 450 is further configured to transition from a light-load operating state to a reset-counting state, during which it responds to the light-load signal ULL 453 and the request signal U. REQ 441. The internal counter signal (not shown) of state machine 450 is set to zero. Afterwards, state machine 450 transitions back to the light load operating state. State machine 450 can also respond to an inverted light load signal. 455 and request signal U REQ 541 then transitions to the detection state. In the detection state, the enable signal U ESR445 can be logic low. The count signal is incremented and checked against a count threshold. If the count signal equals the count threshold, state machine 450 is configured to transition to normal operation mode. If the count signal does not equal the count threshold, state machine 450 transitions back to light load operation state. The count threshold represents a series of events where the period of the detection request signal is less than a second time threshold, providing hysteresis to prevent false triggering of the enable switch when the power converter may still be under light load or no load conditions.

[0063] When the counting signal is not equal to the counting threshold, state machine 450 generates an enable signal U. ESR The first state of 445. Therefore, the enable signal U ESR 445 can be a logic low. The enable switch is off, and secondary control signals are not allowed to control the SR switch.

[0064] When the counting signal equals the counting threshold, state machine 450 transitions to the normal operating state and generates an enable signal U. ESR The second state of 445. Enable signal U ESR 445 is a logic high. The enable switch is closed, and secondary control signals are not allowed to control the SR switch.

[0065] Figure 5 Examples of teachings based on this disclosure are provided. Figure 4 An embodiment of the state machine diagram for an anti-discharge circuit. It should be understood that... Figure 5 The signal mentioned may be an embodiment of any of the signals in the previous figures, and the similarly named and numbered elements mentioned below are coupled and function in a manner similar to that described above.

[0066] The state machine 500 diagram includes a normal operation state 557, a light load operation state 558, a reset count state 559, and a detection state 560. The state machine 500 is configured to respond to a request signal, a light load signal ULL 553, a count signal UCOUNT 554, and an inverted light load signal. 555 transitions to various states. In normal operation, the enable signal U ESR The logic signal is high and the counting signal UCOUNT 554 is low, and the enable switch is closed to allow the secondary control signal to turn on the synchronous rectifier. This is only necessary for the inverted light load signal. 555 is logic high; state machine 500 remains in normal operating state. 557 is an inverted light load signal. 555 indicates that the period of the request signal is below a second time threshold representing that the power converter is not under light load or no load conditions.

[0067] State machine 500 is configured to transition to light-load operation state 558 in response to light-load signal ULL 553. Light-load signal ULL 553 is in response to request signal U... REQ The period of 541 is greater than the timing threshold indicating whether the power converter is under light load or no load conditions. In the light load operation state 558, the enable signal U... ESR It's illogical.

[0068] State machine 500 is configured to respond to light load signal ULL 553 and request signal U REQ 541 then transitions to the reset count state 559. In the reset count state, the count signal UCOUNT 554 is set to zero. State machine 500 is configured to transition back to the light load operation state 559.

[0069] State machine 500 is configured to respond to an inverted light load signal. 555 and request signal U REQ 541 The state transitions from the light load operation state 558 to the detection state 560. In the detection state 560, the enable signal can be logic low. The counter signal UCOUNT 554 is incremented. If the counter signal UCOUNT 554 equals the counting threshold 556, the state machine 500 transitions to the normal operation state 557. If the counter signal UCOUNT 554 does not equal the counting threshold 556, the state machine 500 transitions to the light load operation state 558. As previously mentioned, if the light load signal ULL 4553 and the request signal U are received in the light load operation state 558... REQ 543, state machine 500 transitions to reset count state 559, where the count is reset to zero.

[0070] Figure 6 An example flowchart illustrating the teachings of this disclosure is provided, illustrating an embodiment in which an enable switch is controlled in response to a request signal to allow a secondary control signal to control a synchronous rectifier. The order in which some or all of the process blocks appear in process 400 should not be considered limiting. Rather, those skilled in the art who benefit from this disclosure will understand that some of the process blocks can be performed in a variety of orders not illustrated, or even in parallel.

[0071] Process 600 begins at start block 601 and transitions to decision block 602. At decision block 603, the discharge prevention circuit determines whether the request signal is greater than a timing threshold representing whether the power converter is under light or no-load conditions. If so, process 600 proceeds to block 603. At block 603, the secondary control signal is not allowed to control the SR switch because the enable switch is off, disabling control of the SR switch. The count signal is set to zero. If the condition is not true, process 600 proceeds to decision block 604.

[0072] At decision block 604, the anti-discharge circuit determines whether the period of the request signal is less than the timing threshold. If the condition is not true, the count is reset and process 600 loops back to decision block 602. The SR switch remains disabled. If the condition is true, process 600 proceeds to process block 606. At process block 606, the count signal is incremented. Process 600 proceeds to decision block 607. At decision block 607, the anti-discharge circuit determines whether the count signal is equal to the counting threshold. If the condition is not true, process 600 loops back to decision block 602. If the condition is true, process 600 proceeds to decision block 608. At decision block 608, the enable switch is enabled, which allows the secondary control signal to control the SR switch. The power converter is now in normal operation. Process 600 transitions back to decision block 602.

[0073] The above description of the illustrative embodiments of the invention, including those described in the abstract, is not intended to be exhaustive or to limit the precise forms disclosed. Although specific embodiments and examples of the invention have been described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the invention. Indeed, it should be understood that specific examples of voltage, current, frequency, power range values, time, etc., are provided for illustrative purposes, and other values ​​may be used in other embodiments and examples according to the teachings of the invention.

[0074] Although the invention is defined in the claims, it should be understood that the invention may be defined alternatively according to the following embodiments:

[0075] Example 1: A power converter includes: an energy transfer element coupled between an input and an output of the power converter; a power switch coupled to the energy transfer element; an active clamping switch coupled to the energy transfer element and the power switch; a first controller coupled to the active clamping switch and the power switch; and a second controller configured to control a synchronous rectifier switch; the second controller is further configured to generate a request signal in response to the output of the power converter being below a threshold, the second controller including: a request control circuit configured to generate the request signal, the request... The control circuit is further configured to generate a secondary control signal to control the synchronous rectifier switch; and an anti-discharge circuit configured to prevent the parasitic capacitance of the power switch from discharging due to the switching on of the synchronous rectifier switch, the anti-discharge circuit being further configured to generate a first state of an anti-discharge signal to disable the control of the synchronous rectifier switch by the secondary control signal when the period of the request signal is greater than a first time threshold, and the anti-discharge circuit being further configured to generate a second state of the anti-discharge signal to enable the secondary control signal to control the synchronous rectifier switch when the period of the request signal is less than a second time threshold.

[0076] Example 2: According to the power converter of Example 1, the second controller includes a prevent switch coupled to receive the prevent signal to prevent the discharge of the parasitic capacitance of the power switch caused by the turn-on of the synchronous rectifier switch. The prevent switch is further coupled to receive the prevent signal to enable the secondary control signal to control the synchronous rectifier switch when the period of the request signal is less than a second time threshold.

[0077] Example 3: According to any of the power converters in the preceding embodiments, the anti-discharge circuit includes: a first timer circuit coupled to generate a light load signal in response to the period of the request signal being greater than a first time threshold; a second timer circuit coupled to generate an inverted light load signal in response to the period of the request signal being less than the second time threshold; and an anti-discharge state machine configured to generate the anti-discharge signal according to a plurality of anti-discharge states in response to the request signal, the light load signal, and the inverted light load signal.

[0078] Example 4: According to any of the power converters described in the preceding examples, the plurality of anti-discharge states include: a normal operation state, during which the anti-discharge signal is in a first state, wherein the normal operation state is a default state; a light load operation state, during which the anti-discharge signal is in a second state; and a detection state, during which a count signal is incremented and the anti-discharge state machine transitions to the normal operation state when the count signal equals a count threshold.

[0079] Example 5: According to any of the power converters described in the preceding examples, the anti-discharge state machine is further configured to transition from the normal operating state to the light load operating state in response to the light load signal.

[0080] Example 6: According to any of the power converters described in the preceding embodiments, the anti-discharge state machine is further configured to transition from the light load operating state to a reset count state in response to the light load signal and the request signal, wherein during the reset count state, the count signal is set to zero and the anti-discharge state machine transitions back to the light load operating state.

[0081] Example 7: According to any of the power converters described in the preceding examples, the anti-discharge state machine is further configured to remain in the normal operating state in response to the inverted light load signal.

[0082] Example 8: According to any of the power converters described in the preceding examples, the anti-discharge state machine is further configured to transition to the detection state in response to the inverted light load signal and the request signal, wherein during the detection state, the count signal is incremented and the anti-discharge state machine transitions to the light load operation state in response to the count signal not being equal to the count threshold.

[0083] Example 9: According to any of the power converters described in the preceding examples, the anti-discharge state machine is further configured to transition to the normal operating state in response to the counting signal being equal to the counting threshold.

[0084] Example 10: A power converter according to any of the preceding embodiments: an adjustment control circuit configured to generate a drive signal in response to the request signal to transfer energy from the input of the power converter to the output of the power converter; and a clamping control circuit configured to control an active clamping switch to inject charge stored in a clamping capacitor into an energy transfer element to discharge the parasitic capacitance of the power switch into the energy transfer element before the power switch is turned on.

[0085] Example 11: A power converter according to any of the preceding examples, wherein the second controller is current isolated from the first controller.

[0086] Example 12: According to any of the preceding embodiments, the power converter wherein the switching on of the synchronous rectifier switch is configured to generate a negative secondary current in the secondary winding of the energy transfer element, wherein the switching off of the synchronous rectifier switch transfers energy from the secondary winding to the primary winding of the energy transfer element, causing the parasitic capacitance of the power switch to discharge.

[0087] Example 13: A method for controlling a power converter, comprising: receiving a request signal representing the output of the power converter; comparing the period of the request signal with a first time threshold; disabling an enable switch to prevent discharge of a parasitic capacitance discharger of a power switch caused by the on-state of a synchronous rectifier switch, and resetting a count, in response to the period of the request signal not being greater than the first time threshold; comparing the period of the request signal with a second time threshold, in response to the period of the request signal not being greater than the first time threshold; resetting the count, in response to the period of the request signal not being greater than the second time threshold; incrementing the count, in response to the period of the request signal being greater than the second time threshold; comparing the count with a count threshold; and enabling the enable switch to control the synchronous rectifier switch and resetting the count, in response to the count being equal to the count threshold.

[0088] Example 14: A controller configured for use in a power converter, the controller comprising: a request control circuit coupled to receive a feedback signal representing the output of the power converter, the request control circuit being configured to generate a secondary control signal to control a secondary switch, the request control circuit being further configured to generate the request signal in response to the output of the power converter being below an output reference; a discharge prevention circuit coupled to receive the request signal, the discharge prevention circuit being configured to generate a first state of an enable signal in response to a period of the request signal being greater than a first time threshold, the discharge prevention circuit being further configured to generate a second state of the enable signal in response to a period of the request signal being less than a second time threshold; and an enable switch coupled to receive the enable signal, wherein the first state of the enable signal prevents the secondary control signal from enabling the secondary switch to prevent parasitic capacitance discharge of the power switch caused by the activation of the secondary switch, wherein the second state of the enable signal enables the secondary control signal to control the secondary switch.

[0089] Example 15: The controller according to Example 14, wherein the anti-discharge circuit includes: a first timer coupled to generate a light load signal in response to the period of the request signal being greater than a first time threshold; a second timer coupled to generate an inverted light load signal in response to the period of the request signal being less than the second time threshold; and an anti-discharge state machine configured to generate the enable signal according to a plurality of anti-discharge states in response to the request signal, the light load signal, and the inverted light load signal.

[0090] Example 16: According to any of the controllers described in the preceding embodiments, the plurality of anti-discharge states include: a normal operation state, during which the enable signal is in the second state and the count signal is in the first state; a light load operation state, during which the enable signal is in the first state; and a detection state, during which the count signal is incremented and checked to be equal to a count threshold, wherein the anti-discharge state machine transitions to the normal operation state.

[0091] Example 17: According to any of the controllers described in the preceding examples, the anti-discharge state machine is further configured to transition from the normal operating state to the light-load operating state in response to the light-load signal.

[0092] Example 18: According to any of the controllers described in the preceding examples, the anti-discharge state machine is further configured to transition from the light-load operating state to a reset count state, during which the count signal is set to zero, wherein the anti-discharge state machine transitions back to the light-load operating state.

[0093] Example 19: According to any of the controllers described in the preceding examples, the anti-discharge state machine is further configured to remain in the normal operating state in response to the reverse light load signal.

[0094] Example 20: According to any of the controllers described in the preceding embodiments, the anti-discharge state machine is further configured to transition from the light load operating state to the detection state in response to the inverted light load signal and the request signal, wherein during the detection state, the count signal is incremented, and the anti-discharge state machine transitions to the light load operating state in response to the count signal not being equal to the count threshold.

[0095] Example 21: According to any of the controllers described in the preceding embodiments, wherein the anti-discharge state machine is configured to transition to the normal operating state in response to the counting signal being equal to the counting threshold.

[0096] Example 22: A power converter includes: an energy transfer element coupled between an input and an output of the power converter; a power switch coupled to the energy transfer element, the power switch being configured to control the transfer of energy from the input to the output of the power converter; an active clamping switch coupled to the energy transfer element and the power switch; a first controller coupled to the active clamping switch and the power switch; and a second controller configured to control a secondary switch, the second controller being further configured to respond to the output of the power converter. The second controller generates a request signal when the period of the request signal is below a threshold value. The second controller includes: a request control circuit configured to generate the request signal, the request control circuit further configured to generate a secondary control signal to control the secondary switch; and a prevent switch coupled to prevent control of the secondary switch via the secondary control signal, the prevent switch being coupled to prevent energy transfer from the output of the power converter to the power switch caused by the activation of the secondary switch, the prevent switch being further coupled to enable the secondary control signal to control the secondary switch when the period of the request signal is less than a second time threshold value.

[0097] Example 23: According to the power converter of Example 22, wherein the second controller further includes an anti-discharge circuit, the anti-discharge circuit being configured to generate a first state of an anti-discharge signal to prevent the transfer of energy from the output of the power converter to the power switch caused by the activation of the secondary switch when the period of the request signal is greater than a first time threshold, the anti-discharge circuit being further configured to generate a second state of the anti-discharge signal to enable the secondary control signal to control the secondary switch when the period of the request signal is less than the second time threshold.

[0098] Example 24: According to any of the power converters described in the preceding examples, the anti-discharge circuit is coupled to the anti-discharge switch, and the anti-discharge circuit is further configured to control the anti-discharge switch in response to the request signal.

[0099] Example 25: A power converter according to any of the preceding embodiments, wherein the anti-discharge circuit includes: a first timer coupled to generate a light load signal in response to the period of the request signal being greater than a first time threshold; a second timer coupled to generate an inverted light load signal in response to the period of the request signal being less than the second time threshold; and an anti-discharge state machine configured to generate the anti-discharge signal according to a plurality of anti-discharge states in response to the request signal, the light load signal, and the inverted light load signal.

[0100] Example 26: According to any of the preceding embodiments, the power converter wherein the plurality of anti-discharge states include: a normal operation state, during which the anti-discharge signal is in the second state and the counting signal is in the first state; a light load operation state, during which the anti-discharge signal is in the first state; and a detection state, during which the counting signal is incremented and transitions to the normal operation state when the counting signal equals a counting threshold.

[0101] Example 27: According to any of the power converters described in the preceding examples, the anti-discharge state machine is further configured to transition to the light load operating state in response to the light load signal.

[0102] Example 28: A power converter according to any of the preceding examples, wherein the light load operating state transitions to a reset counting state, during which the counting signal is set to zero, and wherein the anti-discharge state machine transitions back to the light load operating state.

[0103] Example 29: A power converter according to any of the preceding examples, wherein the anti-discharge state machine is configured to remain in the normal operating state in response to the inverted light load signal.

[0104] Example 30: According to any of the power converters described in the preceding embodiments, the anti-discharge state machine is further configured to transition from the light load operating state to the detection state in response to the inverted light load signal and the request signal, wherein during the detection state, the count signal is incremented and the count signal is compared with the count threshold, wherein the anti-discharge state machine transitions to the light load operating state in response to the count signal not being equal to the count threshold.

[0105] Example 31: According to any of the power converters described in the preceding examples, the anti-discharge state machine is further configured to transition to the normal operating state in response to the counting signal being equal to the counting threshold.

Claims

1. A power converter comprising: an energy transfer element coupled between an input of the power converter and an output of the power converter; a power switch coupled to the energy transfer element; an active clamp switch coupled to the energy transfer element and the power switch; a first controller coupled to the active clamp switch and the power switch; and a second controller configured to control a synchronous rectifier switch, the second controller further configured to generate a request signal in response to the output of the power converter being below a threshold, the second controller comprising: a request control circuit configured to generate the request signal, the request control circuit further configured to generate a secondary control signal to control the synchronous rectifier switch; and a prevent discharge circuit configured to prevent a discharge of a parasitic capacitance of the power switch caused by a turn-on of the synchronous rectifier switch, the prevent discharge circuit further configured to generate a first state of a prevent signal to disable the secondary control signal from controlling the synchronous rectifier switch when a period of the request signal is greater than a first time threshold, the prevent discharge circuit further configured to generate a second state of the prevent signal to enable the secondary control signal to control the synchronous rectifier switch when the period of the request signal is less than a second time threshold, wherein the prevent discharge circuit comprises: a first timer circuit coupled to generate a light load signal in response to the period of the request signal being greater than the first time threshold; a second timer circuit coupled to generate an inverted light load signal in response to the period of the request signal being less than the second time threshold; and a prevent discharge state machine configured to generate the prevent signal from a plurality of prevent discharge states in response to the request signal, the light load signal, and the inverted light load signal, wherein the plurality of prevent discharge states comprises: a normal operation state during which the prevent signal is in a second state, wherein the normal operation state is a default state; a light load operation state during which the prevent signal is in a first state; and a detection state during which a count signal is incremented and the prevent discharge state machine transitions to the normal operation state when the count signal is equal to a count threshold.

2. The power converter of claim 1, the second controller comprising a prevent switch coupled to receive the prevent signal to prevent the discharge of the parasitic capacitance of the power switch caused by the turn-on of the synchronous rectifier switch, the prevent switch further coupled to receive the prevent signal to enable the secondary control signal to control the synchronous rectifier switch when the period of the request signal is less than a second time threshold.

3. The power converter of claim 1, the prevent discharge state machine further configured to transition from the normal operation state to the light load operation state in response to the light load signal. ​ 4. The power converter of claim 3, the brown-out state machine further configured to transition from the light load operating state to a reset count state in response to the light load signal and the request signal, wherein during the reset count state the count signal is set to zero and the brown-out state machine transitions back to the light load operating state.

5. The power converter of claim 1, the brown-out state machine further configured to remain in the normal operating state in response to the inverted light load signal.

6. The power converter of claim 3, the brown-out state machine further configured to transition to the detect state in response to the inverted light load signal and the request signal, wherein during the detect state the count signal is incremented and the brown-out state machine transitions to the light load operating state in response to the count signal not equaling the count threshold.

7. The power converter of claim 1, the first controller comprising: a regulation control circuit configured to generate a drive signal to transfer energy from the input of the power converter to the output of the power converter in response to the request signal; and a clamp control circuit configured to control an active clamp switch to inject stored charge in a clamp capacitor into an energy transfer element to discharge a parasitic capacitance of the power switch into the energy transfer element prior to the power switch turning on.

8. The power converter of claim 1, wherein the second controller is galvanically isolated from the first controller, and wherein the first controller is configured to control switching of the power switch in response to the request signal.

9. The power converter of claim 2, wherein a turn-on of the synchronous rectifier switch is configured to generate a negative secondary current in a secondary winding of the energy transfer element, wherein a turn-off of the synchronous rectifier switch transfers energy from the secondary winding to a primary winding of the energy transfer element such that the parasitic capacitance of the power switch is discharged.

10. A method for controlling a flyback power converter, the flyback power converter comprising a synchronous rectifier switch that is turned on to charge an output capacitor once a power switch is turned off, the method comprising: receiving a request signal representative of a request to turn on the power switch, the request signal generated when an output of the flyback power converter falls below a regulation value; comparing a period of the request signal to a first time threshold; in response to the period of the request signal being greater than the first time threshold, disabling an enable switch to prevent a turn-on of the synchronous rectifier switch from causing a discharge of a parasitic capacitance of the power switch to discharge, and resetting a count; in response to the period of the request signal not being greater than the first time threshold, comparing the period of the request signal to a second time threshold; in response to the period of the request signal not being greater than the second time threshold, resetting the count; incrementing the count in response to the period of the request signal being greater than the second time threshold; comparing the count to a count threshold; and enabling the enable switch to control the synchronous rectifier switch and resetting the count in response to the count being equal to the count threshold.

11. A controller configured for use in a power converter, the controller comprising: a request control circuit coupled to receive a feedback signal representative of an output of the power converter, the request control circuit configured to generate a secondary control signal to control a secondary switch, the request control circuit further configured to generate a request signal in response to the output of the power converter being below an output reference; a shoot through prevention circuit coupled to receive the request signal, the shoot through prevention circuit configured to generate a first state of an enable signal in response to a period of the request signal being greater than a first time threshold, the shoot through prevention circuit further configured to generate a second state of the enable signal in response to the period of the request signal being less than a second time threshold, wherein the shoot through prevention circuit comprises: a first timer coupled to generate a light load signal in response to the period of the request signal being greater than the first time threshold, a second timer coupled to generate an inverted light load signal in response to the period of the request signal being less than the second time threshold, and a shoot through prevention state machine configured to generate the enable signal from a plurality of shoot through prevention states in response to the request signal, the light load signal, and the inverted light load signal; and an enable switch coupled to receive the enable signal, wherein the first state of the enable signal prevents the secondary control signal from enabling the secondary switch to prevent discharge of a parasitic capacitance of a power switch caused by a turn on of the secondary switch, wherein the second state of the enable signal enables the secondary control signal to control the secondary switch, wherein the plurality of shoot through prevention states comprises: a normal operation state during which the enable signal is in the second state and a count signal is in a first state, a light load operation state during which the enable signal is in the first state, and a detection state during which a count signal is incremented and checked to be equal to a count threshold, wherein the shoot through prevention state machine is configured to transition to the normal operation state in response to the count signal being equal to the count threshold.

12. The controller of claim 11, the shoot through prevention state machine further configured to transition from the normal operation state to the light load operation state in response to the light load signal.

13. The controller of claim 12, the shoot through prevention state machine further configured to transition from the light load operation state to a reset count state during which the count signal is set to zero, wherein the shoot through prevention state machine transitions back to the light load operation state.

14. The controller of claim 11, the prevent discharge state machine further configured to remain in the normal operation state in response to the inverted light load signal.

15. The controller of claim 12, the prevent discharge state machine further configured to transition from the light load operation state to the detect state in response to the inverted light load signal and the request signal, wherein during the detect state, the count signal is incremented and the prevent discharge state machine transitions to the light load operation state in response to the count signal not equaling the count threshold.

16. A power converter comprising: an energy transfer element coupled between an input of the power converter and an output of the power converter; a power switch coupled to the energy transfer element, the power switch configured to control transfer of energy from the input of the power converter to the output of the power converter; an active clamp switch coupled to the energy transfer element and the power switch; a first controller coupled to the active clamp switch and the power switch; and a second controller configured to control a secondary switch, the second controller further configured to generate a request signal in response to the output of the power converter being below a threshold, the second controller comprising: a request control circuit configured to generate the request signal, the request control circuit further configured to generate a secondary control signal to control the secondary switch, a prevent switch coupled to block control of the secondary switch by the secondary control signal, the prevent switch coupled to prevent transfer of energy from the output of the power converter to the power switch caused by a turn on of the secondary switch, the prevent switch further coupled to enable the secondary control signal to control the secondary switch when a period of the request signal is less than a second time threshold, and a prevent discharge circuit configured to generate a first state of a prevent signal to prevent transfer of energy from the output of the power converter to the power switch caused by the turn on of the secondary switch when the period of the request signal is greater than a first time threshold, the prevent discharge circuit further configured to generate a second state of the prevent signal to enable the secondary control signal to control the secondary switch when the period of the request signal is less than the second time threshold, wherein the prevent discharge circuit comprises: a first timer coupled to generate a light load signal in response to the period of the request signal being greater than the first time threshold, a second timer coupled to generate an inverted light load signal in response to the period of the request signal being less than the second time threshold, and a prevent discharge state machine configured to generate the prevent signal from a plurality of prevent discharge states in response to the request signal, the light load signal, and the inverted light load signal, wherein the plurality of prevent discharge states comprises: ​ a normal operating state during which the prevent signal is in the second state and a count signal is in a first state; a light load operating state during which the prevent signal is in the first state; and a detection state during which the count signal is incremented, the normal operating state being entered when the count signal equals a count threshold.

17. The power converter of claim 16, the prevent discharge circuit coupled to the prevent switch, the prevent discharge circuit further configured to control the prevent switch in response to the request signal.

18. The power converter of claim 16, the prevent discharge state machine further configured to transition to the light load operating state in response to the light load signal.

19. The power converter of claim 18, wherein the light load operating state transitions to a reset count state during which the count signal is set to zero, wherein the prevent discharge state machine transitions back to the light load operating state.

20. The power converter of claim 16, wherein the prevent discharge state machine is configured to remain in the normal operating state in response to the inverted light load signal.

21. The power converter of claim 18, the prevent discharge state machine further configured to transition from the light load operating state to the detection state in response to the inverted light load signal and the request signal, wherein during the detection state the count signal is incremented and the count signal is compared to the count threshold, wherein the prevent discharge state machine transitions to the light load operating state in response to the count signal not equaling the count threshold.

22. The power converter of claim 21, wherein the first controller is configured to control switching of the power switch in response to the request signal.

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