Automated chip testing methods, systems, computer equipment, and storage media

Abstract

This invention relates to the field of computer technology and provides an automatic chip testing method, system, computer equipment, and storage medium. The method includes the following steps: planning the movement trajectory of probes, optical fibers, or wafer stage according to the distribution of the chips to be tested; testing the chips one by one according to the set movement trajectory and a testing strategy, and outputting the test results; the testing strategy is: calling the corresponding test program to test the current chip under test, while simultaneously acquiring the image information of the next chip under test; identifying the acquired image information of the next chip under test and determining whether the model of the next chip under test is the same as the model of the chip currently being tested; until all chips under test have been tested. The beneficial effects of this invention are: it can realize mixed testing of different models of products, greatly improving testing efficiency and reducing costs.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an automatic chip testing method, system, computer device, and storage medium. Background Technology

[0002] A chip, also known as a microcircuit, microchip, or integrated circuit, is a silicon wafer containing integrated circuits. It is very small and is a crucial component of electronic devices such as computers. Due to the intricate structure, complex manufacturing process, and cumbersome procedures involved in chip production, potential defects are inevitably left behind. This can prevent the manufactured chips from meeting standard requirements and lead to malfunctions at any time due to various reasons. Therefore, to ensure chip quality, chips are typically tested (including multiple tests such as electrical parameter measurements and functional tests) to separate good from defective products.

[0003] In existing technologies, testing is mostly done on individual chips. Furthermore, multiple different types of chips are produced together on the production line, but they need to be tested separately, resulting in low efficiency and high testing costs. Summary of the Invention

[0004] The purpose of this invention is to provide an automated chip testing method, system, computer device, and storage medium, aiming to solve the technical problems existing in the prior art as identified in the background art.

[0005] The present invention is implemented as follows: an automated chip testing method includes the following steps:

[0006] Based on the distribution of the chips to be tested, plan the movement trajectory of the probes, optical fibers, or the wafer stage;

[0007] The chip is tested according to the set motion trajectory and the test strategy, and the test results are output.

[0008] The testing strategy is as follows:

[0009] The corresponding test program is invoked to test the current chip under test, and image information of the next chip under test is also obtained.

[0010] The image information of the next chip under test is identified to determine whether the model of the next chip under test is the same as the model of the chip currently being tested.

[0011] When the model of the chip under test is the same as that of the next chip under test, the current test program is used to test the next chip under test directly. When the model of the chip under test is different from that of the next chip under test, after the current chip under test is tested, the test program corresponding to the next chip under test is switched to test.

[0012] This continues until all chips under test have been tested.

[0013] As a further aspect of the present invention: the step of planning the motion trajectory of the probe, optical fiber, or wafer stage according to the distribution of the chip to be tested specifically includes:

[0014] Acquire image information of the array chip and extract all chip information contained in the image information to calibrate the position of the chip information;

[0015] Project the image information after position calibration onto the coordinate system;

[0016] The motion trajectory of the probe, optical fiber, or wafer stage is planned based on the chip's position distribution in the coordinate system.

[0017] As a further aspect of the present invention: the step of identifying the image information of the next chip under test and determining whether the model of the next chip under test is the same as the model of the chip currently being tested specifically includes:

[0018] The image information of the next chip under test is acquired, and the image information of the next chip under test is cropped to retain the image of the feature region, which is the area on the chip surface where there are marks.

[0019] The image of the feature region is input into a preset image recognition model, and the image recognition result of the next chip under test is output to obtain the model of the next chip under test;

[0020] Determine whether the model of the next chip under test is the same as the model of the chip currently being tested.

[0021] As a further aspect of the present invention: the step of switching to the test program corresponding to the next chip under test after the current chip under test has been tested, when the model of the chip under test is different from that of the next chip under test, specifically includes:

[0022] When the model number of the chip under test is different from that of the next chip under test, obtain the model number information of the next chip under test;

[0023] The model information of the next chip under test is input into the pre-established model information and test program mapping model to obtain a test program that matches the next chip under test.

[0024] After the current chip under test is tested, switch to the test program corresponding to the next chip under test.

[0025] As a further aspect of the present invention: the step of testing the chip according to a set motion trajectory and a test strategy, and outputting the test results, specifically includes:

[0026] The chip is tested according to the set motion trajectory and the test strategy.

[0027] When the test result is Y, a pass mark is added to the coordinates used to characterize the corresponding chip position; when the test result is N, a fail mark is added to the coordinates used to characterize the corresponding chip position, and the coordinates containing the fail mark and the test result are added to the set to be processed.

[0028] After all chip tests are completed, the set of chips to be processed is output to the user.

[0029] Another objective of this invention is to provide an automated chip testing system, comprising:

[0030] The trajectory planning module is used to plan the motion trajectory of the probe, optical fiber, or wafer stage based on the distribution of the chip under test.

[0031] The testing module is used to test the chip according to the set motion trajectory and the test strategy, and output the test results.

[0032] The testing module includes:

[0033] The test execution unit is used to call the corresponding test program to test the current chip under test, and at the same time, it also acquires the image information of the next chip under test.

[0034] The identification and determination unit is used to identify the acquired image information of the next chip under test and determine whether the model of the next chip under test is the same as the model of the chip currently being tested; and

[0035] The program calling unit, when the model of the chip under test is the same as that of the next chip under test, directly uses the current test program to test the next chip under test; when the model of the chip under test is different from that of the next chip under test, after the current chip under test is tested, it switches to the test program corresponding to the next chip under test for testing; until all chips under test are tested.

[0036] Another objective of this invention is to provide a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the processor performs the steps of the automatic chip testing method.

[0037] Another objective of this invention is to provide a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform the steps of the automatic chip testing method.

[0038] Compared with the prior art, the beneficial effects of the present invention are: it calls the corresponding test program to test the current chip under test, and at the same time acquires the image information of the next chip under test. That is, a camera device can be mounted on the probe, optical fiber or wafer stage to achieve synchronous shooting, thereby acquiring the image information of the next chip under test, and thus realizing the model identification of the next chip under test, so as to call the corresponding test program in advance. This can greatly improve efficiency. In practical applications, it can also realize mixed testing of different models of products, greatly improving testing efficiency and reducing costs. Attached Figure Description

[0039] Figure 1 This is a flowchart of an automated chip testing method.

[0040] Figure 2 A flowchart for planning the motion trajectory of a probe, fiber optic cable, or substrate stage.

[0041] Figure 3 A flowchart for determining whether the model of the next chip under test is the same as the model of the chip currently being tested.

[0042] Figure 4 This is a flowchart illustrating how to switch to the test program corresponding to the next chip after the current chip under test has been tested.

[0043] Figure 5 A flowchart for testing the chip according to a set motion trajectory and test strategy, and outputting the test results.

[0044] Figure 6 This is a schematic diagram of an automated chip testing system.

[0045] Figure 7 This is a schematic diagram of the structure of a computer device. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0047] The specific implementation of the present invention will be described in detail below with reference to specific embodiments.

[0048] like Figure 1 The diagram shows a flowchart of an automated chip testing method according to an embodiment of the present invention, which includes the following steps:

[0049] S100 plans the movement trajectory of probes, optical fibers, or wafer stage according to the distribution of the chips to be tested.

[0050] S200 performs tests on the chip according to the set motion trajectory and test strategy, and outputs the test results.

[0051] The testing strategy is as follows:

[0052] S201 calls the corresponding test program to test the current chip under test, and at the same time obtains the image information of the next chip under test.

[0053] S202, the image information of the next chip under test is identified, and it is determined whether the model of the next chip under test is the same as the model of the chip currently being tested.

[0054] S203: When the model of the chip under test is the same as that of the next chip under test, the next chip under test is tested directly using the current test program. When the model of the chip under test is different from that of the next chip under test, after the current chip under test is tested, the test program corresponding to the next chip under test is switched to perform the test.

[0055] S204, until all chips under test have been tested.

[0056] In this embodiment of the invention, the chips under test are arranged in an array and then tested sequentially in a concentrated manner to improve the testing effect. In practical applications, image information of the array chips can be acquired using industrial CCD cameras or other methods; this embodiment does not impose specific limitations on this. The chips are tested sequentially according to the motion trajectory and testing strategy to achieve concentrated testing. In practical applications, the corresponding test program is invoked for the current chip under test, while simultaneously acquiring image information of the next chip under test. That is, a camera device can be mounted on the probe, optical fiber, or wafer stage to achieve synchronous shooting and acquire image information of the next chip under test, thereby enabling model identification of the next chip under test and facilitating the advance invocation of the corresponding test program. This greatly improves efficiency and, in practical applications, allows for mixed testing of different product models, significantly improving testing efficiency and reducing costs.

[0057] like Figure 2 As shown, in a preferred embodiment of the present invention, the step of planning the motion trajectory of the probe, optical fiber, or wafer stage according to the distribution of the chip under test specifically includes:

[0058] S101, acquire image information of the array chip, and extract all chip information contained in the image information to calibrate the position of the chip information.

[0059] S102, Project the image information after position calibration onto the coordinate system.

[0060] S103 plans the motion trajectory of the probe, optical fiber, or wafer stage based on the chip's position distribution in the coordinate system.

[0061] In this embodiment of the invention, the chip can be identified by the unique pins on the chip surface or by the production marking information on the chip surface. After the chip is identified, each chip is marked, so that the image information contains multiple chip marks. Then the image information is projected onto a matching coordinate system. The origin of the coordinate system can correspond to a certain corner of the image information. In this way, each chip mark in the image information will get a unique coordinate, and the position information of each chip can be represented by coordinates.

[0062] After obtaining the position information of each chip, the motion trajectory of the probe, fiber optic cable, or wafer stage can be planned. In practical applications, the motion trajectory should preferably be the shortest path that can cover the coordinates of all chips. This embodiment does not impose specific limitations here.

[0063] like Figure 3 As shown, in another preferred embodiment of the present invention, the step of identifying the image information of the next chip under test and determining whether the model of the next chip under test is the same as the model of the chip currently being tested specifically includes:

[0064] S2021, acquire the image information of the next chip under test, and perform cropping processing on the image information of the next chip under test to retain the image of the feature region, which is the area on the chip surface where there are marks.

[0065] S2022, the image of the feature region is input into a preset image recognition model, and the image recognition result of the next chip under test is output to obtain the model of the next chip under test.

[0066] S2023, determine whether the model of the next chip under test is the same as the model of the chip under test currently being tested.

[0067] In this embodiment of the invention, the purpose of cropping the image information of the next chip under test is to retain only the image of the feature region. The feature region is the area on the chip surface with markings, such as production batch number, serial number or model number, etc. Then, the recognition is completed by the image recognition model. The image recognition model here can be implemented based on existing methods such as convolutional neural network, SVM classifier, etc. This embodiment will not describe it in detail.

[0068] like Figure 4 As shown, in another preferred embodiment of the present invention, the step of switching to the test program corresponding to the next chip under test after the current chip under test has been tested, when the model of the chip under test is different from that of the next chip under test, specifically includes:

[0069] S2031, when the model of the chip under test is different from the model of the next chip under test, obtain the model information of the next chip under test;

[0070] S2032, input the model information of the next chip under test into the pre-established model information and test program mapping model to obtain a test program that matches the next chip under test;

[0071] S2033: After the current chip under test is tested, switch to the test program corresponding to the next chip under test for testing.

[0072] In this embodiment of the invention, the model of the next chip under test can be identified through the aforementioned image recognition model. After obtaining the model, the corresponding test program can be directly obtained through the model information and test program mapping model. Then, the test program corresponding to the next chip under test can be tested directly by calling the program.

[0073] like Figure 5 As shown, in another preferred embodiment of the present invention, the step of testing the chip according to the set motion trajectory and the test strategy, and outputting the test results, further includes:

[0074] The S300 performs tests on the chip according to the set motion trajectory and test strategy.

[0075] S400, when the test result is Y, add a pass mark to the coordinates used to characterize the corresponding chip position; when the test result is N, add a fail mark to the coordinates used to characterize the corresponding chip position, and add the coordinates containing the fail mark and the test result to the set to be processed.

[0076] After all chips have been tested, the S500 outputs the set to be processed to the user.

[0077] In this embodiment of the invention, Y represents a test passed or a test is normal, and N represents a test failed or a test is abnormal. The set of chips to be processed here needs to be sent to the user so that the user can further process and analyze the chips that failed the test.

[0078] like Figure 6 As shown, this embodiment of the invention also provides an automated chip testing system, including:

[0079] The trajectory planning module 100 is used to plan the motion trajectory of the probe, optical fiber, or wafer stage according to the distribution of the chip to be tested.

[0080] The test module 200 is used to test the chip according to the set motion trajectory and test strategy, and output the test results.

[0081] The test module 200 includes:

[0082] The test execution unit 201 is used to call the corresponding test program to test the current chip under test, and at the same time, it also obtains the image information of the next chip under test.

[0083] The identification and determination unit 202 is used to identify the acquired image information of the next chip under test and determine whether the model of the next chip under test is the same as the model of the chip currently being tested; and

[0084] The program calling unit 203, when the model of the chip under test is the same as the model of the next chip under test, directly uses the current test program to test the next chip under test; when the model of the chip under test is different from the model of the next chip under test, after the current chip under test is tested, it switches to the test program corresponding to the next chip under test for testing; until all chips under test are tested.

[0085] In this embodiment of the invention, the chip is tested sequentially according to the motion trajectory and testing strategy to achieve centralized testing. In practical applications, the corresponding test program is called to test the current chip under test, and image information of the next chip under test is also acquired. That is, a camera device can be mounted on the probe, optical fiber, or wafer stage to achieve synchronous shooting and acquire image information of the next chip under test, thereby realizing the model identification of the next chip under test, so as to call the corresponding test program in advance. This can greatly improve efficiency. In practical applications, it can also realize mixed testing of different models of products, greatly improving testing efficiency and reducing costs.

[0086] like Figure 7As shown, this embodiment of the invention also provides a computer device, including a memory and a processor. The memory stores a computer program, which, when executed by the processor, causes the processor to perform the following:

[0087] S100 plans the movement trajectory of probes, optical fibers, or wafer stage according to the distribution of the chips to be tested.

[0088] S200 performs tests on the chip according to the set motion trajectory and test strategy, and outputs the test results.

[0089] The testing strategy is as follows:

[0090] S201 calls the corresponding test program to test the current chip under test, and at the same time obtains the image information of the next chip under test.

[0091] S202, the image information of the next chip under test is identified, and it is determined whether the model of the next chip under test is the same as the model of the chip currently being tested.

[0092] S203: When the model of the chip under test is the same as that of the next chip under test, the next chip under test is tested directly using the current test program. When the model of the chip under test is different from that of the next chip under test, after the current chip under test is tested, the test program corresponding to the next chip under test is switched to perform the test.

[0093] S204, until all chips under test have been tested.

[0094] This invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, causes the processor to perform:

[0095] S100 plans the movement trajectory of probes, optical fibers, or wafer stage according to the distribution of the chips to be tested.

[0096] S200 performs tests on the chip according to the set motion trajectory and test strategy, and outputs the test results.

[0097] The testing strategy is as follows:

[0098] S201 calls the corresponding test program to test the current chip under test, and at the same time obtains the image information of the next chip under test.

[0099] S202, the image information of the next chip under test is identified, and it is determined whether the model of the next chip under test is the same as the model of the chip currently being tested.

[0100] S203: When the model of the chip under test is the same as that of the next chip under test, the next chip under test is tested directly using the current test program. When the model of the chip under test is different from that of the next chip under test, after the current chip under test is tested, the test program corresponding to the next chip under test is switched to perform the test.

[0101] S204, until all chips under test have been tested.

[0102] It should be understood that although the steps in the flowcharts of the various embodiments of the present invention are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the various embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0103] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments described above. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0104] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the disclosure in the specification and embodiments. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0105] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method of testing a chip automatically, characterized by, The method comprises the following steps: According to the distribution of the chips to be tested, the motion trajectory of the probe or optical fiber or chip supporting table is planned; According to the set motion trajectory, the chips are tested according to the test strategy, and the test results are outputted; The test strategy is: The corresponding test program of the current chip to be tested is called to test, and the image information of the next chip to be tested is also obtained; The image information of the next chip to be tested is obtained, and the image information of the next chip to be tested is cropped to retain the image of the feature area, and the feature area is the area with marks on the surface of the chip; The image of the feature area is inputted into a preset image recognition model to output the image recognition result of the next chip to be tested, so as to obtain the model of the next chip to be tested; It is judged whether the model of the next chip to be tested is the same as the model of the chip being tested; When the model of the chip to be tested is the same as the model of the next chip to be tested, the next chip to be tested is directly tested by using the current test program; When the model of the chip to be tested is different from the model of the next chip to be tested, the model information of the next chip to be tested is obtained; The model information of the next chip to be tested is inputted into a pre-established model of the mapping between the model information and the test program to obtain the test program matched with the next chip to be tested; After the current chip to be tested is tested, the test program corresponding to the next chip to be tested is switched to test; Until all the chips to be tested are tested; During the testing process: When the test result is Y, a pass mark is added to the coordinates representing the position of the corresponding chip, and when the test result is N, a fail mark is added to the coordinates representing the position of the corresponding chip, and the coordinates with the fail mark and the test result are added to a to-be-processed set; After all the chips are tested, the to-be-processed set is outputted to the user.

2. The method of claim 1, wherein The step of planning the motion trajectory of the probe or optical fiber or chip supporting table according to the distribution of the chips to be tested comprises the following steps: Image information of the array chip is obtained, and all chip information contained in the image information is extracted to calibrate the position of the chip information; The image information after the position calibration is projected into a coordinate system; The motion trajectory of the probe or optical fiber or chip supporting table is planned according to the position distribution of the chip in the coordinate system.

3. A chip automatic test system, characterized by, It comprises: A trajectory planning module for planning the motion trajectory of the probe or optical fiber or chip supporting table according to the distribution of the chips to be tested; A test module for testing the chips according to the set motion trajectory and the test strategy, and outputting the test results; The test module comprises: A test execution unit for calling the corresponding test program of the current chip to be tested to test, and also obtaining the image information of the next chip to be tested; An identification and judgment unit for identifying the obtained image information of the next chip to be tested, and judging whether the model of the next chip to be tested is the same as the model of the chip being tested; and The program calling unit directly tests the next chip under test with the current test program when the type of the chip under test is the same as the type of the next chip under test, and switches to the test program corresponding to the next chip under test to test the next chip under test after the test of the current chip under test is completed until all chips under test are tested.

4. A computer device, comprising: The chip automatic test method comprises a memory and a processor, the memory stores a computer program, and the computer program is executed by the processor to enable the processor to execute the steps of the chip automatic test method according to any one of claims 1 to 3.

5. A computer readable storage medium, characterized in that, The computer program is stored on the computer readable storage medium and is executed by the processor to enable the processor to execute the steps of the chip automatic test method according to any one of claims 1 to 3.

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