A multi-core inter-core real-time communication system and method

Abstract

The application discloses a multi-core inter-core real-time communication system and method, which comprises a hardware layer, a driver layer and a communication layer. Firstly, the hardware layer is used for managing and classifying a plurality of processors, and corresponding memory spaces are divided according to the classification results, and the shared memory is used to realize the access of the processors to the shared resources. Then, the driver layer is used for loading and managing an RPMsg driver program on a virtual hardware platform provided by the hardware layer, registering a driver device to provide data storage services, creating a driver component to provide data transmission services, and providing driver services for the communication layer through a driver calling interface. Finally, the communication layer is used for calling a driver interface function to manipulate an RPMsg driver module, realizing the receiving and transmitting operations of data, and establishing an inter-core logical connection through an RPMsg channel, so as to realize the inter-core communication of the multi-core. The inter-core communication technology based on the RPMsg channel is adopted, and a solution is provided for solving the parallel running and collaborative scheduling of the plurality of processors.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of embedded computers, and particularly relates to a multi-core inter-core real-time communication system and method. BACKGROUND

[0002] With the increasing requirements of computing speed and computing scale in various fields, the traditional single-core processor has been difficult to adapt to large-scale parallel operation. In order to expand the performance of the processor, the multi-core processor emerges as the times require. The multi-core processor allocates tasks to multiple computer cores through its superior processor architecture, and greatly improves the performance of the processor by fully utilizing the processor resources. However, with the increasing demand for real-time performance and parallelism in the application of the embedded field, the delay characteristics of the core cannot guarantee the real-time performance of the whole system, so it is urgent to study the real-time performance of the embedded multi-core system.

[0003] At present, the embedded multi-core processor system utilizes the multi-core characteristics to make different cores run different operating systems, thereby solving the integration requirements of parallelism, real-time performance and other specificities. Among them, the known multi-core inter-core communication methods mainly include two kinds:

[0004] The first one adopts the virtualization technology, that is, an independent software layer is added between the hardware platform and the operating system, so as to uniformly manage the CPU, memory and interrupt and the like, and abstract the virtual hardware resources and the standard access interface, so as to provide a virtual running environment for the operating system and its application running in the software layer, and make it cross-core communication with other systems in the form of a virtual machine. In actual application, the inter-core data interaction needs to be processed through the intermediate virtual machine, which will reduce the real-time performance of the system; at the same time, the virtual machine needs to be created with additional hardware resources to provide support, thereby increasing the overhead of system resources.

[0005] The second one adopts the shared memory mechanism based on the AMP architecture, that is, the position of the shared memory and the length of the communication message are statically configured, the shared memory is divided into a synchronous message buffer and an asynchronous message queue, and the operating systems complete the inter-core communication by reading and writing the shared memory and triggering the inter-core interrupt. Although this scheme can guarantee the real-time response of the communication, the length of the communication message is limited, and the flexibility is poor; in addition, different transmission information needs different driver programs and application programs to realize, and there is no unified transmission framework support, and the realization steps are relatively cumbersome. SUMMARY

[0006] In order to overcome the deficiencies of the above multi-core inter-core communication scheme, the application provides a multi-core inter-core real-time communication system and method, which provides a unified transmission framework for different transmission messages, and provides a driving service for efficient collaborative work between multi-core processors, thereby meeting the parallelism and real-time performance requirements of the system.

[0007] In order to achieve the above object, the application firstly provides a multi-core inter-core real-time communication system, which is characterized by comprising a hardware layer, a driver layer and a communication layer.

[0008] The hardware layer is provided with a main core system, a bare machine system and a shared memory module, wherein the main core system is used for executing non-real-time tasks, the bare machine system is used for processing real-time computing tasks, and the shared memory module is used for dividing memory space.

[0009] The driver layer is provided with a driver management module for loading an RPMsg driver program, registering a driver device and creating a driver component.

[0010] The communication layer is provided with a message sending module, a message receiving module and an RPMsg channel, wherein the message sending module is used for writing messages into a shared memory area and sending a software interrupt signal to a target processor, so as to realize message sending; the message receiving module is used for detecting a software interrupt signal, and when the software interrupt signal is detected, entering an interrupt processing function to read data in the shared memory area and clearing an interrupt flag, so as to complete message receiving and realize inter-core communication; and the RPMsg channel is used for establishing a logical connection between cores and providing inter-core data transmission services.

[0011] Optionally, the main core system comprises a plurality of processors running an operating system, and the executed non-real-time tasks include communication processing, complex calculation and human-computer interaction; the bare machine system comprises at least one processor running a bare machine program, and the processed real-time computing tasks include measurement, acquisition and control.

[0012] Optionally, the shared memory module divides the memory area into an operating system exclusive memory area, a shared memory area and a bare core exclusive area.

[0013] Optionally, the driver management module comprises an RPMsg driver loading unit, a driver device registration unit and a driver component creation unit, the RPMsg driver loading unit is connected with the driver device registration unit, the driver device registration unit is connected with the driver component creation unit, and wherein:

[0014] The RPMsg driver loading unit is used for loading a driver program based on an RPMsg protocol, and through manipulating the RPMsg driver, realizing data receiving and sending operations and completing inter-core interaction of the system;

[0015] The driver device registration unit is used for registering a virtualized driver device, managing a shared memory for inter-core data interaction and providing storage services for the RPMsg driver program;

[0016] The driving component creating unit is used to create an RPMsg channel and an RPMsg endpoint, the channel is identified by a text name and a local or target address, provides transmission service for inter-processor, the endpoint provides logical connection on the channel, and each endpoint has a unique source address and related callback function.

[0017] Optionally, the message sending module comprises a data writing unit and an interrupt triggering unit; the data writing unit is connected with the interrupt triggering unit, and the interrupt triggering unit is connected with the RPMsg channel.

[0018] The data writing unit is used to fill RPMsg header information and payload data according to RPMsg message format, and write the RPMsg message into the shared buffer.

[0019] The interrupt triggering unit is used to send a software interrupt signal to an interrupt controller, and notify a target processor to receive a message.

[0020] Optionally, the message receiving module comprises an interrupt detection unit and a data reading unit; the interrupt detection unit is connected with the RPMsg channel and the data reading unit.

[0021] The interrupt detection unit is used to detect whether an interrupt occurs in a current processor, if yes, enter an interrupt service function to process the interrupt, otherwise, continue to detect.

[0022] The data reading unit is used to read data from the shared buffer, release the memory, and send feedback to a sending end to complete communication.

[0023] Optionally, a hardware abstraction interface is arranged between the hardware layer and the driving layer, and a driving calling interface is arranged between the driving layer and the communication layer, wherein:

[0024] The hardware abstraction interface is used to hide hardware interface details of the hardware layer, and provide a virtual hardware platform for the driving layer.

[0025] The driving calling interface is a group of system calling functions provided by the driving layer for the communication layer, and is used to access and control the RPMsg device.

[0026] On the other hand, the application further provides a multi-core inter-processor real-time communication method, which adopts the multi-core inter-processor real-time communication system described above, and the key lies in comprising the following steps:

[0027] S1: the hardware layer manages and classifies a plurality of processors, divides memory space according to the situation of building an operating system on the processor, realizes access to shared resources by using a shared memory mode, and provides hardware support for the driving layer.

[0028] S2: the driving layer loads and manages the RPMsg driver, registers a driving device to manage shared memory of inter-core data interaction, creates a driving component to establish an inter-core logical connection, and provides data transmission services for the communication layer;

[0029] S3: the communication layer performs inter-core communication in an RPMsg channel-based manner, realizes message sending, message receiving and message feedback.

[0030] Optionally, the processor communicates with the RPMsg channel using a function interface provided by the RPMsg driver, and the RPMsg endpoint provides an inter-processor logical connection on the RPMsg channel; when the processor receives data, the RPMsg copies the data to an internal memory after adding an RPMsg header, searches for a corresponding virtualization device, places a message pointer in shared memory, and finally notifies a remote processor to complete inter-core message interaction.

[0031] Optionally, when the main core system acts as a sending end and the bare core system acts as a receiving end, the main core system first applies for a piece of memory in the USED ring buffer, fills the RPMsg header information and payload data into the memory, links the memory in the Used buffer to the Avail buffer, triggers an inter-core interrupt of the bare core system, and notifies the bare core system to receive data; at this time, the message is logically transmitted from the main core system to the bare core system by the RPMsg channel; then, the bare core system reads data from the Avail buffer, releases the corresponding memory to the Used ring buffer, sends a feedback signal to the main core system and triggers an inter-core interrupt, and notifies the main core system that the message has been successfully received, thereby completing the inter-core communication between the main core and the bare core.

[0032] The significant effect of the application is:

[0033] The application provides a multi-core inter-core real-time communication system and method, first, the hardware layer is classified according to the operating system type used by each processor, generally divided into a main core system and a bare core system, and the memory space is divided according to the resource use of the main core and the bare core, the shared resource is accessed in a shared memory mode, and the hardware details of the hardware layer are hidden through the hardware abstraction interface to provide a virtual hardware platform for the driver layer; then, the driver layer loads and manages the RPMsg driver program on the hardware platform provided by the hardware layer, registers a virtualization driver device to manage the shared memory of inter-core information interaction, creates an RPMsg channel and an RPMsg endpoint to establish a logical connection between cores, and provides data transmission services for the communication layer through the driver calling interface; finally, the communication layer uses the system calling interface provided by the driver layer to realize message sending and receiving, specifically, the sending end stores information in the corresponding part of the shared memory and triggers an inter-core interrupt, the receiving end responds to the inter-core interrupt, copies the message from the shared memory, releases the memory and sends feedback to the sending end to complete the inter-core communication, the inter-core communication technology based on the RPMsg channel is adopted, a solution is provided for solving the parallel running and cooperative scheduling of multiple processors, and the multi-core inter-core real-time scheduling can be realized. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only constitute some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0035] Figure 1 is a multi-core inter-core real-time communication architecture structure provided by the embodiment 1 of the present application.

[0036] Figure 2 is a structure schematic diagram of a shared memory module provided by the present application.

[0037] Figure 3 is a RPMsg driver program structure block diagram of the multi-core inter-core real-time communication system provided by the present application.

[0038] Figure 4 is an inter-core communication schematic diagram of the multi-core inter-core real-time communication system provided by the present application.

[0039] Figure 5 is a multi-core inter-core real-time communication system structure schematic diagram provided by the embodiment 2 of the present application.

[0040] Reference signs: 1 - hardware layer, 2 - driver layer, 3 - communication layer, 4 - main core system, 5 - bare core system, 6 - shared memory module, 7 - driver management module, 8 - RPMsg driver loading unit, 9 - driver device registration unit, 10 - driver component creation unit, 11 - message sending module, 12 - message receiving module, 13 - RPMsg channel, 14 - data writing unit, 15 - interrupt triggering unit, 16 - interrupt detection unit, 17 - data reading unit, 18 - hardware abstraction interface, 19 - driver calling interface. DETAILED DESCRIPTION

[0041] Embodiments of the present application are described below in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by reference to the accompanying drawings are exemplary and are intended to explain the present application, and cannot be understood as a limitation of the present application.

[0042] In the description of the present application, the meaning of "a plurality of" is two or more than two, unless otherwise explicitly and specifically limited.

[0043] Embodiment 1:

[0044] Referring to Figure 1 The present application provides a multi-core inter-core real-time communication system, comprising a hardware layer 1, a driver layer 2 and a communication layer 3, the hardware layer 1, the driver layer 2 and the communication layer 3 are arranged from bottom to top;

[0045] The hardware layer 1 is used for managing and classifying a plurality of processors, and dividing memory space according to the situation of building an operating system on the processor, and simultaneously using a shared memory mode to realize access to shared resources, and providing hardware support for the driver layer 2;

[0046] The drive layer 2 is used for loading and managing an RPMsg drive program, and registers a drive device to manage shared memory of inter-core data interaction, and creates a drive component to establish an inter-core logical connection, and provides a data transmission service for the communication layer 3; wherein the RPMsg drive module is a kind of message passing mechanism based on multi-core, and the underlying data exchange is carried out by virtualization device, and needs to be allocated by Remoteproc drive Resource;After the RPMsg drive is completed, the corresponding probe () Function is entered to complete device registration and component creation. Specifically, the drive first registers a virtualization drive device to manage shared memory of inter-core data interaction, and then establishes an RPMsg channel control device file under the dev directory, and provides an RPMsg end node creation interface function;When the RPMsg end node is created, the drive creates an end node device file under the dev directory, sets the RPMsg end node file name according to the number of created nodes, and users can perform RPMsg channel data transmission by obtaining the RPMsg end node device descriptor.

[0047] The communication layer 3 is used for message sending and message receiving, specifically, the sending end writes data into shared memory, and triggers software interrupt according to the interrupt interface of the target processor, and then establishes an RPMsg channel to realize logical connection with the receiving end;The receiving end detects the interrupt signal by using the interrupt controller, executes the interrupt service program to read the data in the shared memory, releases the memory, and sends feedback to the sending end, finally realizes inter-core information interaction.

[0048] Through Figure 1 It can be seen that the hardware layer 1 is provided with a main core system 4, a bare machine system 5 and a shared memory module 6, the main core system 4 is connected with the shared memory module 6, and the shared memory module 6 is connected with the bare machine system 5;

[0049] The main core system 4 is composed of CPU0, CPUi and a plurality of processors running operating system, and is used for executing communication processing, complex calculation and man-machine interaction and other non-real-time tasks;

[0050] The bare machine system 5 is composed of CPUi+1, CPUn and a plurality of processors running bare machine program, and is used for measurement, acquisition and control and other real-time calculation tasks;

[0051] The shared memory module 6 is used for dividing memory space, and dividing the memory area into three parts of operating system exclusive memory area, shared memory area and bare core exclusive area.

[0052] The hardware layer 1 manages and classifies multiple processors, divides memory space according to the situation of building an operating system on the processor, uses a shared memory mode to realize access to shared resources, and provides hardware support for the driver layer 2. In the embodiment, the hardware layer 1 uses an iTOP-I.MX6Q development board, which has a 32-bit reduced instruction set, low power consumption, and a Cortex-A9 quad-core microprocessor with excellent performance, and can realize parallel computing and collaborative scheduling of multiple processors. Figure 2 It can be seen that, on the basis of a general quad-core A9 homogeneous processor, the concept of asymmetry is introduced, the three-core processor of CPU0, CPU1 and CPU2 running the Linux operating system is called a main core system, and is used to perform complex computing tasks such as communication and human-computer interaction, has the characteristics of high performance, low power consumption, scalability, and can effectively improve the stability and reliability of the system; at the same time, the CPU3 processor running the bare machine program is called a bare core system, and is used to perform high real-time computing tasks such as acquisition, which can effectively improve the parallelism and real-time performance of the system. Due to the difference between the communication interaction interfaces of the operating systems used by the main and bare cores, and the fact that the private cache, interrupt management and other hardware resources of the main and bare cores are not shared, it is difficult for the main and bare cores to communicate with each other and to be efficiently collaboratively scheduled. Therefore, the shared memory module 6 divides the memory area into a Linux exclusive memory area, a shared memory area and a bare core exclusive area, realizes information interaction between the main and bare cores in a shared memory mode, and provides a communication bridge for the hardware layer 1 and the communication layer 3. Figure 2 It can also be seen that the DDR memory is divided into a CPU0-CPU2 exclusive area, a shared memory area and a bare core CPU3 exclusive area, wherein the shared memory area is an information interaction area in which the main core writes information, the bare core reads information or the bare core writes information, and the main core reads information.

[0053] Further, by Figure 1 It can be seen that the driver layer 2 includes a driver management module 7, which is used to load an RPMsg driver, create a driver component and register a driver device.

[0054] In the embodiment, the driver management module 7 is the core of the inter-core communication system, and provides an interaction bridge for the hardware layer 1 and the communication layer 3. Specifically, the driver management module 7 first loads the RPMsg driver located under drivers / rpmsg / , and provides a corresponding user space interface to allow the kernel driver to communicate with the remote processors available on the system, and then registers a virtualization driver device to manage the inter-core shared memory area, and creates an RPMsg channel and an endpoint to establish an inter-core logical connection, thereby providing a driver platform for data transmission and reception operations.

[0055] The structure block diagram of the RPMsg driver of the system is as follows: Figure 3As shown, the processor communicates with the RPMsg channel using the function interface provided by the RPMsg driver, while the RPMsg endpoint provides a logical connection between processors on the RPMsg channel. When the processor receives data, RPMsg copies it to the internal memory after adding an RPMsg header, then searches for the corresponding virtualization device and places the message pointer in the shared memory, and finally notifies the remote processor to complete the inter-core message interaction. In summary, the drive management module 7 includes three drive units, namely the drive module, the drive component, and the drive device, which provide drive services for efficient communication between the main bare cores.

[0056] Further, the drive management module 7 includes an RPMsg driver loading unit 8, a drive device registration unit 9, and a drive component creation unit 10. The RPMsg driver loading unit 8 is connected to the drive device registration unit 9, and the drive device registration unit 9 is connected to the drive component creation unit 10.

[0057] The RPMsg driver loading unit 8 is used to load the RPMsg protocol-based driver and implement data transmission and reception operations by manipulating the RPMsg driver, thereby completing the inter-core interaction of the system.

[0058] The drive device registration unit 9 is used to register virtualization drive devices, manage the shared memory for inter-core data interaction, and provide storage services for the RPMsg driver.

[0059] The drive component creation unit 10 is used to create RPMsg channels and RPMsg endpoints. The channel is identified by a text name and a local or target address, providing transmission services for inter-core processors. The endpoint provides a logical connection on the channel, and each endpoint has a unique source address and related callback function.

[0060] In specific implementation, the RPMsg driver loading unit 8 loads the RPMsg bus-based drive module, so that all data is transmitted on the RPMsg bus, thereby providing communication services for inter-core data interaction. Then, the drive device registration unit 9 is used to register virtualization drive devices and provide an interface function of "virtqueue", which allows user drives to send and receive data with communication counterparts using virtqueue, while managing the shared memory for inter-core data interaction and providing storage services for the RPMsg driver. Then, the drive component creation unit 10 creates RPMsg channels and PRMsg endpoints, which provide inter-core logical connections on the RPMsg channel. Default endpoints are created during initialization and will be bound to the callback function provided by the processor, thereby providing transmission services for inter-core data interaction.

[0061] Further, the communication layer 3 comprises a message sending module 11, a message receiving module 12 and an RPMsg channel 13; the message sending module 11 is connected with the RPMsg channel 13, and the RPMsg channel 13 is connected with the message receiving module 12;

[0062] The message sending module 11 is configured to write a message into a shared memory area and send a target processor side SGI software interrupt signal, so as to realize message sending.

[0063] The message receiving module 12 is configured to detect a software interrupt signal, and after detecting the interrupt signal, enter an interrupt processing function to read data in the shared memory area and clear an interrupt flag, so as to complete message receiving and realize inter-core communication.

[0064] The RPMsg channel 13 is configured to establish a logical connection between cores and provide an inter-core data transmission service.

[0065] In a specific implementation, the message sending module 11 calls an RPMsg driver, writes data into a shared ring buffer managed by a virtual device, and triggers an inter-core interrupt of a target processor; the RPMsg channel 13 establishes a logical connection between a sending end and a receiving end and provides a communication channel for data transmission; the message receiving module 12 detects an inter-core interrupt signal and responds to the interrupt, then copies a message from the buffer, releases memory and sends feedback to the sending end, thereby realizing inter-core information interaction. An inter-core communication schematic diagram of the system is shown in Figure 4 When the main core is the sending end and the bare core is the receiving end, the main core first applies for a piece of memory in the USED ring buffer, fills RPMsg header information and payload data into the memory, links the memory in the Used buffer to the Avail buffer, then triggers a bare core inter-core interrupt to inform the bare core to receive data, at this time, the message is logically transmitted from the main core to the bare core by the RPMsg channel; then, the bare core reads data from the Avail buffer and releases the corresponding memory to the Used ring buffer, at the same time, sends a feedback signal to the main core and triggers an inter-core interrupt to inform the main core that the message has been successfully received, thereby completing the main bare core inter-core communication.

[0066] Further, the message sending module 11 comprises a data writing unit 14 and an interrupt triggering unit 15; the data writing unit 14 is connected with the interrupt triggering unit 15, and the interrupt triggering unit 15 is connected with the RPMsg channel 13;

[0067] The data writing unit 14 is configured to fill RPMsg header information and payload data according to an RPMsg message format and write the RPMsg message into a shared buffer.

[0068] The interrupt triggering unit 15 is configured to send a software interrupt signal to an interrupt controller to inform a target processor to receive a message.

[0069] In a specific implementation, the data writing unit 14 first applies for a piece of memory in a Used buffer of a virtualization device, fills an RPMsg header information and payload data according to an RPMsg message format, writes the RPMsg message into the applied memory, and then links the RPMsg message to an Avail buffer of the virtualization device; the interrupt triggering unit 15 sends a software interrupt signal to an interrupt controller according to an interrupt interface of the target processor after the data writing is completed, and then informs the target processor to receive a message.

[0070] Further, the message receiving module 12 includes an interrupt detecting unit 16 and a data reading unit 17, the interrupt detecting unit 16 is connected with the RPMsg channel 13 and the data reading unit 17.

[0071] The interrupt detecting unit 16 is configured to detect whether an interrupt occurs in a current processor, if yes, enter an interrupt service function to process the interrupt, and if not, continue to detect.

[0072] The data reading unit 17 is configured to read data from a shared buffer and release the memory, and send a feedback to a sending end to complete communication.

[0073] In a specific implementation, the interrupt detecting unit 16 detects an interrupt signal of the current processor in real time, if an interrupt occurs, immediately performs an interrupt response, clears an interrupt flag bit of the interrupt, and waits for a next interrupt; the data reading unit 17 reads data after detecting the interrupt signal, the processor first reads data from an Avail buffer of the virtualization device, then adds the Avail buffer of the virtualization device to a Used buffer, and sends a feedback signal to the sending end, and finally realizes inter-core data transmission and reception.

[0074] Embodiment 2

[0075] By Figure 5 It can be seen that the embodiment provides a multi-core inter-core real-time communication system, which is different from the embodiment 1 in that a hardware abstraction interface 18 is arranged between the hardware layer 1 and the driver layer 2, and a driver calling interface 19 is arranged between the driver layer 2 and the communication layer 3, wherein:

[0076] The hardware abstraction interface 18 is configured to hide hardware interface details of the hardware layer 1, and provide a virtual hardware platform for the driver layer 2.

[0077] The drive call interface 19 is a set of system call functions provided by the drive layer 2 for the communication layer 3, used for system to access and control the RPMsg device.

[0078] In implementation, the hardware layer 1 is mainly responsible for the management and classification of multiple processors, and divides the corresponding memory space according to the classification result, and realizes the access of each processor to the shared resource in the manner of shared memory, and hides all hardware interface details through the hardware abstraction interface 18, and provides hardware support for the drive layer 2. The drive layer 2 loads and manages the RPMsg driver on the virtual hardware platform provided by the hardware layer 1, registers the drive device to provide data storage service, creates the drive component to provide data transmission service, and provides drive service for the communication layer 3 through the drive call interface 19. The communication layer 3 manipulates the RPMsg drive module by calling the drive interface function, realizes the receiving and transmitting operation of data, and establishes the inter-core logical link through the RPMsg channel, and finally completes the inter-core communication of the main bare core.

[0079] It can be seen that the multi-core inter-core real-time communication system provided by the embodiment first classifies the operating system types used by each processor through the hardware layer 1, and is usually divided into a main core system and a bare core system, and divides the memory space according to the resource usage of the main core and the bare core, and realizes the access to the shared resource in the manner of shared memory, and hides the hardware details of the hardware layer 1 through the hardware abstraction interface 18, and provides a virtual hardware platform for the drive layer 2; then, the drive layer 2 loads and manages the RPMsg driver on the hardware platform provided by the hardware layer 1, registers the drive device to manage the shared memory of the inter-core information interaction, creates the RPMsg channel and the RPMsg endpoint to establish the inter-core logical connection, and provides data transmission service for the communication layer 3 through the drive call interface 19; finally, the communication layer 3 uses the system call interface provided by the drive layer 2 to realize the sending and receiving of messages. Specifically, the sending end stores information in the corresponding part of the shared memory, and triggers the inter-core interrupt, and the receiving end responds to the inter-core interrupt, copies the message from the shared memory, releases the memory and sends feedback to the sending end to complete the inter-core communication. The inter-core communication technology based on the RPMsg channel provides a solution for solving the parallel running and cooperative scheduling of multiple processors, and can realize multi-core inter-core real-time scheduling.

[0080] In combination with the above system, the embodiment further provides a multi-core inter-core real-time communication method, including the following steps:

[0081] S1: the hardware layer manages and classifies a plurality of processors, divides the memory space according to the situation of building an operating system on the processor, simultaneously realizes the access to the shared resource by using the shared memory mode, and provides the hardware support for the driving layer;

[0082] S2: the driving layer loads and manages the RPMsg driving program, registers the driving device to manage the shared memory of the inter-core data interaction, simultaneously creates the driving component to establish the inter-core logical connection, and provides the data transmission service for the communication layer;

[0083] S3: the communication layer adopts the inter-core communication mode based on the RPMsg channel, realizes the sending, receiving and feedback of the message.

[0084] In the implementation, the processor communicates with the RPMsg channel by using the function interface provided by the RPMsg driving program, simultaneously the RPMsg end point provides the inter-processor logical connection on the RPMsg channel, when the processor receives the data, the RPMsg copies the data to the internal memory after adding the RPMsg header, then searches the corresponding virtualization device and puts the message pointer in the shared memory, finally informs the remote processor to complete the inter-core message interaction.

[0085] As can be seen from the above, the application adopts the inter-core communication technology based on the RPMsg channel, provides a solution for solving the parallel running and collaborative scheduling of the multiple processors, and can realize the inter-core real-time scheduling of the multiple cores.

[0086] The above only discloses one preferred embodiment of the application, of course, cannot limit the right scope of the application, the person skilled in the art can understand that the whole or part of the above-mentioned embodiment is realized, and the equivalent changes made according to the claims of the application still belong to the range covered by the application.

Claims

1. A multi-core inter-core real-time communication system, characterized by, The hardware layer, the driver layer and the communication layer are included; The hardware layer is provided with a main core system, a bare machine system and a shared memory module, wherein the main core system is used for executing non-real-time tasks, the bare machine system is used for processing real-time computing tasks, and the shared memory module is used for dividing memory space; The driver management module in the driver layer is used for loading an RPMsg driver, registering a driver device and creating a driver component; The communication layer is provided with a message sending module, a message receiving module and an RPMsg channel, wherein the message sending module is used for writing messages into a shared memory area and sending a software interrupt signal to a target processor, so as to realize message sending; the message receiving module is used for detecting a software interrupt signal, entering an interrupt processing function to read data in the shared memory area and clearing an interrupt flag bit after detecting the software interrupt signal, so as to complete message receiving and realize inter-core communication; and the RPMsg channel is used for establishing a logical connection between cores and providing inter-core data transmission services.

2. The multicore inter-core real-time communication system of claim 1, wherein, The main core system includes a plurality of processors running an operating system, and the executed non-real-time tasks include communication processing, complex calculation and human-computer interaction; the bare machine system includes at least one processor running a bare machine program, and the processed real-time computing tasks include measurement, acquisition and control.

3. The multicore inter-core real-time communication system according to claim 1 or 2, characterized in that, The shared memory module divides the memory area into an operating system exclusive memory area, a shared memory area and a bare core exclusive area.

4. The multi-core inter-core real-time communication system of claim 1, wherein, The driver management module includes an RPMsg driver loading unit, a driver device registration unit and a driver component creation unit, the RPMsg driver loading unit is connected with the driver device registration unit, the driver device registration unit is connected with the driver component creation unit, and wherein: The RPMsg driver loading unit is used for loading a driver program based on the RPMsg protocol, and realizing data sending and receiving operations by manipulating the RPMsg driver, so as to complete inter-core interaction of the system; The driver device registration unit is used for registering a virtualized driver device, managing a shared memory for inter-core data interaction and providing storage services for the RPMsg driver program; The driver component creation unit is used for creating an RPMsg channel and an RPMsg endpoint, the channel is identified by a text name and a local or target address, and provides transmission services for inter-core processors, the endpoint provides a logical connection on the channel, and each endpoint has a unique source address and a related callback function.

5. The multicore inter-core real-time communication system of claim 1, wherein, The data writing unit is connected with the interrupt triggering unit, and the interrupt triggering unit is connected with the RPMsg channel; The data writing unit is used for filling RPMsg header information and payload data according to an RPMsg message format, and writing the RPMsg message into a shared buffer area; The interrupt triggering unit is used for sending a software interrupt signal to an interrupt controller, and notifying a target processor to receive a message.

6. The multicore inter-core real-time communication system of claim 5, wherein, The message receiving module includes an interrupt detection unit and a data reading unit, the interrupt detection unit is connected with the RPMsg channel and the data reading unit; The interrupt detection unit is configured to detect whether an interrupt occurs in the current processor, and if so, enter an interrupt service function to process the interrupt, and otherwise, continue detection. The data reading unit is configured to read data from the shared buffer and release the memory, and send feedback to the sending end to complete communication.

7. The multicore inter-core real-time communication system of claim 1, wherein, A hardware abstraction interface is arranged between the hardware layer and the driver layer, and a driver calling interface is arranged between the driver layer and the communication layer, wherein: The hardware abstraction interface is configured to hide hardware interface details of the hardware layer and provide a virtual hardware platform for the driver layer. The driver calling interface is a set of system calling functions provided by the driver layer for the communication layer, and is configured to access and control the RPMsg device by the system.

8. A method for multi-core inter-core real-time communication, using the multi-core inter-core real-time communication system of any one of claims 1-7, characterized in that, The method comprises the following steps: S1: The hardware layer manages and classifies a plurality of processors, divides memory space according to whether an operating system is built on the processor, realizes access to shared resources in a shared memory mode, and provides hardware support for the driver layer; S2: The driver layer loads and manages an RPMsg driver, registers a driver device to manage shared memory for inter-core data interaction, creates a driver component to establish an inter-core logical connection, and provides data transmission services for the communication layer; S3: The communication layer performs inter-core communication in an RPMsg channel-based mode, realizes sending, receiving and feedback of messages.

9. The multi-core inter-core real-time communication method of claim 8, wherein, The processor communicates with the RPMsg channel by using a function interface provided by the RPMsg driver, and the RPMsg endpoint provides an inter-processor logical connection on the RPMsg channel, when the processor receives data, the RPMsg copies the data to an internal memory after adding an RPMsg header, searches for a corresponding virtualization device, places a message pointer in shared memory, and finally notifies a remote processor to complete inter-core message interaction.

10. The multi-core inter-core real-time communication method of claim 8, wherein, When the main core system acts as a sending end and the bare core system acts as a receiving end, the main core system first applies for a piece of memory in a USED ring buffer, fills an RPMsg header information and payload data into the memory, links the memory in the Used buffer to the Avail buffer, triggers an inter-core interrupt of the bare core system to notify the bare core system to receive data, at this time, the message is logically transmitted from the main core system to the bare core system by the RPMsg channel; then, the bare core system reads data from the Avail buffer and releases the corresponding memory to the Used ring buffer, sends a feedback signal to the main core system and triggers an inter-core interrupt to notify the main core system that the message has been successfully received, thereby completing inter-core communication between the main core and the bare core.

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