A power supply construction method, an on-chip power supply, and an electrically erasable programmable memory

Abstract

The embodiment of the application discloses a power supply construction method, an on-chip power supply and an electrically erasable programmable memory; through an improved forming method and structure of an internal power supply, an electrically erasable programmable read-only memory EEPROM circuit and an internal power supply circuit are integrated based on a silicon-oxide-nitride-oxide-silicon SONOS process, effective switching of the power supply between an external power supply voltage and an internal controlled voltage is realized by using an inverting driving enable structure; breakdown problems caused by the external power supply and a negative voltage supercharging structure are avoided, the voltage of the internal secondary power supply can be controlled below 3V, the erasing and writing process of the electrically erasable programmable memory EEPROM can be reliably realized while the low-voltage working, speed advantage and capacity advantage of the SONOS structure are maintained.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of microelectronic technology, and particularly relates to a power supply construction method, an on-chip power supply and an electrically erasable programmable memory. BACKGROUND

[0002] Power supply components provide energy for microelectronic circuits or are used to change the working state of microelectronic circuits, and for microelectronic circuits of different processes, the applicable power supply voltage range often becomes the core of the function implementation of the circuit or device. For an electrically erasable programmable read-only memory (EEPROM) circuit, a voltage difference between a positive bias voltage VPOS and a negative bias voltage VNEG is often used to realize the erasing and writing operation of a memory cell.

[0003] However, due to process reasons, the voltage difference between the external excitation voltage or the chip working power supply VDD and the negative bias voltage VNEG often exceeds the breakdown voltage BV of the device, and therefore, it is necessary to provide an internal / secondary power supply with a limited amplitude for the related circuit.

[0004] On the other hand, a memory cell C of a silicon-oxide-nitride-oxide-silicon (SONOS) structure often includes a 5V MOS (metal-oxide-semiconductor) tube ZNCH5 constructed in a P well, and the zero voltage is adjusted through the implantation of the memory cell C. However, the implantation of the ZNCH5 tube is related to the implantation of the memory cell C, and if the implantation of the memory cell C needs to be adjusted, the change in the threshold voltage polarity of the ZNCH5 tube may cause fluctuations in the storage characteristics. SUMMARY

[0005] The present application discloses a power supply construction method, an on-chip power supply and an electrically erasable programmable memory, and the method includes constructing a power supply function structure that is processed synchronously with a preset chip, and the power supply function structure includes a construction step of a three-terminal device, a construction step of a resistance element and a construction step of an inverting driver.

[0006] Among them, the construction of the power supply function structure is obtained by mask photolithography of a preset number of layers and physical and chemical processes of each layer according to the semiconductor process, and the power supply function structure includes an on-chip current source structure, an on-chip voltage source structure and a driving control structure.

[0007] Specifically, the connection device external power supply to the chip current source structure, the chip voltage source structure and the drive control structure of the excitation end; wherein, the external power supply includes device ground.

[0008] Further, the control end of the first three-terminal device P0 and the second three-terminal device P1 is connected, forming a first bias pair tube, and the control end of the third three-terminal device N0 and the fourth three-terminal device N1 is connected, forming a second bias pair tube; the first bias pair tube and the second bias pair tube are connected in series to form a chip current source structure; wherein, the fourth three-terminal device N1 is connected with the fifth resistor R0 between the device ground.

[0009] Specifically, the chip voltage source structure outputs a controlled first internal voltage VDDI under the excitation of the chip current source structure according to the selection of the first enable signal PEN and / or the second enable signal PENB; wherein, the first internal voltage VDDI is controlled by the first bias signal PBIAS and the first enable signal PEN, and the first internal voltage VDDI is determined after the voltage of the excitation end is gated or divided; the gating or dividing process is completed by the drive control structure.

[0010] Further, the first bias signal PBIAS is connected to the first control end of the fourteenth three-terminal device P6 of the drive control structure; the second end of the fourteenth three-terminal device P6 is connected with the excitation end; the third end of the fourteenth three-terminal device P6 is connected in series with the first inverter driver, the second inverter driver and the third inverter driver.

[0011] Wherein, the chip voltage source structure pulls up the first internal voltage VDDI to the voltage VDDA50 corresponding to the excitation end when the second enable signal PENB is effective, and the second enable signal PENB is opposite to the first enable signal PEN.

[0012] Further, when the voltage of the excitation end is less than or equal to the first voltage threshold, the mirror current of the sixteenth three-terminal device N7, the fifteenth three-terminal device N8 and the tenth three-terminal device P7 branch to the seventeenth three-terminal device N6, and the mirror current of the second three-terminal device P1 to the fourteenth three-terminal device P6; the pull-up current of the fourteenth three-terminal device P6 is greater than the pull-down current of the seventeenth three-terminal device N6; the first enable signal PEN is set, and at the same time, the second enable signal PENB is reset, and the first internal voltage VDDI is equal to the voltage of the excitation end.

[0013] When the voltage of the excitation end is greater than the preset first voltage threshold, the pull-up current of the fourteenth three-terminal device P6 is less than the pull-down current of the seventeenth three-terminal device N6, the first enable signal PEN is reset, and at the same time, the second enable signal PENB is set; the first internal voltage VDDI is determined by the voltage distributed by the eleventh three-terminal device N5 branch.

[0014] Specifically, the preset chip can be an erasable programmable read-only memory (EEPROM), which can be obtained by using a 95nm process, and the preset chip can be constructed by using a SONOS process; the voltage of the excitation end can be between 1.7V and 5.5V; and the first internal voltage VDDI can be configured to be less than or equal to 3V.

[0015] The in-chip voltage source structure includes two charge boost pumps, and the charge boost pumps include a positive voltage VPOS boost pump and a negative voltage VNEG boost pump; and the pressure difference between the positive voltage VPOS boost pump and the negative voltage VNEG boost pump can be used for erasing and writing of the SONOS unit.

[0016] Specifically, the number of mask layers in the construction process of the preset chip can be 17; the three-terminal device can be constructed in the P well, the eleventh three-terminal device N5 can be an NCH5 tube in an NMOS structure, and the twelfth three-terminal device P5 can be a PCH5 tube in a PMOS structure.

[0017] The embodiment of the present application also discloses an in-chip power supply, which comprises an in-chip current source structure, an in-chip voltage source structure and a driving control structure; the in-chip current source structure, the in-chip voltage source structure and the driving control structure are powered by an excitation end of an external power supply, and the external power supply further comprises a device ground end.

[0018] Specifically, the control ends of the first three-terminal device P0 and the second three-terminal device P1 are connected to form a first bias pair tube, and the control ends of the third three-terminal device N0 and the fourth three-terminal device N1 are connected to form a second bias pair tube; wherein the fifth resistor R0 is connected between the fourth three-terminal device N1 and the device ground end.

[0019] Further, the in-chip voltage source structure outputs a controlled first internal voltage VDDI under the excitation of the in-chip current source structure according to the selection of the first enable signal PEN and / or the second enable signal PENB of the driving control structure; wherein the first internal voltage VDDI is controlled by the first bias signal PBIAS and the first enable signal PEN, and the first internal voltage VDDI is determined after the voltage of the excitation end is selected or divided; and the selection or division process is completed by the driving control structure.

[0020] Further, the in-chip power supply of the present application further comprises a first control end of the fourteenth three-terminal device P6 of the driving control structure connected to the first bias signal PBIAS; the second end of the fourteenth three-terminal device P6 and the excitation end are connected to each other; and the third end of the fourteenth three-terminal device P6 is sequentially connected to a first inverter driver, a second inverter driver and a third inverter driver.

[0021] The in-chip voltage source structure pulls up the first internal voltage VDDI to the voltage VDDA 50 corresponding to the excitation end when the second enable signal PENB is effective, and the second enable signal PENB is opposite to the first enable signal PEN.

[0022] Specifically, when the voltage of the excitation end is less than or equal to the first voltage threshold, the sixteenth three-terminal device N7, the fifteenth three-terminal device N8, the tenth three-terminal device P7 branch mirror current to the seventeenth three-terminal device N6, and the second three-terminal device P1 mirror current to the fourteenth three-terminal device P6; the pull-up current of the fourteenth three-terminal device P6 is greater than the pull-down current of the seventeenth three-terminal device N6; the first enable signal PEN is set, and the second enable signal PENB is reset at the same time, and the first internal voltage VDDI is at the same potential as the excitation end.

[0023] Further, when the voltage of the excitation end is greater than the preset first voltage threshold, the pull-up current of the fourteenth three-terminal device P6 is less than the pull-down current of the seventeenth three-terminal device N6, the first enable signal PEN is reset, and the second enable signal PENB is set at the same time; the first internal voltage VDDI is determined by the voltage distributed by the eleventh three-terminal device N5 branch.

[0024] Specifically, the preset chip can be an electrically erasable programmable read-only memory EEPROM, which can be obtained by using a 95nm process, and the preset chip is constructed by using a SONOS process; the voltage of the excitation end can be selected to be between 1.7V and 5.5V; and the first internal voltage VDDI can be configured to be less than or equal to 3V.

[0025] The in-chip voltage source structure can further include two charge boost pumps, and the charge boost pumps include a positive voltage VPOS boost pump and a negative voltage VNEG boost pump; and the pressure difference between the positive voltage VPOS boost pump and the negative voltage VNEG boost pump is used for erasing and writing of the SONOS unit.

[0026] Specifically, the number of mask layers in the construction process of the preset chip is 17; the three-terminal devices are constructed in a P-well, and the eleventh three-terminal device N5 can be an NCH5 tube of an NMOS structure; and the twelfth three-terminal device P5 can be a PCH5 tube of a PMOS structure.

[0027] Correspondingly, the application further discloses an electrically erasable programmable memory, which comprises any one of the in-chip power supplies; wherein the excitation end provides an external power supply for the memory, and the voltage of the external power supply is between 1.7V and 5.5V; and the voltage of the in-chip power supply does not exceed 3V.

[0028] The SONOS memory structure comprises a source region and a drain region formed in a P well, a channel region of the memory between the source region and the drain region, an ONO (Oxide-Nitride-Oxide) dielectric layer on a silicon surface of the channel region, and a polysilicon gate formed on the ONO dielectric layer.

[0029] Further, a side wall of the polysilicon gate is formed on the ONO dielectric layer on both sides of the polysilicon gate; the side wall can be a double-layer structure; an inner layer close to the polysilicon gate is a silicon nitride side wall, and an outer layer is a silicon oxide side wall; the polysilicon gate has a space recessed into the polysilicon gate at both ends of the gate length direction at the bottom of the polysilicon gate, and the space is filled with silicon oxide, so that the total thickness of the dielectric layer at both ends of the polysilicon gate channel is greater than the thickness of the dielectric layer above the channel region.

[0030] By improving the forming method and structure of the internal power supply, the EEPROM circuit and the internal power supply circuit are integrated based on the SONOS process, the effective switching of the power supply between the external power supply voltage and the internal controlled voltage is realized by using the enable structure of the inverse driving, the breakdown problem caused by the external power supply and the negative voltage boosting structure is avoided, the voltage of the internal secondary power supply can be controlled below 3V, the erasing and writing process of the EEPROM can be reliably realized while the low-voltage working, speed advantage and capacity advantage of the SONOS structure are maintained.

[0031] It should be noted that the "first", "second" and similar terms used in the present text are only used to describe the elements in the technical solutions, and do not constitute a limitation on the technical solutions, nor can they be understood as an indication or suggestion of the importance of the corresponding elements; the elements with "first", "second" and similar terms indicate that at least one element is included in the corresponding technical solution. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the present application, and to facilitate further understanding of the technical effects, technical characteristics and purposes of the present application, the present application will be described in detail below in conjunction with the drawings, which constitute an essential part of the specification and are used to illustrate the technical solutions of the present application together with the embodiments of the present application, but do not constitute a limitation on the present application.

[0033] The same reference numerals in the drawings represent the same components, specifically: Figure 1 is a 5V power supply circuit schematic diagram in the related art; Figure 2 is a circuit schematic diagram of the product embodiment of the present application.

[0034] Among them:

[0035] 001-device voltage, i.e. device analog voltage source VDDA (Voltage Device Analog);

[0036] 002 - First bias signal, i.e., PBIAS;

[0037] 003 - Second bias signal, i.e., NBIAS;

[0038] 004 - First enable signal, i.e., PEN;

[0039] 005 - Second enable signal, namely PENB, PEN is inverted with PENB;

[0040] 006 - First intermediate potential, i.e., IB_VDDI;

[0041] 007 - First internal voltage, i.e., VDDI;

[0042] 100-On-chip current source circuit,

[0043] 101 - The first three-terminal device, i.e., P0;

[0044] 102 - The second three-terminal device, i.e., P1;

[0045] 103 - The third three-terminal device, i.e., N0;

[0046] 104 - The fourth three-terminal device, namely N1;

[0047] 105 - The fifth resistor, i.e., R0;

[0048] 200-on-chip voltage source circuit,

[0049] 201 - The fifth three-terminal device, namely P2;

[0050] 202 - The sixth three-terminal device, namely P4;

[0051] 203 - Seventh three-terminal device, i.e., P3;

[0052] 204 - Eighth three-terminal device, namely N2;

[0053] 205 - N4, the ninth terminal device;

[0054] 206 - The thirteenth terminal device, i.e., N3;

[0055] 207 - Terminal 113, i.e., N5;

[0056] 208 - The twelfth and thirteenth terminal device, i.e., P5;

[0057] 300-Drive control circuit,

[0058] 301 - The thirteenth three-terminal device, i.e., P7;

[0059] 302 - Fourteenth three-terminal device, i.e., P6;

[0060] 303 - Fifteenth three-terminal device, i.e., N8;

[0061] 304 - The sixteenth three-terminal device, namely N7;

[0062] 305 - The seventeenth three-terminal device, namely N6;

[0063] 306 - First Inverting Driver;

[0064] 307 - Second Inverting Driver;

[0065] 308 - Third Inverting Driver. Detailed Implementation

[0066] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Of course, the specific embodiments described below are merely illustrative of the technical solutions of the present invention, and not intended to limit the invention. Furthermore, the parts described in the embodiments or drawings are merely illustrative examples of relevant parts of the present invention, and not the entirety of the invention.

[0067] like Figure 2 The power supply construction method shown includes constructing a power supply functional structure that is processed synchronously with a preset chip. The power supply functional structure includes the construction steps of three-terminal devices, the construction steps of resistors, and the construction steps of inverting driving devices. The construction of the power supply functional structure is based on semiconductor technology, which involves photolithography of a preset number of mask layers and the corresponding circuit structure obtained by coordinating the physical and chemical processes of each layer. The power supply functional structure includes an on-chip current source structure 100, an on-chip voltage source structure 200, and a driving control structure 300.

[0068] Furthermore, the external power supply of the device is connected to the excitation terminal 001 of the on-chip current source structure 100, the on-chip voltage source structure 200 and the drive control structure 300, and its external power supply includes the device ground terminal 010.

[0069] Specifically, the control terminals of the first three-terminal device 101, i.e. P0, and the second three-terminal device 102, i.e. P1, are connected to form a first bias pair; and the control terminals of the third three-terminal device 103, i.e. N0, and the fourth three-terminal device 104, i.e. N1, are connected to form a second bias pair.

[0070] Furthermore, the first bias pair and the second bias pair are connected in series to form an on-chip current source structure 100; wherein, the fourth three-terminal device 104, i.e., N1, is connected to the device ground 010 by a fifth resistor device 105, i.e., R0.

[0071] Specifically, the on-chip voltage source structure 200 outputs a controlled first internal voltage 007, i.e. VDDI, under the excitation of the on-chip current source structure 100 according to the selection of the first enable signal 004, i.e. PEN, and / or the second enable signal 005, i.e. PENB; wherein the first internal voltage 007, i.e. VDDI, is controlled by the first bias signal 002, i.e. PBIAS, and the first enable signal 004, i.e. PEN. The first internal voltage 007, i.e. VDDI, is determined by the voltage gating or voltage dividing of the excitation terminal 001; the gating or voltage dividing process is completed by the driving control structure 300.

[0072] Further, the embodiment also includes connecting the first bias signal 002, i.e. PBIAS, to the first control terminal of the fourteenth three-terminal device 302, i.e. P6, of the driving control structure 300; the second terminal of the fourteenth three-terminal device 302, i.e. P6, is connected to the excitation terminal 001; the third terminal of the fourteenth three-terminal device 302, i.e. P6, is sequentially connected to the first inverting driver 306, the second inverting driver 307, and the third inverting driver 308.

[0073] Wherein: the on-chip voltage source structure 200 pulls up the first internal voltage 007, i.e. VDDI, to the voltage VDDA50 corresponding to the excitation terminal 001 when the second enable signal 005, i.e. PENB, is effective; the second enable signal 005, i.e. PENB, and the first enable signal 004, i.e. PEN, are inverted.

[0074] Specifically, when the voltage of the excitation terminal 001 is less than or equal to the first voltage threshold, the current of the sixteenth three-terminal device 304, i.e. N7, the fifteenth three-terminal device 303, i.e. N8, and the tenth three-terminal device 301, i.e. P7 branch is mirrored to the seventeenth three-terminal device 305, i.e. N6; the second three-terminal device 102, i.e. P1, mirrors the current to the fourteenth three-terminal device 302, i.e. P6; the pull-up current of the fourteenth three-terminal device 302, i.e. P6, is greater than the pull-down current of the seventeenth three-terminal device 305, i.e. N6; the first enable signal 004, i.e. PEN, is set, while the second enable signal 005, i.e. PENB, is reset, and the first internal voltage 007, i.e. VDDI, is equal to the voltage of the excitation terminal 001.

[0075] In addition, when the voltage of the excitation terminal 001 is greater than the preset first voltage threshold, the pull-up current of the fourteenth three-terminal device 302, i.e. P6, is less than the pull-down current of the seventeenth three-terminal device 305, i.e. N6; the first enable signal 004, i.e. PEN, is reset, while the second enable signal 005, i.e. PENB, is set; the first internal voltage 007, i.e. VDDI, is determined by the voltage distributed by the eleventh three-terminal device 207, i.e. N5 branch.

[0076] Further, the preset chip can be an electrically erasable programmable read-only memory (EEPROM), which can be obtained by using a 95 nm process, and the preset chip can also be constructed by using a SONOS process; the voltage of the excitation end 001 can be between 1.7 V and 5.5 V; the first internal voltage 007, that is, VDDI can be configured to be less than or equal to 3 V.

[0077] Specifically, the on-chip voltage source structure 200 can use two charge boost pumps, and the combination of the two charge boost pumps includes a positive voltage VPOS boost pump and a negative voltage VNEG boost pump; the pressure difference between the positive voltage VPOS boost pump and the negative voltage VNEG boost pump is used for erasing and writing of the SONOS unit.

[0078] Further, the number of masks in the preset chip construction process can be 17 layers; the three-terminal device can be constructed in the P well, the eleventh three-terminal device 207, that is, N5, can use an NCH5 tube of an NMOS structure, and the twelfth three-terminal device 208, that is, P5, can use a PCH5 tube of a PMOS structure.

[0079] Correspondingly, as shown in Figure 1 、 Figure 2 , the embodiment also provides an on-chip power supply, which includes the on-chip current source structure 100, the on-chip voltage source structure 200, and the driving control structure 300, to replace the original power supply structure 222.

[0080] The on-chip current source structure 100, the on-chip voltage source structure 200, and the driving control structure 300 are powered by an excitation end 001 of an external power supply, and the external power supply includes a device ground 010 end.

[0081] Further, the control end of the first three-terminal device 101, that is, P0, and the control end of the second three-terminal device 102, that is, P1, are connected to form a first bias pair tube; the control end of the third three-terminal device 103, that is, N0, and the control end of the fourth three-terminal device 104, that is, N1, are connected to form a second bias pair tube; and the fifth resistor device 105, that is, R0, is connected between the fourth three-terminal device 104, that is, N1, and the device ground 010.

[0082] Specifically, the on-chip voltage source structure 200 outputs a controlled first internal voltage 007, that is, VDDI, under the excitation of the on-chip current source structure 100 according to the selection of the first enable signal 004, that is, PEN, and / or the second enable signal 005, that is, PENB; the first internal voltage 007, that is, VDDI, is controlled by the first bias signal 002, that is, PBIAS, and the first enable signal 004, that is, PEN; the first internal voltage 007, that is, VDDI, is determined after the voltage of the excitation end 001 is selected or divided; and the selection or division process is completed by the driving control structure 300.

[0083] Further, the power supply embodiment of the present application further comprises a first control terminal of a fourteenth three-terminal device 302, i.e. P6, of the driving control structure 300 connected to the first bias signal 002, i.e. PBIAS; a second terminal of the fourteenth three-terminal device 302, i.e. P6, connected to the excitation terminal 001; and a third terminal of the fourteenth three-terminal device 302, i.e. P6, connected to the first inverting driver 306, the second inverting driver 307 and the third inverting driver 308 in sequence.

[0084] In the above embodiment, the in-die voltage source structure 200 is configured to pull up the first internal voltage 007, i.e. VDDI, to the voltage VDDA50 corresponding to the excitation terminal 001 when the second enable signal 005, i.e. PENB, is active; and the second enable signal 005, i.e. PENB, is inverted with respect to the first enable signal 004, i.e. PEN.

[0085] Specifically, when the voltage of the excitation terminal 001 is less than or equal to the first voltage threshold, the current of the fifteenth three-terminal device 303, i.e. N8, the sixteenth three-terminal device 304, i.e. N7, and the tenth three-terminal device 301, i.e. P7, is mirrored to the seventeenth three-terminal device 305, i.e. N6, and the current of the second three-terminal device 102, i.e. P1, is mirrored to the fourteenth three-terminal device 302, i.e. P6; the pull-up current of the fourteenth three-terminal device 302, i.e. P6, is greater than the pull-down current of the seventeenth three-terminal device 305, i.e. N6; the first enable signal 004, i.e. PEN, is set, while the second enable signal 005, i.e. PENB, is reset, and the first internal voltage 007, i.e. VDDI, is at the same potential as the excitation terminal 001.

[0086] In addition, when the voltage of the excitation terminal 001 is greater than the first voltage threshold, the pull-up current of the fourteenth three-terminal device 302, i.e. P6, is less than the pull-down current of the seventeenth three-terminal device 305, i.e. N6; the first enable signal 004, i.e. PEN, is reset, while the second enable signal 005, i.e. PENB, is set; and the first internal voltage 007, i.e. VDDI, is determined by the voltage distributed by the eleventh three-terminal device 207, i.e. N5.

[0087] Further, the preset chip can be an electrically erasable programmable read-only memory (EEPROM), which can be obtained by using a 95 nm process, and the preset chip can also be constructed by using a SONOS process; the voltage of the excitation terminal 001 can be configured to be between 1.7 V and 5.5 V; and the first internal voltage 007, i.e. VDDI, can be configured to be less than or equal to 3 V.

[0088] Specifically, the in-die voltage source structure 200 can be implemented by using two charge pumps; the charge pumps can include a positive voltage VPOS pump and a negative voltage VNEG pump; and the voltage difference between the positive voltage VPOS pump and the negative voltage VNEG pump can be used for erasing and writing of the SONOS unit.

[0089] Further, the number of mask layers in the preset chip construction process can be 17; the three-terminal device can be constructed in the P-well, the eleventh three-terminal device 207, i.e., N5, can adopt an NCH5 tube of an NMOS structure; and the twelfth three-terminal device 208, i.e., P5, can adopt a PCH5 tube of a PMOS structure.

[0090] Correspondingly, the embodiment further discloses an electrically erasable programmable memory, comprising the in-chip power supply in any of the above; wherein the excitation end 001 provides an external power supply for the memory, and the voltage of the external power supply is between 1.7V and 5.5V; and the voltage of the in-chip power supply is not more than 3V.

[0091] It should be noted that the above embodiments are only for more clearly illustrating the technical solutions of the present application, and those skilled in the art can understand that the implementation manners of the present application are not limited to the above, and the obvious changes, replacements or substitutions based on the above do not exceed the scope of the technical solutions of the present application; other implementation manners also fall within the scope of the present application without departing from the concept of the present application.

Claims

1. A power supply construction method, characterized by comprising: Comprising: The power supply function structure is constructed synchronously with the preset chip, and the power supply function structure comprises a construction step of a three-terminal device, a construction step of a resistor element, and a construction step of an inverting driver; the construction of the power supply function structure is obtained by photolithography of a mask plate with a preset number of layers according to a semiconductor process and in cooperation with a physical and chemical process of each layer to obtain a corresponding circuit structure; wherein the power supply function structure comprises an on-chip current source structure (100), an on-chip voltage source structure (200), and a driving control structure (300); A device external power supply is connected to the excitation end (001) of the on-chip current source structure (100), the on-chip voltage source structure (200), and the driving control structure (300), and the external power supply comprises a device ground (010) end; The control ends of a first three-terminal device (101) P0 and a second three-terminal device (102) are connected to form a first bias pair tube, and the control ends of a third three-terminal device (103) and a fourth three-terminal device (104) are connected to form a second bias pair tube; the first bias pair tube and the second bias pair tube are connected in series to form the on-chip current source structure (100); wherein the fourth three-terminal device (104) and the device ground (010) are connected with a fifth resistor device (105); The on-chip voltage source structure (200) outputs a controlled first internal voltage (007) under the excitation of the on-chip current source structure (100) according to the selection of the first enable signal (004) and / or the second enable signal (005) of the driving control structure (300); wherein the first internal voltage (007) is controlled by the first bias signal (002) and the first enable signal (004), and the first internal voltage (007) is determined after being voltage-gated or voltage-divided by the excitation end (001); the gating or voltage dividing process is completed by the driving control structure (300); The first bias signal (002) is connected to the first control end of the fourteenth three-terminal device (302) of the driving control structure (300); the second end of the fourteenth three-terminal device (302) is connected to the excitation end (001); and the third end of the fourteenth three-terminal device (302) is connected in series with a first inverting driver (306), a second inverting driver (307), and a third inverting driver (308) in sequence; Wherein: the on-chip voltage source structure (200) pulls up the first internal voltage (007) to the voltage corresponding to the excitation end (001) when the second enable signal (005) is effective, and the second enable signal (005) is opposite to the first enable signal (004).

2. The power supply construction method of claim 1, wherein: When the voltage of the excitation terminal (001) is less than or equal to a first voltage threshold, the mirror current of the tenth three-terminal device (301) branch to the seventeenth three-terminal device (305), the mirror current of the second three-terminal device (102) to the fourteenth three-terminal device (302); the pull-up current of the fourteenth three-terminal device (302) is greater than the pull-down current of the seventeenth three-terminal device (305); the first enable signal (004) is set, while the second enable signal (005) is reset, and the first internal voltage (007) is equal to the excitation terminal (001); When the voltage of the excitation terminal (001) is greater than the first voltage threshold, the pull-up current of the fourteenth three-terminal device (302) is less than the pull-down current of the seventeenth three-terminal device (305), the first enable signal (004) is reset, while the second enable signal (005) is set; the first internal voltage (007) is determined by the voltage distributed by the eleventh three-terminal device (207) branch.

3. The power supply construction method of claim 2, wherein: The preset chip is an EEPROM, which is obtained by using a 95nm process, and the preset chip is constructed by using a SONOS process; the voltage of the excitation terminal (001) is between 1.7V and 5.5V; and the first internal voltage (007) is less than or equal to 3V; The on-chip voltage source structure (200) comprises two charge boost pumps, which comprise a positive voltage boost pump and a negative voltage VNEG boost pump; and the pressure difference between the positive voltage VPOS boost pump and the negative voltage VNEG boost pump is used for erasing and writing of a SONOS unit.

4. The power supply construction method of claim 3, wherein: The number of mask layers in the construction process of the preset chip is 17; the three-terminal devices are constructed in a P-well; the eleventh three-terminal device (207) is an NMOS tube; and the twelfth three-terminal device (208) is a PMOS tube.

5. An on-chip power supply comprising: The on-chip current source structure (100), the on-chip voltage source structure (200), and the driving control structure (300); The on-chip current source structure (100), the on-chip voltage source structure (200), and the driving control structure (300) are powered by an excitation terminal (001) of an external power supply, and the external power supply comprises a device ground (010) terminal; The control terminals of the first three-terminal device (101) and the second three-terminal device (102) are connected, forming a first bias pair of tubes, and the control terminals of the third three-terminal device (103) and the fourth three-terminal device (104) are connected, forming a second bias pair of tubes; wherein the fifth resistor (105) is connected between the fourth three-terminal device (104) and the device ground (010). The in-patch voltage source structure (200) outputs a controlled first internal voltage (007) under the excitation of the in-patch current source structure (100) according to the selection of the first enable signal (004) and / or the second enable signal (005) of the drive control structure (300); wherein the first internal voltage (007) is controlled by the first bias signal (002) and the first enable signal (004), and the first internal voltage (007) is determined after being voltage-gated or voltage-divided by the excitation terminal (001); the gating or voltage-dividing process is completed by the drive control structure (300); The first control terminal of the fourteenth three-terminal device (302) of the drive control structure (300) connected to the first bias signal (002); the second terminal of the fourteenth three-terminal device (302) and the excitation terminal (001) are connected to each other; the third terminal of the fourteenth three-terminal device (302) is sequentially connected to the first inverting driver (306), the second inverting driver (307) and the third inverting driver (308). Wherein: when the second enable signal (005) is effective, the in-patch voltage source structure (200) pulls up the first internal voltage (007) to the voltage corresponding to the excitation terminal (001), and the second enable signal (005) is opposite to the first enable signal (004).

6. The in-patch power source of claim 5, wherein: When the voltage of the excitation terminal (001) is less than or equal to the first voltage threshold, the current mirror of the sixteenth three-terminal device (304), the fifteenth three-terminal device (303) and the tenth three-terminal device (301) branch to the seventeenth three-terminal device (305), and the current mirror of the second three-terminal device (102) to the fourteenth three-terminal device (302); the pull-up current of the fourteenth three-terminal device (302) is greater than the pull-down current of the seventeenth three-terminal device (305); the first enable signal (004) is set, and at the same time the second enable signal (005) is reset, and the first internal voltage (007) is equal to the voltage of the excitation terminal (001); When the voltage of the excitation terminal (001) is greater than the preset first voltage threshold, the pull-up current of the fourteenth three-terminal device (302) P6 is less than the pull-down current of the seventeenth three-terminal device (305), the first enable signal (004) is reset, and at the same time the second enable signal (005) is set; the first internal voltage (007) is determined by the voltage distributed by the eleventh three-terminal device (207) branch.

7. The in-patch power source of claim 5 or 6, wherein: The in-patch voltage source structure (200) further comprises two charge boost pumps, the charge boost pumps comprising a positive voltage boost pump and a negative voltage VNEG boost pump; the pressure difference between the positive voltage VPOS boost pump and the negative voltage VNEG boost pump is used for erasing and writing of a SONOS unit.

8. An electrically erasable programmable memory comprising the on-chip power supply of claim 5 or 6; wherein, The excitation terminal (001) provides an external power supply for the memory, and the voltage of the external power supply is between 1.7V and 5.5V; the voltage of the in-patch power source does not exceed 3V.

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