A method, system, and medium for generating a combination logic expression for a decoding component

Abstract

The application discloses a method, system and medium for generating a combination logic expression of a decoding component, and the method comprises the following steps: generating a truth table for any wth bit of W bits of a target decoding signal; for an nth possible value of N instruction code possible values, if the wth bit is derived from any xth bit of the nth possible value, changing the value of the xth bit of the nth possible value from 1'bx to 1'b1, keeping the values of other bits unchanged to obtain a new value of the nth possible value, and the new value of the nth possible value corresponds to the value 1'b1 of the wth bit of the target decoding signal; otherwise, the nth possible value corresponds to the value 1'b1 or 1'b0 of the wth bit of the decoding signal; and inputting the corresponding relationship formed by the nth possible value and the value of the wth bit of the target decoding signal into the truth table of the wth bit of the decoding signal. The application can effectively control the size of the truth table and generate an optimized combination logic expression.

Description

Technical Field

[0001] This invention pertains to microprocessor design technology, specifically relating to a method, system, and medium for generating combinational logic expressions in a microprocessor's decoding unit. Background Technology

[0002] The decoding unit of a microprocessor uses a large number of combinational logic expressions, which are used to translate the instruction codes provided by the instruction fetch unit into multiple decoding signals. A common method for generating these combinational logic expressions is to use conversion tools to transform them into combinational logic expressions based on the correspondence between instruction codes and decoding signal values ​​provided by the truth table.

[0003] Decoding components involve a large number of correspondences between instruction codes and decoded signal values. To facilitate the management of all these correspondences, tables are often used for manual maintenance; these tables are simply called decoding tables. The information maintained by the decoding table consists of two parts: instruction codes and decoded signals. Instruction codes are the input information, and decoded signals are the output information. Each row of the table indicates the value of the decoded signal under a specific instruction code. For example, the decoding table example shown in Table 1 maintains the correspondence between two sets of decoded signals (decoding signal 0 and decoding signal 1) and the values ​​of the instruction codes.

[0004] Table 1: Examples of decoding representations.

[0005] Serial Number Instruction encoding Decoding signal 0 Decoding signal 1 num inst_opcode[31:0] dec_signal0[4:0] dec_signal1[0:0] 0 32'b0000_0000_0000_0000_0000_0000_000x_xxxx inst_opcode[4:0] 1'bx 1 32'b0000_0000_0000_0000_000x_xxxx_0010_0000 inst_opcode[12:8] 1'b0 2 32'b0000_0000_0000_0000_0000_0000_0100_0000 5'b0_0000 1'b1 3 32'b0000_0000_0000_0000_0000_0000_0110_0000 5'b0_0001 1'b0 5 32'bxxxx_x000_0000_0000_0000_0000_1xx0_0000 inst_opcode[31:27] 1'b1

[0006] For ease of description, we use the following naming convention: The instruction encoding is named `inst_opcode`, with a bit width of WI. Therefore, the instruction encoding can be fully represented as `inst_opcode[WI-1:0]`, and `inst_opcode[WI-1:0]` has a maximum of 2^36 bits. WIThere are several possible values; the decoded signal is named dec_signali, the bit width is WDi, and i is the decoded signal number. Therefore, the decoded signal can be completely represented as dec_signali[WDi-1:0]. As can be seen from the example in Table 1, WI=32, WD0=5, WD1=1, and inst_opcode[31:0] has 6 instruction codes; the value of the decoded signal has two sources under different instruction codes. One is from explicit binary constants, and the other is from instruction code fields. For example, the value of dec_signal0[4:0] has two sources. The binary constants it originates from are 5'b0_0000 and 5'b0_0001, and the instruction code fields it originates from are inst_opcode[4:0], inst_opcode[12:8] and inst_opcode[31:27]. However, dec_signal1[0:0] only has one source. The binary constants it originates from are 1'b0, 1'b1 and 1'bx.

[0007] After extracting the truth table from the decoding table, the difficulty in generating the combinational logic expressions for each decoded signal using a conversion tool lies in the following: if the value of the decoded signal originates from the instruction encoding field under a certain instruction encoding, rather than a specific binary constant, then this field correspondence needs to be converted into a binary value correspondence that the conversion tool can recognize. For example, in the example in Table 1, dec_signal0[4:0] originates from the field inst_opcode[4:0] under the instruction encoding value 32'b0000_0000_0000_0000_0000_000_000x_xxxx. This field correspondence needs to be converted into a binary value relationship before it can be recognized by the conversion tool. There are currently two solutions to this difficulty:

[0008] Method 1: Truth Table Full Expansion Method. First, extract the value correspondence between the instruction code and the decoded signal from the decoding table; then, further process the value correspondence to determine if it is a field value relationship. If so, expand all field correspondences according to all possible binary values ​​of the field to generate a binary value correspondence that the conversion tool can recognize; otherwise, do not process the binary value relationship. Then, put all binary value correspondences into the truth table of the decoded signal; finally, generate the combinational logic expression of the decoded signal using the conversion tool. Assuming that the combinational logic expression of dec_signal0[4:0] is generated using Method 1, the three field correspondences with serial numbers 0, 1, and 5 in the decoding table shown in Table 1 need to be expanded according to all possible 5-bit binary values ​​of the field. For example, taking the expansion of the single field correspondence with serial number 0 as an example, such as... Figure 1 As shown, expanding the mapping between individual fields will add 2 to the truth table.WD0 =2 5 = 32 binary value correspondences. Therefore, generating the combinational logic representation of dec_signal0[4:0] ultimately requires adding 3*32=96 binary value correspondences to the truth table. However, adding only 96 binary value correspondences to the truth table is based on the premise that the decoding table is simple and the number of correspondences in the decoding signal fields is small. But in reality, the decoding table has many decoding signals and hundreds of instruction encoding values, resulting in a huge truth table. Since the truth table needs to be maintained manually, maintaining a huge truth table increases maintenance costs and the possibility of introducing errors.

[0009] Method 2: Decoding Signal Source Selection Method. First, determine the bit width of the one-hot code for the decoding signal source selection signal and which source each bit represents based on the decoding table. Then, construct a multiplexer (MUX) using combinational logic expressions, reserving an interface for the decoding signal source selection signal on the MUX. The input to the MUX includes all sources of the decoding signal, including the binary constants involved in the decoding signal values ​​and the instruction encoding field. The output of the MUX is the decoding signal, and the selection signal of the MUX is the decoding signal source selection signal. The number of channels in the MUX equals the bit width of the decoding signal source selection signal. Next, extract the correspondence between the instruction encoding and the binary values ​​of the decoding signal source selection signal from the decoding table and save it to the truth table of the decoding signal source selection signal. Finally, use a conversion tool to generate the combinational logic expression for the decoding signal source selection signal based on the truth table and connect it to the reserved interface of the MUX, thus forming the complete combinational logic expression for the decoding signal. Method 2 is used to generate the combinational logic expression for the decoded signal. The key is to generate the combinational logic expression for the source selection signal of the decoded signal. For example, Method 2 is used to generate the combinational logic expression for the source selection signal of dec_signal0[4:0]. Specifically, as shown below... Figure 2 As shown. Figure 2The source selection signal for dec_signal0[4:0] is inst_field_sel. Since dec_signal0[4:0] has 5 sources, namely 2 binary constant sources 5'b0_0000 and 5'b0_0001, and 3 instruction encoding sources inst_opcode[4:0], inst_opcode[12:8] and inst_opcode[31:27], the bit width of inst_field_sel is set to 5 bits. The one-hot code inst_field_sel[4:0] represents, from the high bit to the low bit, whether dec_signal0[4:0] is from inst_opcode[4:0], inst_opcode[12:8], inst_opcode[31:27], inst_field_sel[2:0], 5'b0_0000 and 5'b0_000 respectively under a certain instruction encoding. After confirming the definition of inst_field_sel[4:0], it is necessary to extract the correspondence between the instruction code and the binary values ​​of inst_field_sel[4:0] from the decoding table and transfer it to the truth table before the conversion tool can be used to generate the combinational logic expression of inst_field_sel[4:0]. Therefore, it can be seen that the combinational logic expression for generating the decoded signal using Method 2 does not directly extract the values ​​of the decoded signal from the decoding table. Instead, it uses the one-hot code value of the decoded signal source selection signal, generates the decoded signal source selection signal through the conversion tool, and finally generates the decoded signal through a multiplexer. This results in a complex decoding logic structure, and the staged generation of the decoded signal prevents the combinational logic expression from being globally optimized by the conversion tool. Summary of the Invention

[0010] The technical problem to be solved by this invention is to provide a method, system, and medium for generating combinational logic expressions for decoding components, addressing the aforementioned problems in the prior art. This invention can effectively control the size of the truth table and generate optimized combinational logic expressions. The truth table generated by this invention does not require manual maintenance, and the combinational logic expressions are directly extracted from the decoding table, which simplifies the logic structure of the decoding signal generated by the conversion tool.

[0011] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0012] A method for generating combinational logic expressions for a decoding component includes traversing W bits of a target decoded signal and generating a truth table for the w-th bit of the target decoded signal obtained by arbitrary traversal, wherein generating the truth table for the w-th bit of the target decoded signal obtained by arbitrary traversal includes:

[0013] S101, Initialize the loop variable n with possible values;

[0014] S102, iterate through the N possible values ​​of the instruction code and extract the nth possible value, where N is the number of possible values ​​of the instruction code;

[0015] S103, according to the decoding table, determine whether the w-th bit of the target decoded signal is derived from any x-th bit of the n-th possible value. If it is true, change the x-th bit of the n-th possible value from 1'bx to 1'b1, and retain the other bit values ​​to obtain the new value of the n-th possible value. Then, assign the new value of the n-th possible value to the w-th bit of the target decoded signal, which is 1'b1. Otherwise, the decoded signal value corresponding to the n-th possible value is derived from a fixed binary constant, either 1'b0 or 1'b1.

[0016] S104, input the correspondence between the nth possible value and the value of the wth bit of the target decoded signal into the truth table of the wth bit of the decoded signal;

[0017] S105, Update the value of the loop variable n (which may have multiple values);

[0018] S106, determine whether the value of the loop variable n is equal to the number of possible values ​​N of the instruction code. If not, jump to step S102; then determine that the W bits of the target decoded signal have been traversed.

[0019] Optionally, the number of possible values ​​N for the instruction encoding is 2. a , where a is the instruction encoding bit width.

[0020] Optionally, when initializing the possible value loop variable n in step S101, the initial value of the possible value loop variable n is 0; updating the value of the possible value loop variable n in step S105 means adding 1 to the original value of the possible value loop variable n.

[0021] Optionally, the step of traversing the W bits of the target decoded signal includes:

[0022] S201, initialize the bit loop variable w;

[0023] S202, extract the w-th bit of the target decoded signal by iterating through the W bits of the target decoded signal;

[0024] S203, Generate a truth table for the w-th bit of the target decoded signal obtained by traversal;

[0025] S204, Update the value of the bit loop variable w;

[0026] S205, determine whether the value of the bit loop variable w is equal to the bit width W of the target decoded signal. If not, jump to step S202; then determine that the W bits of the target decoded signal have been traversed.

[0027] Optionally, when initializing the bit loop variable w in step S201, the initial value of the bit loop variable w is 0; updating the value of the bit loop variable w in step S204 means adding 1 to the original value of the bit loop variable w.

[0028] Optionally, the target decoding signal is any one of the NUM decoding signals that the decoding unit needs to process, and before traversing the W bits of the target decoding signal, the step of traversing the NUM decoding signals is further included:

[0029] S301, initialize the decoding signal loop variable num;

[0030] S302, extract the num-th decoded signal from the NUM decoded signals that need to be processed;

[0031] S303, take the num-th decoded signal with a bit width of W obtained by traversal as the target decoded signal, perform traversal on the W bits of the target decoded signal, and generate a truth table for the w-th bit of the target decoded signal obtained by any traversal.

[0032] S304, Update the value of the decoding signal loop variable num;

[0033] S305, determine whether the value of the decoding signal loop variable num is equal to NUM. If not, jump to step S302; then determine that the NUM decoding signals have been traversed.

[0034] Optionally, when initializing the decoding signal loop variable num in step S301, the initial value of the decoding signal loop variable num is 0; updating the value of the decoding signal loop variable num in step S304 means adding 1 to the original value of the decoding signal loop variable num.

[0035] Optionally, after generating the truth table for the w-th bit of the target decoded signal obtained by arbitrary traversal, the method further includes using a conversion tool to generate a combinational logic expression for the w-th bit of the target decoded signal based on the truth table generated for the w-th bit of the target decoded signal.

[0036] Furthermore, the present invention also provides a system for generating combinational logic expressions of decoding components, including a microprocessor and a memory interconnected thereto, wherein the microprocessor is programmed or configured to execute the steps of the method for generating combinational logic expressions of decoding components.

[0037] Furthermore, the present invention also provides a computer-readable storage medium storing a computer program, the computer program being programmed or configured by a microprocessor to perform the steps of the method for generating the combinational logic expression of the decoding component.

[0038] The method for generating combinational logic expressions for the decoding component of this invention includes generating a truth table for any w-th bit of the W bits of the target decoded signal. This includes: for the nth possible value of N possible instruction codes, if the w-th bit originates from any x-th bit of the nth possible value, then the x-th bit of the nth possible value is changed from 1'bx to 1'b1, while other bit values ​​are retained to obtain a new value for the nth possible value. This new value is then assigned to the w-th bit of the target decoded signal as 1'b1. Otherwise, the nth possible value corresponds to either 1'b1 or 1'b0 of the w-th bit of the decoded signal. The correspondence between the nth possible value and the w-th bit of the target decoded signal is input into the truth table of the w-th bit of the decoded signal. Compared with the prior art, this invention has the following main advantages:

[0039] 1. This invention can effectively control the size of the decoding table. When the decoded signal value originates from an instruction encoding field under a certain instruction encoding, this invention expands the value correspondence from one to `width` bits, where `width` is the field width. Furthermore, the larger the number of bits in the field, the larger the `width` becomes. width The larger the difference, the smaller the size of the decoding table expanded by the method of the present invention compared to the full expansion of the truth table. Therefore, the method of the present invention can effectively control the size of the decoding table.

[0040] 2. This invention can generate optimized combinational logic expressions for decoded signals. The method of this invention only requires a small-scale expansion of the decoding table to directly generate the combinational logic expressions for decoded signals using a conversion tool, unlike the source selection method which requires a multiplexer to indirectly generate the combinational logic expressions. Therefore, compared to the source selection method, the combinational logic expressions generated by this invention can be globally optimized by the conversion tool, thus generating optimized combinational logic expressions for decoded signals.

[0041] 3. The truth table generated by the method of the present invention does not require manual maintenance. The combinational logic expression generated by the method of the present invention is directly extracted from the decoding table, thus simplifying the logic structure of the decoding signal generated by the conversion tool. Attached Figure Description

[0042] Figure 1 This is a schematic diagram illustrating the correspondence between the values ​​of the decoded signal and the instruction encoding field in the truth table full expansion method of existing technology.

[0043] Figure 2 This is a schematic diagram of the existing decoding signal source selection method.

[0044] Figure 3 This is a flowchart illustrating the core method of an embodiment of the present invention.

[0045] Figure 4This is a flowchart illustrating the method of an embodiment of the present invention.

[0046] Figure 5 This is a schematic diagram showing the correspondence between the values ​​of the decoded signal and the instruction encoding field in the method of this embodiment of the invention. Detailed Implementation

[0047] The method for generating the combinational logic expression of the decoding component in this embodiment includes traversing the W bits of the target decoded signal and generating a truth table for the w-th bit of the target decoded signal obtained by any traversal, such as... Figure 3 As shown, the truth table generated for the w-th bit of the target decoded signal obtained by arbitrary traversal includes:

[0048] S101, Initialize the loop variable n with possible values;

[0049] S102, iterate through the N possible values ​​of the instruction code and extract the nth possible value, where N is the number of possible values ​​of the instruction code;

[0050] S103, according to the decoding table, determine whether the w-th bit of the target decoded signal originates from any x-th bit of the n-th possible value. If so, change the x-th bit of the n-th possible value from 1'bx to 1'b1, and retain the other bit values ​​to obtain the new value of the n-th possible value. Then, assign the new value of the n-th possible value to the w-th bit of the target decoded signal, 1'b1. Otherwise, the decoded signal value corresponding to the n-th possible value originates from a fixed binary constant 1'b0 or 1'b1 (a binary constant 0 or 1), rather than from a bit of the n-th possible value.

[0051] S104, input the correspondence between the nth possible value and the value of the wth bit of the target decoded signal into the truth table of the wth bit of the decoded signal;

[0052] S105, Update the value of the loop variable n (which may have multiple values);

[0053] S106, determine whether the value of the loop variable n is equal to the number of possible values ​​N of the instruction code. If not, jump to step S102; then determine that the W bits of the target decoded signal have been traversed.

[0054] The number of possible values ​​N for the instruction code can be determined based on the instruction code bit width. a In this embodiment, the number of possible values ​​N for the instruction encoding is 2. a , where a is the instruction encoding bit width.

[0055] In step S101 of this embodiment, when initializing the possible value loop variable n, the initial value of the possible value loop variable n is 0; in step S105, updating the value of the possible value loop variable n means adding 1 to the original value of the possible value loop variable n.

[0056] See Figure 4 This embodiment involves traversing the W bits of the target decoded signal, including:

[0057] S201, initialize the bit loop variable w;

[0058] S202, extract the w-th bit of the target decoded signal by iterating through the W bits of the target decoded signal;

[0059] S203, Generate a truth table for the w-th bit of the target decoded signal obtained by traversal;

[0060] S204, Update the value of the bit loop variable w;

[0061] S205, determine whether the value of the bit loop variable w is equal to the bit width W of the target decoded signal. If not, jump to step S202; then determine that the W bits of the target decoded signal have been traversed.

[0062] See Figure 4 In this embodiment, when initializing the bit loop variable w in step S201, the initial value of the bit loop variable w is 0; updating the value of the bit loop variable w in step S204 means adding 1 to the original value of the bit loop variable w.

[0063] See Figure 4 In this embodiment, the target decoding signal is any one of the NUM decoding signals that the decoding unit needs to process. Before traversing the W bits of the target decoding signal, the step of traversing the NUM decoding signals is also included:

[0064] S301, initialize the decoding signal loop variable num;

[0065] S302, extract the num-th decoded signal from the NUM decoded signals that need to be processed;

[0066] S303, take the num-th decoded signal with a bit width of W obtained by traversal as the target decoded signal, perform traversal on the W bits of the target decoded signal, and generate a truth table for the w-th bit of the target decoded signal obtained by any traversal.

[0067] S304, Update the value of the decoding signal loop variable num;

[0068] S305, determine whether the value of the decoding signal loop variable num is equal to NUM. If not, jump to step S302; then determine that the NUM decoding signals have been traversed.

[0069] See Figure 4In this embodiment, when initializing the decoding signal loop variable num in step S301, the initial value of the decoding signal loop variable num is 0; updating the value of the decoding signal loop variable num in step S304 means adding 1 to the original value of the decoding signal loop variable num.

[0070] In this embodiment, after generating a truth table for the w-th bit of the target decoded signal obtained by arbitrary traversal, the method further includes using a conversion tool to generate a combinational logic expression for the w-th bit of the target decoded signal based on the truth table generated from the w-th bit of the target decoded signal. Since using a conversion tool to generate the combinational logic expression for the w-th bit of the target decoded signal based on the truth table generated from the w-th bit of the target decoded signal is an existing method, its implementation details will not be described here.

[0071] like Figure 4 As shown, the complete steps of the method in this embodiment include: 1) starting to generate all combinational logic expressions for NUM decoded signals; 2) generating combinational logic expressions for all bits of the first decoded signal, num = 0; 3) generating combinational logic expressions starting from the 0th bit of the num-th decoded signal, w = 0, and the bit width of the num-th decoded signal is W; 4) generating the truth table for the w-th bit of the num-th decoded signal; 5) continuing to generate the truth table for the next bit of the num-th decoded signal, w = w + 1; 6) checking if w is equal to W. If w is equal to W, it means that all bits of the num-th decoded signal have been generated. If the combinational logic expression is generated, proceed to step 7); if w is not equal to W, it means that some bits of the num-th decoded signal have not yet generated a combinational logic expression, so proceed to step 4); 7) Continue generating the combinational logic expression for all bits of the next decoded signal, num = num + 1; 8) Check if num is equal to NUM. If num is equal to NUM, it means that all bits of all decoded signals have generated their combinational logic expressions, so proceed to step 9); if num is not equal to NUM, it means that some bits of the decoded signal have not yet generated their combinational logic expressions, so proceed to step 3); 9) End.

[0072] The detailed steps of step 4) are as follows: 4-1) Generate a correspondence between the first possible value of the instruction code and the value of the w-th bit of the decoded signal, starting from the first possible value of the instruction code, n = 0, the total number of possible values ​​of the instruction code is N, and N equals 2^(instruction code bit width); 4-2) Determine whether the w-th bit of the decoded signal originates from a bit of the n-th possible value of the instruction code, i.e., the x-th bit, according to the decoding table. If yes, jump to step 4-4); if not, jump to step 4-3); 4-3) The n-th possible value of the instruction code corresponds to the value 1'b1 or 1'b0 of the w-th bit of the decoded signal, jump to step 4-6); 4-4) Change the x-th bit of the n-th possible value of the instruction code from 1'bx to 1'b1, and retain the other bit values ​​of the n-th possible value of the instruction code to obtain the new value of the n-th possible value of the instruction code; 4-5) Instruction encoding The new value of the nth possible value corresponds to the value 1'b1 of the wth bit of the decoded signal; 4-6) Input the correspondence between the nth possible value of the instruction code and the value of the wth bit of the decoded signal into the truth table of the wth bit of the decoded signal; 4-7) Continue to generate the correspondence between the next possible value of the instruction code and the value of the wth bit of the decoded signal, n = n + 1; 4-8) Check if n is equal to N. If n is equal to N, it means that the correspondence between all possible values ​​of the instruction code and the value of the wth bit of the decoded signal has been saved into the truth table of the wth bit of the decoded signal, then jump to step 4-9); if n is not equal to N, it means that some possible values ​​of the instruction code have not yet been determined to correspond to the value of the wth bit of the decoded signal, then jump to step 4-2); 4-9) The conversion tool generates the combinational logic expression of the wth bit of the decoded signal according to the truth table of the wth bit of the decoded signal.

[0073] In summary, the method for generating combinational logic expressions for the decoding component in this embodiment includes the following steps: First, the method independently generates a truth table for each bit of the decoded signal based on the decoding table. Second, when a bit of the decoded signal originates from a bit of the instruction encoding field under a certain instruction encoding, the bit from that instruction encoding is changed from 1'bx to 1'b1, forming a new value for that instruction encoding. This new value is then input into the truth table, forming a new correspondence between the decoded signal and the instruction encoding. Third, when the bit of the decoded signal is a constant value (1'b0 or 1'b1) under other instruction encodings, no special processing is required; the existing value correspondence is simply input into the truth table. Finally, a conversion tool is used to convert the truth table into a combinational logic expression for that bit of the decoded signal. Repeating the above steps several times according to the number of bits in the decoded signal yields the complete combinational logic expression for the decoded signal. The method for generating combinational logic expressions for the decoding component in this embodiment has the following advantages: 1. The method in this embodiment can effectively control the size of the decoding table. In the decoding table, when the value of the decoded signal originates from the instruction encoding field under a certain instruction encoding, the method in this embodiment will expand the value correspondence from 1 to `width` values, where `width` is the field width. For example, using the method in this embodiment to expand the value correspondence of `dec_signal0[4:0]` from a certain instruction encoding, such as... Figure 5 As shown, comparison Figure 1 and Figure 5 It can be observed that the method of the present invention only needs to expand the above value relationship from 1 to a value correspondence between the decoding signal and the instruction encoding with width = 5, in order to obtain the combinational logic expression of the decoding signal, while the truth table full expansion method requires expansion to 2 width =2 5 Only by establishing the correspondence between the values ​​of each decoded signal and the instruction code can this be obtained. Furthermore, the larger the number of bits in the field, the greater the difference between width and 2. width The larger the difference, the smaller the size of the decoding table expanded by the method in this embodiment compared to the full truth table expansion method. Therefore, the method in this embodiment can effectively control the size of the decoding table. 2. The method in this embodiment can generate optimized combinational logic expressions for the decoded signal. The method in this embodiment only needs to expand the decoding table on a small scale to directly generate the combinational logic expressions for the decoded signal through the conversion tool, unlike the decoding signal source selection method which requires a multiplexer to indirectly generate the combinational logic expressions for the decoded signal. Therefore, compared to the decoding signal source selection method, the combinational logic expressions generated by the method in this embodiment can be globally optimized by the conversion tool, thereby generating optimized combinational logic expressions for the decoded signal.

[0074] Furthermore, this embodiment also provides a system for generating combinational logic expressions for decoding components, including a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to execute the steps of the aforementioned method for generating combinational logic expressions for decoding components. Additionally, this embodiment also provides a computer-readable storage medium storing a computer program for being programmed or configured by a microprocessor to execute the steps of the aforementioned method for generating combinational logic expressions for decoding components.

[0075] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0076] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A method for generating combinational logic expressions for decoding components, characterized in that, This includes iterating through the W bits of the target decoded signal and generating a truth table for the w-th bit of the target decoded signal obtained by any iteration, wherein generating the truth table for the w-th bit of the target decoded signal obtained by any iteration includes: S101, Initialize the loop variable n with possible values; S102, iterate through the N possible values ​​of the instruction code and extract the nth possible value, where N is the number of possible values ​​of the instruction code; S103, according to the decoding table, determine whether the w-th bit of the target decoded signal is derived from any x-th bit of the n-th possible value. If it is true, change the x-th bit of the n-th possible value from 1'bx to 1'b1, and retain the other bit values ​​to obtain the new value of the n-th possible value. Then, assign the new value of the n-th possible value to the w-th bit of the target decoded signal, which is 1'b1. Otherwise, the decoded signal value corresponding to the n-th possible value is derived from a fixed binary constant, either 1'b0 or 1'b1. S104, input the correspondence between the nth possible value and the value of the wth bit of the target decoded signal into the truth table of the wth bit of the decoded signal; S105, Update the value of the loop variable n (which may have multiple values); S106, determine whether the value of the loop variable n is equal to the number of possible values ​​N of the instruction code. If not, jump to step S102; then determine that the W bits of the target decoded signal have been traversed.

2. The method for generating combinational logic expressions for decoding components according to claim 1, characterized in that, The number of possible values ​​N for the instruction encoding is 2. a , where a is the instruction encoding bit width.

3. The method for generating combinational logic expressions for decoding components according to claim 1, characterized in that, When initializing the possible value loop variable n in step S101, the initial value of the possible value loop variable n is 0; updating the value of the possible value loop variable n in step S105 means adding 1 to the original value of the possible value loop variable n.

4. The method for generating combinational logic expressions for decoding components according to claim 1, characterized in that, The step of traversing the W bits of the target decoded signal includes: S201, initialize the bit loop variable w; S202, extract the w-th bit of the target decoded signal by iterating through the W bits of the target decoded signal; S203, Generate a truth table for the w-th bit of the target decoded signal obtained by traversal; S204, Update the value of the bit loop variable w; S205, determine whether the value of the bit loop variable w is equal to the bit width W of the target decoded signal. If not, jump to step S202; then determine that the W bits of the target decoded signal have been traversed.

5. The method for generating combinational logic expressions for decoding components according to claim 4, characterized in that, In step S201, when initializing the bit loop variable w, the initial value of the bit loop variable w is 0; in step S204, updating the value of the bit loop variable w means adding 1 to the original value of the bit loop variable w.

6. The method for generating combinational logic expressions for decoding components according to claim 1, characterized in that, The target decoding signal is any one of the NUM decoding signals that the decoding unit needs to process. Before traversing the W bits of the target decoding signal, the step of traversing the NUM decoding signals is also included: S301, initialize the decoding signal loop variable num; S302, extract the num-th decoded signal from the NUM decoded signals that need to be processed; S303, take the num-th decoded signal with a bit width of W obtained by traversal as the target decoded signal, perform traversal on the W bits of the target decoded signal, and generate a truth table for the w-th bit of the target decoded signal obtained by any traversal. S304, Update the value of the decoding signal loop variable num; S305, determine whether the value of the decoding signal loop variable num is equal to NUM. If not, jump to step S302; then determine that the NUM decoding signals have been traversed.

7. The method for generating combinational logic expressions for decoding components according to claim 6, characterized in that, In step S301, when initializing the decoding signal loop variable num, the initial value of the decoding signal loop variable num is 0; in step S304, updating the value of the decoding signal loop variable num means adding 1 to the original value of the decoding signal loop variable num.

8. The method for generating combinational logic expressions for decoding components according to claim 1, characterized in that, After generating the truth table for the w-th bit of the target decoded signal obtained by arbitrary traversal, the method further includes using a conversion tool to generate the combinational logic expression for the w-th bit of the target decoded signal based on the truth table generated for the w-th bit of the target decoded signal.

9. A system for generating combinational logic expressions for decoding components, comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is programmed or configured to perform the steps of the method for generating combinational logic expressions of the decoding components according to any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, The computer program is used to be programmed or configured by a microprocessor to perform the steps of the method for generating combinational logic expressions of the decoding components according to any one of claims 1 to 8.

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