A hard-core interface module for APF control system

Abstract

The present invention discloses a hard-core interface module of an APF control system, which communicates with an MCU by reading and writing a dual-port RAM; the input signals of the top-level entity of the hard-core interface module include: a clock signal, waveform data, slave board data, slave board status, dual-port RAM read-write status, a fault signal, and a notification signal; the output signals of the top-level entity of the hard-core interface module include: a first enable signal, data output, address output, command output, and a notification signal. The hard-core interface module of the APF control system controls the real-time operation of various electrical data, switch status, stability of the running line and other important information of the power grid system collected by the hard-core, and timely displays them on the control terminal while transmitting the configuration parameters issued by the terminal, so as to realize real-time control of the operation status of the power grid system.

Description

Technical Field

[0001] The present invention relates to the technical field of APF control systems, and in particular to a hard-core interface module of an APF control system. Background Art

[0002] Electrical information data and operating status data play a key role in the safe and stable operation of the entire power system, so it is necessary to monitor various operating parameters of the power grid in real time and analyze the operating quality of the power grid based on the collected data to coordinate and optimize the power grid. The power grid quality and the operation of the active power filter device need to be monitored by the terminal monitoring system. Through unified monitoring and management of the power grid system, the operating efficiency can be improved and the risk of failure can be controlled within a controllable range.

[0003] How to efficiently and timely feed back the large amount of complex data generated by the APF control system with multiple computing modules working together to the control terminal, and at the same time save and send the configuration parameters issued by the control terminal to the relevant modules in the APF control system to achieve efficient monitoring and management of the power grid system, is a problem that technical personnel in this field need to face. Summary of the invention

[0004] In view of the technical problems currently existing in the art, in a first aspect, the present invention discloses a hard-core interface module of an APF control system, wherein the hard-core interface module communicates with an MCU by reading and writing a dual-port RAM;

[0005] The input signals of the top-level entity of the hard-core interface module include: clock signal, waveform data, slave board data, slave board status, dual-port RAM read and write status, fault signal, and notification signal;

[0006] The output signal of the top-level entity of the hard core interface module includes: a first enable signal, a data output, an address output, a command output, and a notification signal; the command output includes a command sent by the MCU to the hard core;

[0007] The bottom layer modules of the hard core interface module include:

[0008] Status monitoring module: used for monitoring the dual-port RAM and outputting the read and write status of the dual-port RAM;

[0009] Waveform data writing module: used for writing the waveform data collected from the grid side or from the output side of the APF control system into the dual-port RAM, the waveform data including voltage waveform data and / or current waveform data;

[0010] A slave board data writing module: used for writing the slave board data and the slave board status into the dual-port RAM;

[0011] Command writing and reading module: used for writing the command sent by the MCU to the hard core into the dual-port RAM;

[0012] Parameter transfer module: used to control the transfer of configuration parameters between the MCU and the hard core;

[0013] Fault signal writing module: used for writing the fault signal into the dual-port RAM and modifying the fault pointer information at the same time;

[0014] Time-sharing multiplexing module: used to control the time-sharing multiplexing of reading and writing of the dual-port RAM by all the above-mentioned bottom modules;

[0015] The multiplexing module is configured to: send a second enable signal to the status detection module when it is determined that the dual-port RAM is not occupied; and the status detection module is configured to: start working after receiving the second enable signal.

[0016] In a second aspect, the present invention proposes an APF, including a main board, wherein the main board is electrically connected to at least three devices, each device includes three slave boards, and the three slave boards are respectively an A-phase slave board, a B-phase slave board, and a C-phase slave board.

[0017] In a third aspect, the present invention proposes an APF control system, which includes a hard core implemented based on FPGA, an MCU and a dual-port RAM for communication between the hard core and the MCU, and the APF control system also includes the above-mentioned hard core interface module.

[0018] Through the hard-core interface module of the APF control system, the various electrical data, switch status, stability of the running lines and other important information of the power grid system collected by the hard-core control are displayed on the control terminal in a timely manner, and the configuration parameters issued by the terminal are transmitted, so as to realize real-time control of the operation status of the power grid system. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 , one Top-level entity diagrams of some hard-core interface modules;

[0020] Figure 2 , one The underlying modules of some hard-core interface modules;

[0021] Figure 3 , one Schematics of some hard-core interface modules;

[0022] Figure 4 , one Some APF structure diagrams. DETAILED DESCRIPTION

[0023] First, the terms of the present invention are explained as follows:

[0024] FPGA, Field Programmable Gate Array, preferably Intel's Agilex TM , and uses Intel's Develop. MCU (microcontroller unit), based on soft core implementation, preferably Nios II fast core. Avalon interface: used for high-speed data stream transmission, reading and writing registers, memory and control of off-chip devices, UART: Universal Asynchronous Receiver / Transmitter. JTAG: Test Access Interface. SDRAM: Synchronous Dynamic Random Access Memory. "Program" can be written in any form of programming language, including compiled language or interpreted language or declarative language or procedural language, and can be expanded in any form, including as an independent program or as a module, component, subroutine or other unit suitable for use in a computing environment. The program can but does not have to correspond to a file in a file system. The term "time division multiplexing (TDM)" can achieve the purpose of multiple-channel transmission by using different time periods of the same physical connection to transmit different signals. In the present invention, this term is mainly aimed at processing the spatial optimization requirements when more than two modules are needed in the FPGA design, and the spatial optimization of multiple modules with the same functions that are not used at the same time.

[0025] The technical solution of the present invention is described below in conjunction with the accompanying drawings.

[0026] Some hard-core interface modules communicate with the MCU by reading and writing dual-port RAM. The top-level entity of the hard-core interface module is as follows Figure 1 As shown, the input signal includes: clock signal, waveform data, slave board data, slave board status, dual-port RAM read and write status, fault signal, and notification signal; the output signal includes: enable signal, data output (Data_out), address output (Add_out), command output, and notification signal; the command output includes the command sent by the MCU to the hard core;

[0027] Some hard-core interface modules include Figure 2 The main low-level modules in:

[0028] Status monitoring module: monitors the dual-port RAM and outputs the read and write status of the dual-port RAM;

[0029] Waveform data writing module: used for writing the voltage waveform data and current waveform data into the dual-port RAM;

[0030] A slave board data writing module: used for writing the slave board data and the slave board status into the dual-port RAM;

[0031] Command writing and reading module: used for writing the command sent by the MCU to the hard core into the dual-port RAM;

[0032] Parameter transfer module: used to control the transfer of configuration parameters between the MCU and the hard core;

[0033] Fault signal writing module: used for writing the fault signal into the dual-port RAM and modifying the fault pointer information at the same time;

[0034] Time-sharing multiplexing module: used to control the time-sharing multiplexing of reading and writing of the dual-port RAM by all the above-mentioned bottom-level modules.

[0035] The multiplexing module is configured to: send a second enable signal to the status detection module when it is determined that the dual-port RAM is not occupied; and the status detection module is configured to: start working after receiving the second enable signal.

[0036] The principles of some hard-core interface modules are as follows Figure 3 , the communication between the hard core and the MCU is realized through the dual-port RAM, where the dual-port RAM consists of five read-write consistent RAM blocks, which are configured as:

[0037] The first RAM block is used to store the read and write status of the dual-port RAM;

[0038] The second RAM block is used to store the waveform data, the slave board data, and the slave board status;

[0039] The third RAM block is used to store cache data including data for query by the MCU;

[0040] Fourth RAM block: used to store data exchanged between the hard core and the MCU;

[0041] The fifth RAM block: used to store fault codes.

[0042] The state detection module of some embodiments is configured to: perform state detection on the dual-port RAM at regular intervals;

[0043] The state detection module sends the state of the dual-port RAM to any one or more modules of the command writing and reading module, the parameter transfer module, the fault signal writing module, and the waveform data writing module;

[0044] After receiving the status of the dual-port RAM, any one or more of the command writing and reading module, the parameter transfer module, the fault signal writing module, and the waveform data writing module sends a request RAM instruction to the time-sharing multiplexing module.

[0045] The hard core interface module of some embodiments also performs the following steps: the time-sharing multiplexing module writes the command reading module, the parameter transfer module, the fault signal writing module, the waveform data writing module, and the status detection module in order from high to low priority, allowing the request RAM instruction of the corresponding module.

[0046] Some of the submodules of the parameter passing module include:

[0047] MCU configuration parameter cache module: used to read configuration parameters from the external memory and store them in the internal memory, wherein the configuration parameters are configuration parameters modified by the MCU; read the configuration parameters in the internal memory and write them into the external memory;

[0048] Update and initialization module: when the data of the APF control system is updated, it is used to send the index directory and value of the configuration parameters to: the waveform data writing module used to check whether the mutual inductor value has changed; the UART module used to notify the slave board to check whether the value of the configuration parameter needs to be modified; the protection module used to check whether the configuration parameter has been modified; the DFT module used to check whether the configuration parameter needs to be modified;

[0049] The configuration data caching module is used to cache the configuration parameters sent by the control terminal of the APF control system.

[0050] In some more specific implementations, the waveform data writing module includes a sampling writing module and a sampling data processing module, wherein:

[0051] Detection module: detects the read and write status of the dual-port RAM every 400Ms, and sends a write signal to the dual-port RAM if the dual-port RAM is in an idle state;

[0052] Sampling signal sending module: sends a sampling signal every 7811 clock cycles to control the sampling writing module to perform writing;

[0053] A sampling and writing module is used to collect the waveform data, generate a write enable signal, a write address and write data, and write the waveform data into the second RAM block at one time.

[0054] The waveform data includes voltage waveform data and / or current waveform data, specifically: three-phase grid voltage waveform data, three-phase grid current waveform data, three-phase load current waveform data, three-phase total compensation current waveform data;

[0055] Sampling data processing module: used to convert the waveform data into actual values.

[0056] In some more specific implementations, the submodules of the sampling writing module include:

[0057] A second RAM block status monitoring module: used for querying the second RAM block status at regular intervals and sending a write instruction to the second RAM block;

[0058] Sampling execution module: used for executing the acquisition of the waveform data;

[0059] Auxiliary sampling control module: used to send sampling commands to the sampling execution module at regular intervals.

[0060] The configuration of the MCU in some embodiments is implemented by embedding the Nios II architecture on the FPGA, specifically including the following steps:

[0061] Loading a soft core based on the Nios II architecture on the FPGA implements the CPU function of the MCU;

[0062] Based on the Nios II architecture, multiple functional modules including Avalon-MM tri-state bridge, UART module, Jtag port debugging module, SDRAM controller module, several interval timers, flash memory interface, and several parallel IO ports are integrated.

[0063] Some structures such as Figure 4 The APF shown includes a main board, which is electrically connected to at least three devices, each of which includes three slave boards, and the three slave boards are respectively an A-phase slave board, a B-phase slave board, and a C-phase slave board.

[0064] Some APF control systems include a hard core implemented based on FPGA, an MCU, and a dual-port RAM for communication between the hard core and the MCU. The hard core also includes a hard core interface module as in any of the above embodiments.

[0065] A dual-port RAM is opened inside the FPGA to realize the communication between the MCU and the hard core. The size of the dual-port RAM in this specific embodiment is 1024bit×64bit. The dual-port RAM is divided into 5 blocks, namely RAM#1, RAM#2, RAM#3, RAM#4, and RAM#5. Each RAM block stores different data. A 32-bit MCU is configured, which has a 32bit×32bit multiplier inside. After actual testing, the MCU works relatively stably at 50M. The interface signal between the hard core and the MCU and the dual-port RAM is fixed. There is no direct signal exchange between the hard core and the MCU, and it is transferred by the dual-port RAM.

[0066] Dual-port RAM has two completely independent sets of data lines, address lines and read-write control lines on an SRAM memory, and allows two independent systems to randomly access the memory at the same time. It is a shared multi-port memory that allows the MCU or the hard core to randomly read or write it at the same time, but does not allow the MCU to read and write an address unit at the same time, nor does it allow the hard core to read and write the same address unit.

[0067] After the MCU (or FPGA hard core) prepares the address and data to be written on address_a and data_a, it can send a write command. The pulse width of the write command must be at least 1 global clock length (50M), and it is not allowed to exceed 5 global clock lengths, otherwise the dual-port RAM will be written twice; the above-mentioned dual-port RAM write function, when the main frequency is 50M, has been tested in practice, and the command pulse width is 10M. Address_a and data_a can only change after wren_a is low, otherwise the wrong data will be written to the wrong address. It takes about 4 global clocks to write a dual-port RAM once.

[0068] When the MCU reads the address unit that the hard core is writing, the data read by the MCU is the historical value of the address unit; when the hard core reads the address unit that the MCU is writing, the data read by the hard core is also the historical value of the address unit. However, when the MCU and the hard core write to the same address at the same time, the value of the address unit is uncertain. The historical value is saved to the cache module.

[0069] The present invention is explained below by a specific embodiment.

[0070] Example 1

[0071] 1. Design of embedded MCU interface

[0072] Build the MCU interface module in Quartus, and the types and functions of its pins are listed in Table 1.

[0073] Table 1. MCU interface function table

[0074]

[0075]

[0076]

[0077] The MCU interface based on the Nios II soft-core processor integrates many modules. The main modules are described in Table 2:

[0078] Table 2. Description of each main module of MCU interface

[0079] name describe CPU Nios II Processor tri_state_bridge_0 Avalon-MM Tri-State Bridge Button Parallel IO port led Parallel IO port RS232 Universal asynchronous serial port (UART) module, using 232 level RS232_485 Universal asynchronous serial port (UART) module, using 232 level RS232_dis Universal asynchronous serial port (UART) module, using 232 level jtag_uart_0 Jtag port debugging module CFI_FLASH Flash memory interface SDRAM SDRAM Controller PIO_In Parallel IO port PIO_Out Parallel IO port sysid SystemIDPeripheral Timer_1 Interval timer Timer_2 Interval timer Sys_State Parallel IO port RAM_Control Parallel IO port RAM_Addr Parallel IO port RAM_Data_A Parallel IO port RAM_Data_B Parallel IO port RAM_Byte_En Parallel IO port

[0080] 2. Design of hard-core read-write RAM

[0081] In order to implement the hard core read and write RAM operations, thereby realizing information exchange between the MCU and the hard core, the input and output signal definitions of the top-level entity of the hard core interface module are shown in Table 3.

[0082] Table 3. Input and output signal definitions of top-level entities

[0083]

[0084]

[0085] The following table shows the interface signals of the hard core and dual-port RAM. Byteena_a is the write byte enable signal, which divides the 64-bit data written to the RAM into 8 bytes, corresponding to the 8 bits of byteena_a. When the corresponding bit is high, the byte can be written to the corresponding address unit, and the other byte data in the address unit remain unchanged from the previous historical value.

[0086] The interface signals between the MCU and the dual-port RAM are similar, except that there is an additional clock matching module in the middle to avoid multiple writes or reads to the dual-port RAM.

[0087] Table 4. Interface signals between hard core and dual-port RAM

[0088] Signal width illustrate data_a 64bit Write data to dual-port RAM address_a 10bit Read or write the address of the dual-port RAM wren_a 1bit Write request signal for dual-port RAM rden_a 1bit Read request signal of dual-port RAM byteena_a 8bit Byte enable signal for writing dual-port RAM q_a 64bit Dual-port RAM output data

[0089] The following is a detailed explanation of each underlying module:

[0090] 2.1 Condition Monitoring Module

[0091] This module is equivalent to the control register area, completing the output of all RAM read and write status. Table 5 is the definition of the main input and output signals of this module.

[0092] Table 5. Input and output signals of status monitoring submodule

[0093]

[0094]

[0095] It should be noted that when the RAM is in an idle state, the state of the RAM block is detected every 1ms. The signal En comes from the time-sharing multiplexing submodule. When the time-sharing multiplexing module determines that the current RAM is not occupied, En is high level, notifying the RAM state monitoring module to start working.

[0096] 2.2 Waveform data writing module

[0097] This module is used to control the FPGA hard core to write waveform data into the second RAM block for MCU to read and display. Table 6 is the definition of the main input and output signals of this module. This module includes a sampling writing module and a sampling data processing module.

[0098] Table 6 Definition of main input and output signals of waveform data writing module

[0099]

[0100] The function of the sampling data processing module is to convert the sampled voltage and current data into actual values. It should be noted that the relationship between the actual value of the grid voltage and the sampled value is:

[0101]

[0102] Among them U s is the actual value of the grid voltage, U s ’ is the sampling value. The 2849 in the program is also derived from this.

[0103] The relationship between the actual value and the sampled value of the grid current is:

[0104]

[0105] where i s is the actual value of the grid voltage, i s ’ is the sampling value. N represents the turns ratio of the external current transformer. This parameter is sent through the screen and processed and identified by the FPGA_MCU_APF_Grid_Cur_Index_Rd module. The current sampling on the APF output side is the same as the current sampling on the grid side, so the processing method is the same.

[0106] The sampling writing module consists of the following small modules, which supports parallel computing of multiple small modules.

[0107] 2.2.1 Second RAM block status monitoring module FPGA_MCU_RAM_Sample

[0108] The function is to check the status of RAM#2 every 400ms. If the MCU is shown as idle, it starts to send a signal to write to the RAM block, indicating that the RAM is being used;

[0109] 2.2.2 Auxiliary sampling control module FPGA_MCU_RAM_Volt_Cur_Sample_Control

[0110] Its function is to send out a sampling signal every 7811 clock cycles (because the voltage and current waveform data are both 128 points / cycle) to control the sampling execution module to collect data from twelve channels.

[0111] 2.2.3 Sampling execution module FPGA_MCU_RAM_Volt_Cur

[0112] Execute data collection of twelve channels, namely ABC three-phase grid voltage, ABC three-phase grid current, ABC three-phase load current and ABC three-phase total compensation current. Each data is a point, and a write enable signal, write address, write data, etc. are generated, and written to the corresponding position in RAM at one time.

[0113] 2.3 Write data from the board to the module

[0114] The function of this module is to write the voltage, current, temperature, protection and other data sent from the controller into RAM. The main input and output signal definitions of the submodule of writing data from the controller to RAM are shown in Table 7:

[0115] Table 7. Slave controller data write RAM control submodule

[0116] Signal type significance Index_St Notification signal input Notify the module that it can start working Slave_Index_1A[63..0] Data Entry Phase A data from board Slave_Index_1B[63..0] Data Entry Phase data from plate B Slave_Index_1C[63..0] Data Entry Phase C data from board Slave_State_1A[7..0] Status Input Protect data from board A phase Slave_State_1B[7..0] Status Input Protect data from board B Slave_State_1C[7..0] Status Input Protect data from board C phase Wr_Req Notification Output Write RAM enable signal Addr[9..0] Address signal output Write RAM address Byte_En[7..0] Byte enable signal output Byte Enable Wr_Data[63..0] Write data output Write RAM data RAM_Next Notification signal output Notification signal

[0117] 2.4 Command writing and reading module

[0118] The function of this module is to write the commands from the MCU interface to the FPGA hard core into the RAM, and then the FPGA hard core reads the commands. The main input and output signal definitions are shown in Table 8:

[0119] Table 8. Main input and output signals of command writing and reading submodule

[0120] Signal type significance Rd_St Notification signal input Notify the module that it can start working RAM_3_W_Ord[15..0] Command signal input Write command pointer RAM_3_R_Ord[15..0] Command signal input Read command pointer RAM_Data[63..0] Data Entry Data written to RAM RAM_Command Command signal input Notification signal after command reading Wr_Req Notification signal output Write RAM enable signal Addr[9..0] Address signal output Write RAM address Byte_En[7..0] Byte enable signal output Byte Enable Wr_Data[63..0] Write data output Write RAM data Rd_Req Notification signal output Read RAM enable signal Confi_Rd_St Notification signal output Notification signal

[0121] 2.5 Parameter passing module

[0122] The function of this module is to control the parameter transfer between MCU and FPGA hard core. The main input and output signal definitions are shown in Table 9:

[0123] Table 9. Main input and output signals of parameter transfer submodule

[0124]

[0125] The parameter transfer submodule consists of three small modules:

[0126] 2.5.1MCU configuration parameter cache module FPGA_MCU_RAM_Config_Rd

[0127] The function is that when the MCU modifies the parameters, the module reads the modified parameters from the external RAM and caches the parameters in the internal RAM to facilitate parameter recall. When the MCU requests the main controller parameters, it reads the parameters in the internal RAM and then writes the parameters to the external RAM for final display on the screen.

[0128] It should be noted that the external RAM is not in the main controller of the APF control system.

[0129] 2.5.2 Update and initialize module FPGA_RAM_Config_RAM_Control

[0130] When data update or power-on signal is detected, the module sends the index directory (Sys_Index) and value of the system configuration parameters stored in RAM to the following modules: waveform writing module, to check whether the mutual inductor value has changed; UART module, to notify the slave board to check whether the corresponding data needs to be modified; protection module, to check whether the corresponding parameters have been modified; DFT module, to check whether the corresponding parameters need to be modified. This module is mainly used to update and initialize system data. When the mainboard program needs to use configuration parameters, it detects the three parameters Sys_Config_Ud, Sys_Index, and Cof_RAM_Data to determine whether the control terminal has issued new configuration parameters, thereby updating the parameters. Whenever the configuration data is issued, the module first caches the changed data into the configuration data cache module, and then reads all the parameters in the RAM from beginning to end. Each time a parameter is read, Sys_Config_Ud is pulled high once, Sys_Index outputs the index corresponding to the currently read configuration parameter, and Cof_RAM_Data outputs the parameter value.

[0131] 2.5.3 Send configuration data cache module FPGA_MCU_Config_RAM

[0132] Cache all configuration data sent from the control terminal screen.

[0133] 2.6 Fault signal writing module

[0134] The function of this module is to write the fault information into RAM and modify the fault pointer information in RAM when a fault occurs in the hard core. The definition of input and output signals is shown in Table 10:

[0135] Table 10. Main input and output signals of fault signal writing submodule

[0136]

[0137]

[0138] 2.7 Time-division multiplexing module

[0139] The function of this module is to time-multiplex the read and write signals of the above modules to the RAM, to prevent multiple modules from reading or writing to the RAM at the same time. The definition of input and output signals is shown in Table 11.

[0140] Table 11. Definition of input and output signals of time-division multiplexing submodule

[0141]

[0142]

[0143] 3.APF

[0144] The structure of APF is as follows Figure 4 , wherein the main controller is implemented based on FPGA. ,Method for defining device ID: the main controller automatically assigns ID through the ,number of the optical fiber communication interface.

[0145] The three-phase IDs of device 1 are: 0x010A, 0x010B, 0x010C;

[0146] The three-phase IDs of device 2 are: 0x020A, 0x020B, 0x020C;

[0147] The three-phase IDs of device 3 are: 0x030A, 0x030B, 0x030C;

[0148] When the ID is 0x0100, 0x0200, 0x0300, ..., it means that it refers to a certain device (including ABC three-phase), and 0xAAAA refers to all devices.

[0149] 4. Hard core and MCU

[0150] like Figure 3The main controller consists of two modules: the hard core part and the MCU.

[0151] The hard core mainly includes data acquisition submodule, grid voltage phase-locked submodule, sliding window DFT submodule, grid-side PR regulator submodule, reactive DQ extraction submodule, harmonic injection reference generation submodule, APF working mode selection submodule, high-speed optical fiber communication interface submodule, etc. It also includes some auxiliary submodules, such as hardware protection, timing control, MCU data interface submodule and contactor control submodule, etc.; the control of the DC side voltage is realized from the controller.

[0152] The hard core part is responsible for processing the main functions of APF, including harmonic extraction, reference synthesis, high-speed asynchronous serial communication, etc. This part has high real-time requirements, fast computing speed, and mostly pipeline processing; MCU is responsible for processing content that does not require high real-time performance, mainly including user interactive display communication. In this implementation, a 32-bit MCU is configured, which has a 32-bit×32-bit multiplier inside. The operating clock can work at 100M, but the 100M main frequency puts a lot of pressure on the external SDRAM. After actual testing, the MCU is relatively stable when working at 50M, and 100M is sometimes unstable. It can also be appropriately increased according to actual conditions.

[0153] 5. Dual-port RAM

[0154] Preferably, a dual-port RAM is opened up inside the FPGA to implement communication between the MCU and the hard core.

[0155] In a specific embodiment, the size of the dual-port RAM is 1024 bits × 64 bits, a total of 64 kbits. The dual-port RAM is divided into 5 blocks, namely RAM#1, RAM#2, RAM#3, RAM#4, and RAM#5. Each RAM block stores different data, but the read and write operations of the RAM blocks are consistent.

[0156] Some embodiments provide a method for implementing the dual-port RAM based on SRAM, comprising the following steps:

[0157] Two independent access systems are set on the SRAM for the MCU and the hard core to access the SRAM respectively, and each access system includes a data line, an address line and a read-write control line;

[0158] The communication between the hard core and the MCU is achieved by reading the SRAM, including the following steps:

[0159] Allows the hard core and MCU to randomly read or write the SRAM simultaneously through their respective access systems;

[0160] The MCU is not allowed to read and write to an address unit on the SRAM at the same time;

[0161] The hard core is not allowed to read and write to an address location on this SRAM at the same time.

[0162] In some implementations, the first RAM block coordinates the hard core and the MCU to read or write the second RAM block based on status information, and the status information includes: RAM2 read and write status, RAM4 read and write status, RAM2 device ID, parameter transfer device ID, write fault pointer, read fault pointer, read command pointer, write command pointer, and valid data bits of MCU transfer parameters.

[0163] The dual-port RAM supports communication between the hard core and the MCU, and displays various electrical data, switch status, stability of the running lines and other information of the real-time operation of the power grid system on the display screen, so as to realize real-time control of the operation status of the power grid system and store important data.

[0164] When the MCU reads the address unit that the hard core is writing, the data read by the MCU is the historical value of the address unit; when the hard core reads the address unit that the MCU is writing, the data read by the hard core is also the historical value of the address unit. However, when the MCU and the hard core write to the same address at the same time, the value of the address unit is uncertain. The historical value is usually saved in the cache module.

[0165] The interface signals between the hard core and the MCU and the dual-port RAM are fixed, as shown in Table 12. The interface signals between the MCU and the dual-port RAM are similar, except that an additional clock matching module is added in the middle to avoid multiple writes or reads to the dual-port RAM.

[0166] Table 12. Interface signals between hard core and dual-port RAM

[0167]

[0168] Among them, Byteena_a is the write byte enable signal, which divides the 64-bit data written to RAM into 8 bytes, corresponding to the 8 bits of byteena_a. When the corresponding bit is high, the byte can be written to the corresponding address unit, and the other byte data in the address unit remain unchanged from the previous historical value.

[0169] The timing of reading and writing the dual-port RAM is further explained through the following specific embodiments, taking the reading and writing timing of the MCU as an example (the hard core timing is similar to it).

[0170] 5.1 Reading Dual-Port RAM Timing

[0171] Preferably, the length of the RAM address is up to 10 bits, and the upper 6 bits are for easy expansion. When reading the RAM, the upper bits of the 10-bit address are filled with 0 to expand it into a 16-bit address. The data read from the dual-port RAM is placed in the array corresponding to receive_data.

[0172] After the MCU (or hard core) prepares the read address on the address line address_a, it can send a read command. The pulse width of the command must be at least 1 global clock length (50M), and it is not allowed to exceed 5 global clock lengths, otherwise the dual-port RAM will be read twice; the above dual-port RAM read function, when the main frequency is 50M, the command pulse is 10M when the MCU is tested. After sending the command, after a suitable time, the data can be read from the q_a signal. It takes about 4 global clocks to read the dual-port RAM once. Address_a must change after rden_a is low, otherwise the wrong data will be read.

[0173] 5.2 Write Dual-Port RAM Timing

[0174] After the MCU (or hard core) prepares the address and data to be written on address_a and data_a, it can send a write command. The pulse width of the write command must be at least 1 global clock length (50M), and it is not allowed to exceed 5 global clock lengths, otherwise the dual-port RAM will be written twice; The above dual-port RAM write function, when the main frequency is 50M, has been tested and the command pulse is 10M wide. Address_a and data_a can only change after wren_a is low, otherwise the wrong data will be written to the wrong address. It takes about 4 global clocks to write a dual-port RAM once.

[0175] It should be noted that the speed of reading and writing dual-port RAM is very fast. For an MCU with a main frequency of 50M, it takes about 1ns to read or write a dual-port RAM.

[0176] 5.3 Data of each RAM block

[0177] 5.3.1 RAM#1 data definition

[0178] RAM#1 is equivalent to the control register area, where all RAM read and write status data are stored; the hard core and MCU will often query the space here to decide to operate on the RMA space; the detailed address definition is shown in the following table:

[0179] Table 13. Address definition of RAM#1

[0180]

[0181] 5.3.2 RAM#2 data definition

[0182] Stores relevant information of the APF system that needs to be displayed on the control terminal. First, the hard core collects data and writes it to the relevant RAM; the MCU reads this data and then updates the relevant data of the control terminal. The hard core writes at a rate of 200ms. Only after all the data is written, the MCU is allowed to read from it to ensure integrity. The reading and writing of the hard core and the MCU are controlled by RAM2_state in RAM#1; for other data in this RAM block, it is refreshed immediately as long as there is an update of the operating status feedback information from the slave controller. The refresh rate depends on the rate at which the MCU reads the RAM. The hard core only needs to send the compensation current waveform of a certain device required by the MCU. The hard core determines which device the compensation waveform that the MCU needs the hard core to transmit is by reading the data in RAM2_ID. The following table gives the detailed data definition of this RAM block:

[0183] Table 14. RAM#2 data definition

[0184]

[0185]

[0186]

[0187] The following table gives the detailed definition of device status:

[0188] Table 15. Device status definitions

[0189] Command Code illustrate 0x0000 stop 0x0001 run 0x0002 Fault 0x0003 Offline 0x0004 Emergency Stop 0x0005 Standby 0x0006 Does not exist other spare

[0190] 5.3.3.RAM#3 data definition

[0191] It is equivalent to a data buffer. The hard core accepts the commands of the MCU and then executes them in sequence. It should be noted that the hard core does not save the commands of the MCU and does not return status signals. The MCU needs to query the relevant data of other RAM blocks to determine whether the execution of the command is completed.

[0192] Table 16. RAM#3 data definition

[0193]

[0194] Table 17. Command format

[0195]

[0196]

[0197] Note: The main controller automatically assigns IDs through the number of the optical fiber communication interface;

[0198] 5.3.4.RAM#4 data definition

[0199] Used to transfer parameters between the hard core and MCU. Parameters are transferred in pages. One page of 9 data 0x340~0x342 is used to save the data sent from the hard core to the MCU; 0x343~0x345 is used to send MUC to the hard core parameter settings; data transfer is controlled by RAM4_ord, RAM4_ID, RAM4_addr, and RAM4_ENOB in RAM#1.

[0200] Table 18. Data format for hard core write and MCU read

[0201]

[0202] Table 19. Data format for MCU write and hard core read

[0203]

[0204] See the table below for specific parameters:

[0205] Table 20. Read and write data parameters

[0206]

[0207]

[0208]

[0209]

[0210] 5.3.5 RAM#5 data definition

[0211] It is mainly responsible for the storage and access of fault codes, ensuring that when multiple faults occur at the same time, the old faults that have not been read by the MCU cannot be overwritten by new faults, and that 32 fault code buffer areas can be written simultaneously; when a fault occurs, the hard core puts the ID of the faulty device and the specific fault code into the buffer area of ​​0x3e0~0x3fd according to the position pointed to by the write pointer 0x3ff, for the MCU to read and save.

[0212] Table 21. Data definition of RAM#5

[0213]

[0214] Table 22. Event code encoding

[0215]

[0216]

[0217] The embodiments and functional operations of the subject matter described in this specification can be implemented in the following: computer programs or instructions, digital electronic circuits, tangibly implemented computer software or firmware, computer hardware, including the structures disclosed in this specification and their structural equivalents, or a combination of one or more of the above. Computers suitable for executing computer programs include and can be based on general-purpose microprocessors or special-purpose microprocessors or both of the above processors, or any other kind of central processing unit.

[0218] Specific implementations of the subject matter have been described. Other implementations are within the scope of the following claims. For example, the activities recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes described in the accompanying drawings do not necessarily require the specific order or sequential order shown in order to achieve the desired results. In certain implementations, multitasking and parallel processing may be advantageous.

Claims

1. A hard-core interface module of an APF control system, which communicates with the MCU by reading and writing dual-port RAM; characterized in that: The input signals of the top-level entity of the hard-core interface module include: clock signal, waveform data, slave board data, slave board status, dual-port RAM read and write status, fault signal, and notification signal; The output signals of the top-level entity of the hard core interface module include: a first enable signal, data output, address output, command output, and notification signal; the command output includes a command sent by the MCU to the hard core; The bottom layer modules of the hard core interface module include: Status monitoring module: used for monitoring the dual-port RAM and outputting the read and write status of the dual-port RAM; Waveform data writing module: used for writing the waveform data collected from the grid side or from the output side of the APF control system into the dual-port RAM, the waveform data including voltage waveform data and / or current waveform data; A slave board data writing module: used for writing the slave board data and the slave board status into the dual-port RAM; Command writing and reading module: used for writing the command sent by the MCU to the hard core into the dual-port RAM; Parameter transfer module: used to control the transfer of configuration parameters between the MCU and the hard core; Fault signal writing module: used for writing the fault signal into the dual-port RAM and modifying the fault pointer information at the same time; Time-sharing multiplexing module: used to control the time-sharing multiplexing of reading and writing of the dual-port RAM by all the above-mentioned bottom modules; Wherein, the multiplexing module is configured to: send a second enabling signal to the status monitoring module when it is determined that the dual-port RAM is not occupied; and the status monitoring module is configured to: start working after receiving the second enabling signal.

2. The hard core interface module according to claim 1, characterized in that: The hard core interface module performs the following steps: The status monitoring module performs status detection on the dual-port RAM at regular intervals; The state monitoring module sends the state of the dual-port RAM to any one or more modules of the command writing and reading module, the parameter transfer module, the fault signal writing module, and the waveform data writing module; After receiving the status of the dual-port RAM, any one or more of the command writing and reading module, the parameter transfer module, the fault signal writing module, and the waveform data writing module sends a request RAM instruction to the time-sharing multiplexing module.

3. The hard core interface module according to claim 2, characterized in that: The hard core interface module also performs the following steps: the time-sharing multiplexing module writes the command reading module, the parameter transfer module, the fault signal writing module, the waveform data writing module, and the status monitoring module in order from high to low priority, allowing the request RAM instruction of the corresponding module.

4. The hard core interface module according to claim 1, characterized in that: The dual-port RAM is composed of five read-write consistent RAM blocks, which are configured as follows: The first RAM block is used to store the read and write status of the dual-port RAM; The second RAM block is used to store the waveform data, the slave board data, and the slave board status; The third RAM block is used to store cache data including data for query by the MCU; Fourth RAM block: used to store data exchanged between the hard core and the MCU; The fifth RAM block: used to store fault codes.

5. The hard core interface module according to claim 4, characterized in that: The submodules of the parameter transfer module include: MCU configuration parameter cache module: used to read configuration parameters from the external memory and store them in the internal memory, wherein the configuration parameters are configuration parameters modified by the MCU; read the configuration parameters in the internal memory and write them into the external memory; Update and initialization module: when the data of the APF control system is updated, it is used to send the index directory and value of the configuration parameters to: the waveform data writing module used to check whether the mutual inductor value has changed; the UART module used to notify the slave board to check whether the value of the configuration parameter needs to be modified; the protection module used to check whether the configuration parameter has been modified; the DFT module used to check whether the configuration parameter needs to be modified; The configuration data caching module is used to cache the configuration parameters sent by the control terminal of the APF control system.

6. The hard core interface module according to claim 4, characterized in that: The waveform data writing module includes a sampling writing module and a sampling data processing module, wherein: A sampling and writing module is used to collect the waveform data, generate a write enable signal, a write address and write data, and write the waveform data into the second RAM block at one time. The waveform data includes voltage waveform data and / or current waveform data, specifically: three-phase grid voltage waveform data, three-phase grid current waveform data, three-phase load current waveform data, and three-phase total compensation current waveform data; Sampling data processing module: used to convert the waveform data into actual values.

7. The hard core interface module according to claim 6, characterized in that: The submodules of the sampling writing module include: A second RAM block status monitoring module: used to query the status of the second RAM block at regular intervals and send a write instruction to the second RAM block; Sampling execution module: used for executing the acquisition of the waveform data; Auxiliary sampling control module: used to send sampling commands to the sampling execution module at regular intervals.

8. The hard core interface module according to claim 7, characterized in that: The configuration of the MCU is implemented by embedding the NiosII architecture on the FPGA, specifically comprising the following steps: loading a soft core based on the NiosII architecture on the FPGA to implement the CPU function of the MCU; Based on the NiosII architecture, multiple functional modules including an Avalon-MM tri-state bridge, a UART module, a Jtag port debugging module, an SDRAM controller module, several interval timers, a flash memory interface, and several parallel IO ports are integrated.

9. An APF control system, characterized in that: The APF control system includes a hard core implemented based on FPGA, an MCU and a dual-port RAM for communication between the hard core and the MCU. The hard core also includes a hard core interface module as described in any one of claims 1 to 8.

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