A host device that replaces a synchronous serial interface with a serial peripheral interface

Abstract

The application relates to a host device using a serial peripheral interface to replace a synchronous serial interface, the host device comprising two serial peripheral interfaces SPI, namely a first SPI1 and a second SPI2, the first SPI1 comprising a first data output interface SPI1MISO, a first data input interface SPI1MOSI and a first clock signal SPI1Clock, the second SPI2 comprising a second frame synchronization signal output interface SPI2MOSI and a second clock signal SPI2Clock, and the first clock signal SPI1Clock being connected with the second clock signal SPI2Clock. Compared with the prior art, the application has the advantages of realizing the same effect as SSI communication by only adding one interface.

Description

TECHNICAL FIELD

[0001] The present application relates to a host device, in particular to a host device using a serial peripheral interface (SPI) to replace a synchronous serial interface (SSI). BACKGROUND

[0002] The SSI (Synchronous Serial Interface) is a full-duplex serial interface, which is characterized by a high communication rate, usually up to 2Mbps or above. A schematic diagram of a host device with SSI is shown in Figure 1 , and a signal timing diagram is shown in Figure 2 .

[0003] The SPI (Serial Peripheral Interface) is also a full-duplex synchronous communication bus interface. A schematic diagram of a host device with SPI is shown in Figure 3 , and a SPI protocol timing diagram is shown in Figure 4 .

[0004] The existing mainstream chips such as 51 series, STM32 series and their domestic chips do not support the SSI protocol, and due to the high communication rate, it is also usually impossible to use the IO port simulation method to simulate communication. There are few chips supporting the SSI protocol, such as the SAM4S series of Atmel Corporation, and the price is also relatively high. The chip selection is low, and the purchase and use of the chip are also easily limited, which is not convenient for transplantation and replacement of the use platform.

[0005] Therefore, it is impossible to communicate with the common ST single-chip microcomputer, and only chips specially supporting the SSI protocol can be used for communication. SUMMARY

[0006] The purpose of the present application is to overcome the defects of the prior art and provide a host device using a serial peripheral interface to replace a synchronous serial interface.

[0007] The purpose of the present application can be achieved by the following technical solutions:

[0008] According to one aspect of the present application, a host device using a serial peripheral interface to replace a synchronous serial interface is provided, the host device comprising two serial peripheral interfaces SPI, a first SPI1 and a second SPI2, the first SPI1 comprising a first data output interface SPI1 MISO, a first data input interface SPI1 MOSI and a first clock signal SPI1 Clock, the second SPI2 comprising a second frame synchronization signal output interface SPI2 MOSI and a second clock signal SPI2 Clock, the first clock signal SPI1 Clock and the second clock signal SPI2 Clock being connected.

[0009] As a preferred technical solution, the second clock signal SPI2 Clock is provided with a clock output interface for the host device to provide an external clock signal.

[0010] As a preferred technical solution, the second frame synchronization signal output interface SPI2 MOSI is a pulse signal output interface for the host device to provide an external frame synchronization signal.

[0011] As a preferred technical solution, the first data output interface SPI1 MISO is used for the host device to provide data output.

[0012] As a preferred technical solution, the first data input interface SPI1 MOSI is used for the host device to provide data input.

[0013] As a preferred technical solution, the first SPI1 uses a DMA transmission mode.

[0014] As a preferred technical solution, the DMA transmission mode uses a single Normal or Circular mode.

[0015] As a preferred technical solution, the first SPI1 uses an interrupt or blocking transmission mode.

[0016] As a preferred technical solution, the length of the data transmitted by the first SPI1 can be customized.

[0017] As a preferred technical solution, the host device further comprises an MCU connected with the two serial peripheral interfaces SPI respectively.

[0018] Compared with the prior art, the present application has the following advantages:

[0019] 1) Compared with using an SSI special chip, the present application only needs to add one interface to achieve the same effect as communicating with an SSI, and for most chips, adding one interface is much more convenient than replacing a chip.

[0020] 2) The application can use common ST (STMicroelectronics), GD (Megchip), SH (Chipone), 51 single-chip and other chips supporting SPI communication, and is not limited to chips supporting SSI communication protocol, thereby greatly reducing development and transplantation costs, greatly increasing selectivity, and being more affordable.

[0021] 3) Currently, chips are in short supply on the international market, and selecting domestic chips is easier to obtain and can greatly reduce costs.

[0022] 4) The SPI protocol is similar to the SSI protocol, but cannot be directly replaced, but after the improvement of the application scheme, the SSI protocol can be replaced by the SPI to communicate. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a schematic diagram of an existing SSI host;

[0024] Figure 2 is a signal timing diagram of the SSI protocol;

[0025] Figure 3 is a schematic diagram of an SPI host;

[0026] Figure 4 is a signal timing diagram of the SPI protocol;

[0027] Figure 5 is a schematic diagram of a host device of the application;

[0028] Figure 6 is a specific schematic diagram of the host device of the application. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by those of ordinary skill in the art without creative labor should belong to the protection scope of the application.

[0030] As Figure 5 and Figure 6As shown in the figure, a host device using a serial peripheral interface to replace a synchronous serial interface, the host device includes two serial peripheral interfaces SPI, respectively, the first SPI1 and the second SPI2, the first SPI includes a first data output interface SPI1 MISO, a first data input interface SPI1 MOSI and a first clock signal SPI1 Clock, the second SPI2 includes a second frame synchronization signal output interface SPI2 MOSI and a second clock signal SPI2 Clock, the first clock signal SPI1 Clock and the second clock signal SPI2 Clock are connected. The application can provide the same external interface as the SSI host by combining SPI1 and SPI2, and finally realize the same communication effect as the SSI protocol. Compared with using SSI special chip, the application only needs to increase 1 IO port to realize the same effect as SSI communication. For most chips, it is much more convenient to add 1 IO port than to replace the chip.

[0031] The second clock signal SPI2 Clock is provided with a clock output interface for the host device to provide an external clock signal. The second frame synchronization signal output interface SPI2 MOSI is a pulse signal output interface for the host device to provide an external frame synchronization signal.

[0032] The application SPI1 outputs SPI1 MISO, inputs SPI1 MOSI, transmits and receives data, and provides external data output and data input signals in the SSI host.

[0033] The first SPI1 adopts a DMA transmission mode, which can not only reduce the CPU resource overhead of the chip, but also realize continuous output of the clock. The DMA transmission mode adopts a single Normal or circular Circular mode, and the single mode is re-enabled after each interruption, and the circular mode does not need to be re-enabled.

[0034] The first SPI1 is not limited to the DMA transmission mode, and can also adopt an interruption or blocking transmission mode.

[0035] The length of the transmission data of the first SPI1 can be self-defined, and is no longer limited by the SSI protocol.

[0036] As shown in the figure, Figure 6 The host device further includes an MCU connected with the two serial peripheral interfaces SPI, and the MCU is further connected with a power supply circuit, a crystal oscillator circuit and the like.

[0037] The special terms are explained as follows:

[0038] SSI is Synchronous Serial Interface, Synchronous Serial Interface;

[0039] SPI is Serial Peripheral Interface, Serial Peripheral Interface;

[0040] DMA is Direct Memory Access, Direct Memory Access;

[0041] CS is Chip Select, Chip Select;

[0042] NSS is Negative Slave Select, Negative Slave Select;

[0043] MISO is Master In, Slave Out, Master In, Slave Out;

[0044] MOSI is Master Out, Slave In, Master Out, Slave In;

[0045] Frame Sync is Frame Sync signal, Frame Sync signal;

[0046] EXIT is External Interrupt pin, External Interrupt pin;

[0047] IO is Input / Output pin, Input / Output pin.

[0048] The above merely illustrates the present application, but the protection scope of the present application is not limited to this, any skilled person in this field can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A host device that uses a serial peripheral interface instead of a synchronous serial interface, characterized in that, The host device comprises two serial peripheral interfaces (SPI), namely a first SPI 1 and a second SPI 2, the first SPI 1 comprises a first data output interface SPI1 MISO, a first data input interface SPI1 MOSI and a first clock signal SPI1 Clock, the second SPI 2 comprises a second frame synchronization signal output interface SPI2 MOSI and a second clock signal SPI2 Clock, and the first clock signal SPI1 Clock and the second clock signal SPI2 Clock are connected; The second clock signal SPI2 Clock is provided with a clock output interface, which is used for the host device to provide an external clock signal; and the second frame synchronization signal output interface SPI2 MOSI is a pulse signal output interface, which is used for the host device to provide an external frame synchronization signal. The first data output interface SPI1 MISO is used for the host device to provide data output; and the first data input interface SPI1 MOSI is used for the host device to provide data input. Only one IO port is added to realize the same effect as the SSI communication.

2. The host device employing a serial peripheral interface in place of a synchronous serial interface of claim 1, wherein, The first SPI 1 adopts a DMA transmission mode.

3. The host device employing a serial peripheral interface in place of a synchronous serial interface of claim 2, wherein, The DMA transmission mode adopts a single Normal mode or a circular Circular mode.

4. The host device employing a serial peripheral interface in place of a synchronous serial interface of claim 1, wherein, The first SPI 1 adopts an interrupt or blocking transmission mode.

5. The host device employing a serial peripheral interface in place of a synchronous serial interface of claim 1, wherein, The length of the data transmitted by the first SPI 1 can be customized.

6. The host device employing a serial peripheral interface in place of a synchronous serial interface of claim 1, wherein, The host device further comprises an MCU connected with the two serial peripheral interfaces (SPI) respectively.

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