Heterogeneous integrated package structure of cooling structure and forming method thereof

Abstract

The present application relates to a cooling structure heterogeneous integration package structure and a forming method thereof, wherein the double-sided cooling structure heterogeneous integration package structure comprises: a micro-channel adapter plate, the front surface of which is provided with a first micro-channel; a glass wafer, which is anodically bonded with the two sides of the front surface of the micro-channel adapter plate, wherein the glass wafer is provided with a cavity, which is communicated with the first micro-channel; a chip stack structure, which is connected with the middle area of the front surface of the micro-channel adapter plate; and a micro-channel liquid cooling plate, the front surface of which is connected with the chip stack structure, and the back surface of the micro-channel liquid cooling plate is provided with a second micro-channel, which is communicated with the cavity of the glass wafer. The intercommunication of the upper and lower channels is realized by the glass wafer, which has high reliability, is corrosion-resistant and is not easy to age, thereby reducing the risk of long-term use failure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor packaging, in particular to a heterogeneous integrated packaging structure of a cooling structure and a forming method thereof. BACKGROUND

[0002] The existing liquid micro-channel cooling method for 2D / 3D packaging mainly adopts single-sided cooling or double-sided cooling. There are mainly two ways of integrating the liquid micro-channel, the first way is to embed the micro-channel in the chip substrate, and the second way is to embed the micro-channel in the non-chip substrate. After packaging, the micro-channel heat sink is attached to the back of the chip. If it is double-sided cooling, it is realized through the bottom embedded TSV micro-channel adapter plate and the top micro-channel heat sink. Embedding the micro-channel in the chip substrate increases the complexity and difficulty of the chip front-end process, reduces the flexibility of the back-end process, and at the same time, due to the embedded micro-channel in the chip, stress concentration points are easily formed at the micro-channel, micro-cracks are easily formed in the chip substrate and extended to the device layer, causing the device layer to fail. The cooling method of embedding the micro-channel in the non-chip substrate currently adopted mainly uses the process of micro-assembly of a single chip to assemble a single chip on the micro-channel structure. When multiple chips need to be stacked, this integration method is low in efficiency. The existing double-sided cooling scheme often uses resin or solder ring for the intercommunication of the upper and lower channels. The resin or solder ring has the risk of aging and failure in long-term use, which increases the risk of failure in long-term use of the double-sided cooling structure. SUMMARY

[0003] To solve at least part of the above problems in the prior art, the present application provides a heterogeneous integrated packaging structure of a cooling structure and a forming method thereof. The intercommunication of the upper and lower channels is realized by a glass wafer, which is high in reliability, corrosion-resistant and not easy to age, thereby reducing the risk of failure in long-term use. Moreover, the chip wafer stacking structure is formed through wafer-level stacking process, and the integration efficiency is high after the wafer is integrated with the micro-channel liquid cooling plate.

[0004] In a first aspect of the present application, the present application provides a heterogeneous integrated packaging structure of a double-sided cooling structure, comprising:

[0005] a micro-channel adapter plate, the front surface of which has a first micro-channel;

[0006] a glass wafer or a silicon wafer, which is connected to the front surface of the micro-channel adapter plate, wherein the glass wafer or the silicon wafer has a cavity, and the cavity is in communication with the first micro-channel;

[0007] a chip stacking structure, which is connected to the middle region of the front surface of the micro-channel adapter plate;

[0008] A micro-channel liquid cooling plate, a front surface of the micro-channel liquid cooling plate is connected with the chip stack structure, and a back surface of the micro-channel liquid cooling plate has a second micro-channel, the second micro-channel is in communication with the cavity of the glass wafer or the silicon wafer.

[0009] Further, the glass wafer is anodically bonded with the micro-channel adapter plate; or

[0010] The glass wafer or the silicon wafer is fusion bonded with the micro-channel adapter plate through a dielectric layer.

[0011] Further, further comprising:

[0012] Plastic sealing material arranged in the gap between the micro-channel liquid cooling plate and the glass wafer and the chip stack structure;

[0013] A through-silicon via penetrating through the micro-channel adapter plate;

[0014] A dielectric layer arranged on the back surface of the micro-channel adapter plate;

[0015] A rewiring layer located in the dielectric layer and electrically connected with the through-silicon via; and

[0016] A solder ball arranged on the rewiring layer.

[0017] Further, the first micro-channel in the middle region of the front surface of the micro-channel adapter plate is sealed, and the first micro-channel on both sides is not sealed;

[0018] The back surface of the chip stack structure has a first solder layer, and the front surface of the micro-channel liquid cooling plate has a second solder layer, the chip stack structure is connected with the micro-channel liquid cooling plate by bonding the first solder layer and the second solder layer.

[0019] In the second aspect of the present application, the present application provides a forming method of a heterogeneous integrated packaging structure with a double-sided cooling structure, comprising:

[0020] Manufacturing a micro-channel adapter plate, wherein the front surface of the micro-channel adapter plate has a first micro-channel and a through-silicon via;

[0021] Connecting a glass wafer with a cavity with the front surface of the micro-channel adapter plate through anodic bonding, wherein the cavity of the glass wafer is in communication with the first micro-channel;

[0022] Forming a chip wafer stack structure and connecting the chip wafer stack structure with the micro-channel liquid cooling plate, and then dicing to obtain a single integrated structure, the single integrated structure comprising a single chip stack structure and a single micro-channel liquid cooling plate, wherein the back surface of the single micro-channel liquid cooling plate has a second micro-channel;

[0023] The single chip stack structure is arranged on the micro-channel adapter plate by connecting the chip bumps on the front side of the single chip stack structure with the through silicon vias of the micro-channel adapter plate;

[0024] The plastic encapsulation is injected and solidified on the single integrated structure, on the glass wafer and in the gap between the two; and

[0025] The glass wafer and the single micro-channel liquid cooling plate are thinned to expose the cavity and the second micro-channel, wherein the cavity and the second micro-channel are communicated after being thinned; and

[0026] The back side of the micro-channel adapter plate is thinned to expose the through silicon vias, and then a dielectric layer and a rewiring layer are arranged on the back side of the micro-channel adapter plate, and solder balls are arranged on the rewiring layer.

[0027] Further, the glass wafer and the micro-channel adapter plate can be connected through dielectric layer fusion bonding; or

[0028] A silicon wafer with a cavity is used to replace the glass wafer and the micro-channel adapter plate through dielectric layer fusion bonding.

[0029] Further, the first micro-channel is formed on the front side of the adapter plate with the through silicon vias by etching, then the first micro-channel in the middle region is sealed by using silicon dioxide, the first micro-channels on both sides are not sealed, and finally the silicon dioxide above the through silicon vias is removed by etching to expose the through silicon vias; and

[0030] A first solder layer is formed on the back side of the first layer chip wafer, then a chip wafer stack structure is formed, a second solder layer is formed on the front side of the micro-channel liquid cooling plate, then the first solder layer on the back side of the chip wafer stack structure is bonded with the second solder layer on the front side of the micro-channel liquid cooling plate to form an integrated structure of the chip wafer stack structure and the micro-channel liquid cooling plate, and finally the wafer is cut to form a single integrated structure.

[0031] In a third aspect of the present application, the present application provides a single-sided cooling structure heterogeneous integrated packaging structure, comprising:

[0032] A micro-channel liquid cooling plate having an unsealed micro-channel on the back side thereof;

[0033] A chip stack structure arranged on the front side of the micro-channel liquid cooling plate;

[0034] A plastic encapsulation layer arranged around the chip stack structure and the micro-channel liquid cooling plate;

[0035] A dielectric layer arranged on the front side of the chip stack structure;

[0036] A rewiring layer located in the dielectric layer and electrically connected with the chip bumps and solder balls of the chip stack structure; and

[0037] solder balls arranged on the redistribution layer.

[0038] Further, the back surface of the chip stack structure has a first solder layer, and the front surface has a chip bump.

[0039] The front surface of the micro-channel liquid cooling plate has a second solder layer, and the second solder layer is bonded with the first solder layer, so that the chip stack structure is connected with the micro-channel liquid cooling plate.

[0040] In a fourth aspect of the present application, the present application provides a method for forming a single-sided cooling structure heterogeneous integrated packaging structure, comprising:

[0041] forming a chip wafer stack structure, connecting the chip wafer stack structure with the micro-channel liquid cooling plate, and then dicing to obtain a single integrated structure, the single integrated structure comprising a single chip stack structure and a single micro-channel liquid cooling plate, wherein the back surface of the single micro-channel liquid cooling plate has a micro-channel;

[0042] connecting the front surface of the single chip stack structure with the redistribution layer on the carrier wafer;

[0043] forming a plastic encapsulation layer by plastic encapsulating the periphery of the single integrated structure;

[0044] thinning the back surface of the single micro-channel liquid cooling plate to expose the micro-channel; and

[0045] removing the carrier wafer to expose the redistribution layer, and then arranging solder balls on the redistribution layer.

[0046] Further, the back surface of the chip stack structure has a first solder layer, and the front surface has a chip bump.

[0047] The front surface of the micro-channel liquid cooling plate has a second solder layer, and the second solder layer is bonded with the first solder layer, so that the chip stack structure is connected with the micro-channel liquid cooling plate.

[0048] The present application has at least the following beneficial effects: the cooling structure heterogeneous integrated packaging structure and the forming method thereof disclosed by the present application realize the intercommunication of upper and lower channels through a glass wafer, the glass wafer and the micro-channel adapter plate are connected through anode bonding, which has high reliability, the glass wafer is corrosion-resistant and not easy to age, which reduces the risk of long-term use failure and has low cost; the chip wafer stack structure is formed through wafer-level stacking process, integrated with the micro-channel liquid cooling plate, and then diced to obtain multiple integrated structures comprising a single chip stack structure and a single micro-channel liquid cooling plate, which realizes efficient integration of chips and cooling structures. BRIEF DESCRIPTION OF DRAWINGS

[0049] To further clarify the above and other advantages and features of the present embodiments, a more particular description of embodiments of the application will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. It is appreciated that these drawings depict only typical embodiments of the application and are therefore not to be considered limiting of its scope. The drawings incorporate graphics for purposes of clarity that are not necessarily drawn to scale.

[0050] Figure 1 A cross-sectional view of a flip-chip package structure with a double-sided cooling structure according to an embodiment of the present application is shown;

[0051] Figure 2 A cross-sectional view of a flip-chip package structure with another double-sided cooling structure according to an embodiment of the present application is shown;

[0052] Figures 3A to 3G A cross-sectional view of a process of forming a flip-chip package structure with a double-sided cooling structure according to an embodiment of the present application is shown;

[0053] Figure 4 A cross-sectional view of a flip-chip package structure with a single-sided cooling structure according to an embodiment of the present application is shown; and

[0054] Figures 5A to 5E A cross-sectional view of a process of forming a flip-chip package structure with a single-sided cooling structure according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0055] It should be noted that components in the various figures can be exaggerated for the purpose of illustration and are thus not necessarily drawn to scale.

[0056] In the present application, the embodiments are merely intended to illustrate the solutions of the present application and should not be understood as limiting.

[0057] In the present application, the quantifier "one", "a" does not exclude the scenario of multiple elements unless specifically indicated.

[0058] It should also be noted herein that, in the embodiments of the present application, only a part of components or assemblies can be shown for the sake of clarity and simplicity, but those skilled in the art can understand that, under the teaching of the present application, the required components or assemblies can be added according to the specific scenario as needed.

[0059] It should also be noted herein that, within the scope of the present application, the phrases "the same", "equal", "equal to" do not mean that the two values are absolutely equal, but allow a certain reasonable error, that is, the phrases also cover "substantially the same", "substantially equal", "substantially equal to".

[0060] It should also be noted that in the description of the present application, the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not mean that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are only for descriptive purposes and cannot be understood as indicating relative importance.

[0061] In addition, the embodiments of the present application describe the process steps in a specific order, but this is only for the convenience of distinguishing between steps and is not limited to the order of the steps. In different embodiments of the present application, the order of the steps can be adjusted according to the adjustment of the process.

[0062] Figure 1 A cross-sectional schematic diagram of a heterogeneous integration package structure with a double-sided cooling structure according to an embodiment of the present application is shown.

[0063] As shown in Figure 1 A heterogeneous integration package structure with a double-sided cooling structure includes a micro-channel adapter plate 101, a first micro-channel 1011, a through-silicon via 1012, a glass wafer 102, a chip stack structure 103, a micro-channel liquid cooling plate 104, a plastic sealing material 105, a dielectric layer 106, a redistribution layer 107, and a solder ball 108.

[0064] The front surface of the micro-channel adapter plate 101 has a first micro-channel 1011, wherein the first micro-channel 1011 in the middle region is sealed by silicon dioxide, and the first micro-channel on both sides is not sealed by silicon dioxide.

[0065] The through-silicon via 1012 penetrates the micro-channel adapter plate 101. The through-silicon via 1012 exposes the silicon dioxide seal.

[0066] The glass wafer 102 is anodically bonded to the two sides of the front surface of the micro-channel adapter plate 101. The glass wafer 102 has a cavity 1021 that communicates with the first micro-channel 1011. The glass wafer 102 and the micro-channel adapter plate 102 are connected by anodic bonding, which is more secure, has high reliability, is resistant to corrosion, and is not easily aged. The glass wafer 102 is a hollow ring wafer, and the cavity is located at the edge of the glass wafer.

[0067] The chip stack structure 103 is connected with the middle area of the front surface of the micro-channel adapter plate 101. The chip stack structure 103 is located in the glass wafer 102. The front surface of the chip stack structure 103 has chip bumps, and the chip stack structure 103 is arranged on the front surface of the micro-channel adapter plate 101 by welding the chip bumps and the through silicon vias 1012. The back surface of the chip stack structure 103 has a first solder layer 1031.

[0068] The front surface of the micro-channel liquid cooling plate 104 has a second solder layer 1041. The chip stack structure 103 is connected with the micro-channel liquid cooling plate 104 by bonding the first solder layer 1031 and the second solder layer 1041. The micro-channel liquid cooling plate 104 is located in the glass wafer 102. The chip stack structure 103 and the micro-channel liquid cooling plate 104 are connected by the high-thermal-conductivity metal solder layer, which improves the heat dissipation performance. The back surface of the micro-channel liquid cooling plate 104 has a second micro-channel 1042, which is not sealed and communicates with the cavity 1021 of the glass wafer 102. The cavity 1021 of the glass wafer 102 communicates the first micro-channel 1011 and the second micro-channel 1042, realizing the intercommunication of the upper and lower channels.

[0069] The plastic sealing material 105 is arranged in the gap between the micro-channel liquid cooling plate 104 and the glass wafer 102.

[0070] The dielectric layer 106 is arranged on the back surface of the micro-channel adapter plate 101.

[0071] The rewiring layer 107 is located in the dielectric layer 106 and is electrically connected with the through silicon vias 1012.

[0072] The solder balls 108 are arranged on the rewiring layer 107.

[0073] Figure 2 A cross-sectional schematic view of a heterogeneous integrated package structure of another double-sided cooling structure according to an embodiment of the present application is shown.

[0074] The fan-out package structure with micro-channels includes a micro-channel adapter plate 201, a first micro-channel 2011, a through silicon via 2012, a glass wafer or a silicon wafer 202, a chip stack structure 203, a micro-channel liquid cooling plate 204, a plastic sealing material 205, a dielectric layer 206, a rewiring layer 207, and solder balls 208. The back surface of the micro-channel liquid cooling plate 204 has a second micro-channel 2042, and the front surface of the micro-channel liquid cooling plate 104 has a second solder layer 2041. The back surface of the chip stack structure 203 has a first solder layer 2031. The chip stack structure 203 is connected with the micro-channel liquid cooling plate 204 by bonding the first solder layer 2031 and the second solder layer 2041.

[0075] Figure 2 The above-mentioned embodiments and Figure 1Compared to the previous embodiment, the only difference is that the glass wafer or silicon wafer 202 is soldered to the microfluidic adapter plate 201, or fused bonded using a dielectric layer such as silicon dioxide or silicon nitride. The fused bonding method provides a stronger, more reliable connection, and is also corrosion-resistant and less prone to aging.

[0076] Figures 3A to 3G A cross-sectional schematic diagram of the process of forming a heterogeneous integrated packaging structure with a double-sided cooling structure according to an embodiment of the present invention is shown.

[0077] A method for forming a heterogeneous integrated packaging structure with double-sided cooling includes:

[0078] Step 1, as follows Figure 3A As shown, an integrated microchannel adapter plate 301 is fabricated. A first microchannel 3012 is formed on the front side of the adapter plate, which has through-silicon vias (TSVs) 3011, by etching. Then, silicon dioxide 302 is used to seal the central region of the first microchannel, while the microchannels on both sides are not sealed. Finally, the silicon dioxide above the TSVs is removed by etching, exposing the TSVs. The TSVs 3011 are located on the front side of the microchannel adapter plate 301, on the same side as the first microchannels 3012, and the depth of the TSVs 3011 is greater than the depth of the first microchannels 3012.

[0079] Step 2, as follows Figure 3B As shown, a hollow glass wafer 303 is anoly bonded to the front side of a microfluidic adapter plate 301. The glass wafer 303 is a hollow annular wafer, with the cavity located at its edge. The cavity of the glass wafer 303 communicates with the first microchannels 3012 on both sides of the microfluidic adapter plate 301, and the first microchannels of the microfluidic adapter plate 301 are integrally connected. Therefore, the cavity of the glass wafer 303 is integrally connected with the first microchannels 3012 of the microfluidic adapter plate. The anoly bonded connection between the glass wafer 303 and the microfluidic adapter plate 301 provides a stronger and more reliable connection, and the glass wafer is corrosion-resistant and less prone to aging. In other embodiments of the invention, the glass wafer is connected to the front side of the microfluidic adapter plate using solder welding, or by fusion bonding using a dielectric layer such as silicon dioxide or silicon nitride. Alternatively, the glass wafer can be replaced with a silicon wafer, which is then connected to the front side of the microfluidic adapter plate by welding or fusion bonding. Among them, fusion bonding is more robust, more reliable, and more resistant to corrosion and aging.

[0080] Step 3, as follows Figure 3CAs shown, the first solder layer 305 is formed on the back of the first chip wafer 304, and then the chip wafer stack structure is formed. The second solder layer 306 is formed on the front of the micro-channel liquid cooling plate, and then the first solder layer on the back of the chip wafer stack structure is bonded with the second solder layer on the front of the micro-channel liquid cooling plate to form an integrated structure of the chip wafer stack structure and the micro-channel liquid cooling plate. Finally, the wafer is cut to form a single integrated structure. The single integrated structure includes a single chip stack structure 307 and a single micro-channel liquid cooling plate 308. The back of the first chip wafer 304 is metallized and a first solder layer is grown, and then a wafer-level process is used to stack multiple chip wafers back-to-back to form a chip wafer stack structure, and the chip wafers are filled with underfill adhesive. The back of the second chip wafer is connected to the front of the first chip wafer, the front of the second chip wafer is connected to the back of the third chip wafer, and so on to form a chip wafer stack structure. The chip wafer stack structure is formed by wafer-level stacking process, and after integration with the micro-channel liquid cooling plate, the wafer is cut to obtain multiple integrated structures containing a single chip stack structure and a single micro-channel liquid cooling plate, with high integration efficiency.

[0081] Step 4, as shown in Figure 3D The single integrated structure is arranged on the front of the micro-channel adapter plate 3011 by connecting the front of the single chip stack structure 307 with the through silicon via 3011 of the micro-channel adapter plate 3011. The front of the single chip stack structure has chip bumps, which are soldered with the through silicon via 3011, and then the underfill material is filled between the front of the single chip stack structure 307 and the micro-channel adapter plate 301. The single integrated structure is located in the glass wafer 303.

[0082] Step 5, as shown in Figure 3E The plastic encapsulant 309 is injected and cured on the single integrated structure, on the glass wafer 303, and in the gap between them.

[0083] Step 6, as shown in Figure 3F The glass wafer 303 and the single micro-channel liquid cooling plate 308 are thinned to expose the cavity and the second micro-channel 3081. After thinning, the second micro-channel 3081 in the micro-channel liquid cooling plate communicates with the cavity of the glass wafer 303, the cavity of the glass wafer 303 communicates with the first micro-channel 3012 of the micro-channel adapter plate 301, and the second micro-channel 3081 in the micro-channel liquid cooling plate communicates with the first micro-channel 3012 of the micro-channel adapter plate through the cavity of the glass wafer 303.

[0084] Step 7, as shown in Figure 3GAs shown, the back of the microfluidic adapter plate 301 is thinned to expose the through silicon vias 3011, and then a dielectric layer 310 and a redistribution layer 311 are arranged on the back of the microfluidic adapter plate 301, and solder balls 312 are arranged on the redistribution layer 311. The dielectric layer 311 is first arranged on the back of the microfluidic adapter plate 301, then the dielectric layer 311 is etched to form a circuit pattern, and finally the redistribution layer 312 is formed by filling metal in the circuit pattern. Multiple repetitions of the above steps can form multiple layers of dielectric layers and redistribution layers. The redistribution layer 312 is electrically connected to the through silicon vias 3011.

[0085] Figure 4 A cross-sectional view of a single-side cooling heterogeneous integration package structure is shown.

[0086] As shown, a single-side cooling heterogeneous integration package structure includes a chip stack structure 401, a first solder layer 4011, a microfluidic liquid cooling plate 402, a second solder layer 4021, a plastic encapsulation layer 403, a dielectric layer 404, a redistribution layer 405, and solder balls 406. Figure 4

[0087] The back of the chip stack structure 401 has the first solder layer 4011, and the front has chip bumps. The front of the microfluidic liquid cooling plate 402 has the second solder layer 4021, and the back has an unsealed microfluidic channel 4022. The chip stack structure 401 is arranged on the front of the microfluidic liquid cooling plate 402 by bonding the first solder layer 4011 and the second solder layer 4021.

[0088] The plastic encapsulation layer 403 is arranged around the chip stack structure 401 and the microfluidic liquid cooling plate 402 to encapsulate the chip stack structure 401 and the microfluidic liquid cooling plate 402.

[0089] The dielectric layer 404 is arranged on the front of the chip stack structure 401.

[0090] The redistribution layer 405 is located in the dielectric layer 404 and is electrically connected to the chip bumps of the chip stack structure 401 and the solder balls 406.

[0091] The solder balls 406 are arranged on the redistribution layer 405.

[0092] Figures 5A to 5E A cross-sectional view of a process for forming a single-side cooling heterogeneous integration package structure is shown.

[0093] A method for forming a single-side cooling heterogeneous integration package structure includes:

[0094] Step 1, as shown, Figure 5A ​As shown, a first bonding layer 5011 is formed on the back side of the first-layer chip wafer, and then a chip wafer stack structure is formed. A second bonding layer 5021 is formed on the front side of the microfluidic liquid cooling plate. The first bonding layer 5011 on the back side of the chip wafer stack structure is then bonded to the second bonding layer 5021 on the front side of the microfluidic liquid cooling plate to form an integrated structure of the chip wafer stack structure and the microfluidic liquid cooling plate. Finally, the wafer is diced to form a single integrated structure. The single integrated structure includes a single chip stack structure 501 and a single microfluidic liquid cooling plate 502. The single microfluidic liquid cooling plate 502 has microchannels 5022. The back side of the first-layer chip wafer is metallized and a first bonding layer is grown. Then, multiple chip wafers are stacked back-to-back using wafer-level processes to form a chip wafer stack structure, and underfill adhesive is filled between the chip wafers. The back side of the second-layer chip wafer is connected to the front side of the first-layer chip wafer, the front side of the second-layer chip wafer is connected to the back side of the third-layer chip wafer, and so on, to form a chip wafer stack structure. First, a chip wafer stacking structure is formed through a wafer-level stacking process. After integration with a microfluidic liquid cooling plate, the structure is diced to obtain multiple integrated structures containing a single chip stacking structure and a single microfluidic liquid cooling plate, resulting in high integration efficiency.

[0095] Step 2, as follows Figure 5B As shown, the front side of the single chip stack structure 501 is connected to the redistribution layer 504 on the carrier 503. The front side of the single chip stack structure has chip bumps, which are soldered to the redistribution layer 504. Then, an underfill material is filled between the front side of the single chip stack structure 501 and the redistribution layer 504. A dielectric layer 505 and a redistribution layer 504 located in the dielectric layer 505 are disposed on the carrier 503, with the surface of the redistribution layer 504 exposed above the dielectric layer 505.

[0096] Step 3, as follows Figure 5C As shown, a molding layer 506 is formed by molding the perimeter of a single integrated structure.

[0097] Step 4, as follows Figure 5D As shown, the back side of a single microchannel liquid cooling plate 502 is thinned to expose the microchannel 5022.

[0098] Step 5, as follows Figure 5E As shown, the substrate is removed to expose the redistribution layer 504, and then solder balls 507 are placed on the redistribution layer 504.

[0099] The application has at least the following beneficial effects: the heterogeneous integrated packaging structure of the cooling structure and the forming method thereof disclosed by the application realize the intercommunication of the upper and lower flow channels through a glass wafer, the glass wafer and the micro-flow channel adapter plate are connected through anode bonding, the reliability is high, the glass wafer is corrosion-resistant and is not easy to age, the risk of long-term use failure is reduced, and the cost is low; the chip wafer stacking structure is formed through wafer-level stacking process, integrated with the micro-flow channel liquid cooling plate, and then singulated, a plurality of integrated structures containing a single chip stacking structure and a single micro-flow channel liquid cooling plate can be obtained, and efficient integration of the chip and the cooling structure is realized.

[0100] While some embodiments of the application have been described above, it is understood that they have been presented by way of example only. Numerous variations, changes, and substitutions will occur to those skilled in the art without departing from the scope of the application. It is therefore intended that the appended claims cover all such variations as fall within the scope of the application.

Claims

1. A heterogeneous integrated packaging structure with a double-sided cooling structure, characterized in that, include: The microchannel adapter plate has a first microchannel on its front side; the first microchannel in the middle area of ​​the front side of the microchannel adapter plate is sealed, while the first microchannels on both sides are not sealed. A glass wafer or silicon wafer is connected to the front side of the microfluidic adapter plate, wherein the glass wafer or silicon wafer has a cavity that communicates with the first microfluidic channel; the glass wafer is anoly bonded to the microfluidic adapter plate; or the glass wafer or silicon wafer is fused to the microfluidic adapter plate through a dielectric layer. A chip stacking structure, which is connected to the central region of the front side of the microchannel adapter plate; The microfluidic liquid cooling plate has its front side connected to the chip stacking structure, and its back side has a second microfluidic channel, which communicates with the cavity of the glass wafer or silicon wafer.

2. The heterogeneous integrated packaging structure with double-sided cooling structure according to claim 1, characterized in that, Also includes: Molding compound is disposed in the microchannel liquid cooling plate and in the gap between the chip stack structure and the glass wafer; Through-silicon vias that penetrate the microchannel adapter plate; A dielectric layer is disposed on the back side of the microchannel adapter plate; A redistribution layer, located in the dielectric layer and electrically connected to the through-silicon via; and Solder balls are arranged on the redistribution layer.

3. The heterogeneous integrated packaging structure with double-sided cooling as described in claim 1, characterized in that, The chip stack structure has a first solder layer on the back side and the microchannel liquid cooling plate has a second solder layer on the front side. The chip stack structure is connected to the microchannel liquid cooling plate by bonding the first solder layer and the second solder layer.

4. A method for forming a heterogeneous integrated packaging structure with a double-sided cooling structure, characterized in that, include: A microfluidic adapter board is fabricated, wherein the front side of the microfluidic adapter board has a first microfluidic channel and a through-silicon via (TSV). The first microfluidic channel is formed on the front side of the adapter board with TSV by etching. Then, the first microfluidic channel in the middle area is sealed with silicon dioxide, while the first microfluidic channels on both sides are not sealed. Finally, the silicon dioxide above the TSV is removed by etching to expose the TSV. A glass wafer with a cavity is connected to the front side of a microfluidic adapter plate via anodic bonding or dielectric layer fusion bonding, wherein the cavity of the glass wafer is connected to a first microchannel; or a silicon wafer with a cavity is used instead of the glass wafer and fused to the microfluidic adapter plate via dielectric layer fusion bonding. A chip wafer stack structure is formed and connected to a microchannel liquid cooling plate. Then, the stack structure is diced to obtain a single integrated structure, which includes a single chip stack structure and a single microchannel liquid cooling plate, wherein the back side of the single microchannel liquid cooling plate has a second microchannel. A single integrated structure is arranged on the front side of the microchannel adapter by connecting the chip bumps on the front side of the individual chip stack structure to the through-silicon vias of the microchannel adapter. Injection molding and curing of molding compound is performed on a single integrated structure, on a glass wafer, and in the gap between the two. as well as The glass wafer and a single microchannel liquid cooling plate are thinned to expose a cavity and a second microchannel, wherein the thinned cavity and the second microchannel are connected; and The back side of the microchannel adapter board is thinned to expose through-silicon vias (TSVs). Then, a dielectric layer and a redistribution layer are placed on the back side of the microchannel adapter board, and solder balls are placed on the redistribution layer. The glass wafer is connected to the microchannel adapter plate by dielectric layer fusion bonding; or A cavity-filled silicon wafer is used instead of a glass wafer and is fused and bonded to the microchannel adapter plate through a dielectric layer.

5. The method for forming a heterogeneous integrated packaging structure with a double-sided cooling structure according to claim 4, characterized in that, A first bonding layer is formed on the back side of the first-layer chip wafer, and then a chip wafer stacking structure is formed. A second bonding layer is formed on the front side of the microfluidic liquid cooling plate. Then, the first bonding layer on the back side of the chip wafer stacking structure is bonded to the second bonding layer on the front side of the microfluidic liquid cooling plate to form an integrated structure of the chip wafer stacking structure and the microfluidic liquid cooling plate. Finally, the wafer is diced to form a single integrated structure.

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