Deterministic delay and arbitrary range delay compensation adjustment device between multiple DA channels

Abstract

This invention discloses a deterministic delay and arbitrary range delay compensation adjustment architecture between multiple DA channels. In this architecture, each DAC consists of a set of ADC_CLK and SYSREF, and each FPGA consists of a set of REF_CLK and SYSREF. This architecture is used to design the clock block diagram and the deterministic delay synchronization output rate of multiple DACs. The frequency multiplier multiplies the reference input to output DAC_CLK and REF_CLK. DAC_CLK is set according to the DAC operating frequency, and REF_CLK is determined according to the operating range of the frequency divider. In this system, REF_CLK = DAC_CLK / N (N<=40). The frequency divider receives REF_CLK1 and divides it to output the required SYSREF. The clock fan-out fans out DAC_CLK into N DAC_CLKs according to the number of DACs. Through reasonable clock arrangement, only the clock fan-out chip can be used when the number of DACs is increased, ensuring that the output time remains stable after multiple power-on cycles while reducing hardware costs.

Description

Technical Field

[0001] This invention relates to the field of quantum computing, and more particularly to a device for determining and adjusting the delay between multiple DA channels and the delay within an arbitrary range. Background Technology

[0002] Quantum computing utilizes fundamental principles such as superposition and coherence of quantum states to perform exponentially parallel computations. With N ideal qubit units, 2^N parallel computations can be achieved. Quantum computing is expected to solve some application problems that are currently impossible or difficult to solve using classical computing, such as the prime factorization algorithm (Short's algorithm). It has broad application prospects in fields such as information security, finance, medicine, and materials science.

[0003] A quantum computer mainly consists of quantum chips (superconducting, silicon-based spin, etc.), a precision measurement and control system, a quantum instruction set, and quantum algorithms. The quantum computer manipulates qubits (qubits) through a precise measurement and control system to implement a specific application algorithm, and finally obtains the calculation result through measurement. The quantum measurement and control system mainly consists of a low-noise precision voltage unit, a pulse generation unit, a radio frequency pulse unit, a reflection measurement unit, and a high-precision microwave source.

[0004] The radio frequency pulse unit is mainly responsible for manipulating the qubit, which directly affects the fidelity of the manipulation and is an important component of the quantum measurement and control system.

[0005] Existing solutions:

[0006] 1. Adjust the delay between multiple channels through phase feedback, that is, check the DAC output or perform software or delay chip processing based on the DAC's own feedback;

[0007] 2. A clock chip generates a synchronized SYSREF and reference clock for multiple DACs, and then the JESD204B is used to synchronize the DAC outputs.

[0008] Disadvantages of existing technology:

[0009] 1. In a quantum measurement and control system, the radio frequency pulse unit needs to be used in conjunction with other devices. That is, when an external trigger signal arrives, the radio frequency pulse unit needs to output the required data at a fixed time. The data output by multiple channels not only needs to be in phase, but the time from the trigger to the data output needs to be completely consistent when the device is started multiple times. Current technology can only meet the phase consistency requirement, but cannot guarantee that the output time remains stable after multiple power-ups.

[0010] 2. Current systems are generally designed so that REF_CLK and SYSREF are at the same level of output. That is, after the external reference enters the board, it is multiplied by a PLL and then distributed to the DAC and FPGA. However, PLLs have output limitations. For example, the HMC7044 only has 14 output channels and can only support one FPGA to connect 6 DACs. If you want to connect more DACs, you need to add another HMC7044. Moreover, high-frequency DACs have higher requirements for PLLs, which increases the hardware cost. Summary of the Invention

[0011] In order to overcome the shortcomings and deficiencies of the existing technology, the present invention provides a device for determining the delay and adjusting the delay within an arbitrary range between multiple DA channels.

[0012] The technical solution adopted in this invention is a deterministic delay and arbitrary range delay compensation adjustment device between multiple DA channels. In this device, each DAC is composed of a set of DAC_CLK and SYSREF, and each FPGA is composed of a set of REF_CLK and SYSREF. It is used to design clock block diagrams and deterministic delay synchronization output of multiple DACs.

[0013] Furthermore, in the clock block diagram, the frequency multiplier will multiply the input frequency to output DAC_CLK and REF_CLK. DAC_CLK is set according to the DAC operating frequency, and REF_CLK is determined according to the operating range of the frequency divider. In this system, REF_CLK = DAC_CLK / N (N<=40). The frequency divider will receive REF_CLK and divide it to output the required SYSREF. The clock fan-out will fan out DAC_CLK into N DAC_CLKs according to the number of DACs.

[0014] Furthermore, the multiple DACs achieve deterministic delay-synchronized output. The FPGA and DAC communicate via the JESD204B protocol. Upon receiving the SYSREF signal, both the DAC and FPGA generate a local clock. Once the FPGA and DAC successfully establish a link, the DAC sends feedback to the FPGA via SYNC. Upon receiving the feedback signal from the DAC, the FPGA sends data to the DAC on the rising edge of its local clock. After sending the feedback, the DAC waits for several local clock cycles before releasing all data, thus synchronizing the DAC output.

[0015] Furthermore, the deterministic delay synchronization output condition of the multiple DACs is as follows:

[0016] The SYSREF of the FPGA is synchronized with the SYSREF of the DAC, and the SYSREF of all DACs is synchronized.

[0017] The phase difference between DAC_CLK cycles does not exceed one DAC_CLK cycle;

[0018] During multiple power-ups, the frequency divider synchronizes the output of all its channels through a program.

[0019] When performing PCB layout and routing, ensure that all clock traces are of equal length.

[0020] Furthermore, the routing delay from SYSREF entering the FPGA to generating the local clock can be calculated by the program and is denoted as TS. The time from data encoding to transmission to the high-speed link is TF. The PCB routing delay can be calculated by the PCB and is denoted as TP. After the data reaches the DAC via the high-speed link, it is encoded and decoded before being buffered inside the DAC, which can be obtained from the DAC's own specifications and is denoted as TD. The delay from SYSREF entering the DAC to generating the local clock is denoted as TM. The routing delay after the trigger signal enters the FPGA can be calculated by the program and is denoted as Tt.

[0021] Furthermore, the total time from data transmission from the FPGA to the high-speed link interface is:

[0022] T1 = TS + TF;

[0023] PCB trace delay is:

[0024] T2=TP;

[0025] The total time from the high-speed link interface to the DAC buffer is:

[0026] T3 = TD + TM;

[0027] The total time for the trigger signal to enter the FPGA is:

[0028] T4=Tt.

[0029] All delays are:

[0030] T = T1 + T2 + T3 + T4.

[0031] When laying out and routing the PCB, ensure that the high-speed link traces of all DACs are of equal length.

[0032] Beneficial effects:

[0033] This invention proposes a deterministic delay and arbitrary range delay compensation adjustment device between multiple DA channels. Through reasonable clock arrangement, it can realize the use of only the clock fan-out chip when DACs are added, ensuring that the output time remains stable after multiple power-on cycles while reducing hardware costs. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and form part of this application, do not constitute a limitation thereof. In the drawings:

[0035] Figure 1 This is a block diagram of the clock design for this invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0037] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] Example 1

[0039] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Deterministic delay compensation and adjustment device between multiple DA channels, and delay compensation within arbitrary range.

[0041] To achieve deterministic delay synchronous output of multiple DACs, each DAC requires a set of DAC_CLK and SYSREF, and each FPGA requires a set of REF_CLK and SYSREF.

[0042] Based on this, the following clock block diagram is designed: Figure 1 As shown, the frequency multiplier can multiply the reference input to output DAC_CLK and REF_CLK. DAC_CLK is set according to the DAC's operating frequency, and REF_CLK can be determined according to the operating range of the frequency divider. In this system, REF_CLK = DAC_CLK / N (N<= 40). The frequency divider will receive REF_CLK and divide it to output the required SYSREF. The clock fan-out will fan out DAC_CLK into N DAC_CLKs according to the number of DACs.

[0043] DAC synchronization implementation principle:

[0044] The FPGA and DAC communicate via the JESD204B protocol. After receiving SYSREF, both the DAC and FPGA generate a local clock. Once the FPGA and DAC successfully establish a link, the DAC sends feedback to the FPGA via SYNC. After receiving the feedback signal from the DAC, the FPGA sends data to the DAC on the rising edge of its local clock. After sending the feedback, the DAC waits for several local clock cycles before releasing all the data, thus ensuring synchronized DAC output.

[0045] The above shows the conditions required for DAC synchronization:

[0046] The SYSREF of the FPGA is synchronized with the SYSREF of the DAC, and the SYSREF of all DACs is synchronized.

[0047] The phase difference between DAC_CLK cycles does not exceed one DAC_CLK cycle.

[0048] During multiple power-ups, the frequency divider can be programmed to ensure that all its channel outputs are synchronized.

[0049] Clock fanouts vary individually, but are not affected by multiple power-ups, and the maximum variation is only 50ps. 50ps corresponds to a sampling rate of 20G, and there are currently no DACs on the market with such a high sampling rate.

[0050] At the same time, when performing PCB layout and routing, all clock traces are made to be of equal length.

[0051] Deterministic delay implementation achieves reasonable clock planning, synchronizing the SYSREF of the FPGA and DAC, and synchronizing the SYSREF of all DACs. The routing delay from the SYSREF entering the FPGA to generating the local clock can be calculated by the program and is denoted as TS. The time from data encoding to transmission to the high-speed link is denoted as TF. The PCB routing delay can be calculated by the PCB and is denoted as TP. After the data reaches the DAC via the high-speed link, it is encoded and decoded and then buffered within the DAC, which can be obtained from the DAC's own indicators and is denoted as TD. The delay from the SYSREF entering the DAC to generating the local clock is denoted as TM. The routing delay after the trigger signal enters the FPGA can be calculated by the program and is denoted as Tt. Therefore, the total time from data transmission from the FPGA to the high-speed link interface can be calculated as follows:

[0052] T1 = TS + TF;

[0053] PCB trace delay is:

[0054] T2=TP;

[0055] The total time from the high-speed link interface to the DAC buffer is:

[0056] T3 = TD + TM;

[0057] The total time for the trigger signal to enter the FPGA is:

[0058] T4 = Tt;

[0059] Thus, all delays can be obtained as T = T1 + T2 + T3 + T4. As long as the value of (T – N * local clock cycle) is close to the middle of [0, local clock cycle], synchronization can be guaranteed.

[0060] Since the FPGA has only one SYSREF input, after it is fed into the FPGA, REF_CLK is used to perform timing and then sent to all JSED204B modules. The timing can ensure that Ts is consistent.

[0061] Ensuring that all high-speed link traces of all DACs are of equal length during PCB layout and routing can guarantee consistent T2.

[0062] Because the SYSREF of all DACs is synchronized, the TM of all DACs can be kept consistent.

[0063] After the trigger signal enters the FPGA, it is timed using REF_CLK and then sent to all JSED204B modules. Timing can ensure that T4 is consistent.

[0064] For TF and TD, there are fluctuations due to DAC and FPGA limitations, but their values ​​are much smaller than the local clock period. These fluctuations can be offset by adjusting the phase of SYSREF and delaying SYSREF accordingly, so that the value of T–N*local clock period is closer to the middle of [0, local clock period].

[0065] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "consistency setting," "installation," "connection," "linking," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0066] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various equivalent changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A device for determining and adjusting the delay within an arbitrary range between multiple DA channels, characterized in that, In this device, each DAC consists of a set of DAC_CLK and SYSREF, and each FPGA consists of a set of REF_CLK and SYSREF. This is used to design the clock block diagram and the deterministic delay synchronization output of multiple DACs. In the clock block diagram, the frequency multiplier will multiply the reference input to output DAC_CLK and REF_CLK. DAC_CLK is set according to the DAC's operating frequency, and REF_CLK is determined according to the operating range of the frequency divider. In this system, REF_CLK = DAC_CLK / N, N<=40. The frequency divider will receive REF_CLK and divide it to output the required SYSREF. The clock fan-out will fan out DAC_CLK into N DAC_CLKs according to the number of DACs. The deterministic delay synchronous output condition of the multi-DAC is: The SYSREF of the FPGA is synchronized with the SYSREF of the DAC, and the SYSREF of all DACs is synchronized. The DAC_CLKs are synchronized and their phase difference does not exceed one DAC_CLK cycle; During multiple power-ups, the frequency divider synchronizes the output of all its channels through a program. When performing PCB layout and routing, ensure that all clock traces are of equal length.

2. The deterministic delay and arbitrary range delay compensation adjustment device between multiple DA channels as described in claim 1, characterized in that, The multi-DAC deterministic delay synchronous output is achieved through communication between the FPGA and the DAC via the JESD204B protocol. Upon receiving the SYSREF signal, both the DAC and the FPGA generate a local clock. Once the FPGA and DAC successfully establish a link, the DAC sends feedback to the FPGA via SYNC. Upon receiving the feedback signal from the DAC, the FPGA sends data to the DAC on the rising edge of its local clock. After sending the feedback, the DAC waits for several local clock cycles before releasing all data, thus synchronizing the DAC output.

3. The deterministic delay and arbitrary range delay compensation adjustment device between multiple DA channels as described in claim 1, characterized in that, The routing delay from SYSREF entering the FPGA to generating the local clock is calculated by the program and is denoted as TS. The time from data encoding to transmission to the high-speed link is denoted as TF. The PCB routing delay is calculated by the PCB and is denoted as TP. After the data reaches the DAC through the high-speed link, it is encoded and decoded and then buffered in the DAC. The data is obtained through the DAC's own indicators and is denoted as TD. The delay from SYSREF entering the DAC to generating the local clock is denoted as TM. The routing delay after the trigger signal enters the FPGA is calculated by the program and is denoted as Tt.

4. The deterministic delay and arbitrary range delay compensation adjustment device between multiple DA channels as described in claim 1, characterized in that, The total time from data transmission from the FPGA to the high-speed link interface is: T1 = TS + TF; PCB trace delay is: T2=TP; The total time from the high-speed link interface to the DAC buffer is: T3 = TD + TM; The total time for the trigger signal to enter the FPGA is: T4=Tt.

5. The deterministic delay and arbitrary range delay compensation adjustment device between multiple DA channels as described in claim 1, characterized in that, All delays are: T = T1 + T2 + T3 + T4.

6. The deterministic delay and arbitrary range delay compensation adjustment device between multiple DA channels as described in claim 1, characterized in that, When laying out and routing the PCB, ensure that the high-speed link traces of all DACs are of equal length.

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