Fpga prototyping method, system, medium and computing device of controller

Abstract

The application discloses a kind of controller's FPGA prototype verification method, system, medium and computing device, it is applied to controller's FPGA prototype verification system, the controller's FPGA prototype verification system includes DFI-AXI protocol bus bridge and controller IP core, the method includes by the DFI-AXI protocol bus bridge to the DFI protocol signal received is converted, obtains AXI protocol signal;Wherein, the DFI-AXI protocol bus bridge is based on FIFO to the DFI protocol signal is written and read;The AXI protocol signal is sent to the controller IP core;By the controller IP core, the AXI protocol signal is converted, obtains target protocol signal;The target protocol signal is sent to controller memory grain, to realize the FPGA prototype verification of the controller;Wherein, the controller memory grain is hung on FPGA.The application can be carried out to the complete FPGA prototype verification of controller.

Description

Technical Field

[0001] This invention relates to the field of FPGA (Field Programmable Gate Array) prototyping technology, and more specifically, to an FPGA prototyping method, system, medium, and computing device for a controller. Background Technology

[0002] With Moore's Law, the number of transistors integrated on a single chip is increasing, leading to greater complexity in integrated circuit design and a corresponding increase in the difficulty of chip functional verification. FPGA prototyping, due to its advantages in cost and speed, has become an irreplaceable verification solution in the field of integrated circuit design functional verification.

[0003] The existing FPGA-based prototype verification system verifies the DDR (Double Data Rate) controller by using a self-designed Physical Interface (PHY) converter module. This module converts the DFI (DDR PHY Interface) interface signals sent by the DDR controller to be verified into the interface signals required by the self-designed PHY, thereby enabling the DDR controller to read and write to DDR memory.

[0004] However, in practice, it has been found that the verifiable functionality of the DDR controller to be verified is severely limited by the functionality of the self-designed PHY. If the self-designed PHY only supports read and write data transmission with a DDR burst length (BL) of 8 bytes, then it is impossible to verify the functional scenario of a DDR burst length of 4 bytes. Furthermore, because the self-designed PHY interface module does not implement cross-clock domain transmission of interface signals, the high-speed DDR controller to be verified cannot run on an FPGA prototyping system with a lower clock frequency due to signal rate mismatch. Therefore, the existing technical solutions cannot achieve complete FPGA prototyping verification of the DDR controller.

[0005] There is currently no effective solution to the above problems. Summary of the Invention

[0006] This invention provides an FPGA prototype verification method, system, medium, and computing device for a controller, which can perform complete FPGA prototype verification of the controller.

[0007] According to one aspect of the present invention, an FPGA prototyping method for a controller is provided, applied to an FPGA prototyping system for a controller, the FPGA prototyping system for the controller including a DFI-AXI protocol bus bridge and a controller IP core, the method comprising:

[0008] The received DFI protocol signal is converted into an AXI protocol signal by the DFI-AXI protocol bus bridge; wherein, the DFI-AXI protocol bus bridge writes to and reads the DFI protocol signal based on FIFO;

[0009] The AXI protocol signal is sent to the controller IP core;

[0010] The controller IP core converts the AXI protocol signal to obtain the target protocol signal.

[0011] The target protocol signal is sent to the controller memory chip to realize the FPGA prototype verification of the controller; wherein the controller memory chip is externally attached to the FPGA.

[0012] As an optional implementation, the DFI protocol signal includes at least one of a control signal, an address signal, and a data signal, wherein:

[0013] The control signal is an activation command, a read command, a write command, a self-refresh command, or a ZQ calibration command;

[0014] The address signal is the read address corresponding to the read instruction or the write address corresponding to the write instruction;

[0015] The data signal is the write data corresponding to the write instruction.

[0016] As an optional implementation, the step of converting the received DFI protocol signal to an AXI protocol signal via the DFI-AXI protocol bus bridge includes:

[0017] The received DFI protocol signal is sampled through the DFI-AXI protocol bus bridge to obtain the target control signal and the target address signal;

[0018] The target control signal is decoded to obtain the target instruction corresponding to the target control signal;

[0019] The target address signal is decoded to obtain the logical address of the controller; wherein the logical address includes at least the target region, target region group, row address, and column address of the controller memory particle;

[0020] The target instruction and the logical address are determined as AXI protocol signals.

[0021] As an optional implementation, if the target instruction is a read instruction, sending the AXI protocol signal to the controller IP core includes:

[0022] Obtain the AXI read address port that matches the read command;

[0023] The logical address in the AXI protocol signal is sent to the controller IP core through the AXI read address port.

[0024] As an optional implementation, if the target instruction is a write instruction, sending the AXI protocol signal to the controller IP core includes:

[0025] Obtain the AXI write address port and AXI write data port that match the write instruction;

[0026] The DFI protocol signal is sampled to obtain the data to be written;

[0027] The logical address in the AXI protocol signal is sent to the controller IP core through the AXI write address port;

[0028] The data to be written is sent to the controller IP core through the AXI write data port.

[0029] According to another aspect of the present invention, an FPGA prototype verification system for the controller is also provided, comprising a DFI-AXI protocol bus bridge and a controller IP core, wherein:

[0030] The DFI-AXI protocol bus bridge is used to convert the received DFI protocol signal into an AXI protocol signal; and send the AXI protocol signal to the controller IP core; wherein, the DFI-AXI protocol bus bridge module writes and reads the DFI protocol signal based on FIFO;

[0031] The controller IP core is used to convert the AXI protocol signal to obtain the target protocol signal; and send the target protocol signal to the controller memory chip to realize the FPGA prototype verification of the controller; wherein, the controller memory chip is externally connected to the FPGA.

[0032] As an optional implementation, the DFI protocol signal includes at least one of a control signal, an address signal, and a data signal, wherein:

[0033] The control signal is an activation command, a read command, a write command, a self-refresh command, or a ZQ calibration command;

[0034] The address signal is the read address corresponding to the read instruction or the write address corresponding to the write instruction;

[0035] The data signal is the write data corresponding to the write instruction.

[0036] As an optional implementation, the DFI-AXI protocol bus bridge includes an initialization module, a DFI command decoding module, and a DFI address decoding module, wherein:

[0037] The initialization module is used to sample the received DFI protocol signal to obtain the target control signal and the target address signal;

[0038] The DFI command decoding module is used to decode the target control signal to obtain the target command corresponding to the target control signal;

[0039] The DFI address decoding module is used to decode the target address signal to obtain the logical address of the controller; wherein, the logical address includes at least the target region, target region group, row address and column address of the controller memory particle;

[0040] The AXI protocol signal includes the target instruction and the logical address.

[0041] As an optional implementation, the DFI-AXI protocol bus bridge further includes a read transaction transfer module and an AXI_Master transfer module, wherein:

[0042] The read transaction transmission module is configured to, if the target instruction is a read instruction, read and store the logical address based on FIFO; obtain the AXI read address port matching the read instruction; and send the logical address to the AXI_Master transmission module through the AXI read address port.

[0043] As an optional implementation, the DFI-AXI protocol bus bridge further includes a write transaction transfer module, wherein:

[0044] The write transaction transmission module is configured to: if the target instruction is a write instruction, read and store the logical address based on a FIFO; sample the DFI protocol signal to obtain the data to be written; store the data to be written based on a FIFO; obtain the AXI write address port and AXI write data port that match the write instruction; send the logical address to the AXI_Master transmission module through the AXI write address port; and send the data to be written to the AXI_Master transmission module through the AXI write data port.

[0045] According to another aspect of the present invention, a computing device is also provided, the computing device comprising: at least one processor, a memory, and an input / output unit; wherein the memory is used to store a computer program, and the processor is used to invoke the computer program stored in the memory to execute the FPGA prototype verification method of the controller described above.

[0046] According to another aspect of the present invention, a computer-readable storage medium is also provided, which includes instructions that, when executed on a computer, cause the computer to perform the FPGA prototyping method of the controller described above.

[0047] In this embodiment of the invention, signal conversion and transmission between DFI protocol signals and AXI protocol signals are realized through the DFI-AXI protocol bus bridge. At the same time, the problem of cross-clock domain transmission of signals between the DFI signal clock domain and the AXI signal clock domain is solved through FIFO, which enables complete FPGA prototype verification of the controller. Attached Figure Description

[0048] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this application, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0049] Figure 1 This is a flowchart illustrating an optional FPGA prototype verification method for a controller according to an embodiment of the present invention.

[0050] Figure 2 This is a schematic diagram of the structure of an optional controller FPGA prototyping system provided according to an embodiment of the present invention;

[0051] Figure 3 This is a schematic diagram of the structure of a DFI-AXI protocol bus bridge according to an embodiment of the present invention;

[0052] Figure 4 This is a schematic diagram of the structure of a medium provided according to an embodiment of the present invention;

[0053] Figure 5 This is a schematic diagram of the structure of a computing device provided according to an embodiment of the present invention. Detailed Implementation

[0054] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0056] The following is for reference. Figure 1 , Figure 1 This is a flowchart illustrating an FPGA prototyping method for a controller according to an embodiment of the present invention. It should be noted that the embodiments of the present invention can be applied to an FPGA prototyping system for a controller, which includes a DFI-AXI protocol bus bridge and a controller IP core.

[0057] Figure 1 The flowchart of the FPGA prototype verification method for a controller provided in an embodiment of the present invention, shown below, includes:

[0058] Step S101: The received DFI protocol signal is converted through the DFI-AXI protocol bus bridge to obtain the AXI protocol signal.

[0059] In this embodiment of the invention, the DFI-AXI protocol bus bridge writes to and reads the DFI protocol signals based on a FIFO; the DFI protocol signals include at least one of control signals, address signals, and data signals, wherein:

[0060] The control signal is an activation command, a read command, a write command, a self-refresh command, or a ZQ calibration command; the address signal is the read address corresponding to the read command or the write address corresponding to the write command; the data signal is the write data corresponding to the write command.

[0061] This embodiment can be used in scenarios where an FPGA prototyping system verifies a DDR controller. This method is applicable to FPGA prototyping platforms that integrate a DFI-AXI protocol bus bridge and a built-in DDR controller IP core. The method is implemented using a combination of hardware and software and is typically integrated into the FPGA prototyping system.

[0062] like Figure 1 As shown, the FPGA prototype verification method for the controller provided in this embodiment of the invention involves the following structure: a DDR controller to be verified, a DFI-AXI protocol bus bridge ported into the FPGA, a DDR controller IP core provided inside the FPGA, and DDR memory chips external to the FPGA.

[0063] The DFI-AXI protocol bus bridge is used to receive signals sent by the DDR controller to be verified in the form of DFI protocol, and decodes and buffers the received data signals inside the protocol bus bridge, and finally converts them into AXI protocol signals and outputs them to the DDR controller IP core provided inside the FPGA.

[0064] The DDR controller IP core provided inside the FPGA is used to receive the AXI protocol signal sent by the DFI-AXI protocol bus bridge. The received signal is decoded, arbitrated, and buffered within the DDR controller IP core provided inside the FPGA, and finally converted into a DDR protocol signal and output to the DDR memory chip connected to the FPGA.

[0065] The DDR memory chip attached to the FPGA is used to receive DDR protocol signals from the DDR controller IP core provided inside the FPGA, and to perform data read and write operations inside the DDR memory chip according to the received signals.

[0066] As an optional implementation, step S101 converts the received DFI protocol signal to an AXI protocol signal via the DFI-AXI protocol bus bridge in the following specific manner:

[0067] The received DFI protocol signal is sampled through the DFI-AXI protocol bus bridge to obtain the target control signal and the target address signal;

[0068] The target control signal is decoded to obtain the target instruction corresponding to the target control signal;

[0069] The target address signal is decoded to obtain the logical address of the controller; wherein the logical address includes at least the target region, target region group, row address, and column address of the controller memory particle;

[0070] The target instruction and the logical address are determined as AXI protocol signals.

[0071] In this embodiment of the invention, the DDR controller to be verified sends control signals, address signals, and data signals to the DFI-AXI protocol bus bridge in the form of the DFI protocol. The control signals mainly refer to the relevant control commands defined in the DDR protocol, such as activation, read instructions, write instructions, self-refresh instructions, ZQ calibration instructions, etc.; the address signals and data signals refer to the read / write addresses and read / write data corresponding to the DDR read / write commands, respectively.

[0072] In this step, the DFI-AXI protocol bus bridge receives the control signal, address signal, and data signal of the DFI protocol signal. Inside the bus bridge, it samples, decodes, and buffers these signals, and finally outputs the decoded read / write address and read / write data in the form of the AXI protocol to the DDR controller IP core provided inside the FPGA.

[0073] Specifically: The DFI-AXI protocol bus bridge receives control signals such as dfi_cs_n, dfi_act_n, dfi_ras_n, dfi_cas_n, and dfi_we_n from the DDR controller to be verified, and decodes the corresponding DDR instructions such as activation, read, write, self-refresh, and ZQ calibration instructions based on the content of the above five control signals.

[0074] Based on the decoded DDR instructions, the address signal dfi_address sent by the DDR controller to be verified is decoded to generate a valid DDR logical address. The format of the logical address is {bank (target area of ​​memory chip), bank_group (target area group of memory chip), row address, column address}, and the generated DDR logical address is cached in the corresponding read / write address fifo.

[0075] Simultaneously, it receives read and write data signals such as dfi_wrdata and dfi_rddata from the DDR controller to be verified, and caches the read and write data in the corresponding read and write FIFOs according to the decoded DDR instructions;

[0076] Finally, based on the decoded DDR instructions, the cached write address signal is output from the axi_awaddr port, the cached write data signal is output from the axi_wdata port, the cached read address signal is output from the axi_araddr port, and the read data signal is input from the axi_rdata port.

[0077] After receiving the read data axi_rdata, the DFI-AXI protocol bus bridge internally converts it from serial to parallel to generate the dfi_rddata and dfi_rddata_valid signals, which are then output to the DDR controller, thus completing the read and write operation of the DDR controller to be verified.

[0078] Step S102: Send the AXI protocol signal to the controller IP core.

[0079] As an optional implementation, if the target instruction is a read instruction, step S102, which sends the AXI protocol signal to the controller IP core, can specifically be as follows:

[0080] Obtain the AXI read address port that matches the read command;

[0081] The logical address in the AXI protocol signal is sent to the controller IP core through the AXI read address port.

[0082] Optionally, if the target instruction is a write instruction, step S102, which sends the AXI protocol signal to the controller IP core, can specifically be as follows:

[0083] Obtain the AXI write address port and AXI write data port that match the write instruction;

[0084] The DFI protocol signal is sampled to obtain the data to be written;

[0085] The logical address in the AXI protocol signal is sent to the controller IP core through the AXI write address port;

[0086] The data to be written is sent to the controller IP core through the AXI write data port.

[0087] In this embodiment of the invention, the DDR controller IP core provided inside the FPGA includes an AXI_Slave transmission module, which is used to receive AXI protocol signals transmitted from the DFI-AXI protocol bus bridge, and decode the control signals, address signals and data signals contained in the AXI protocol signals, convert them into DDR protocol signals and output them to the DDR memory chips connected to the FPGA.

[0088] In this step, since the DDR controller IP core provided internally by the FPGA is invoked, the corresponding power-on initialization, mode register configuration, self-refresh, signal training and calibration operations within the DDR memory chip are all completed by the DDR controller IP core provided internally by the FPGA. Therefore, the DDR controller to be verified only needs to transmit the relevant read / write instructions, read / write addresses, and read / write data.

[0089] Step S103: The AXI protocol signal is converted by the controller IP core to obtain the target protocol signal.

[0090] Step S104: Send the target protocol signal to the controller memory chip to realize the FPGA prototype verification of the controller.

[0091] In this embodiment of the invention, the controller memory chip is externally connected to the FPGA. The DDR memory chip performs data write and read operations to its internal address based on received signals. The read data is then fed back to the DDR controller IP core provided within the FPGA in DDR protocol format. The DDR controller IP core within the FPGA converts the read data into AXI protocol format and feeds it back to the DFI-AXI protocol bus bridge. Finally, the read data is fed back to the DDR controller to be verified by the DFI protocol bus bridge in DFI protocol format. The execution of read / write operations of the DDR controller to be verified on the FPGA prototype verification system is successfully achieved.

[0092] This invention enables signal conversion and transmission between DFI protocol signals and AXI protocol signals through a DFI-AXI protocol bus bridge. At the same time, it solves the problem of cross-clock domain transmission of signals between the DFI signal clock domain and the AXI signal clock domain through FIFO, and enables complete FPGA prototype verification of the controller.

[0093] After introducing the method of exemplary embodiments of the present invention, the following references are made. Figure 2 An exemplary embodiment of the present invention provides an FPGA prototype verification system for a controller, the system comprising a DFI-AXI protocol bus bridge 201 and a controller IP core 202, wherein:

[0094] The DFI-AXI protocol bus bridge 201 is used to convert the received DFI protocol signal into an AXI protocol signal; and send the AXI protocol signal to the controller IP core; wherein, the DFI-AXI protocol bus bridge module writes and reads the DFI protocol signal based on FIFO;

[0095] In this embodiment of the invention, the DFI protocol signal includes at least one of a control signal, an address signal, and a data signal, wherein:

[0096] The control signal is an activation command, a read command, a write command, a self-refresh command, or a ZQ calibration command; the address signal is the read address corresponding to the read command or the write address corresponding to the write command; the data signal is the write data corresponding to the write command.

[0097] The controller IP core 202 is used to convert the AXI protocol signal to obtain a target protocol signal; and send the target protocol signal to the controller memory chip to realize the FPGA prototype verification of the controller; wherein, the controller memory chip is externally connected to the FPGA.

[0098] Please refer to the following: Figure 3 , Figure 3 This is a schematic diagram of a DFI-AXI protocol bus bridge according to an embodiment of the present invention; the DFI-AXI protocol bus bridge 201 includes an initialization module 2011, a DFI command decoding module 2012, a DFI address decoding module 2013, a read transaction transmission module 2014, a write transaction transmission module 2015, and an AXI_Master transmission module 2016, wherein:

[0099] The initialization module 2011 is used to sample the received DFI protocol signal to obtain the target control signal and the target address signal;

[0100] The DFI command decoding module 2012 is used to decode the target control signal to obtain the target command corresponding to the target control signal;

[0101] The DFI address decoding module 2013 is used to decode the target address signal to obtain the logical address of the controller; wherein the logical address includes at least the target region, target region group, row address and column address of the controller memory particle;

[0102] The AXI protocol signal includes the target instruction and the logical address.

[0103] The read transaction transmission module 2014 is used to read and store the logical address based on FIFO if the target instruction is a read instruction; and to obtain the AXI read address port that matches the read instruction; and to send the logical address to the AXI_Master transmission module 2016 through the AXI read address port.

[0104] The write transaction transmission module 2015 is configured to: if the target instruction is a write instruction, read and store the logical address based on FIFO; sample the DFI protocol signal to obtain the data to be written; store the data to be written based on FIFO; obtain the AXI write address port and AXI write data port matching the write instruction; send the logical address to the AXI_Master transmission module 2016 through the AXI write address port; and send the data to be written to the AXI_Master transmission module 2016 through the AXI write data port.

[0105] In this embodiment of the invention, the initialization module 2011 is used to simulate the power-on initialization process of the DDR according to the timing requirements of the DFI protocol, providing feedback to the DDR controller to be verified indicating that the initialization process is complete. After receiving the dfi_init_start signal from the DDR controller to be verified, the initialization module 2011 pulls the dfi_init_complete signal high and sends it back to the DDR controller to inform it that the power-on initialization operation is complete. Simultaneously, the initialization module 2011 receives the dfi_freq_ratio and dfi_init_freq signals from the DDR controller to configure the clock frequency and frequency ratio. This module supports three clock frequency ratio operating modes specified by the DFI protocol: 1:1, 1:2, and 1:4.

[0106] The DFI command decoding module 2012 receives and samples DFI command signals from the DDR controller, mainly including control signals such as dfi_cs_n, dfi_act_n, dfi_ras_n, dfi_cas_n, and dfi_we_n. The DFI command decoding module 2012 samples these DFI command signals and decodes them into corresponding DDR protocol instructions, such as mode register configuration commands, activation commands, read commands, and write commands. The decoded instructions are then transmitted to the DFI address decoding module 2013.

[0107] The DFI address decoding module 2013 receives and samples the DFI address signal from the DDR controller and the control signal from the DFI command decoding module 2012. Based on the control signal from the DFI command decoding module 2012, the DFI address decoding module 2013 decodes the DFI address from the DDR controller into the corresponding DDR logical address signal. In this module, when an activation command is received from the DFI command decoding module 2012, the corresponding dfi_address signal is the row address; when a read or write command is received from the DFI command decoding module 2012, the corresponding dfi_address signal is the column address. As described above, the DFI address decoding module 2013 ultimately caches and generates a valid DDR logical address format, which is {bank, bank_group, row address, column address}. Finally, the DFI address decoding module 2013 outputs the control signal and the valid address signal to the write transaction transmission module and the read transaction transmission module.

[0108] The write transaction transmission module receives the address signal to be written to the DDR from the DFI address decoding module 2013 and the write data signal dfi_wrdata and write data enable signal dfi_wrdata_en from the DDR controller. Internally, the write transaction transmission module contains a write transmission state machine, which buffers the received write address and write data signals into the corresponding write address FIFO and write data FIFO according to the timing requirements of the DFI protocol. The module also contains two asynchronous FIFOs: one to buffer the write address signal from the DFI address decoding module 2013, and the other to buffer the write data signal dfi_wrdata from the DDR controller. These two asynchronous FIFOs divide the write transaction module into two clock domains: one for the DFI interface and one for the AXI interface. The FIFO buffering the write data has a serial-to-parallel conversion function, converting four 32-bit dfi_wrdata data signals into one 128-bit write data signal before writing it into the FIFO. This function is to meet the protocol conversion requirements from DFI write data signals to AXI write data signals. The write transaction transmission module ultimately transmits the write address signal and write data signal, which are cached in two FIFOs, to the AXI_Master transmission module 2016.

[0109] The read transaction transmission module receives the address signal of the DDR to be read from the DFI address decoding module 2013 and the read data signal from the DDR controller IP provided by the FPGA. Internally, the read transaction transmission module contains a read transmission state machine, which buffers the received read address signal into the corresponding read address FIFO according to the timing requirements of the DFI protocol. The module also contains two asynchronous FIFOs: one for buffering the read address signal from the DFI address decoding module 2013, and the other for buffering the read data signal from the DDR controller IP provided by the FPGA. These two asynchronous FIFOs divide the read transaction module into two clock domains: one for the DFI interface and one for the AXI interface. The read transaction transmission module then transmits the read address signal buffered in the FIFO to the AXI_Master transmission module 2016. The read transaction transmission module simultaneously receives read data from the AXI_Master transmission module 2016, generates four 32-bit dfi_rddata signals and a read data valid signal dfi_rddata_valid through serial-to-parallel conversion, and feeds these two DFI signals back to the DDR controller to be verified.

[0110] The AXI_Master transmission module 2016 receives write address and write data signals from the write transaction transmission module and converts them into AXI protocol signals for transmission to the DDR controller IP provided by the FPGA. Simultaneously, it receives read address signals from the read transaction transmission module, converts them into AXI protocol signals for transmission to the DDR controller IP provided by the FPGA, and receives read data from the DDR controller IP provided by the FPGA, transmitting it to the read transaction transmission module. According to AXI protocol requirements, the AXI_Master transmission module 2016 has five channels. The read and write channels are independent of each other, and the data and address channels are separate, with data flowing in one direction. Each channel contains a state machine to process and transmit data.

[0111] In summary, the DFI-AXI protocol bus bridge device for verifying DDR controllers in FPGA prototype verification systems provided by this invention is mainly used to complete the signal conversion and transmission between DFI protocol signals and AXI protocol signals, while solving the problem of cross-clock domain transmission of signals between the DFI signal clock domain and the AXI signal clock domain.

[0112] After introducing the methods and systems of exemplary embodiments of the present invention, the following references are made. Figure 4 A computer-readable storage medium according to exemplary embodiments of the present invention will be described, please refer to... Figure 4 The computer-readable storage medium shown is an optical disc 40, on which a computer program (i.e., a program product) is stored. When the computer program is run by a processor, it implements the steps described in the above method implementation, such as converting the received DFI protocol signal to an AXI protocol signal through the DFI-AXI protocol bus bridge; wherein the DFI-AXI protocol bus bridge writes and reads the DFI protocol signal based on FIFO; sending the AXI protocol signal to the controller IP core; converting the AXI protocol signal to a target protocol signal through the controller IP core; and sending the target protocol signal to the controller memory chip to realize the FPGA prototype verification of the controller; wherein the controller memory chip is externally connected to the FPGA; the specific implementation of each step will not be repeated here.

[0113] It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical and magnetic storage media, which will not be elaborated here.

[0114] After introducing the methods, systems, and media of exemplary embodiments of the present invention, the following references are made. Figure 5 A computing device for FPGA prototype verification of a controller, according to an exemplary embodiment of the present invention.

[0115] Figure 5 A block diagram is shown of an exemplary computing device 50 suitable for implementing embodiments of the present invention, which may be a computer system or a server. Figure 5 The computing device 50 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of the present invention.

[0116] like Figure 5 As shown, the components of computing device 50 may include, but are not limited to: one or more processors or processing units 501, system memory 502, and bus 503 connecting different system components (including system memory 502 and processing unit 501).

[0117] The computing device 50 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by the computing device 50, including volatile and non-volatile media, removable and non-removable media.

[0118] System memory 502 may include computer system readable media in the form of volatile memory, such as random access memory (RAM) 5021 and / or cache memory 5022. Computing device 50 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, ROM 5023 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 5 Not shown in the image (usually referred to as a "hard drive"). Although not shown in Figure 5 The diagram illustrates that disk drives for reading and writing to removable non-volatile disks (e.g., "floppy disks") and optical disc drives for reading and writing to removable non-volatile optical discs (e.g., CD-ROMs, DVD-ROMs, or other optical media) can be provided. In these cases, each drive can be connected to bus 503 via one or more data media interfaces. System memory 502 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of the present invention.

[0119] A program / utility 5025 having a set (at least one) of program modules 5024 may be stored, for example, in system memory 502, and such program modules 5024 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment. Program modules 5024 typically perform the functions and / or methods described in the embodiments of the present invention.

[0120] The computing device 50 can also communicate with one or more external devices 504 (such as a keyboard, pointing device, display, etc.). This communication can be performed through the input / output (I / O) interface 505. Furthermore, the computing device 50 can also communicate with one or more networks (such as a local area network (LAN), a wide area network (WAN), and / or a public network, such as the Internet) via a network adapter 506. Figure 5 As shown, network adapter 506 communicates with other modules of computing device 50 (such as processing unit 501) via bus 503. It should be understood that, although... Figure 5 As not shown, it can be used in conjunction with computing device 50 with other hardware and / or software modules.

[0121] The processing unit 501 executes various functional applications and data processing by running programs stored in the system memory 502. For example, it converts the received DFI protocol signal to an AXI protocol signal via the DFI-AXI protocol bus bridge; wherein the DFI-AXI protocol bus bridge writes and reads the DFI protocol signal based on FIFO; sends the AXI protocol signal to the controller IP core; converts the AXI protocol signal to a target protocol signal via the controller IP core; and sends the target protocol signal to the controller memory chip to realize the FPGA prototype verification of the controller; wherein the controller memory chip is externally connected to the FPGA. The specific implementation of each step will not be repeated here. It should be noted that although several units / modules or sub-units / sub-modules of the controller's FPGA prototype verification system are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present invention, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules for embodiment.

[0122] In the description of this invention, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0123] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0124] In the several embodiments provided by this invention, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the coupling or direct coupling or communication connection shown or discussed may be through some communication interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0125] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0126] In addition, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0127] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this invention, essentially, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0128] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0129] Furthermore, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all of the operations shown must be performed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

Claims

1. A method for FPGA prototyping of a controller, applied to an FPGA prototyping system for a controller, the FPGA prototyping system for the controller including a DFI-AXI protocol bus bridge and a controller IP core, the method comprising: The received DFI protocol signal is converted into an AXI protocol signal by the DFI-AXI protocol bus bridge; wherein, the DFI-AXI protocol bus bridge writes to and reads the DFI protocol signal based on FIFO; The DFI-AXI protocol bus bridge sends the AXI protocol signal to the controller IP core; The controller IP core converts the AXI protocol signal to obtain the target protocol signal. The controller IP core sends the target protocol signal to the controller memory chip to realize the FPGA prototype verification of the controller; wherein, the controller memory chip is externally attached to the FPGA; The process of converting the received DFI protocol signal to an AXI protocol signal via the DFI-AXI protocol bus bridge includes: The received DFI protocol signal is sampled through the DFI-AXI protocol bus bridge to obtain the target control signal and the target address signal; The target control signal is decoded to obtain the target instruction corresponding to the target control signal; The target address signal is decoded to obtain the logical address of the controller; wherein the logical address includes at least the target region, target region group, row address, and column address of the controller memory particle; The target instruction and the logical address are determined as AXI protocol signals.

2. The FPGA prototype verification method for the controller according to claim 1, wherein the DFI protocol signal includes at least one of a control signal, an address signal, and a data signal, wherein: The control signal is an activation command, a read command, a write command, a self-refresh command, or a ZQ calibration command; The address signal is the read address corresponding to the read instruction or the write address corresponding to the write instruction; The data signal is the write data corresponding to the write instruction.

3. The FPGA prototype verification method for the controller according to claim 1, wherein if the target instruction is a read instruction, the AXI protocol signal is sent to the controller IP core, comprising: Obtain the AXI read address port that matches the read command; The logical address in the AXI protocol signal is sent to the controller IP core through the AXI read address port.

4. The FPGA prototype verification method for the controller according to claim 1, wherein if the target instruction is a write instruction, the step of sending the AXI protocol signal to the controller IP core includes: Obtain the AXI write address port and AXI write data port that match the write instruction; The DFI protocol signal is sampled to obtain the data to be written; The logical address in the AXI protocol signal is sent to the controller IP core through the AXI write address port; The data to be written is sent to the controller IP core through the AXI write data port.

5. An FPGA prototype verification system for a controller, the FPGA prototype verification system for the controller comprising a DFI-AXI protocol bus bridge and a controller IP core, wherein: The DFI-AXI protocol bus bridge is used to convert the received DFI protocol signal into an AXI protocol signal; and send the AXI protocol signal to the controller IP core; wherein, the DFI-AXI protocol bus bridge module writes and reads the DFI protocol signal based on FIFO; The controller IP core is used to convert the AXI protocol signal to obtain a target protocol signal; and send the target protocol signal to the controller memory chip to realize the FPGA prototype verification of the controller; wherein, the controller memory chip is externally connected to the FPGA; The DFI-AXI protocol bus bridge includes an initialization module, a DFI command decoding module, and a DFI address decoding module, wherein: The initialization module is used to sample the received DFI protocol signal to obtain the target control signal and the target address signal; The DFI command decoding module is used to decode the target control signal to obtain the target command corresponding to the target control signal; The DFI address decoding module is used to decode the target address signal to obtain the logical address of the controller; wherein, the logical address includes at least the target region, target region group, row address and column address of the controller memory particle; The AXI protocol signal includes the target instruction and the logical address.

6. The FPGA prototype verification system for the controller according to claim 5, wherein the DFI protocol signal includes at least one of a control signal, an address signal, and a data signal, wherein: The control signal is an activation command, a read command, a write command, a self-refresh command, or a ZQ calibration command; The address signal is the read address corresponding to the read instruction or the write address corresponding to the write instruction; The data signal is the write data corresponding to the write instruction.

7. The FPGA prototype verification system for the controller according to claim 5, wherein the DFI-AXI protocol bus bridge further includes a read transaction transmission module and an AXI_Master transmission module, wherein: The read transaction transmission module is configured to, if the target instruction is a read instruction, read and store the logical address based on FIFO; obtain the AXI read address port matching the read instruction; and send the logical address to the AXI_Master transmission module through the AXI read address port.

8. The FPGA prototype verification system for the controller according to claim 7, wherein the DFI-AXI protocol bus bridge further includes a write transaction transmission module, wherein: The write transaction transmission module is used to read and store the logical address based on FIFO if the target instruction is a write instruction; and to sample the DFI protocol signal to obtain the data to be written. The system stores the data to be written based on a FIFO; obtains the AXI write address port and AXI write data port that match the write instruction; sends the logical address to the AXI_Master transmission module through the AXI write address port; and sends the data to be written to the AXI_Master transmission module through the AXI write data port.

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