Array substrate and manufacturing method thereof, display panel and display device

Abstract

The embodiments of the present disclosure provide an array substrate and a preparation method thereof, a display panel and a display device. The array substrate comprises a substrate, a first active layer, a first insulating layer, a first conductive layer, a second insulating layer and a pixel electrode which are stacked in sequence, at least part of the orthographic projection of the first active layer on the substrate is located in the sub-pixel region, the material of the first active layer comprises an oxide, the first conductive layer comprises a gate line and a first gate electrode, the material of the gate line comprises a metal, the first gate electrode is connected to the gate line, the material of the first gate electrode comprises a transparent conductive material, the orthographic projection of the first gate electrode on the substrate and the orthographic projection of the first active layer on the substrate have a first overlapping region, the first overlapping region is located in the sub-pixel region, and the pixel electrode is connected to the first active layer. The technical solution of the present disclosure is conducive to improving the aperture ratio of the product.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, a display panel and a display device. Background Art

[0002] Virtual Reality (VR) and Augmented Reality (AR) are currently popular display technologies. In VR display, the core component is the head-mounted display (HMD). Since the screen is very close to the eyes, the VR device is a near-eye display device. Near-eye display devices have extremely high requirements for screen resolution.

[0003] LCD (Liquid Crystal Display) technology is easier to achieve high resolution than Organic Light-Emitting Diode (OLED) display technology and is the mainstream display technology in current VR / AR products. With the popularization of VR / AR products, the resolution requirements for display products are getting higher and higher. As the resolution increases, the number of metal traces increases, resulting in a gradual decrease in the pixel aperture ratio. How to increase the pixel aperture ratio while increasing the resolution is a technical problem that needs to be solved. Summary of the invention

[0004] Embodiments of the present disclosure provide an array substrate and a method for manufacturing the same, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides an array substrate, including a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the plurality of gate lines and the plurality of data lines intersect each other to define a plurality of sub-pixel areas, and the array substrate includes:

[0006] substrate;

[0007] A first active layer is located on one side of the substrate, at least a portion of an orthographic projection of the first active layer on the substrate is located in the sub-pixel region, the material of the first active layer includes an oxide semiconductor material, and the first active layer is connected to the data line;

[0008] A first conductive layer is located on a side of the substrate facing the first active layer, the first conductive layer includes a gate line and a first gate electrode, the gate line is made of a conductive metal material, the first gate electrode is connected to the gate line, the first gate electrode is made of a transparent conductive material, an orthographic projection of the first gate electrode on the substrate and an orthographic projection of the first active layer on the substrate have a first overlapping region, and the first overlapping region is located in a sub-pixel region;

[0009] A first insulating layer, located between the first active layer and the first conductive layer;

[0010] A second insulating layer is located on a side of the first active layer and the first conductive layer away from the substrate;

[0011] The pixel electrode is located on a side of the second insulating layer away from the substrate, and the pixel electrode is connected to the first active layer.

[0012] In one embodiment, the first active layer extends along a first direction in the sub-pixel region, and in the first direction, the first active layers in adjacent sub-pixel regions are staggered with each other along a second direction.

[0013] In one embodiment, an extension direction of the first active layer is not perpendicular to the first direction, and an extension direction of the first active layer is not perpendicular to the second direction.

[0014] In one embodiment, the array substrate further includes a planar layer and a connecting electrode, the planar layer is located between the second insulating layer and the pixel electrode, the connecting electrode is located between the second insulating layer and the planar layer, the second insulating layer is provided with a third via hole penetrating the second insulating layer, and the connecting electrode is connected to the first active layer through the third via hole; the planar layer is provided with a fourth via hole, and the pixel electrode is connected to the connecting electrode through the fourth via hole, and the material of the connecting electrode includes a transparent conductive material.

[0015] In one embodiment, the orthographic projection of the third via hole on the substrate and the first overlapping area are located in the same sub-pixel area.

[0016] In one embodiment, the orthographic projection of the fourth via hole on the substrate is located within the range of the orthographic projection of the gate line on the substrate; the array substrate also includes a third insulating layer and a boss, the third insulating layer is located on the side of the pixel electrode away from the substrate, the boss is located on the side of the third insulating layer away from the substrate, and the orthographic projection of the boss on the substrate is located within the range of the orthographic projection of the fourth via hole on the substrate.

[0017] In one embodiment, the first conductive layer is located on a side of the first active layer away from the substrate, the data line is located between the substrate and the first active layer, the data line includes a first surface area, and the first active layer is overlapped and connected to a portion of the first surface area.

[0018] In one embodiment, the array substrate also includes a buffer layer, which is located between the data line and the first active layer. The buffer layer is provided with a first via hole, and the surface of the data line exposed through the first via hole is a first surface area. The first active layer is overlapped and connected to a portion of the first surface area through the first via hole.

[0019] In one embodiment, the first active layer includes a first conductor region outside the first overlapping region, the first conductor region is overlapped and connected to a portion of the first surface region through a first via, the first conductor region includes a side wall along an overlap boundary between the first conductor region and the first surface region, and a slope angle of the side wall is less than 90°.

[0020] In one embodiment, the array substrate further includes a fourth insulating layer, the fourth insulating layer is located between the second insulating layer and the connecting electrode, and the data line is located between the second insulating layer and the fourth insulating layer.

[0021] In one embodiment, the array substrate includes a display area and a frame area outside the display area, the data line, the first active layer, the first conductive layer and the pixel electrode are all located in the display area, the array substrate further includes a first electrode, a second active layer, a second electrode and a second gate electrode located in the frame area, the second active layer is arranged in the same layer as the first active layer, and the second gate electrode is arranged in the same layer as the gate line;

[0022] The first electrode and the second electrode are located on a side of the second insulating layer away from the substrate; or, the first electrode and the second electrode are arranged in the same layer as the gate line.

[0023] As a second aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a method for preparing an array substrate, wherein the array substrate includes a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the plurality of gate lines and the plurality of data lines intersect with each other to define a plurality of sub-pixel regions, and the method for preparing the array substrate includes:

[0024] Forming a first active layer on the substrate, wherein at least a portion of the orthographic projection of the first active layer on the substrate is located in the sub-pixel region, the material of the first active layer includes oxide, and the first active layer is connected to the data line;

[0025] forming a first insulating layer on a side of the first active layer facing away from the substrate;

[0026] A first conductive layer is formed on a side of the first insulating layer away from the substrate, the first conductive layer includes a gate line and a first gate electrode, the gate line is made of metal, the first gate electrode is connected to the gate line, the first gate electrode is made of a transparent conductive material, an orthographic projection of the first gate electrode on the substrate and an orthographic projection of the first active layer on the substrate have a first overlapping region, and the first overlapping region is located in a sub-pixel region;

[0027] forming a second insulating layer on a side of the first conductive layer facing away from the substrate;

[0028] A pixel electrode is formed on a side of the second insulating layer away from the substrate, and the pixel electrode is connected to the first active layer.

[0029] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display panel, including the array substrate in the embodiments of the present disclosure, and also including a color film substrate, the color film substrate is arranged opposite to the array substrate, the pixel electrode faces the color film substrate, and the display panel also includes a liquid crystal arranged between the array substrate and the color film substrate.

[0030] As a fourth aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, including the array substrate or the display panel in the embodiments of the present disclosure.

[0031] In the array substrate of the disclosed embodiment, the material of the first active layer includes an oxide semiconductor material, and such a first active layer is a transparent material, so that the first active layer and the first gate electrode are both transparent materials. At least part of the first active layer is arranged in the sub-pixel area, and the first overlapping area is arranged in the sub-pixel area, which reduces the space occupied by the first active layer and the first overlapping area outside the sub-pixel area and improves the product aperture ratio. In addition, since the first active layer and the first gate electrode are both transparent materials, the first active layer and the first gate electrode located in the sub-pixel area will not affect the transmittance of the sub-pixel area.

[0032] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0034] Figure 1 is a partial plan view of an array substrate in an embodiment of the present disclosure;

[0035] Figure 2 for Figure 1 The AA cross-sectional view of the array substrate in one embodiment is shown;

[0036] Figure 3 is a partial plan view of an array substrate in another embodiment of the present disclosure;

[0037] Figure 4 is a partial plan view of an array substrate in another embodiment of the present disclosure;

[0038] Figure 5 is a schematic AA cross-sectional view of an array substrate in another embodiment of the present disclosure;

[0039] Figure 6 is a schematic diagram of an AA cross-section of an array substrate in another embodiment of the present disclosure;

[0040] Figure 7 for Figure 6 An enlarged schematic diagram of part B in FIG.

[0041] Figure 8 is a schematic AA cross-sectional view of an array substrate in another embodiment of the present disclosure;

[0042] Fig. 9 for Figure 8 A magnified schematic diagram of part C;

[0043] Fig.10 is a cross-sectional schematic diagram of an array substrate in another embodiment of the present disclosure;

[0044] Fig.11 is a plan view of an array substrate in an embodiment of the present disclosure;

[0045] Fig.12 is a cross-sectional schematic diagram of an array substrate in an embodiment of the present disclosure;

[0046] Fig.13 FIG. 4 is a schematic cross-sectional view of an array substrate in another embodiment of the present disclosure.

[0047] Description of reference numerals:

[0048] 11. substrate; 121. data line; 13. buffer layer; 141. first conductor area; 142. second conductor area; 143. first channel; 15. first insulating layer; 161. gate line; 162. second gate electrode; 163. first gate electrode; 17. second insulating layer; 18. flat layer; 19. pixel electrode; 21. connecting electrode; 22. third insulating layer; 23. boss; 24. common electrode layer; 25. auxiliary shielding line; 26. fourth insulating layer; 27. shading layer; 31. first via hole; 32. second via hole; 33. third via hole; 34. fourth via hole; 35. fifth via hole; 41. first electrode; 42. second electrode; 144. third conductor area; 145. fourth conductor area; 146; second channel. DETAILED DESCRIPTION

[0049] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure, and different embodiments may be combined arbitrarily without conflict. Therefore, the drawings and descriptions are considered to be illustrative in nature and not restrictive.

[0050] Figure 1is a partial plan view of an array substrate in an embodiment of the present disclosure, Figure 2 for Figure 1 The AA cross-sectional view of the array substrate in one embodiment is shown in FIG. Figure 3 is a partial plan view of an array substrate in another embodiment of the present disclosure, Figure 4 FIG. 1 is a partial plan view of an array substrate in another embodiment of the present disclosure. Figure 1 and Figure 2 As shown, the array substrate includes a plurality of gate lines 161 extending along a first direction X and a plurality of data lines 121 extending along a second direction Y. The plurality of gate lines 161 are sequentially arranged at intervals along the second direction Y, and the plurality of data lines 121 are sequentially arranged at intervals along the first direction X. The plurality of gate lines 161 and the plurality of data lines 121 intersect with each other to define a plurality of sub-pixel regions. The array substrate includes a substrate 11, a first active layer 140, a first conductive layer, a first insulating layer 15, a second insulating layer 17 and a pixel electrode 19. The second direction Y is not parallel to the first direction X. Exemplarily, the second direction Y is perpendicular to the first direction X.

[0051] like Figure 2 As shown, the first active layer 140 is located on one side of the substrate 11 , and the orthographic projection of the first active layer 140 on the substrate 11 is at least partially located in the sub-pixel region. The material of the first active layer 140 includes oxide, and the first active layer 140 is connected to the data line 121 .

[0052] The first conductive layer is located on the side of the substrate 11 facing the first active layer 140, and the first conductive layer includes a gate line 161 and a first gate electrode 163. The material of the gate line 161 may include a conductive metal. The first gate electrode 163 is connected to the gate line 161. The material of the first gate electrode 163 includes a transparent conductive material. The orthographic projection of the first gate electrode 163 on the substrate 11 and the orthographic projection of the first active layer 140 on the substrate 11 have a first overlapping region. The first overlapping region is located in the sub-pixel region.

[0053] The first insulating layer 15 is located between the first active layer 140 and the first conductive layer. The second insulating layer 17 is located on the side of the first active layer 140 and the first conductive layer away from the substrate 11. The pixel electrode 19 is located on the side of the second insulating layer 17 away from the substrate 11, and the pixel electrode 19 is connected to the first active layer 140.

[0054] In the array substrate of the embodiment of the present disclosure, the material of the first active layer 140 includes an oxide semiconductor material, and such a first active layer 140 is a transparent material, so that the first active layer 140 and the first gate electrode 163 are both transparent materials. At least a portion of the first active layer 140 is arranged in the sub-pixel region, and the first overlapping region is arranged in the sub-pixel region, which reduces the space occupied by the first active layer 140 and the first overlapping region outside the sub-pixel region, and improves the pixel aperture ratio. In addition, since the first active layer 140 and the first gate electrode 163 are both transparent materials, the first active layer 140 and the first gate electrode 163 located in the sub-pixel region will not affect the transmittance of the sub-pixel region.

[0055] The technical solution disclosed in the present invention can be applied to ultra-high PPI display products. When applied to ultra-high PPI display products, the first active layer adopts a transparent material, the first gate electrode adopts a transparent material, and at least a part of the first active layer is located in the sub-pixel area, and the first overlapping area is located in the sub-pixel area, thereby reducing the occupation of the first active layer and the first gate electrode in the non-pixel area, improving the product aperture ratio, and reducing the influence of metal routing in the ultra-high PPI product on the product aperture ratio.

[0056] Exemplarily, the material of the substrate 11 may include glass, for example, the material of the substrate 11 is glass. Exemplarily, the material of the substrate 11 may include an organic material, for example, the material of the substrate 11 may be polyimide (PI).

[0057] The material of the first active layer 140 may include an oxide semiconductor material. The material of the first active layer 140 may include indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO) or indium gallium oxide (IGO), etc., or the material of the first active layer 140 may be a doped oxide semiconductor material.

[0058] Exemplarily, the material of the first active layer 140 may include an oxide semiconductor material with high mobility and high light stability. For example, the material of the first active layer 140 may include an oxide semiconductor doped with a rare earth element. The oxide material with high light stability is less affected by light. When a thin film transistor with a high light stability oxide as an active layer is exposed to light, its negative bias is relatively small, and the negative bias is generally less than 1V. The first active layer 140 of the embodiment of the present disclosure is less affected by light, and a light shielding layer 27 (such as Fig.10 shown).

[0059] like Figure 2As shown, the first active layer 140 is closer to the substrate than the first conductive layer, that is, the first conductive layer is located on the side of the first active layer 140 away from the substrate 11. In another embodiment, the first conductive layer is closer to the substrate 11 than the first active layer 140, that is, the first active layer 140 is located on the side of the first conductive layer away from the substrate 11.

[0060] like Figure 1 As shown, the first active layer 140 may extend in the sub-pixel region along the first direction X. The first gate electrode 163 may extend in the sub-pixel region along the second direction Y. In the first direction X, the first active layers 140 in adjacent sub-pixel regions may be located on the same straight line extending in the first direction X.

[0061] In one embodiment, Figure 3 As shown, in the first direction X, the first active layers 140 in adjacent sub-pixel regions are staggered. Figure 3 As shown, the first active layers 140 are staggered in the first direction X and staggered in the second direction Y. If the two first active layers 140 in two adjacent sub-pixel regions are translated along the first direction X to the same straight line extending along the second direction Y, then there is no overlapping area between the two first active layers 140. Figure 1 In the embodiment, the first active layer 140 in the sub-pixel region P1 and the first active layer 140 in the sub-pixel region P2 are both translated along the first direction X to the same data line 121 a , and there is no overlapping area between the two first active layers 140 .

[0062] exist Figure 1 In the illustrated embodiment, in the first direction X, the first active layers 140 in adjacent sub-pixel regions are located on the same straight line extending along the first direction X. In order to meet the requirements of the manufacturing process of the first active layer 140, the spacing d between two adjacent first active layers 140 along the first direction X needs to be greater than or equal to a preset value. This results in the number of first active layers 140 disposed in the first direction X being limited, so that the number of sub-pixels in the first direction X is limited, and the improvement of resolution is limited.

[0063] Figure 3 In the illustrated embodiment, by arranging adjacent first active layers 140 in the first direction X to be staggered with each other, the value of the interval d can be reduced, for example Figure 3 d2 can be less than Figure 1 Thus, the number of the first active layer 140 in the first direction X can be increased, the number of sub-pixels in the first direction X can be increased, and the resolution of the product can be improved, which is conducive to achieving ultra-high resolution of the product.

[0064] In one embodiment, Figure 4 As shown, the extension direction of the first active layer 140 is not perpendicular to the first direction X, and the extension direction of the first active layer 140 is not perpendicular to the second direction Y. In other words, the first active layer 140 is tilted relative to the gate line and the data line in the sub-pixel area. In this way, the size of the first active layer 140 in the first direction X can be reduced, the number of the first active layer 140 in the first direction X can be increased, the number of sub-pixels in the first direction X can be increased, and the resolution of the product can be improved.

[0065] In one embodiment, Figure 2 As shown, the array substrate may further include a planar layer 18 and a connecting electrode 21. The planar layer 18 is located between the second insulating layer 17 and the pixel electrode 19, and the connecting electrode 21 is located between the second insulating layer 17 and the planar layer 18. The second insulating layer 17 is provided with a third via hole 33 penetrating the second insulating layer 17, and the connecting electrode 21 is connected to the first active layer 140 through the third via hole 33. The planar layer 18 is provided with a fourth via hole 34. The fourth via hole 34 exposes at least part of the surface of the connecting electrode 21. The pixel electrode 19 is connected to the connecting electrode 21 through the fourth via hole 34, and the material of the connecting electrode 21 includes a transparent conductive material. The connecting electrode 21 made of a transparent conductive material will not block light, thereby further improving the aperture ratio and transmittance of the product.

[0066] In the embodiment of the present disclosure, the transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO), etc. The material of the connecting electrode 21 may include at least one of ITO and IZO.

[0067] Figure 2 In the array substrate shown, the pixel electrode 19 is directly connected to the first active layer 140 through the connecting electrode 21, which reduces the use of the drain electrode metal layer. Such a structure reduces the opaque metal pattern and improves the aperture ratio and transmittance of the array substrate.

[0068] In one embodiment, Figure 1 to Figure 4 As shown, the orthographic projection of the fourth via hole 34 on the substrate 11 is located within the range of the orthographic projection of the gate line 161 on the substrate 11. The array substrate may further include a third insulating layer 22 and a boss 23. The third insulating layer 22 is located on the side of the pixel electrode 19 that is away from the substrate 11. The boss 23 is located on the side of the third insulating layer 22 that is away from the substrate 11, and the orthographic projection of the boss 23 on the substrate 11 is located within the range of the orthographic projection of the fourth via hole 34 on the substrate 11.

[0069] It should be noted that, in the LCD, the boss 23 can be used to support the main spacer on the color filter substrate to maintain the box thickness of the LCD. The orthographic projection of the fourth via hole 34 on the substrate 11 is set to be located within the range of the orthographic projection of the gate line 161 on the substrate 11, and the orthographic projection of the boss 23 on the substrate 11 is set to be located within the range of the orthographic projection of the fourth via hole 34 on the substrate 11, which makes the orthographic projection of the boss 23 on the substrate 11 located within the range of the orthographic projection of the gate line 161 on the substrate 11, avoiding the boss 23 affecting the aperture ratio of the product.

[0070] The orthographic projection of the fourth via hole 34 on the substrate 11 is set to be within the range of the orthographic projection of the gate line 161 on the substrate 11 , so as to prevent light leakage from the fourth via hole 34 .

[0071] In addition, the fourth via hole 34 is located at a pit position. If the boss 23 is located outside the fourth via hole 34, the pit at the fourth via hole 34 position will affect the flatness of the upper surface of the array substrate, and further affect the flatness of the alignment film, and affect the liquid crystal alignment. In the process of forming the boss 23, the material used to form the boss 23 can fill the pit at the fourth via hole 34 position, and then form the boss 23 above the filled pit, which makes the boss 23 supported by the boss 23 material, and can increase the stability of the boss 23. In addition, the boss 23 is located at the fourth via hole 34 position, which can avoid the pit at the fourth via hole 34 position from affecting the flatness of the upper surface of the array substrate, and can improve the flatness of the upper surface of the array substrate, and further improve the flatness of the alignment film, which is beneficial to the liquid crystal alignment.

[0072] In one embodiment, the material of the planar layer 18 may include an organic material, for example, the material of the planar layer 18 may include an organic resin material or a photoresist.

[0073] In one embodiment, the material of the boss 23 may include an organic material, for example, the material of the planar layer 18 may include an organic resin material or a photoresist.

[0074] In one embodiment, Figure 1 to Figure 4As shown, the orthographic projection of the third via hole 33 on the substrate 11 is located in the same sub-pixel area as the first overlapping area. It should be noted that the portion of the data line 121 connected to the first active layer 140 can be regarded as the source electrode, and the connecting electrode 21 can be regarded as the drain electrode. The source electrode and the drain electrode are structures in a thin film transistor. It is understandable that vias are prone to light leakage. The third via hole 33 is set in the sub-pixel area. Since the sub-pixel area is the light-transmitting area, unnecessary light leakage caused by the third via hole 33 can be avoided. The orthographic projection of the third via hole 33 on the substrate 11 is set to be located in the same sub-pixel area as the first overlapping area, so that the third via hole 33 can be avoided from occupying the space of other sub-pixel areas, the area of ​​the pixel electrode in the sub-pixel area can be increased, the liquid crystal molecules at the edge of the sub-pixel area can be avoided from being disordered, and the display effect can be improved.

[0075] Figure 5 FIG. 2 is a schematic diagram of an AA cross-section of an array substrate in another embodiment of the present disclosure. Figure 5 As shown, the first conductive layer is located on the side of the first active layer 140 away from the substrate 11, and the data line is located between the substrate 11 and the first active layer 140. The data line 121 includes a first surface area, and the first active layer 140 overlaps and connects with a portion of the first surface area. Figure 5 In the illustrated embodiment, there is no insulating layer between the first active layer 140 and the data line 121. The surface of the data line 121 facing away from the substrate 11 is the first surface area.

[0076] In the related art, the data line is located on the side of the gate line away from the first active layer 140, and at least two insulating film layers are between the data line and the first active layer 140. The connection resistance between the data line and the first active layer 140 is relatively large, which increases the power consumption of the product. Figure 5 In the illustrated embodiment, the data line 121 is disposed between the substrate 11 and the first active layer 140 , which can reduce the connection resistance between the data line 121 and the first active layer 140 and reduce the power consumption of the product.

[0077] Figure 6 FIG. 2 is a schematic diagram of an AA cross-section of an array substrate in another embodiment of the present disclosure. Figure 6 As shown, the array substrate may further include a buffer layer 13, and the buffer layer 13 is located between the data line 121 and the first active layer 140. The buffer layer 13 is provided with a first via hole 31, and the orthographic projection of the first via hole 31 on the substrate 11 at least partially overlaps with the orthographic projection of the data line 121 on the substrate 11. The surface of the data line 121 exposed through the first via hole 31 is the first surface area. The first active layer 140 is overlapped and connected to a portion of the first surface area through the first via hole 31.

[0078] Figure 7 for Figure 61 is an enlarged schematic diagram of part B in FIG. It can be understood that after the pattern of the first active layer 140 is formed, the first active layer 140 is to be conductively connected, so that the first active layer 140 includes a first conductive region 141, a second conductive region 142, and a first channel 143 located between the first conductive region 141 and the second conductive region 142. The first conductive region 141 is overlapped and connected to a part of the first surface region. The pixel electrode is connected to the second conductive region 142. Figure 7 As shown, after the first active layer 140 is conductively conductive, the upper surface portion (i.e., the portion close to the upper surface) of the conductive region is sufficiently conductive, while the lower surface portion (i.e., the portion close to the lower surface) is insufficiently conductive. For example, the upper surface portion (i.e., the portion close to the upper surface) 141a of the first conductive region 141 is sufficiently conductive, while the lower surface portion (i.e., the portion close to the lower surface) 141b of the first conductive region 141 is insufficiently conductive.

[0079] If the first conductive region 141 is completely overlapped with the first surface region, the first surface region will only overlap with the lower surface portion 141b of the first conductive region 141. The lower surface portion 141b of the first conductive region 141 is not sufficiently conductive, so that the contact resistance between the first conductive region 141 and the data line 121 is too large, resulting in a turn-on current I on Too low will affect the performance of thin film transistors.

[0080] In the present disclosure, Figure 5 and Figure 6 As shown, the first active layer 140 is overlapped and connected with a part of the first surface area, so that the first surface area is not only in contact with and connected to the lower surface part 141b of the first conductive area 141, but also in contact with and connected to the upper surface part 141a of the first conductive area 141. Even if the lower surface part 141b of the first conductive area 141 has the problem of insufficient conductivity, the contact connection between the first surface area and the upper surface part 141a of the first conductive area 141 can make the data line 121 and the first conductive area 141 maintain good electrical contact, reduce the contact resistance between the data line 121 and the first conductive area 141, and avoid the contact resistance between the data line 121 and the first conductive area 141 being too large due to insufficient conductivity, and the thin film transistor turn-on current I on The problem of low current makes the thin film transistor have a higher turn-on current, thereby improving the performance of the thin film transistor.

[0081] In one embodiment, Figure 7As shown, the first conductive region 141 includes a side wall, and the side wall is arranged along the overlapping boundary between the first conductive region 141 and the first surface region, and the slope angle β of the side wall is less than 90°. The slope angle β of the side wall is set to be less than 90°, so that the thickness of the first active layer 140 material at the side wall position is relatively small, which is conducive to the complete conductiveness of the first active layer 140 material at the side wall position. Therefore, when there is a problem of insufficient conductiveness, the complete conductiveness of the first active layer 140 material at the side wall position can further increase the contact area between the first surface region and the first conductive region 141, reduce the contact resistance between the data line 121 and the first conductive region 141, and improve the performance of the thin film transistor.

[0082] Exemplarily, the slope angle β of the side wall may be any value less than 90°, for example, the slope angle β may be 30°, 45° or 60°.

[0083] Figure 8 AA is a schematic cross-sectional view of an array substrate in another embodiment of the present disclosure. Fig. 9 for Figure 8 In one embodiment, as Figure 8 and Fig. 9 As shown, the first conductive area 141 is provided with a second via hole 32 penetrating the material of the first active layer 140, and the orthographic projection of the second via hole 32 on the substrate 11 partially overlaps with the orthographic projection of the first surface area on the substrate 11, so that a portion of the surface of the first surface area is exposed through the second via hole 32, thereby making the first conductive area 141 overlap and connect with a portion of the first surface area. Fig. 9 It can be seen that the first surface area is not only in contact with the lower surface portion 141b of the first conductive area 141, but also in contact with the upper surface portion 141a of the first conductive area 141. Even if the lower surface portion 141b of the first conductive area 141 is insufficiently conductive, the contact connection between the first surface area and the upper surface portion 141a of the first conductive area 141 can keep good electrical contact between the data line 121 and the first conductive area 141, thereby reducing the contact resistance between the data line 121 and the first conductive area 141.

[0084] In one embodiment, Figure 2 As shown, the array substrate may further include a fourth insulating layer 26, the fourth insulating layer 26 is located between the second insulating layer 17 and the connecting electrode, and the data line 121 is located between the second insulating layer 17 and the fourth insulating layer 26. The data line 121 is connected to the first active layer 140 through a fifth via hole 35 that penetrates the fourth insulating layer 26 and the second insulating layer 17.

[0085] In another embodiment, the data line 121 may be disposed in the same layer as the connecting electrode 21, that is, the data line 121 may be located between the second insulating layer 17 and the planar layer 18. The material of the data line 121 may include a conductive metal.

[0086] It should be noted that in the present disclosure, E and F are disposed in the same layer, that is, E and F are located between the same two film layers. For example, the data line 121 and the connecting electrode 21 are disposed in the same layer, that is, the data line 121 and the connecting electrode 21 are both located between the second insulating layer 17 and the flat layer 18.

[0087] Exemplarily, the width of the data line 121 may be 0.5 μm to 2 μm (including end values). For example, the width of the data line 121 may be 0.5 μm, 1 μm, 1.5 μm or 2 μm.

[0088] In one embodiment, Figure 2 and Figure 5 As shown, the array substrate may further include a third insulating layer 22 and an auxiliary shielding line 25. The third insulating layer 22 is located on the side of the pixel electrode 19 away from the substrate 11. The auxiliary shielding line 25 is located on the side of the third insulating layer 22 away from the substrate 11. The orthographic projection of the auxiliary shielding line 25 on the substrate 11 is located within the orthographic projection range of the data line 121 on the substrate 11. The material of the auxiliary shielding line 25 may be an opaque conductive material, such as a metal.

[0089] In the related art, for LCD products, a black matrix is ​​set on the color filter substrate to block light and prevent color crossover between pixels. The black matrix on the color filter substrate is farther away from the backlight than the array substrate, and the effect of preventing color crossover is limited. The array substrate of the embodiment of the present disclosure is provided with an auxiliary shielding line 25 on the array substrate. The auxiliary shielding line 25 is closer to the backlight than the black matrix, which can better block light, improve the color crossover between adjacent pixels, and improve the display effect.

[0090] In one embodiment, Figure 2 and Figure 5 As shown, the array substrate further includes a common electrode layer 24. The common electrode layer 24 is located on the side of the third insulating layer 22 away from the substrate 11, and the common electrode layer 24 is in contact with and connected to the auxiliary shielding line 25. The auxiliary shielding line 25 is set to be connected to the common electrode layer 24, so that the auxiliary shielding line 25 can be connected to the common electrode signal, avoiding instability caused by the auxiliary shielding line 25 being in a floating state; and, the auxiliary shielding line 25 is connected to the common electrode layer 24, so that the auxiliary shielding line 25 can avoid the common electrode layer 24, and the auxiliary shielding line 25 and the common electrode layer 24 can be set on the upper surface of the third insulating layer 22 at the same time, simplifying the process.

[0091] In one embodiment, Figure 2 and Figure 5 As shown, the positive projection of the auxiliary shielding line 25 on the substrate 11 is located within the range of the positive projection of the common electrode layer 24 on the substrate 11. Figure 2 and Figure 5 As shown, the auxiliary shielding line 25 may be disposed on a side of the third insulating layer 22 away from the substrate 11 , and the common electrode layer 24 is disposed on a side of the auxiliary shielding line 25 away from the substrate 11 .

[0092] In another embodiment, Figure 6 As shown, the common electrode layer 24 may be disposed on a side of the third insulating layer 22 away from the substrate 11 , and the auxiliary shielding line 25 may be disposed on a side of the common electrode layer 24 away from the substrate 11 .

[0093] Fig.10 FIG. 1 is a cross-sectional schematic diagram of an array substrate in another embodiment of the present disclosure. Fig.10 As shown, the array substrate may further include a light shielding layer 27. The light shielding layer 27 is located between the substrate 11 and the buffer layer 13. The orthographic projection of the light shielding layer 27 on the substrate 11 includes the orthographic projection of the first channel 143 on the substrate 11.

[0094] By providing the light shielding layer 27 , the light shielding effect on the first channel 143 can be improved, so as to prevent the first channel 143 from being negatively biased due to light, and further improve the performance of the thin film transistor.

[0095] Fig.11 FIG. 4 is a plan view of an array substrate in an embodiment of the present disclosure. Fig.12 is a cross-sectional schematic diagram of an array substrate in an embodiment of the present disclosure, Fig.13 FIG. 4 is a schematic cross-sectional view of an array substrate in another embodiment of the present disclosure.

[0096] In one embodiment, Fig.11 As shown, the array substrate includes a display area 101 and a frame area 102 outside the display area. The data line 121, the first active layer 140, the first conductive layer, and the pixel electrode 19 are all located in the display area.

[0097] The array substrate further includes a second thin film transistor located in the border area 102, and the second thin film transistor may include a first electrode 41, a second active layer, a second electrode 42, and a second gate electrode 162. One of the first electrode 41 and the second electrode 42 may be a source electrode, and the other may be a drain electrode. The second gate electrode 162 is disposed in the same layer as the gate line, that is, the second gate electrode 162 and the gate line are located between the same two film layers, for example, the gate line is located between the first insulating layer 15 and the second insulating layer 17, and the second gate electrode 162 is also located between the first insulating layer 15 and the second insulating layer 17.

[0098] like Fig.12 and Fig.13 As shown, the second active layer is disposed in the same layer as the first active layer 140. For example, the second active layer and the first active layer 140 are located between the same two film layers, for example, Fig.12 In the embodiment, the second active layer and the first active layer 140 are both located between the buffer layer 13 and the first insulating layer 15 .

[0099] In one embodiment, the second active layer is formed simultaneously with the first active layer 140, and the second active layer is made of the same material as the first active layer 140. In another embodiment, the material of the second active layer is different from the material of the first active layer 140, and the material of the second active layer may include various materials such as amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, and polythiophene.

[0100] like Fig.12 and Fig.13 As shown, the second active layer includes a third conductive region 144, a fourth conductive region 145, and a second channel 146 located between the third conductive region 144 and the fourth conductive region 145. The third conductive region 144 is connected to the first electrode 41, and the second electrode 42 is connected to the fourth conductive region 145. The orthographic projection of the second channel 146 on the substrate 11 is located within the range of the orthographic projection of the second gate electrode 162 on the substrate 11.

[0101] In one embodiment, Fig.12 As shown, the first electrode 41 and the second electrode 42 can be arranged in the same layer as the gate line 161. That is, the first electrode 41 and the second electrode 42 are located between the first insulating layer 15 and the second insulating layer 17, and the first electrode 41 and the second electrode 42 are respectively connected to the third conductive area 144 and the sixth conductive area 145 through via holes penetrating the first insulating layer 15.

[0102] In one embodiment, Fig.13As shown, the first electrode 41 and the second electrode 42 may be located on the side of the second insulating layer 17 away from the substrate 11. Exemplarily, the first electrode 41 and the second electrode 42 may be arranged in the same layer as the connecting electrode 21, that is, the first electrode 41 and the second electrode 42 may be located between the second insulating layer 17 and the flat layer 18. When the first electrode 41 and the second electrode 42 are arranged in the same layer as the connecting electrode 21, the material of the first electrode 41 and the second electrode 42 may be the same as the material of the connecting electrode 21, or may be different. When the material of the first electrode 41 and the second electrode 42 may be different from the material of the connecting electrode 21, the first electrode 41 and the second electrode 42 and the connecting electrode 21 may be formed by different patterning processes. The first electrode 41 is connected to the third conductor area 144 through the seventh via hole penetrating the second insulating layer 17 and the first insulating layer 15, and the second electrode 42 is connected to the fourth conductor area 145 through the eighth via hole penetrating the second insulating layer 17 and the first insulating layer 15. In another embodiment, the first electrode 41 and the second electrode 42 may be located between the fourth insulating layer 26 and the planar layer 18 .

[0103] The second thin film transistor located in the border area is usually used in the gate drive circuit (GOA circuit). In the GOA circuit, the voltage and current borne by the thin film transistor are higher than those of the thin film transistor in the display area. In the embodiment of the present disclosure, the materials of the first electrode 41 and the second electrode 42 of the second thin film transistor in the border area can both be conductive metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), which can be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc. In this way, the voltage resistance of the second thin film transistor can be enhanced to meet the needs of the GOA circuit.

[0104] In the array substrate of the embodiment of the present disclosure, the first active layer 140 of the thin film transistor corresponding to the sub-pixel area is made of oxide material, and the second active layer of the thin film transistor in the GOA circuit can be made of various materials such as oxide material, amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene.

[0105] The present disclosure also provides a method for preparing an array substrate. The array substrate includes a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, and the plurality of gate lines and the plurality of data lines intersect each other to define a plurality of sub-pixel areas. In one embodiment, the method for preparing the array substrate may include:

[0106] In step S11, a first active layer 140 is formed on one side of the substrate 11. At least part of the orthographic projection of the first active layer 140 on the substrate 11 is located in the sub-pixel region. The material of the first active layer 140 includes an oxide semiconductor material. The first active layer 140 is connected to the data line.

[0107] In step S12 , a first insulating layer 15 is formed on a side of the first active layer 140 facing away from the substrate 11 .

[0108] In step S13, a first conductive layer is formed on a side of the first insulating layer 15 facing away from the substrate 11, the first conductive layer includes a gate line 161 and a first gate electrode 163, the material of the gate line 161 includes a conductive metal, the first gate electrode 163 is connected to the gate line 161, the material of the first gate electrode 163 includes a transparent conductive material, and an orthographic projection of the first gate electrode 163 on the substrate 11 and an orthographic projection of the first active layer 140 on the substrate 11 have a first overlapping region, and the first overlapping region is located in the sub-pixel region.

[0109] In step S14 , a second insulating layer 17 is formed on a side of the first conductive layer facing away from the substrate 11 .

[0110] In step S15 , a pixel electrode 19 is formed on a side of the second insulating layer 17 facing away from the substrate 11 , and the pixel electrode 19 is connected to the first active layer 140 .

[0111] The method for preparing the array substrate of the embodiment of the present disclosure retains the first insulating layer 15, that is, the active layer is covered by the first insulating layer 15, and the first part to be conductorized and the second part to be conductorized are conductorized by an ion doping process, which can reduce the diffusion of oxygen in the film layer, further enhance the short channel effect, and facilitate the formation of short channel thin film transistor devices.

[0112] Exemplarily, the material of the first active layer 140 may include an oxide material with high mobility and high light stability. For example, the material of the first active layer 140 may include an oxide semiconductor doped with a rare earth element. Exemplarily, the first active layer 140 may be an oxide material, and the mobility of the material of the first active layer 140 is greater than 20 cm2 / (volt·second). The light stability of the material of the first active layer 140 may be represented by an NBTIS value. For example, the negative bias of the thin film transistor of the first active layer 140 is less than 2V within 2 hours, and the test conditions are: the illumination temperature is 65°C to 75°C, the illumination intensity is 6000 nits to 30000 nits, and the gate electrode voltage is 20V to 30V. In the embodiment of the present disclosure, the high mobility of the high mobility material and the ion doping process are used to ensure the charging rate of the thin film transistor. It is no longer necessary to use the high temperature annealing of the second insulating layer 17 to activate the conductive area of ​​the first active layer 140. Therefore, the high temperature annealing process of the second insulating layer 17 can be cancelled, further simplifying the process.

[0113] Below through Figure 2The preparation process of the array substrate shown further illustrates the technical solution of the embodiment of the present disclosure. It is understandable that the "patterning" mentioned herein includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist when the patterned material is an inorganic material or metal, and includes processes such as mask exposure and development when the patterned material is an organic material. The evaporation, deposition, coating, and coating mentioned herein are all mature preparation processes in the relevant technology.

[0114] In step S11, a first active layer 140 is formed on one side of the substrate. This step may include: depositing a buffer layer 13 on the substrate; depositing a first active film on the side of the buffer layer 13 away from the substrate 11; processing the first active film by a patterning process to form a first active layer 140, wherein at least part of the orthographic projection of the first active layer 140 on the substrate 11 is located in the sub-pixel region, and the material of the first active layer 140 includes an oxide semiconductor material. The material of the buffer layer may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the buffer layer may be a single-layer structure or a composite film structure of two or more layers. The thickness of the buffer layer may be 1000 angstroms to 6000 angstroms. The material of the first active layer 140 may include an oxide semiconductor material, and the material of the first active layer 140 may include indium gallium zinc oxide (IGZO) or indium zinc oxide (IZO) or indium gallium oxide (IGO), etc., or the material of the first active layer 140 may be a doped oxide semiconductor material. The first active layer 140 made of an oxide semiconductor material has a higher transmittance, and such a first active layer 140 can improve the transmittance of the product and reflect the aperture ratio of the product.

[0115] In step S12, a first insulating layer 15 is formed on a side of the first active layer 140 that is away from the substrate. The thickness of the first insulating layer 15 may be 500 angstroms to 3000 angstroms.

[0116] In step S13, a first conductive layer is formed on a side of the first insulating layer 15 away from the substrate 11. This step may include: forming a gate line 161 on a side of the first insulating layer 15 away from the substrate; depositing a transparent conductive film on a side of the gate line 161 away from the substrate 11; patterning the transparent conductive film to form a first gate electrode 163. The material of the gate line 161 includes a conductive metal, the first gate electrode 163 is connected to the gate line 161, and the material of the first gate electrode 163 includes a transparent conductive material. The orthographic projection of the first gate electrode 163 on the substrate and the orthographic projection of the first active layer 140 on the substrate 11 have a first overlapping area, and the first overlapping area is located in the sub-pixel area. In other embodiments, the first gate electrode 163 may be formed on a side of the first insulating layer 15 away from the substrate 11, and then the gate line 161 may be formed.

[0117] In step S14, a second insulating layer 17 is formed on a side of the first conductive layer away from the substrate 11. The second insulating layer 17 is provided with a sixth via hole, which can expose at least a portion of the surface of the first conductive region of the first active layer 140.

[0118] In step S15 , a pixel electrode 19 is formed on a side of the second insulating layer 17 facing away from the substrate 11 , and the pixel electrode 19 is connected to the first active layer 140 . This step may include: forming a data line 121 on a side of the second insulating layer 17 away from the substrate 11, the data line 121 being connected to the first conductor region through a sixth via hole; forming a fourth insulating layer 26 on a side of the data line 121 away from the substrate 11, the fourth insulating layer 26 being provided with a third via hole 33 penetrating the fourth insulating layer 26, the second insulating layer 17 and the first insulating layer 15, the third via hole 33 exposing at least a portion of the surface of the second conductor region of the first active layer 140; forming a connecting electrode 21 on a side of the fourth insulating layer 26 away from the substrate 11, the connecting electrode 21 being connected to the second conductor region of the first active layer 140 through the third via hole 33; forming a planar layer 18 on a side of the connecting electrode 21 away from the substrate 11, the planar layer 18 being provided with a fourth via hole 34, the fourth via hole 34 exposing at least a portion of the surface of the connecting electrode 21; forming a pixel electrode 19 on a side of the planar layer 18 away from the substrate 11, the pixel electrode 19 being connected to the connecting electrode 21 through the fourth via hole.

[0119] In an exemplary embodiment, the first insulating layer 15, the second insulating layer 17, the third insulating layer 22, the fourth insulating layer 26, and the buffer layer 13 may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The buffer layer is used to improve the water and oxygen resistance of the substrate 11. The first insulating layer 15 may be called a gate insulating (GI) layer, and the second insulating layer 17 may be called an interlayer insulating (ILD) layer. The data line 121, the gate line 161, the first electrode 41, and the second electrode 42 may be made of a conductive metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc.

[0120] The embodiment of the present disclosure also provides a display panel, which may include the array substrate in any embodiment of the present disclosure, and may also include a color filter substrate, which is arranged opposite to the array substrate. The pixel electrode 19 of the array substrate faces the color filter substrate. The color filter substrate includes a second substrate, and a black matrix is ​​arranged on the side of the second substrate facing the array substrate. The color filter substrate may also include a color filter located in each sub-pixel area, and the black matrix may be located between adjacent color filters. The orthographic projections of the gate line 161 and the data line 121 on the substrate 11 are located within the range of the orthographic projection of the black matrix on the substrate 11.

[0121] Exemplarily, the orthographic projection of the auxiliary shielding line 25 on the substrate 11 is located within the range of the orthographic projection of the black matrix on the substrate 11 .

[0122] Exemplarily, the display panel may further include liquid crystal located between the array substrate and the color film substrate.

[0123] The embodiments of the present disclosure further provide a display device, which may include the array substrate in any embodiment of the present disclosure or the display panel in any embodiment of the present disclosure.

[0124] The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0125] The display device can be applied to VR or AR scenarios.

[0126] It should be noted that the structure of the display area and the structure of the border area described in different embodiments of the present disclosure can be arbitrarily combined with each other without conflict.

[0127] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0128] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0129] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0130] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0131] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0132] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: The array substrate includes a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, wherein the plurality of gate lines and the plurality of data lines intersect each other to define a plurality of sub-pixel areas. The array substrate includes: substrate; a first active layer, located at one side of the substrate, wherein at least a portion of an orthographic projection of the first active layer on the substrate is located in the sub-pixel region, the material of the first active layer includes an oxide semiconductor material, and the first active layer is connected to the data line; the first active layer extends along the first direction in the sub-pixel region, and in the first direction, the first active layers in adjacent sub-pixel regions are staggered with each other along the second direction; a first conductive layer, located on a side of the substrate facing the first active layer, the first conductive layer comprising the gate line and a first gate electrode, the material of the gate line comprising a conductive metal material, the first gate electrode being connected to the gate line, the material of the first gate electrode comprising a transparent conductive material, an orthographic projection of the first gate electrode on the substrate and an orthographic projection of the first active layer on the substrate having a first overlapping region, the first overlapping region being located in the sub-pixel region; wherein the first conductive layer is located on a side of the first active layer away from the substrate, the data line is located between the substrate and the first active layer, the data line comprises a first surface region, the first active layer and the first surface region are mutually intersecting; The array substrate further comprises a buffer layer, the buffer layer is located between the data line and the first active layer, a first via hole is formed in the buffer layer, a surface of the data line exposed through the first via hole is the first surface area, the first active layer is overlapped and connected to a part of the first surface area through the first via hole; the first active layer comprises a first conductorized area located outside the first overlapping area, the first conductorized area is overlapped and connected to a part of the first surface area through the first via hole, the first conductorized area comprises a side wall along the overlap boundary between the first conductorized area and the first surface area, and the slope angle of the side wall is less than 90°; a first insulating layer, located between the first active layer and the first conductive layer; a second insulating layer, located on a side of the first active layer and the first conductive layer away from the substrate; A pixel electrode is located on a side of the second insulating layer away from the substrate, and the pixel electrode is connected to the first active layer.

2. The array substrate according to claim 1, characterized in that: It also includes a planar layer and a connecting electrode, wherein the planar layer is located between the second insulating layer and the pixel electrode, the connecting electrode is located between the second insulating layer and the planar layer, the second insulating layer is provided with a third via hole penetrating the second insulating layer, and the connecting electrode is connected to the first active layer through the third via hole; the planar layer is provided with a fourth via hole, and the pixel electrode is connected to the connecting electrode through the fourth via hole, and the material of the connecting electrode includes a transparent conductive material.

3. The array substrate according to claim 2, characterized in that: The orthographic projection of the third via hole on the substrate and the first overlapping area are located in the same sub-pixel area.

4. The array substrate according to claim 2, characterized in that: The orthographic projection of the fourth via hole on the substrate is located within the range of the orthographic projection of the gate line on the substrate; the array substrate also includes a third insulating layer and a boss, the third insulating layer is located on the side of the pixel electrode away from the substrate, the boss is located on the side of the third insulating layer away from the substrate, and the orthographic projection of the boss on the substrate is located within the range of the orthographic projection of the fourth via hole on the substrate.

5. The array substrate according to claim 2, characterized in that: It also includes a fourth insulating layer, wherein the fourth insulating layer is located between the second insulating layer and the connecting electrode, and the data line is located between the second insulating layer and the fourth insulating layer.

6. The array substrate according to claim 1, characterized in that: The array substrate comprises a display area and a frame area outside the display area, the data line, the first active layer, the first conductive layer and the pixel electrode are all located in the display area, the array substrate further comprises a first electrode, a second active layer, a second electrode and a second gate electrode located in the frame area, the second active layer and the first active layer are arranged in the same layer, and the second gate electrode and the gate line are arranged in the same layer; The first electrode and the second electrode are located on a side of the second insulating layer away from the substrate; or, the first electrode and the second electrode are arranged in the same layer as the gate line.

7. A method for preparing an array substrate, characterized in that: The array substrate includes a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, the plurality of gate lines and the plurality of data lines intersecting each other to define a plurality of sub-pixel areas, and the preparation method of the array substrate includes: A first active layer is formed on a substrate, wherein at least a portion of an orthographic projection of the first active layer on the substrate is located in the sub-pixel region, the material of the first active layer includes an oxide, and the first active layer is connected to the data line; the first active layer extends along the first direction in the sub-pixel region, and in the first direction, the first active layers in adjacent sub-pixel regions are staggered with each other along the second direction; forming a first insulating layer on a side of the first active layer away from the substrate; A first conductive layer is formed on a side of the first insulating layer away from the substrate, the first conductive layer includes the gate line and a first gate electrode, the material of the gate line includes metal, the first gate electrode is connected to the gate line, the material of the first gate electrode includes a transparent conductive material, an orthographic projection of the first gate electrode on the substrate and an orthographic projection of the first active layer on the substrate have a first overlapping region, and the first overlapping region is located in the sub-pixel region; wherein the first conductive layer is located on a side of the first active layer away from the substrate, the data line is located between the substrate and the first active layer, the data line includes a first surface region, and the first active layer and the first surface region overlap. The array substrate further comprises a buffer layer, the buffer layer is located between the data line and the first active layer, the buffer layer is provided with a first via hole, the surface of the data line exposed through the first via hole is the first surface area, the first active layer is overlapped and connected with a part of the first surface area through the first via hole; the first active layer comprises a first conductor area located outside the first overlapping area, the first conductor area is overlapped and connected with a part of the first surface area through the first via hole, the first conductor area comprises a side wall along the overlap boundary between the first conductor area and the first surface area, and the slope angle of the side wall is less than 90°; forming a second insulating layer on a side of the first conductive layer away from the substrate; A pixel electrode is formed on a side of the second insulating layer away from the substrate, and the pixel electrode is connected to the first active layer.

8. A display panel, characterized in that: It comprises the array substrate according to any one of claims 1 to 6, and further comprises a color film substrate, wherein the color film substrate is arranged opposite to the array substrate, the pixel electrode faces the color film substrate, and the display panel further comprises a liquid crystal arranged between the array substrate and the color film substrate.

9. A display device, characterized in that: An array substrate comprising any one of claims 1 to 6 or a display panel comprising claim 8.

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