An experimental circuit and method based on a second order dynamic circuit mimicking a bomb defusing process

Abstract

The application discloses an experimental circuit and method based on a second-order dynamic circuit simulating a bomb defusing process, and relates to the technical field of teaching experimental circuits. The application comprises a second-order dynamic circuit, a logic judgment circuit, a timing display circuit and an external alarm circuit. The application uses a disconnecting switch to simulate the operation of cutting a wire in the bomb defusing process, uses a Laplace transform method to analyze the second-order dynamic circuit, converts the second-order dynamic circuit into a star connection through a star-delta conversion method, finally judges the wire breaking position, and uses an alarm lamp and a buzzer to simulate the bomb defusing effect. In the dynamic circuit, the breaking of three different wires will respectively cause the voltage of one node of the circuit to increase, remain unchanged or decrease. After the logic judgment circuit discriminates the voltage change, a logic control signal is generated to stop the countdown or trigger the external alarm device to alarm, so that the success or failure of the bomb defusing is simulated. The interesting experiment is used to guide students to analyze the second-order dynamic circuit by using the Laplace transform method.

Description

Technical Field

[0001] This invention relates to the field of teaching experimental circuits, and in particular to an experimental circuit and method for simulating bomb disposal based on a second-order dynamic circuit. Background Technology

[0002] A second-order dynamic circuit is a linear circuit containing two independent dynamic elements, described by a linear second-order differential equation with constant coefficients. The Laplace transform is a commonly used integral transform in engineering mathematics, with wide applications in many engineering and scientific research fields, particularly in systems science such as mechanical systems, electrical systems, automatic control systems, reliability systems, and stochastic service systems. Therefore, how to use the Laplace transform to analyze second-order dynamic circuits has become a key teaching content in circuit design disciplines at universities.

[0003] Currently, in the teaching process of universities, the analysis of second-order dynamic circuits using the Laplace transform is mostly taught through written and oral methods, lacking corresponding experiments. The drawback of this teaching method is that second-order dynamic circuits have numerous and complex components; relying solely on oral instruction makes it difficult for students to fully grasp how to use the Laplace transform to analyze second-order dynamic circuits. Summary of the Invention

[0004] This invention provides an experimental circuit and method for simulating bomb disposal based on a second-order dynamic circuit, which can solve the problem of the lack of corresponding teaching experiments for analyzing second-order dynamic circuits using Laplace transforms.

[0005] This invention provides an experimental circuit for simulating bomb disposal based on a second-order dynamic circuit, comprising:

[0006] The second-order dynamic circuit includes: one end of resistor R1 and one end of resistor R2 are both connected to the positive terminal of power supply V1; the other end of resistor R1 is connected to one end of switch S3; the other end of switch S3 is connected to capacitor C1 and resistor R3 respectively; the other end of resistor R3 is connected to the other end of resistor R2 and one end of inductor L1 respectively; the other end of capacitor C1 is connected in series with switch S1 and then grounded; the other end of inductor L1 is connected in series with switch S2 and then grounded; and the negative terminal of power supply V1 is grounded.

[0007] A dual-threshold comparator, both of whose inputs are connected to the non-grounded terminal of the inductor L1;

[0008] The logic judgment circuit includes: a countdown end detection circuit and an alarm logic synthesis circuit; the first input terminal of the alarm logic synthesis circuit is connected to the first output terminal of the dual-threshold comparator, and the output terminal of the countdown end circuit is connected to the second input terminal of the alarm logic synthesis circuit.

[0009] The countdown display circuit includes: a timing pulse generating circuit, a preset reset switch, a countdown circuit, and a countdown display; the input terminal of the timing pulse generating circuit is connected to the second output terminal of the dual-threshold comparator, the output terminal of the timing pulse generating circuit is connected to the first input terminal of the countdown circuit, the output terminal of the preset reset switch is connected to the second input terminal of the countdown circuit, the first output terminal of the countdown circuit is connected to the input terminal of the countdown end detection circuit, and the first output terminal of the countdown circuit is connected to the input terminal of the countdown display.

[0010] An external alarm circuit, the input of which is connected to the output of the alarm logic synthesis circuit.

[0011] Additionally, switches S1, S2, and S3 are used to simulate the black, green, and red wires during the bomb disposal process, respectively. When switch S1 is open, it means the black wire is cut and the circuit does not respond. When switch S2 is open, it means the green wire is cut and the bomb disposal is successful. When switch S3 is open, it means the red wire is cut and the bomb disposal fails.

[0012] Additionally, the dual-threshold comparator includes: an operational amplifier U10A whose non-inverting input is connected to power supply V2, whose inverting input is connected to a second-order dynamic circuit, and whose output is connected to the first input of an OR gate U3A; an operational amplifier U1A whose non-inverting input is connected to the output of the second-order dynamic circuit, whose inverting input is connected to the VCC terminal of a 555 timer U2, and whose output is connected to the input of a NOT gate U8A; and the threshold voltages of the two operational amplifiers are the upper threshold voltage and the lower threshold voltage, respectively.

[0013] Additionally, the countdown circuit includes: the output terminal of the 555 timer U2 is connected to the 74LS190 counter U7, and the VCC terminal is connected to the input terminal of the 74LS190 counter U6; the 74LS190 counter U6 is connected to the digital tube U4, and the 74LS190 counter U7 and the digital tube U5 respectively form a single-digit clock display; the 555 timer U2 forms a multivibrator to provide counting pulses for the counting circuit, and the output signal of the U8A inverter is connected to the zero-reset port of the 555 timer U2 to control the switching between zero-reset and oscillation states.

[0014] Additionally, the logic judgment circuit includes: a NOR gate U12B connected to the output of the 74LS190 counter U6 and connected to the first input of the AND gate U11A; the input of the NOR gate U12A connected to the output of the U7 and the output connected to the second input of the AND gate U11A; the output of the AND gate U11A connected to the second input of the U3A; and the output of the OR gate U3A connected to the input of the 555 timer U9. When the countdown circuit counts down from the set value to 0, the outputs of both NOR gates U12A and U12B become 1, and the output of the AND gate U11A becomes 1. This signal, through the OR gate U3A, causes the multivibrator formed by the 555 timer U9 to start oscillating, generating an alarm signal.

[0015] Additionally, the external alarm circuit includes: the output terminal of the multivibrator formed by the 555 timer U9 is connected to LED1 and buzzer LS1.

[0016] Additionally, the Laplace transform analysis method based on this experimental circuit includes: performing a Laplace transform on the second-order dynamic circuit to obtain the corresponding complex frequency domain circuit, and calculating the voltage U across inductor L1 in the complex frequency domain circuit. L The expression for (s);

[0017] The voltage U across inductor L1 L (s) Perform an inverse Laplace transform to obtain the voltage U across inductor L1. L The time-domain expression U corresponding to (s) L ;

[0018] When switch S1 is open and switches S2 and S3 are closed, neither the alarm is triggered nor the countdown is stopped.

[0019] When switch S2 is open and switches S1 and S3 are closed, the countdown circuit stops, and the bomb is successfully defused.

[0020] When switch S3 is open and switches S1 and S2 are closed, the bomb detonates, the alarm circuit flashes, a buzzer sounds, and the bomb disposal fails.

[0021] Furthermore, when all three switches S1, S2, and S3 remain closed and the circuit enters a steady state, capacitor C1 is considered an open circuit and inductor L1 is considered a short circuit. At this time, the Laplace transform is used to convert the second-order dynamic circuit from the time domain to the complex frequency domain. The conversion process is as follows: First, the models of the three resistors R1, R2, R3, capacitor C1, and inductor L1 in the circuit are converted from the time domain to the complex frequency domain. The time domain model of the DC voltage source can be regarded as a step function V1ε(t), and its corresponding complex frequency domain model is V1 / s, where V1 is the voltage across the power supply, s is the complex frequency domain variable, and t is time.

[0022] After converting the three resistors R1, R2, and R3 in the second-order dynamic circuit into a star connection through a star-delta conversion, the voltage U across the inductor L1 is... L (s) is:

[0023]

[0024] In the formula, V1 is the voltage across the power supply, s is a variable in the complex frequency domain, and R... 12 R is the combined resistance value of resistors R1 and R2 after a star connection. 23 R is the combined resistance value of resistors R2 and R3 after star connection. 31 L1 is the combined resistance value of resistor R3 and resistor R1 after star connection, C1 is the value of inductance, and C1 is the value of capacitance.

[0025] The above equation can be further transformed into:

[0026]

[0027] In the formula, s is a variable in the complex frequency domain, and a, b, m, and n all refer to coefficients in the derivation process and have no specific meaning.

[0028] When p1, p2, ... p n When D(s) = 0 has distinct real roots, find U after determining all undetermined coefficients. L The original function corresponding to all terms in the complex frequency domain model of expression (s) can be used to perform the inverse Laplace transform and obtain the voltage U across the inductor L1. L The time-domain expression is:

[0029] In the formula, K1, K2, ... K n The coefficients are undetermined, p1, p 2 ,…p n Let D(s) = 0 be the root, and e be the natural constant.

[0030] Furthermore, the formula used for star-delta conversion of the three resistors R1, R2, and R3 in the second-order dynamic circuit is as follows:

[0031]

[0032] Where R1 is the resistance value of resistor R1 mentioned before the star connection, R2 is the resistance value of resistor R2 mentioned before the star connection, R3 is the resistance value of resistor R3 mentioned before the star connection, R 12 R is the combined resistance value of resistors R1 and R2 after a star connection. 23 R is the combined resistance value of resistors R2 and R3 after star connection. 31This is the combined resistance value of resistor R3 and resistor R1 after a star connection.

[0033] Additionally, when p1, p2, ... p n When the voltage U across the inductor L1 is a non-real root of D(s) = 0, L The expression for (s) is decomposed into:

[0034]

[0035] Multiplying both sides of the above equation by (s-p1), we get

[0036]

[0037] Let s = p1, then all terms in the equation become zero except for the first term. This is how we obtain the solution.

[0038]

[0039] Similarly, K2, K3, ... K can be obtained. n Therefore, the formulas for each undetermined coefficient are:

[0040]

[0041] This invention provides an experimental circuit and method for simulating bomb disposal based on a second-order dynamic circuit. Compared with the prior art, its advantages are as follows:

[0042] This invention analyzes second-order dynamic circuits using the Laplace transform. Three switches in the second-order dynamic circuit simulate three different colored wires during bomb disposal. Disconnecting the switches (cutting different wires) alters the changes in the second-order dynamic circuit and the different reactions of the alarm circuit: S1 disconnects, representing cutting the black wire, triggering neither the alarm nor stopping the countdown; S2 disconnects, representing cutting the green wire, stopping the countdown and indicating successful bomb disposal; S3 disconnects, representing cutting the red wire, causing the alarm circuit to flash and sound an alarm, indicating bomb disposal failure. This invention addresses the lack of Laplace transform experiments in current textbooks, using engaging experiments to help students better understand and learn how to use the Laplace transform to analyze second-order dynamic circuits from a practical perspective. Attached Figure Description

[0043] Figure 1 The component connection diagram of an experimental circuit and method for simulating bomb disposal process based on a second-order dynamic circuit provided in an embodiment of the present invention;

[0044] Figure 2 A block diagram of an experimental circuit and method for simulating bomb disposal based on a second-order dynamic circuit, provided for an embodiment of the present invention;

[0045] Figure 3A schematic diagram of an experimental circuit and method for simulating bomb disposal process based on a second-order dynamic circuit, provided in an embodiment of the present invention;

[0046] Figure 4 A steady-state schematic diagram of a second-order dynamic circuit for simulating a bomb disposal process based on a second-order dynamic circuit, provided in an embodiment of the present invention;

[0047] Figure 5 A schematic diagram of the resistance model conversion for an experimental circuit and method for simulating bomb disposal process based on a second-order dynamic circuit, provided in an embodiment of the present invention;

[0048] Figure 6 A schematic diagram of inductor model conversion for an experimental circuit and method for simulating bomb disposal process based on a second-order dynamic circuit, provided in an embodiment of the present invention;

[0049] Figure 7 A schematic diagram of capacitor model conversion for an experimental circuit and method for simulating bomb disposal process based on a second-order dynamic circuit, provided in an embodiment of the present invention;

[0050] Figure 8 A resistor star connection and delta connection diagram for an experimental circuit and method based on a second-order dynamic circuit to simulate a bomb disposal process, provided in an embodiment of the present invention;

[0051] Figure 9 A schematic diagram of a triangular connection for an experimental circuit and method for simulating bomb disposal process based on a second-order dynamic circuit, provided in an embodiment of the present invention;

[0052] Figure 10 A star-connection schematic diagram of an experimental circuit and method for simulating bomb disposal process based on a second-order dynamic circuit, provided for an embodiment of the present invention;

[0053] Figure 11 The experimental circuit diagram of the second-order dynamic circuit after switch S1 is opened, which is provided for the embodiment of the present invention to simulate the bomb disposal process based on the second-order dynamic circuit.

[0054] Figure 12 The experimental circuit diagram of the bomb disposal process based on a second-order dynamic circuit for simulating the process of bomb disposal provided in an embodiment of the present invention is shown after switch S2 is turned off.

[0055] Figure 13 The experimental circuit diagram of the bomb disposal process based on a second-order dynamic circuit for simulating the bomb disposal process provided in the embodiment of the present invention is shown after switch S3 is turned off.

[0056] Figure 14 A dual-threshold comparator circuit diagram for an experimental circuit and method based on a second-order dynamic circuit to simulate the bomb disposal process, provided in an embodiment of the present invention;

[0057] Figure 15 A countdown circuit and logic judgment circuit diagram for an experimental circuit and method based on a second-order dynamic circuit to simulate the bomb disposal process, provided for an embodiment of the present invention;

[0058] Figure 16 An alarm circuit diagram for an experimental circuit and method based on a second-order dynamic circuit to simulate the bomb disposal process is provided in an embodiment of the present invention. Detailed Implementation

[0059] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0060] As shown in the figure, this embodiment of the invention provides a dynamic circuit experimental circuit that simulates a bomb disposal process, comprising four parts: a second-order dynamic circuit, a logic judgment circuit, a timing display circuit, and an external alarm circuit.

[0061] The components and working principles of each circuit section are as follows:

[0062] 1. Second-order dynamic circuits, such as Figure 3 As shown, let the capacitor voltage be U. C The inductor voltage is U L The inductor current is I L When all three switches are closed, since the inductor and capacitor have no stored energy before power-on, their initial values ​​are all 0. According to the switching rule, we have:

[0063] U C (0+)=U C (0-)=0,I L (0+)=I L (0-)=0

[0064] After a sufficiently long period of time, the circuit reaches a steady state, where the capacitor is considered an open circuit and the inductor is considered a short circuit. Figure 4 As shown:

[0065]

[0066] Using Laplace transform Figure 3 To transform the circuit from the time domain to the complex frequency domain, first, the resistors, inductors, and capacitors in the circuit are respectively determined according to... Figure 5 , Figure 6 , Figure 7The model completes the conversion from the time domain to the complex frequency domain. In the figure, model (a) is the time domain model of each component, and model (b) is its corresponding complex frequency domain model, where i(0-) and u(0-) are the initial values ​​of the inductor current and capacitor voltage, respectively. The time domain model of the DC voltage source can be regarded as a step function V1ε(t). Therefore, by referring to Table 1, its complex frequency domain model (i.e., the image function) is V1 / s, where V1 is the voltage across the power supply, s is the complex frequency domain variable, and t is time. Based on the above parameter conversion, the model can be... Figure 3 Convert to Figure 9 .

[0067]

[0068] Table 1

[0069] Then Figure 7 In (a), resistors R1, R2, and R3 are converted from a delta to a star connection. The process of converting a delta resistor connection to a star connection is as follows: Figure 8 As shown, Figure 9 The triangle connection is converted into a star connection, such as... Figure 10 As shown.

[0070] The formula used in the conversion process is:

[0071]

[0072] Where R1 is the resistance value of resistor R1 mentioned before the star connection, R2 is the resistance value of resistor R2 mentioned before the star connection, R3 is the resistance value of resistor R3 mentioned before the star connection, R 12 R is the combined resistance value of resistors R1 and R2 after a star connection. 23 R is the combined resistance value of resistors R2 and R3 after star connection. 31 This is the combined resistance value of resistor R3 and resistor R1 after a star connection.

[0073] according to Figure 10 The voltage U across inductor L1 can be obtained from the series-parallel connection. L (s) is

[0074]

[0075]

[0076] The above equation can be further transformed into the following form.

[0077]

[0078] Find the roots p1, p2, ... p of D(s) = 0. n

[0079] When p1, p2, ... p n When the real roots are not equal, the voltage U across inductor L1 is... L The expression (s) can be decomposed into the following expression:

[0080]

[0081] In the formula, K1, K2, ... Kn are undetermined coefficients.

[0082] Multiplying both sides of the above equation by (s-p1), we get

[0083]

[0084] Let s = p1, then all terms in the equation become zero except for the first term. This is how we obtain the solution.

[0085]

[0086] Similarly, K2, K3, ... K can be obtained. n Therefore, the formulas for each undetermined coefficient are:

[0087]

[0088] After determining all the undetermined coefficients, find the voltage U across inductor L1 by referring to Table 1. L The antiderivatives corresponding to all the component image functions in the expression (s):

[0089]

[0090] The inverse Laplace transform can then be performed to obtain U. L The time-domain expression of (s)

[0091] In the formula, K1, K2, ... K n The coefficients are undetermined, p1, p2, ... p n Let D(s) = 0 be the root, and e be the natural constant.

[0092] (1) When switch S1 is open and switches S2 and S3 are closed, the circuit becomes a first-order inductor circuit, such as... Figure 11 As shown, the circuit is analyzed using the three-element method. Since the switch switching time (i.e., the time it takes for the student to cut the wire) is uncertain, therefore, it is assumed that... According to the three-element formula, we have:

[0093]

[0094] After the voltage source is short-circuited and removed, the equivalent resistance R across inductor L1 is... eq = (R1+R3)||R2, then the time constant is... Substituting into the three-element formula, we get:

[0095]

[0096] Based on the voltage and current relationship across the inductor, we can obtain: Select appropriate circuit parameters to make U before and after switch S1 switching. L The trend of change of (t) is basically the same. UL(t) is between the two threshold voltages of the dual-threshold comparator. The output of the dual-threshold comparator remains unchanged, neither triggering an alarm nor stopping the countdown.

[0097] (2) When switch S2 is open and switches S1 and S3 are closed: at this time, the inductor is open, and the circuit is as follows: Figure 12 It consists of three resistors and a capacitor. The circuit becomes a first-order integrator. Since the time constant τ=(R1||(R2+R3))C1, and the three resistors are made with relatively small resistances, the time constant of the circuit can be made much less than 1 millisecond. Therefore, the capacitor is instantly charged to U. C =V1, and remain unchanged. Set reasonable resistor and capacitor parameters so that the threshold voltage of comparator U1A in the dual-threshold comparator is slightly lower than U. L (t), after switch S2 is opened, the output of U1A jumps, the countdown circuit stops, and the bomb is successfully dismantled.

[0098] (3) Switch S3 is open, and S1 and S2 are closed: At this time, resistor R1 is open-circuited, and the circuit consists of resistors R2 and R3, capacitors, and inductors. Figure 5 , Figure 6 , Figure 7 The Laplace transform model transforms the circuit into the complex frequency domain, such as... Figure 13 As shown (initial values ​​of capacitors and inductors are calculated based on the steady-state values ​​of the circuit before switching). The equations are derived using the nodal voltage method:

[0099]

[0100] The above equation can be further transformed into the following form.

[0101]

[0102] Find the roots p1, p2, ... p of D(s) = 0. n

[0103] When p1, p2, ... p n When there are unequal real roots, let U L The expression F(s) = F(s) can be decomposed into the following expression:

[0104]

[0105] In the formula, K1, K2, ... K n These are undetermined coefficients.

[0106] Multiplying both sides of the above equation by (s-p1), we get

[0107]

[0108] Let s = p1, then all terms in the equation become zero except for the first term. This is how we obtain the solution.

[0109]

[0110] Similarly, K2, K3, ... K can be obtained. n Therefore, the formulas for each undetermined coefficient are:

[0111]

[0112] After finding all the undetermined coefficients, find U. L The antiderivatives corresponding to all the component image functions in the expression (s)

[0113]

[0114] The inverse Laplace transform can then be performed to obtain U. L Time-domain expression

[0115]

[0116] Select appropriate resistor, capacitor, and inductor parameters so that U is open when switch S3 is open. L The voltage suddenly drops below the lower threshold voltage of U10A in the dual-threshold comparator. At this time, U10A outputs a high level, the bomb detonates, the alarm circuit flashes, the buzzer sounds, and the bomb disposal fails.

[0117] 2. Dual-threshold comparator: Two operational amplifiers, U1A and U10A, constitute a dual-threshold comparator, such as... Figure 14 As shown, the threshold voltages are the upper and lower threshold voltages. When the input UL voltage is between the upper and lower threshold voltages, both operational amplifiers output a low level. The low level output of U1A is inverted by the NOT gate of U8A and outputs a high level, keeping the multivibrator composed of U2 (555 timer) oscillating and providing counting pulses for the countdown circuit. The low level output of U10A keeps the multivibrator composed of U9 (555 timer) in a zero state, not outputting square wave pulses, and the LED and buzzer do not work. When the UL voltage is higher than the upper threshold voltage, the output of U1A flips to a high level, and becomes a low level after being inverted by U8A. The multivibrator composed of U2 enters a zero state, does not output counting pulses, and the countdown circuit stops counting. The output state of U10A remains unchanged.

[0118] When the UL voltage is lower than the lower threshold voltage, the output of U10A flips to a high level, the multivibrator formed by U9 enters the oscillation state, and the output square wave causes the LED to blink and the buzzer to sound. The output state of U1A remains unchanged.

[0119] 3. Countdown Circuit and Logic Judgment Circuit: The countdown circuit consists of U2 (555 timer), two 74LS190 counters (U6 and U7), and U4 and U5 digital displays, as shown below. Figure 15 As shown. U2 forms a multivibrator, providing counting pulses for the counting circuit. The output signal of the inverter U8A is connected to the zero-reset port of U2, controlling the switching between zero-reset and oscillation states. Each 74LS190 chip and a digital tube form a single-digit clock display. The demonstration circuit only uses a two-digit display; this part can be expanded according to actual needs.

[0120] Switch S4 is the circuit reset button. After the circuit is powered on, switch S4 is first turned off to set the expected countdown time into the circuit. Then switch S4 is turned on, and the circuit starts counting down, thus beginning the experiment.

[0121] The logic circuit consists of two NOR gates U12A and U12B, an AND gate U11A, and an OR gate U3A. When the countdown circuit reaches 0 from the set value, the outputs of both NOR gates U12A and U12B become 1, and the output of the AND gate U11A also becomes 1. This signal, through the OR gate U3A, causes the multivibrator U9 to start oscillating, thus generating an alarm signal indicating that the bomb disposal failed within the specified time. Simultaneously, the signal output from U11A is also connected to the CTEN pins of the two counters, stopping the counters from counting down and maintaining their current 0 output state.

[0122] 4. External alarm circuit: The external alarm circuit is as follows Figure 16 As shown, the circuit consists of a multivibrator (U9, a 555 timer), an LED, and a buzzer. In a practical circuit, a solenoid valve can be added to control the jet, and the spray device can simulate the effect of a bomb detonation. The output signal of U3A is connected to the reset terminal of U9. When the signal is low, the buzzer does not work, and the multivibrator does not output pulses. When the output signal of U3A is high, the buzzer sounds, the multivibrator outputs a square wave, and the LED flashes.

[0123] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. An experimental circuit based on a second order dynamic circuit simulating a bomb disposal process, characterized in that, The application relates to a dual-threshold comparator, a logic judgment circuit and a countdown display circuit. The second-order dynamic circuit comprises: one end of a first resistor R1 and one end of a second resistor R2 are connected with a positive pole of a first power supply V1, the other end of the first resistor R1 is connected with one end of a third switch S3, the other end of the third switch S3 is connected with a capacitor C1 and a third resistor R3 respectively, the other end of the third resistor R3 is connected with the other end of the second resistor R2 and one end of an inductor L1 respectively, the other end of the capacitor C1 is connected with the ground through a first switch S1 in series, the other end of the inductor L1 is connected with the ground through a second switch S2 in series, and the negative pole of the first power supply V1 is connected with the ground. The dual-threshold comparator comprises: the non-ground end of the inductor L1 is connected with the positive pole of a second power supply V2, the output end of the second-order dynamic circuit is connected with the inverting input end of a first operational amplifier U10A, and the output end of the first operational amplifier U10A is connected with the first input end of an OR gate U3A. The logic judgment circuit comprises: a countdown end discrimination circuit and an alarm logic comprehensive circuit; the first input end of the alarm logic comprehensive circuit is connected with the first output end of the dual-threshold comparator, and the output end of the countdown end discrimination circuit is connected with the second input end of the alarm logic comprehensive circuit. The countdown display circuit comprises: a timing pulse generating circuit, a number setting reset switch, a countdown circuit and a timing display; the input end of the timing pulse generating circuit is connected with the second output end of the dual-threshold comparator, the output end of the timing pulse generating circuit is connected with the first input end of the countdown circuit, the output end of the number setting reset switch is connected with the second input end of the countdown circuit, the first output end of the countdown circuit is connected with the input end of the countdown end discrimination circuit, and the second output end of the countdown circuit is connected with the input end of the timing display. The first switch S1, the second switch S2 and the third switch S3 are used for simulating the black line, the green line and the red line in the bomb disarming process respectively; the first switch S1 is disconnected to represent that the black line is cut off, and the circuit has no reaction; the second switch S2 is disconnected to represent that the green line is cut off, and the bomb disarming is successful; and the third switch S3 is disconnected to represent that the red line is cut off, and the bomb disarming is failed. The dual-threshold comparator comprises: the non-ground end of the inductor L1 is connected with the positive pole of a second power supply V2, the output end of the second-order dynamic circuit is connected with the inverting input end of a first operational amplifier U10A, and the output end of the first operational amplifier U10A is connected with the first input end of an OR gate U3A.

2. An experimental circuit based on a second order dynamic circuit simulation of a bomb disposal process as claimed in claim 1, characterized in that, The logic judging circuit comprises: a second NOR gate U12B connected with the output end of the first 74LS190 counter U6 and connected to the first input end of the AND gate U11A; the input end of the first NOR gate U12A is connected with the output end of the second 74LS190 counter U7, and the output end of the first NOR gate U12A is connected to the second input end of the AND gate U11A; the output end of the AND gate U11A is connected to the second input end of the OR gate U3A; the output end of the OR gate U3A is connected with the input end of the second 555 timer U9; when the countdown circuit is counted down to 0 from the set value, the outputs of the first NOR gate U12A and the second NOR gate U12B are both changed to 1, and the output of the AND gate U11A is changed to 1; the signal passes through the OR gate U3A, so that the multi-resonance oscillator composed of the second 555 timer U9 starts to oscillate, and an alarm signal is generated; The threshold voltages of the first operational amplifier U10A and the second operational amplifier U1A are upper threshold voltage and lower threshold voltage respectively.

3. An experimental circuit based on the simulation of a second order dynamic circuit disarming process as claimed in claim 1, wherein, The external alarm circuit further comprises: the output end of the multi-resonance oscillator composed of the second 555 timer U9 is connected with the LED1 and the buzzer LS1.

4. The Laplace transform analysis method of the experimental circuit imitating the bomb disposal process based on the second-order dynamic circuit according to any one of claims 1-3, characterized in that, It comprises: Taking Laplace transform on the second order dynamic circuit, a corresponding complex frequency domain circuit is obtained, in which an expression of voltage U L (s) across inductor L1 is obtained. The voltage U across the inductor L1 L (s) is subjected to a Laplace transform inverse transform to obtain the voltage U across the inductor L1 L (s) is subjected to a Laplace transform inverse transform to obtain the voltage U across the inductor L1 L (t); When the first switch S1 is open and the second switch S2 and the third switch S3 are closed, the second-order dynamic circuit becomes a first-order inductive circuit, and the voltage U across the inductor L1 before and after the first switch S1 is switched L (t) the voltage U across the inductor L1 is basically consistent L (t) is between the upper threshold voltage and the lower threshold voltage of the double-threshold comparator, and the output of the double-threshold comparator remains unchanged, neither triggering an alarm nor stopping the countdown. When the second switch S2 is opened and the first switch S1 and the third switch S3 are closed, the inductor is disconnected, the second-order dynamic circuit becomes a first-order integral circuit, and the threshold voltage of the second operational amplifier U1A is slightly lower than the voltage U across the inductor L1 L (t), the output of the second operational amplifier U1A jumps after the second switch S2 is opened, the countdown circuit stops, and the bomb is successfully disarmed. The third switch S3 is opened, the first switch S1 and the second switch S2 are closed, the first resistor R1 is disconnected, and the voltage U of the inductor L1 L (t) The first operational amplifier U10A in the double-threshold comparator drops below the lower threshold voltage, the first operational amplifier U10A outputs a high level, the bomb explodes, the alarm circuit flashes, the buzzer alarms, and the bomb disarming fails.

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