A DNA data storage high-efficiency coding circuit

Abstract

The invention discloses a DNA data storage efficient coding circuit, comprising: an enable signal output by a control module connected to a base conversion module, a rotation coding module and a linear cyclic code coding module, for controlling the sending of data input and output requests and the current status display of the remaining modules. The 32-bit 15-decimal number output by the base conversion module is connected to the rotation coding module, for converting 31-bit binary data into 32-bit 15-decimal numbers. The 32-bit 15-decimal number output by the rotation coding module is connected to the rotation coding module, for converting the 32-bit 15-decimal data into binary data suitable for DNA base synthesis through cyclic shift and accumulation operations. The linear cyclic code coding module is used to input the continuously input 32-bit data into a linear cyclic code coding unit through serial-to-parallel conversion, merging, etc. to obtain a coding codeword with a certain error correction capability. The DNA storage-specific coding algorithm hardware circuit proposed by the invention can achieve high data throughput while occupying less hardware logic resources.

Description

Technical Field

[0001] The present invention relates to the bioinformatics field of DNA data storage, and in particular to a high-throughput DNA data storage efficient coding circuit. Background Art

[0002] The world today has fully entered the era of big data, and all life-related activities involve the storage and processing of data. With the rapid development of information technology in recent years, all aspects of human life have gradually realized digital transformation, and modern data has shown exponential growth, far exceeding the growth rate of existing storage capacity. However, existing storage media, such as magnetic storage (such as tapes or hard drives), optical storage (such as Blu-ray) and solid-state storage (such as flash memory), can no longer meet the growing demand for storage capacity. Although modern data storage media based on magnetism, light and integrated circuits have made rapid progress, their storage volume density has reached 10 10 ~10 12 bit / cm 3 , approaching the limit. In contrast, DNA storage uses as few molecules or atoms as possible to store one bit of information, and has the potential for higher density storage. For example, the storage volume density of Escherichia coli chromosomal DNA is estimated to be about 10 19 bit / cm 3 , which is about 6 orders of magnitude higher than the current best storage medium. More importantly, with the rapid development of synthetic biology, represented by high-throughput DNA synthesis technology and artificial synthetic chromosome work, it marks that human beings have entered a new era in the ability to design, synthesize, edit and read DNA. In this context, high-density information storage using DNA molecules as storage media has become a very promising research direction and has received increasing attention from academia and industry.

[0003] DNA storage of digital information is the use of artificially synthesized deoxyribonucleotides (DNA) to store digital information. DNA storage information has the advantages of high storage density, no electromagnetic interference, long-term high reliability and low maintenance cost. The principle of using DNA to store digital information is: the conversion and flow of digital information between binary code streams, quaternary base sequences and actual DNA fragments. At present, the technical process based on this principle mainly includes two aspects: 1. Information writing, which mainly includes two parts: DNA encoding and DNA synthesis. DNA encoding is to encode the binary code stream of information such as text, pictures or videos through computer algorithms to obtain a base sequence composed of A / T / C / G. Then the second step: DNA synthesis, write the information data into the corresponding DNA fragment, and save it in multi-mode; 2. Information reading, which includes two parts: DNA information retrieval and sequencing and DNA information encoding. When a data reading request is received, the corresponding DNA sample library needs to be physically retrieved and sampled. After selecting a sample, the next step is to sequence it to generate a set of DNA sequence information. Then identification, assembly, error correction and decoding are performed to restore the data stored in the DNA medium to the original digital information to obtain the original text, pictures, sounds and videos.

[0004] The main challenges of current DNA information storage are high unit storage cost, slow information reading and writing speed, low stability, and inability to efficiently connect to existing information systems. In order to improve the stability of synthetic DNA, it is necessary to select a suitable DNA storage encoding method based on the constraints of DNA molecular biology. In this regard, information encoding methods in multiple information fields have been introduced into the scope of DNA storage encoding. Professor Goldman of the European Analytical Biology Laboratory achieved reliable data recovery by adding quadruple redundancy and a simple verification mechanism, but due to the quadruple redundant design, the logic density and cost control achieved by this method are not ideal. The Grass team of the Swiss Federal Institute of Technology introduced the Reed-Solomon (RS) erasure code to solve the partial loss in the oligonucleotide chain pool and the base substitution errors in the fragment, while ensuring reliable data recovery. The logical density of the data part exceeds 1 bit / nt. Erlich et al. introduced the fountain code to better adapt to the massive fragmented storage mode, further increasing the logical density of the data part to 1.57 bit / nt. Another idea is that Anavy et al. and Choi used degenerate bases to expand the polynomial representation of DNA, pushing the logic density to more than 2 bits / nt, but this method also faces the problem of requiring higher sequencing coverage. In addition, the introduction of non-natural bases to expand storage units in the future can further improve the logic density.

[0005] There are two important factors to consider when designing DNA encoding algorithms: (1) error correction design is required for information transmission; (2) simple and direct data retrieval is required. Unlike traditional storage media, DNA storage introduces base insertion and deletion errors during synthesis and sequencing, which makes encoding more challenging. Based on this, DAN data encoding and decoding must consider the design of error correction codes and data retrieval codes. To address this problem, Press et al. proposed an encoding scheme based on hash coding and greedy exhaustive decoding, which can correct insertion and deletion errors in the case of single-molecule copies, but requires a high degree of redundancy to achieve error correction and has a high decoding complexity. Sabary et al. proposed several dynamic DNA reconstruction algorithms that can be directly used for DNA sequence reconstruction under high error rates. Song et al. from Tianjin University designed a highly robust DNA sequence reconstruction algorithm based on DeBruijn Graph, which can quickly reconstruct error-free DNA fragment sequences from multiple sequences containing a large number of insertion and deletion errors and substitution errors. This method can reliably read data from low-quality PCR products (sequence length errors are completely wrong) and achieve highly robust reading.

[0006] Although DNA storage has made great progress in recent years, it has not yet been widely used. The main reasons are: (1) high cost. Currently, the cost of synthesizing one base of DNA is about RMB 1.04 (there may be some deviations depending on the synthesis requirements). The cost of storing 1TB of content in DNA is about 70 million times that of a hard disk. (2) It takes a long time. Storing information in DNA requires encoding and DNA synthesis, and reading information requires DNA sequencing and decoding. On the one hand, DNA synthesis and sequencing take a lot of time, and the longer the base sequence, the longer the synthesis and sequencing time. On the other hand, DNA data storage encoding is mostly based on general processing platforms. Due to the serial operation of general processing platforms and other reasons, DNA storage encoding is slow and has low processing throughput, making it difficult to cope with large-scale DNA data storage application scenarios. It is estimated that the overall write throughput of current DNA data storage may be at the level of kilobytes per second. Within 10 years, systems that compete with mainstream cloud archive storage systems will need to provide read and write throughput of one billion bytes per second. To this end, it has become a trend to design high-throughput DNA storage-specific encoding chips using algorithms that meet DNA storage requirements and are suitable for hardware implementation. Summary of the invention

[0007] The present invention provides a high-throughput DNA data storage efficient encoding circuit, which solves the problems of slow information encoding speed and low processing throughput in current DNA data storage, as described below:

[0008] A DNA data storage high-efficiency coding circuit, the circuit comprising: a control module, a base conversion module, a rotation coding module and a linear block code coding module, wherein:

[0009] The control module is used to coordinate and control the sending of input and output requests of other modules;

[0010] A base conversion module is used to convert 31-bit binary data into 32-bit base 15 numbers;

[0011] A rotary encoding module for converting base 15 data into binary data suitable for DNA base synthesis;

[0012] The linear block code encoding module is used to perform linear block code encoding on the continuously input 32-bit data to obtain a code word with error correction capability.

[0013] The control module is used to coordinate and control the sending of input and output requests of other modules. The specific implementation process is as follows:

[0014] The control module includes a state control unit and a state display unit; the control state unit includes a counter and a state selector, wherein the count value output by the counter is connected to the state selector, and finally the state selector is controlled by the count value to output different states;

[0015] The state display unit includes four different working states and a selector. When the state selector outputs different selection signals, the selector outputs different working states to control the operation and termination of the remaining modules.

[0016] The base conversion module is used to convert 31-bit binary data into 32-bit base 15 data. The specific implementation process is as follows:

[0017] The system conversion module includes a binary to hexadecimal conversion unit, a hexadecimal pre-conversion unit, and a pentadecimal carry merging unit; the binary to hexadecimal conversion unit adds zeros to the highest bit of the 31-bit binary number, and divides the 31-bit binary number into eight groups of four bits, each group is a hexadecimal bit, and each bit in the hexadecimal number is represented by H. i (i∈[0,7],i∈Z) represents;

[0018] The hexadecimal pre-conversion unit is to rewrite the hexadecimal base 16 into the form of (15+1), so that each bit P in the fifteenth base j (j∈[0,7],j∈Z) is represented by a hexadecimal polynomial; the fifteen-decimal carry merging unit performs a final carry operation between the digits of the fifteen-decimal number to obtain the fifteen-decimal number P7P6P5P4P3P2P1P0.

[0019] Furthermore, the binary to hexadecimal conversion unit adds zeros to the highest bit of the 31-bit binary number, and divides the 31-bit binary number into eight groups of four bits, each of which is a hexadecimal bit, and each bit in the hexadecimal number is represented by H. i (i∈[0,7],i∈Z) represents;

[0020] The specific implementation process is as follows: the 31-bit serial input binary data is grouped into 4 bits by serial-to-parallel conversion method and output in time sequence to a 4-bit register (H0~H7) representing hexadecimal. For the last 3 bits of data output, the 4-bit output in hexadecimal is achieved by filling 0 in the highest bit of register H7.

[0021] The hexadecimal pre-conversion unit is to rewrite the hexadecimal base 16 into the form of (15+1), so that each digit P in the fifteenth system is j (j∈[0,7],j∈Z) is represented by a hexadecimal polynomial. The specific implementation process is as follows:

[0022] (2.3.1) Each digit of the fifteen-digit system is rewritten as follows:

[0023] P i =2 3 ·clk1+2 2 ·clk2+2 1 ·clk3+2 0 ·clk4.

[0024] (2.3.2) The hexadecimal pre-conversion unit is composed of eight identical and independent processing units, and the 32-bit hexadecimal pre-conversion is realized through the shift and accumulation operations inside the processing unit;

[0025] (2.3.2) The processing unit includes two adders, a shift register, a two-way gate and a counter;

[0026] (2.3.3) According to the form described in (2.3.1), when the first clock rising edge arrives, data clk1 enters the processing unit, and the adder in the processing unit adds data clk1 and 0 in the shift register and stores it in the shift register through the gate, and the counter increases by one; when the second clock rising edge arrives, data clk2 enters the processing unit, and the adder in the processing unit adds data clk2 and the shifted data in the shift register and stores it in the shift register through the gate, and the counter increases by one; when the third clock rising edge arrives, data clk3 enters the processing unit, and the adder in the processing unit adds data clk3 and the shifted data in the shift register and stores it in the shift register through the gate, and the counter increases by one; when the fourth clock rising edge arrives, data clk4 enters the processing unit, and the adder in the processing unit adds data clk4 and the shifted data in the shift register and outputs it through the gate, and the counter is cleared.

[0027] Among them, the fifteen-decimal carry merging unit performs the final carry operation between the digits of the fifteen-decimal number to obtain the fifteen-decimal number P7P6P5P4P3P2P1P0. The specific implementation process is as follows:

[0028] (2.4.1) The hardware implementation of the 15-bit carry merging unit includes an 8-bit shift register, an XOR gate, an AND gate, an adder and a gate;

[0029] (2.4.2) The shift register is used to store two adjacent 15-bit numbers, the lower 4 bits of the register are stored in P0, and the upper 4 bits of the register are stored in P1; the XOR gate is used to compare the lower 4 bits in the shift register with 4'b1111, and the AND gate is used to clear the lower 4 bits in the shift register;

[0030] (2.4.3) The lower four bits of the data in the shift register are XORed with 4'1111 when the clock rises. If the result is 0, the lower four bits of the shift register are XORed with "0" and the upper four bits of the register are incremented by one. Otherwise, the lower four bits of the shift register are shifted and output, and the upper four bits of the register are moved to the lower four bits, and the new data is shifted to the upper four bits. The above process is repeated until the final fifteen-bit number is output.

[0031] Furthermore, the rotation encoding module is used to convert the base-15 data into binary data suitable for DNA base synthesis, and the specific implementation process is as follows;

[0032] (3.1) The rotation encoding algorithm is used to group the 32-bit data into four bits, and then add one to each group of data and add it to the previous group of data and output it;

[0033] (3.2) The rotary encoding module includes a counter, two adders, and a 4-bit register;

[0034] (3.3) Wherein, the counter is used to record the number of operations on the input data. Every four bits of the input data are added by one in turn by the adder, and then added to the value in the register again and output. The counter is added by one after each operation, and the operation result is output when the counter value reaches 8.

[0035] The linear block code encoding module is used to perform linear block code encoding on the continuously input 32-bit data to obtain a codeword with a certain error correction capability, using the Galois field G(2 12 ) as an example, the specific implementation process is as follows:

[0036] (4.1) The linear block code encoding module includes a data buffer module, 16 RS code encoders, a gate, a counter, and a comparator, wherein:

[0037] (4.2) The data buffer module is used to detect the write response signal, buffer the 96-bit data input in three cycles and send a read signal in the third cycle, output 8 12-bit data to 8 RS encoders, including a buffer register, a buffer counter, a buffer comparator and a buffer selector;

[0038] (4.3) The 16 12-bit RS code encoders are used to perform RS encoding on the input data, and 8 12-bit RS encoders form a group to form a ping-pong structure. The 8 12-bit numbers from the data buffer module are input into two groups of RS encoders in turn;

[0039] (4.4) The selector is used to select the destination of the data output from the data buffer module, and the two groups of RS encoders are selected in turn by the flip signal control;

[0040] (4.5) The counter is used to record the number of times the RS encoder is written. When the number of times each group of 8 RS encoders is written reaches 4000 after comparison by the comparator, the counter stops timing, indicating that the data processing is completed.

[0041] The beneficial effects of the technical solution provided by the present invention are:

[0042] 1. The present invention solves the problems of slow information encoding speed and low processing throughput in current DNA data storage;

[0043] 2. The DNA storage-specific encoding algorithm hardware circuit proposed in the present invention can achieve high data throughput while occupying less hardware logic resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 It is the overall architecture of the hardware implementation of the DNA data storage efficient coding circuit architecture in the solution of the present invention;

[0045] Figure 2 It is a structural diagram of the base conversion module in the solution of the present invention;

[0046] Figure 3 It is a structural schematic diagram of a hexadecimal to fifteen-decimal conversion unit circuit in the solution of the present invention;

[0047] Figure 4 It is a structural schematic diagram of the fifteen-base carry merging unit circuit in the solution of the present invention;

[0048] Figure 5 It is a structural schematic diagram of the rotary encoding module in the solution of the present invention;

[0049] Figure 6 It is a structural diagram of the RS encoding module in the solution of the present invention. DETAILED DESCRIPTION

[0050] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention are described in further detail below.

[0051] See also Figure 1 The embodiment of the present invention provides a high-throughput DNA data storage efficient coding circuit, the coding circuit comprising: a control module 1, a base conversion module 2, a rotation coding module 3 and a linear cyclic code coding module 4,

[0052] Among them, the enable signal output by the control module 1 is connected to the base conversion module 2, the rotation encoding module 3 and the linear cyclic code encoding module 4, which is used to control the sending of data input and output requests and the current status display of the remaining modules. The 32-bit 15-decimal number output by the base conversion module 2 is connected to the rotation encoding module 3, which is used to convert the 31-bit binary data into 32-bit 15-decimal numbers. The 32-bit 15-decimal number output by the rotation encoding module 3 is connected to the rotation encoding module 3, which is used to convert the 32-bit 15-decimal data into binary data suitable for DNA base synthesis through cyclic shift and accumulation operations. The linear cyclic code encoding module 4 is used to input the continuously input 32-bit data into the linear cyclic code encoding unit through serial-to-parallel conversion, merging, etc. to obtain a coded codeword with a certain error correction capability.

[0053] Among them, the embodiment of the present invention uses the Galois field G(2 12 ) as an example to introduce the linear cyclic code encoding algorithm.

[0054] See also Figure 2The binary conversion module 2 includes: a control logic circuit 20, a binary to hexadecimal conversion unit 21, a hexadecimal pre-conversion to fifteen-decimal unit 22, and a fifteen-decimal carry merging unit 23, and is specifically implemented as follows:

[0055] The binary-to-hexadecimal conversion unit 21 is used to convert a 31-bit binary number into a 32-bit hexadecimal number by adding 0 to the highest bit.

[0056] The hexadecimal pre-conversion unit 22 is used for converting a 32-bit hexadecimal number into a 32-bit fifteen-bit number by bitwise expansion.

[0057] The fifteen-decimal carry merging unit 23 is used to perform a pre-carry operation between the digits of the fifteen-decimal number to obtain a simplified fifteen-decimal number.

[0058] The hexadecimal pre-conversion unit 22 is used to convert a 32-bit hexadecimal number into a 32-bit fifteen-bit number by bitwise expansion. The specific implementation is as follows:

[0059] The hexadecimal pre-conversion unit 22 is composed of eight identical and independent processing units 220 , wherein the processing unit 220 includes: an adder 2200 , a shift register 2201 , a two-way selector 2202 , and a counter 2203 .

[0060] Each digit of the fifteen-digit system can be rewritten as follows:

[0061] P i =2 3 ·clk1+2 2 ·clk2+2 1 ·clk3+2 0 ·clk4.

[0062] According to the above form, when the first clock rising edge arrives, data clk1 enters the processing unit 9, the adder 10 in the processing unit 9 adds the data clk1 and the 0 in the shift register 11 and stores it in the shift register 11 through the gate 12, and the counter 13 increases by one; when the second clock rising edge arrives, data clk2 enters the processing unit 9, the adder 10 in the processing unit 9 adds the data clk2 and the shifted data in the shift register 11 and stores it in the shift register 11 through the gate 12, and the counter 13 increases by one. 13 plus one; when the third clock rising edge arrives, the data clk3 enters the processing unit 9, the adder 10 in the processing unit 9 adds the data clk3 and the shifted data in the shift register 11, and then stores it in the shift register 11 through the gate 12, and the counter 13 adds one; when the fourth clock rising edge arrives, the data clk4 enters the processing unit 9, the adder in the processing unit 9 adds the data clk4 and the shifted data in the shift register 11, and then outputs it through the gate 12, and the counter 13 is cleared.

[0063] The 15-decimal carry merging unit 23 is used to perform carry operations between the digits of the 15-decimal numbers that have not been processed by carry operations to obtain the final 15-decimal number. The specific implementation is as follows: The hardware implementation of the 15-decimal carry merging unit 23 includes registers 14, 15, comparator 16, subtractor 17, adder 18 and selector 19. Among them, registers 14 and 15 are used to store two 15-decimal numbers with similar digits. The register 14 storing the lower digit is compared with the 15 in the comparator when the clock rises. If the lower digit is greater than or equal to 15, the lower digit is reduced by 15, and the register 15 storing the higher digit is increased by 1; if the lower digit is less than 15, the lower digit is output and the higher digit is input, and the above process is repeated until the data is input.

[0064] See also Figure 1 , Figure 3 The hardware implementation of the rotary encoding module 2 includes: a counter 20, an adder 21, and a register 22, wherein the counter 20 is used to record the number of operations of the input data, and the first four bits of the input data are output after being added by the adder 21 and the value in the register 22, and the counter 20 is added by one. When the value of the counter 20 is 8, the operation result is output.

[0065] See also Figure 1 , Figure 4 The RS encoding module 3 is composed of a data buffer module 23, 16 12-bit RS code encoders 24, a gate 25, a counter 26, and a comparator 27, wherein:

[0066] The data buffer module 23 is used to detect the write response signal, buffer the 96-bit data input within three cycles and send a read signal in the third cycle, output 8 12-bit data to 8 RS encoders 24, including: a buffer register 28, a buffer counter 29, a buffer comparator 30 and a buffer selector 31.

[0067] The 16 12-bit RS code encoders 24 are used to perform RS encoding on the input data. Eight 12-bit RS encoders form a group to form a ping-pong structure. The eight 12-bit numbers from the data buffer module 23 are input into two groups of RS encoders 24 in turn.

[0068] The selector 25 is used to select the destination of the data output from the data buffer module, and the two groups of RS encoders 24 are selected in turn by the flip signal control.

[0069] The counter 26 is used to record the number of times the RS encoder 24 is written. When the number of times each group of 8 RS encoders 24 is written reaches 4000 after comparison by the comparator 27, the counter 26 stops timing, indicating that the data processing is completed.

[0070] See also Figure 1 The control module 4 is implemented by: a gate 32, a counter 33 and a comparator 34. The counter 33 is used to record the number of times data is written into the hardware device. The gate 32 is controlled by the input completion signal, the write completion signal and the read completion signal, and selects the four states of read-write, read-only, completion and error.

[0071] In conjunction with the accompanying drawings, the method of using the present invention is as follows: 3504*31*6-bit original data is grouped into 31 bits and input into the base conversion module 1 after the hardware device and the input end have successfully shaken hands. The base conversion module 1 converts the 31-bit input data into 32-bit base 15 data and sends it to the rotation encoding module 2. The rotation encoding module 2 rotationally encodes the input data into output data that satisfies the continuous base constraint and sends it to the RS encoding module 3. The RS encoding module 3 generates a check code while outputting the input data, and finally forms an RS code output including 3504 192-bit information codes and 496 192-bit check codes.

[0072] The above description is only the preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0073] The hardware circuit proposed in the embodiment of the present invention is implemented using a field programmable gate array (FPGA). Figure 1The RAM memory in the embodiment of the present invention can be implemented by using the RAM module integrated in the FPGA chip. In the embodiment of the present invention, the linear block code is selected as an RS (n, k) code encoder with a code length of 4000 and an information sequence length of 3504, and the implementation effect of a DNA data storage dedicated coding circuit proposed in the patent of the present invention is introduced.

[0074] Unless otherwise specified, the models of the components in the embodiments of the present invention are not limited, and any device that can perform the above functions may be used.

[0075] Those skilled in the art can understand that the accompanying drawing is only a schematic diagram of a preferred embodiment, and the serial numbers of the embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments.

[0076] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A DNA data storage high-efficiency coding circuit, characterized in that: The circuit comprises: a control module, a base conversion module, a rotation encoding module and a linear block code encoding module, wherein: The control module is used to coordinate and control the sending of input and output requests of other modules; A base conversion module is used to convert 31-bit binary data into 32-bit base 15 numbers; A rotary encoding module for converting base 15 data into binary data suitable for DNA base synthesis; A linear block code encoding module is used to perform linear block code encoding on the continuously input 32-bit data to obtain a codeword with error correction capability; The rotation encoding module is used to convert the base 15 data into binary data suitable for DNA base synthesis, and the specific implementation process is as follows; (3.1) The rotation encoding module is used to group the 32-bit data into four bits, add one to each group of data, and then add the sum with the previous group of data and output; (3.2) The rotary encoding module includes a counter, two adders, and a 4-bit register; (3.3) Wherein, the counter is used to record the number of operations on the input data. Every four bits of the input data are added by one in turn by the adder, and then added to the value in the register again and output. The counter is added by one after each operation, and the operation result is output when the counter value reaches 8.

2. A DNA data storage high-efficiency coding circuit according to claim 1, characterized in that: The control module is used to coordinate and control the sending of input and output requests of other modules. The specific implementation process is as follows: The control module includes a state control unit and a state display unit; the state control unit includes a counter and a state selector, wherein the count value output by the counter is connected to the state selector, and finally the state selector is controlled by the count value to output different states; The state display unit includes four different working states and a selector. When the state selector outputs different selection signals, the selector outputs different working states to control the operation and termination of the remaining modules.

3. The DNA data storage high-efficiency coding circuit according to claim 1, characterized in that: The base conversion module is used to convert 31-bit binary data into 32-bit base 15 numbers. The specific implementation process is as follows: The system conversion module includes a binary to hexadecimal conversion unit, a hexadecimal pre-conversion unit, and a pentadecimal carry merging unit; the binary to hexadecimal conversion unit adds zeros to the highest bit of the 31-bit binary number, and divides the 31-bit binary number into eight groups of four bits, each group is a hexadecimal bit, and each bit in the hexadecimal number is represented by H. i ,i∈[0,7],i∈Z represents; The hexadecimal pre-conversion unit is to rewrite the hexadecimal base 16 into the form of (15+1), so that each bit P in the fifteenth base j ,j∈[0,7],j∈Z is represented by a hexadecimal polynomial; the fifteen-decimal carry merging unit performs the final carry operation between the digits of the fifteen-decimal number to obtain the fifteen-decimal number P7P6P5P4P3P2P1P0.

4. A DNA data storage high-efficiency coding circuit according to claim 3, characterized in that: The binary to hexadecimal conversion unit adds zeros to the highest bit of the 31-bit binary number, and divides the 4-bit number into eight groups, each of which is a hexadecimal bit. Each bit in the hexadecimal system is represented by H. i ,i∈[0,7],i∈Z represents; The serial-to-parallel conversion method is used to group the 31-bit binary data into 4-bit registers H0 to H7 in hexadecimal format in a time sequence. For the last 3 bits of data output, the 4-bit output in hexadecimal format is achieved by filling the highest bit of register H7 with 0.

5. The DNA data storage high-efficiency coding circuit according to claim 3, characterized in that: The hexadecimal pre-conversion unit is to rewrite the hexadecimal base 16 into the form of (15+1), so that each bit P in the fifteenth base j ,j∈[0,7],j∈Z is represented by a hexadecimal polynomial. The specific implementation process is as follows: (2.3.1) Each digit of the fifteen-digit system is rewritten as follows: P i =2 3 ·clk1+2 2 ·clk2+2 1 ·clk3+2 0 ·clk4 (2.3.2) The hexadecimal pre-conversion unit is composed of eight identical and independent processing units, and the 32-bit hexadecimal pre-conversion is realized through the shift and accumulation operations inside the processing unit; (2.3.2) The processing unit includes two adders, a shift register, a two-way gate and a counter; (2.3.3) According to the form described in (2.3.1), when the first clock rising edge arrives, data clk1 enters the processing unit, and the adder in the processing unit adds data clk1 and 0 in the shift register and stores it in the shift register through the gate, and the counter increases by one; when the second clock rising edge arrives, data clk2 enters the processing unit, and the adder in the processing unit adds data clk2 and the shifted data in the shift register and stores it in the shift register through the gate, and the counter increases by one; when the third clock rising edge arrives, data clk3 enters the processing unit, and the adder in the processing unit adds data clk3 and the shifted data in the shift register and stores it in the shift register through the gate, and the counter increases by one; when the fourth clock rising edge arrives, data clk4 enters the processing unit, and the adder in the processing unit adds data clk4 and the shifted data in the shift register and outputs it through the gate, and the counter is cleared.

6. The DNA data storage high-efficiency coding circuit according to claim 3, characterized in that: The 15-decimal carry merging unit performs the final carry operation between the digits of the 15-decimal number to obtain the 15-decimal number P7P6P5P4P3P2P1P0. The specific implementation process is as follows: (2.4.1) The hardware implementation of the 15-bit carry merging unit includes an 8-bit shift register, an XOR gate, an AND gate, an adder and a gate; (2.4.2) The shift register is used to store two adjacent 15-bit numbers, the lower 4 bits of the register are stored in P0, and the upper 4 bits of the register are stored in P1; the XOR gate is used to compare the lower 4 bits in the shift register with 4'b1111, and the AND gate is used to clear the lower 4 bits in the shift register; (2.4.3) The lower four bits of the data in the shift register are XORed with 4'1111 when the clock rises. If the result is 0, the lower four bits of the shift register are XORed with "0" and the upper four bits of the register are incremented by one. Otherwise, the lower four bits of the shift register are shifted and output, and the upper four bits of the register are moved to the lower four bits, and the new data is shifted into the upper four bits. The above process is repeated until the final fifteen-bit number is output.

7. A DNA data storage high-efficiency coding circuit according to claim 1, characterized in that: The linear block code encoding module is used to perform linear block code encoding on the continuously input 32-bit data to obtain a codeword with error correction capability. The encoder is a Galois field G(2 12 ) on the RS (4000, 3504) encoder, the implementation process is as follows: (4.1) The linear block code encoding module includes a data buffer module, 16 12-bit RS code encoders, a gate, a counter, and a comparator, wherein: (4.2) The data buffer module is used to detect the write response signal, buffer the 96-bit data input in three cycles and send a read signal in the third cycle, output 8 12-bit data to 8 RS encoders, including a buffer register, a buffer counter, a buffer comparator and a buffer selector; (4.3) The 16 12-bit RS code encoders are used to perform RS encoding on the input data. Eight 12-bit RS code encoders form a group to form a ping-pong structure. The eight 12-bit data from the data buffer module are input into two groups of RS coders in turn. (4.4) The selector is used to select the destination of the data output from the data buffer module, and the two groups of RS encoders are selected in turn by the flip signal control; (4.5) The counter is used to record the number of times the RS encoder is written. When the number of times each group of 8 RS encoders is written reaches 4000 after comparison by the comparator, the counter stops timing, indicating that the data processing is completed.

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