Hash table reconstruction method, device, computer equipment and medium

Abstract

The present application relates to a hash table reconstruction method, apparatus, computer equipment, and medium. The method is applied to a disk array controller connected to a host computer and including a cache. The method comprises: reading cache status data from a pre-built hash table when the disk array controller is restarted after a power outage; when the status data indicates that the cache is locked and cache operations have not been completed, resetting the status data to reconstruct the hash table to obtain a new hash table; and responding to input and output commands from the host computer based on the new hash table. This method enables rapid response to the host computer even when the disk array controller is restarted after an abnormal power outage.

Description

Technical Field

[0001] The present application relates to the field of data storage technology, and in particular to a hash table reconstruction method, apparatus, computer equipment, and medium. Background Art

[0002] With the advancement of data storage technology, the use of NVMe (Non-Volatile Memory Express) devices has become increasingly widespread. More and more users are adopting the combination of PCIe (Peripheral Component Interconnect Express) and NVMe to achieve high-speed and secure storage. Based on the NVMe protocol, the process of processing host commands requires the disk array controller to execute the commands.

[0003] When a disk array controller executes commands and the system is powered on again after an abnormal power outage, traditional implementations require the following operations to respond to host commands: Based on hash table information, data in the cache (memory) is written to disk to perform a cache flush; and the hash table is cleared to re-manage the hash table in the RAID (Redundant Arrays of Independent Disks) cache.

[0004] However, for example, if a disk array controller is connected to five disks and handles 4KB of I / O (input and output) data, each disk providing 200 IOPS (Input / Output Operations Per Second), and the RAID cache manages 8GB of data, the estimated cache flush time is over 30 minutes. This traditional cache flush method significantly impacts the disk array controller's power-on preparation time, which in turn affects the response and execution of host commands. This is because after system power-up, the disk array controller's response time to host I / O commands is constrained, typically ranging from several seconds to over ten seconds. Summary of the Invention

[0005] Based on this, it is necessary to provide a hash table reconstruction method, device, computer equipment and medium to address the above technical problems.

[0006] A hash table reconstruction method is applied to a disk array controller, wherein the disk array controller is connected to a host and includes a cache. The method includes:

[0007] When the disk array controller is restarted after power failure, the cache status data is read from the pre-built hash table;

[0008] When the state data indicates that the cache is locked and the cache operation is not completed, the state data is reset to reconstruct the hash table to obtain a new hash table;

[0009] Respond to the host's input and output commands based on the new hash table.

[0010] In one embodiment, the hash table includes multiple entries, the state data includes state data corresponding to the multiple entries, and the method further includes:

[0011] Obtaining pre-set configuration information, including the size of the hash table, the size of the table entries, and bus characteristics for reading the hash table;

[0012] Determine the number of entries corresponding to each read task and the total number of read tasks based on the size of the hash table, the size of the table entries, and the bus characteristics of the hash table read;

[0013] The above-mentioned reading of cache status data from the pre-built hash table includes:

[0014] The cache status data is read from the hash table based on the number of entries in each read task and the total number of read tasks.

[0015] In one embodiment, the bus characteristics of the hash table read include the bus width and the transmission length supported by the bus. The number of entries corresponding to each read task and the total number of read tasks are determined based on the size of the hash table, the size of the table entries, and the bus characteristics of the hash table read, including:

[0016] Determine a ratio of the size of the hash table to a first product to obtain a total number of read tasks, where the first product is a product of a bus width and a transfer length supported by the bus in bus characteristics for reading the hash table;

[0017] The ratio of the first product to the size of the table entry is determined to obtain the number of table entries corresponding to each reading task.

[0018] In one embodiment, the disk array controller includes a hash table entry original cache, and the reading of cache status data from the hash table based on the number of entries read each time and the total number of reads includes:

[0019] Determine whether each reading task is completed;

[0020] When there is an unfinished read task, a read task is initiated based on the number of entries in each read task;

[0021] Write the state data corresponding to the read table entry into the hash table entry original cache;

[0022] Return to the step of determining whether each reading task is completed, until each reading task is completed.

[0023] In one embodiment, the disk array controller includes a hash table entry reconstruction cache, and the method further includes:

[0024] Read the current entry's state data from the hash table entry original cache;

[0025] When the state data indicates that the cache is locked and the cache operation is not completed, the state data is reset to reconstruct the hash table to obtain a new hash table, including:

[0026] When the status data of the current entry indicates that the cache is locked and the cache operation is not completed, the status data of the current entry is reset to obtain a new entry;

[0027] Write the new table entry into the hash table to reconstruct the cache;

[0028] Each new entry is read from the hash table entry reconstruction cache and written into the hash table to reconstruct the hash table to obtain a new hash table.

[0029] In one embodiment, the status data of each of the above-mentioned table entries includes multiple status information bits and values ​​of each status information bit. The above-mentioned status information bits include whether the write cache operation is locked and whether the disk data is in the cache. The above-mentioned cache operation includes a write cache operation. When the status data of the current table entry indicates that the cache is locked and the cache operation is not completed, the status data of the current table entry is reset to obtain a new table entry, including:

[0030] When the value of the write cache operation lock is valid, the cache is determined to be locked;

[0031] When the status data in the current entry indicates that the disk data is in the cache, the value of the write cache operation lock is valid, and the write cache is not completed, the value of the write cache operation lock is reset to invalid to obtain a new entry.

[0032] In one embodiment, the method further includes:

[0033] When the status data in the current entry indicates that the disk data is not in the cache, the value of the write cache operation lock is valid, and the write cache is not completed, the values ​​of all status information bits of the current entry are reset to invalid to obtain a new entry.

[0034] In one embodiment, the state information bit further includes a read cache operation lock, the cache operation includes a read cache operation, and the method further includes:

[0035] When the value of the read cache operation lock is valid, the cache is determined to be locked;

[0036] When the status data in the current entry indicates that the disk data is in the cache, the value of the read cache operation lock is valid, and the read cache is not completed, the value of the read cache operation lock is reset to invalid to obtain a new entry.

[0037] In one embodiment, the state information bit further includes disk lock, the cache operation includes a disk flush operation, and the method further includes:

[0038] When the value of disk lock is valid, the cache is locked.

[0039] When the status data in the current entry indicates that the disk data is in the cache, the disk lock value is valid, and the disk lock operation is not completed, the disk lock value is reset to invalid to obtain a new entry.

[0040] In one embodiment, the configuration information further includes configuration information of an abnormal event handling mode, and the method further includes:

[0041] When the status data in the current entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the abnormal state, an abnormal event is generated and reported;

[0042] When the status data in the current table entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the normal state, the values ​​of each status information bit in the current table entry are reset to invalid.

[0043] In one embodiment, the method further includes:

[0044] When the values ​​of the status information bits in the current entry are all invalid, the step of resetting the status data of the current entry to obtain a new entry is not performed.

[0045] In one embodiment, the above-mentioned reading each new entry from the hash table entry reconstruction cache and writing it into the hash table to obtain a new hash table includes:

[0046] Determine the total number of times the hash table is written and the number of entries written each time according to the configuration information;

[0047] Determine whether the task of reading each new table entry from the hash table reconstruction cache and writing it into the hash table is completed;

[0048] When there are entries in the hash table reconstruction cache that have not been written into the hash table, a write task is initiated based on the number of entries written each time;

[0049] Return to the step of determining whether the task of reading each new table entry from the hash table entry reconstruction cache and writing it into the hash table is completed, until all the table entries in the hash table entry reconstruction cache are written into the hash table.

[0050] In one embodiment, the configuration information further includes bus characteristics for writing the hash table, the bus characteristics for writing the hash table including the bus width and the transfer length supported by the bus, and determining the total number of writes to the hash table and the number of entries in each write based on the configuration information includes:

[0051] Determine a ratio of the size of the hash table to a second product to obtain a total number of writes to the hash table, where the second product is a product of a bus width and a transfer length supported by the bus in characteristics of a bus for writing the hash table;

[0052] The ratio of the second product to the size of the table entry is determined to obtain the number of table entries written each time.

[0053] In one embodiment, the disk array controller is connected to a non-volatile memory, and the method further includes:

[0054] When the disk array controller experiences an abnormal power failure, the hash table is written to the non-volatile memory;

[0055] When power is cycled, the hash table is retrieved from the non-volatile memory.

[0056] In one embodiment, responding to the host's input and output commands according to the new hash table includes:

[0057] Determine the hash address corresponding to the input and output commands according to a preset hash algorithm;

[0058] Read the entry corresponding to the hash address from the new hash table;

[0059] Execute the cache search operation based on the state data of the table entry corresponding to the hash address;

[0060] When the status data in the table entry corresponding to the hash address indicates that the disk data is in the cache, it is determined that the result of the search operation is that the data corresponding to the input / output command is in the cache;

[0061] When the input / output command is a read command, the data corresponding to the read command is read from the cache and the execution result of the input / output command is generated;

[0062] Feedback the execution results of input and output commands to the host.

[0063] In one embodiment, the method further includes:

[0064] When the input / output command is a write command, the data corresponding to the write command is written into the cache, and the corresponding execution result is generated and fed back to the host;

[0065] When the input / output command is a disk write command, the data corresponding to the disk write command is written back to the disk, and the corresponding execution result is generated and fed back to the host.

[0066] In one embodiment, before writing the data corresponding to the write command into the cache, the method further includes:

[0067] Set the write cache lock value in the entry corresponding to the hash address to valid;

[0068] After writing the data corresponding to the write command into the cache, the method further includes:

[0069] The write cache lock value in the entry corresponding to the hash address is set to invalid.

[0070] A disk array cache hash table reconstruction system, the system includes a disk array controller and a host, the disk array controller is connected to the host, the disk array controller includes a hash table reconstruction device, wherein,

[0071] The hash table reconstruction device is used to read the cache status data from the pre-built hash table when the disk array controller is powered on again. When the status data indicates that the cache is locked and the cache operation has not been completed, the status data is reset to reconstruct the hash table to obtain a new hash table.

[0072] The disk array controller is used to respond to input and output commands from the host according to the new hash table.

[0073] In one embodiment, the above-mentioned state data includes state data of multiple table entries, and the hash table reconstruction device includes a hash table reconstruction unit, a hash table entry original cache, a hash table entry reconstruction cache, and a register, and the hash table entry original cache, the hash table entry reconstruction cache, and the register are respectively connected to the hash table reconstruction unit, wherein,

[0074] The hash table reconstruction unit is configured to determine the number of entries to be read each time and the number of reads based on the configuration information in the register, read the status data of each entry from the hash table based on the number of entries to be read each time and the number of reads, write the status data of each entry into the hash table entry original cache, read each entry from the hash table entry original cache, reset the status data of each entry based on the status data of each entry, reconstruct a new entry, write the new entry into the hash table entry reconstruction cache, read each new entry from the hash table entry reconstruction cache, write the new entry into the hash table, and obtain a new hash table.

[0075] The above hash table entry original cache is used to store the status data of each entry read from the hash table;

[0076] The above-mentioned hash table entry reconstruction cache is used to store each new entry;

[0077] The above registers are used to store configuration information.

[0078] A disk array cache hash table reconstruction device is applied to a disk array controller, the disk array controller is connected to a host, the disk array controller includes a cache, and the device includes:

[0079] The read module is used to read the cache status data from the pre-built hash table when the disk array controller is restarted after power failure;

[0080] A reconstruction module is used to reset the state data to reconstruct the hash table to obtain a new hash table when the state data indicates that the cache is locked and the cache operation is not completed;

[0081] The response module is used to respond to the input and output commands of the host according to the new hash table.

[0082] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the following steps when executing the computer program:

[0083] When the disk array controller is restarted after power failure, the cache status data is read from the pre-built hash table;

[0084] When the state data indicates that the cache is locked and the cache operation is not completed, the state data is reset to reconstruct the hash table to obtain a new hash table;

[0085] Respond to the host's input and output commands based on the new hash table.

[0086] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the following steps:

[0087] When the disk array controller is restarted after power failure, the cache status data is read from the pre-built hash table;

[0088] When the state data indicates that the cache is locked and the cache operation is not completed, the state data is reset to reconstruct the hash table to obtain a new hash table;

[0089] Respond to the host's input and output commands based on the new hash table.

[0090] The above-mentioned hash table reconstruction method, device, computer equipment and medium read the cache status data from a pre-built hash table when the disk array controller is restarted after power failure, and reconstruct the hash table according to the information indicated by the status data. After the hash table reconstruction is completed, the host command can be responded to without flushing the data in the RAID Cache to the disk. Because the hash table reconstruction time is greatly reduced compared to the cache flush operation time, the present application can shorten the response time of the disk array controller to the host command when the disk array controller is restarted after power failure, and can achieve a rapid response to the host even in the event of an abnormal power failure, thereby accelerating the response speed and data processing speed of the disk array controller and the host. BRIEF DESCRIPTION OF THE DRAWINGS

[0091] Figure 1 A diagram illustrating an application environment of a hash table reconstruction method according to an embodiment;

[0092] Figure 2 Schematic diagram of a flow chart of a hash table reconstruction method in one embodiment;

[0093] Figure 3 A schematic diagram of a process for reading a hash table in one embodiment;

[0094] Figure 4 A schematic diagram of a process for reconstructing a hash table according to an embodiment;

[0095] Figure 5 A schematic diagram of the process of writing a hash table in one embodiment;

[0096] Figure 6 A block diagram of a disk array cache hash table reconstruction system according to an embodiment;

[0097] Figure 7 A schematic diagram of the internal structure of a hash table reconstruction device in another embodiment;

[0098] Figure 8 A block diagram of a disk array cache hash table reconstruction device according to an embodiment;

[0099] Figure 9 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0100] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0101] Please refer to Figure 1 , Figure 1 A schematic diagram of an application environment of a hash table reconstruction method provided by an exemplary embodiment of the present application. Figure 1 As shown, the application environment includes a host 100 and a disk array controller 101. The host 100 and the disk array controller 101 perform data exchange based on the NVMe protocol to implement the hash table reconstruction method of the present application.

[0102] Host 100 is used to write host input and output commands to SQ (Submission Queue, submission queue), write SQ DB (equivalent to Figure 1 The write submission queue register in the IO register notifies the disk array controller to obtain the above input and output commands, where DB is the Doorbell register.

[0103] After receiving the notification, the disk array controller 101 retrieves the above-mentioned input and output commands from the SQ queue and executes the commands. During the process of executing the commands, when the disk array controller 101 restarts after power failure, it reads the cache status data from the pre-built hash table. When the status data indicates that the cache is locked and the cache operation is not completed, the status data is reset to reconstruct the hash table to obtain a new hash table. The host's input and output commands are responded to according to the new hash table. After the command execution is completed, the command execution result is written to the CQ (Completion Queue) and an interrupt is sent to notify the host to view the command execution result in the CQ.

[0104] The host 100 is also used to check the command completion status in the CQ after receiving the interrupt, process the command execution results in the CQ, and update the CQ Head BD (equivalent to Figure 1 The second register in the CQ DB register (equivalent to Figure 1 The write completion queue register in the memory) replies to the disk array controller 101.

[0105] In one embodiment, Figure 2 As shown, a hash table reconstruction method is provided, which is applied to Figure 1The disk array controller is connected to the host, and the disk array controller includes a cache. The above hash table reconstruction method includes the following steps:

[0106] S11. When the disk array controller is restarted after power failure, the cache status data is read from the pre-built hash table.

[0107] The disk array controller mentioned above may be a RAID controller. The cache mentioned above is a type of storage on the RAID controller used to store small amounts of temporary data that requires quick access. In this application, the RAID controller uses the cache to store data written to the RAID array, thereby avoiding frequent disk accesses and improving system performance. When the RAID controller receives a write request, it stores the data in the cache and then periodically writes the data to the disk. During this process, the RAID controller uses a hash table to manage the cache data structure.

[0108] Specifically, a hash table is a special data structure that uses a key (K) and a hash algorithm to determine a location (P), then stores the data in the hash table entry corresponding to P. When cache data needs to be queried, inserted, or deleted, the RAID controller uses the key and hash algorithm to determine the corresponding location, then reads or modifies the hash table entry corresponding to P to perform cache insertion, query, and deletion operations. By using a hash table, the RAID controller can quickly access cache data, thereby improving system performance.

[0109] The cache status data mentioned above refers to the status of the cache on the disk array controller. Specifically, this status data may include information such as cache availability, whether it has been allocated, and whether it has been locked. This status information can help the disk array controller better manage the cache, improving cache performance and reliability.

[0110] In actual application scenarios, the disk array controller may experience abnormal power failure while executing host commands. When abnormal power failure is detected, the disk array controller obtains cache status data from the hash table, analyzes and processes the cache status data.

[0111] Specifically, the hash table stores cache status data. This cache status data may represent the RAID cache status, and may also indicate the cache operation types supported by the RAID cache, such as read and write operations. The specific storage location of the hash table can be determined based on actual needs or application scenarios and is not specifically defined herein.

[0112] Please continue to refer to Figure 1 Based on the NVMe protocol, the typical process of processing host commands includes the following steps:

[0113] (1) Host command is written to SQ;

[0114] (2) The host writes the SQ DB register to the SQ Tail Doorbell (equivalent to Figure 1 The first register in the RAID controller is notified to fetch the command, where Figure 1 The submission queue register in is the SQ DB register;

[0115] (3) After receiving the notification, the NVMe RAID Controller takes the command from the SQ queue;

[0116] (4) RAID Controller executes commands:

[0117] When RAID Cache is supported, host I / O data is written to or read from the cache. Simultaneously, the firmware issues a command to write cache data to disk, performing a write-to-disk operation. If RAID Cache is not supported, disk access is performed.

[0118] (5) After the command execution is completed, the RAID Controller writes the command execution result to the CQ;

[0119] (6) The RAID Controller sends an interrupt notification to the host to check the command execution results in the CQ;

[0120] (7) After the host receives the interrupt, it checks the command completion status in CQ;

[0121] (8) After the host processes the command execution results in CQ, it updates the CQ Head BD (equivalent to Figure 1 The second register in the CQ DB register is written to reply to the RAID Controller, where Figure 1 The completion queue register in is the CQ DB register.

[0122] The hash table reconstruction method of the present application is specifically applied to step (4) above. According to the NVMe protocol, for a RAID controller, in step (5): if the RAID controller completes the operation of writing the CQ to the host, it is considered that the RAID controller has completed the host IO command. Otherwise, the host IO command has not been completed.

[0123] It should be noted that the hash table reconstruction method of the present application is not limited to the NVMe protocol, but can also be used for other cache operations such as SATA and SAS. As long as the cache operation is completed and a response is fed back to the host, the hash table can be reconstructed.

[0124] S12. When the state data indicates that the Cache is locked and the Cache operation is not completed, the state data is reset to reconstruct the hash table to obtain a new hash table.

[0125] The above-mentioned status data has an indicative function, and its specific content can indicate the status of the cache or the status of the cache operation. The above-mentioned cache is locked and the cache operation is not completed. Specifically, for example, the cache is locked for write operations, but the write cache operation is not completed.

[0126] The above-mentioned resetting of the state data refers to resetting the state data to new data content. The above-mentioned reconstruction of the hash table is achieved by resetting the state data to obtain a new hash table.

[0127] S13. Respond to the host's input and output commands according to the new hash table.

[0128] The above-mentioned input and output commands may be read commands or write commands, etc. The above-mentioned responding to the host's input and output commands according to the new hash table refers to executing the host's input and output commands according to the data content in the new hash table.

[0129] When the disk controller executes host input / output commands, if RAID Cache is supported, host I / O (Input / Output) data is written to or read from the cache. Simultaneously, the firmware initiates a command to write the cache data to disk, performing a flush operation. If RAID Cache is not supported, the disk access operation is executed.

[0130] Specifically, for write cache, once the host IO data is written to the cache, the current IO write operation is completed, and the CQ can be fed back to the host, without having to wait until the data is written to the disk before feeding back the CQ to the host. For read cache, if the read data hits the cache, the data in the cache is written to the host, and the CQ is fed back to the host, without having to read the data from the disk and write it to the host before feeding back the CQ. This greatly reduces the number of disk accesses and access time, and also reduces the execution time of host commands. Among them, RAID Cache (equivalent to the cache mentioned above) manages the cache data structure in the form of a hash table. When the disk controller executes the host's input and output commands, it needs to respond to the host's input and output commands based on the status of the cache data maintained in the hash table.

[0131] In traditional methods, when a RAID controller is powered on again after an abnormal power outage, the following operations must be completed before it can respond to host commands:

[0132] According to the hash table information, write the data in the cache to the disk and perform a cache flush operation.

[0133] Perform the hash table clear operation and RAID Cache re-manages the hash table.

[0134] However, this cache flush method significantly reduces the RAID controller's power-on preparation time, which in turn affects the response and execution of host commands. Furthermore, performing a cache flush during a normal system shutdown will significantly increase system shutdown time. Even if backup capacitors are used to write the RAID cache hash table and cache data to non-volatile memory for data protection, the RAID controller's power-on preparation time will still be affected when the system is powered on again.

[0135] Therefore, the hash table reconstruction method in this application reconstructs the hash table information. After the system is powered on, there is no need to perform a cache flush operation. After the hash table reconstruction is completed, the host's input and output commands can be responded to, which greatly improves the response time of the RAID Controller to the host commands.

[0136] In one embodiment, the hash table may include multiple entries, the state data may include state data corresponding to the multiple entries, and the method may further include:

[0137] Obtaining pre-set configuration information, including the size of the hash table, the size of the table entries, and bus characteristics for reading the hash table;

[0138] Determine the number of entries corresponding to each read task and the total number of read tasks based on the size of the hash table, the size of the table entries, and the bus characteristics of the hash table read;

[0139] Read the cache status data from the pre-built hash table, including:

[0140] The cache status data is read from the hash table based on the number of entries in each read task and the total number of read tasks.

[0141] In the present application, the above-mentioned hash table includes multiple table entries, and each table entry includes corresponding status data. The above-mentioned configuration information is stored in a register file. The above-mentioned register refers to a register provided in a disk array controller. The above-mentioned configuration information includes but is not limited to the starting address of the hash table, the size of the hash table, the size information of the hash table entry, and the bus transmission characteristics (equivalent to the bus characteristics of reading the hash table mentioned above). Among them, the size of the hash table here refers to the number of hash table entries contained in the hash table, the size of the hash table entry here refers to the number of bytes occupied by each hash table entry, and the bus transmission characteristics here refer to parameters such as the data size and transmission speed transmitted by the bus.

[0142] The above method determines the number of entries corresponding to each read task and the total number of read tasks based on the size of the hash table, the size of the table items, and the bus characteristics of the hash table read, including:

[0143] Determine the total number of read tasks based on the Hash table size and bus characteristics in the configuration information;

[0144] The number of table entries corresponding to each of the above-mentioned reading tasks is determined according to the Hash table size, the size of the table entries, and the number of reading tasks in the above-mentioned configuration information.

[0145] In this application, the disk array controller can calculate how many bus read tasks need to be split into to read the hash table based on the hash table size and bus transmission characteristics, so that the entire hash table can be read within the constraints of the bus transmission characteristics. For example, if the hash table size is 1000 hash table items and the bus transmission characteristics are 100 hash table items per transmission, then the hash table read task needs to be split into 10 bus read tasks, each reading 100 hash table items, to read the entire hash table.

[0146] In this application, the aforementioned state data exists in the form of multiple entries. The aforementioned step of reading cache state data from a pre-built hash table splits the read task into k read tasks, each of which reads the state data within m entries. k and m are calculated based on configuration information to enable reading the entire hash table within the constraints of bus transmission characteristics, thereby improving the efficiency of reading state data.

[0147] In one embodiment, the bus characteristics of the hash table read include the bus width and the transmission length supported by the bus. The number of entries corresponding to each read task and the total number of read tasks are determined based on the size of the hash table, the size of the table entries, and the bus characteristics of the hash table read, including:

[0148] Determine a ratio of the size of the hash table to a first product to obtain a total number of read tasks, where the first product is a product of a bus width and a transfer length supported by the bus in bus characteristics for reading the hash table;

[0149] The ratio of the first product to the size of the table entry is determined to obtain the number of table entries corresponding to each reading task.

[0150] In this application, the transmission length supported by the above-mentioned bus can be the burst size supported by the bus. For example, it is assumed that the above-mentioned bus width and the transmission length supported by the bus are C and D respectively. The hash table size is A, and the table item size is B. The total number of the above-mentioned read tasks is k. The number of table items corresponding to each read task is k1. Among them, the units of C, D, k and k1 are all bytes. Then the above-mentioned k and k1 can be calculated by the following calculation formula:

[0151] k=A / (C*D)

[0152] k1=(C*D) / B

[0153] Wherein, C*D is an integer multiple of B. Through this implementation, the present application can realize reading hash table entries under the limitation of bus transmission characteristics.

[0154] In one embodiment, the disk array controller includes a hash table entry raw cache, and the cache status data is read from the hash table according to the number of entries read each time and the total number of reads, including:

[0155] Determine whether each reading task is completed;

[0156] When there is an unfinished read task, a read task is initiated based on the number of entries in each read task;

[0157] Write the state data corresponding to the read table entry into the hash table entry original cache;

[0158] Return to the step of determining whether each reading task is completed, until each reading task is completed.

[0159] In this application, the above-mentioned Hash table item original cache is used to store the original Hash table information read. Each read table item is written into the hash table item original cache. The above-mentioned number of table items corresponding to each read task is determined based on the above-mentioned configuration information and the number of read tasks, which may specifically include:

[0160] The number of table entries corresponding to each of the above-mentioned read tasks is determined according to the resource size of the original cache of the hash table entry, configuration information, and the number of read tasks.

[0161] Through this implementation, the present application can read each table item in the hash table in batches and write the hash table item original cache.

[0162] In one embodiment, the disk array controller includes a hash table entry reconstruction cache, and the method may further include:

[0163] Read the current entry's state data from the hash table entry original cache;

[0164] When the state data indicates that the cache is locked and the cache operation is not completed, the state data is reset to reconstruct the hash table to obtain a new hash table, which may include:

[0165] When the status data of the current entry indicates that the cache is locked and the cache operation is not completed, the status data of the current entry is reset to obtain a new entry;

[0166] Write the new table entry into the hash table to reconstruct the cache;

[0167] Each new entry is read from the hash table entry reconstruction cache and written into the hash table to reconstruct the hash table to obtain a new hash table.

[0168] In this application, the aforementioned Hash table item reconstruction cache is used to store newly reconstructed Hash table items. After reading each item from the aforementioned hash table item original cache, it is necessary to determine whether each item needs to be reset based on its status data. When the status data in the item indicates that the cache is locked and the cache operation has not been completed, it is determined that the status data needs to be reset to obtain a new item.

[0169] According to this implementation, the present application can reset the status data of each table entry in sequence to ultimately reconstruct the entire hash table.

[0170] In one embodiment, the status data of each of the above-mentioned table entries includes multiple status information bits and values ​​of each status information bit, the above-mentioned status information bits include whether the write cache operation is locked and whether the disk data is in the cache, the above-mentioned cache operation includes a write cache operation, and when the status data of the current table entry indicates that the cache is locked and the cache operation is not completed, the status data of the current table entry is reset to obtain a new table entry, which may include:

[0171] When the value of the write cache operation lock is valid, the cache is determined to be locked;

[0172] When the status data in the current entry indicates that the disk data is in the cache, the value of the write cache operation lock is valid, and the write cache is not completed, the value of the write cache operation lock is reset to invalid to obtain a new entry.

[0173] The status information bits corresponding to the above-mentioned entries may include V and W_L. The values ​​of the above-mentioned status information bits may include 0 and 1, where 0 indicates that the value is invalid and 1 indicates that the value is valid. The status information bits are defined as follows:

[0174] 1) V: Valid. This indicates whether the dev_lba data is in the cache. A high value (equivalent to a value of 1) indicates that the disk data is in the cache. dev_lba represents the LBA (Logical Block Address) address of the disk maintained by the hash table entry.

[0175] 2) W_L: Write Lock (write cache operation lock), whether the dev_lba data is locked during the write cache operation. High active, indicating that the hash table entry is locked during the write cache operation and the write cache operation is about to be performed.

[0176] The fields are described as follows:

[0177] In the hash table entry, when V = 1 and other status information bits are 0, it means that the data of dev_lba (equivalent to the disk data mentioned above) is in the cache and the cache operation is completed.

[0178] In the hash table entry, when V = 1 and W_L = 1 (equivalent to the value of the write cache operation lock being valid), and other status information bits are 0, it means that the data of dev_lba is in the cache, the write cache operation is locked, but the write cache operation is not completed.

[0179] Resetting the write cache operation lock value to invalid may include resetting the write cache operation lock value to 0. That is, when reconstructing the table entry, W_L=0, and other status information bits remain unchanged. The invalid and valid values ​​of the status information bits in this application can be set according to actual needs and are not specifically limited here.

[0180] Through this implementation, the present application can achieve that when the write cache operation is locked and the write cache operation is not completed, the value of the write cache operation lock status information bit can be reset to reconstruct the hash table, so as to respond to the host command with a new hash table. The data in the RAID Cache does not need to be flushed to the disk, thereby improving the response time of the RAID Controller to the host command.

[0181] In one embodiment, the above method may further include:

[0182] When the status data in the current entry indicates that the disk data is not in the cache, the value of the write cache operation lock is valid, and the write cache is not completed, the values ​​of all status information bits of the current entry are reset to invalid to obtain a new entry.

[0183] If W_L = 1 in the hash entry and all other status bits are 0, it means that the data in dev_lba is not in the cache, and the write cache operation is locked, but the write cache operation is not completed. In this case, all the status bits in the entry need to be invalidated, that is, reset to 0, to obtain a new entry.

[0184] In one embodiment, the above-mentioned status information bit may further include a read cache operation lock, the cache operation includes a read cache operation, and the method further includes:

[0185] When the value of the read cache operation lock is valid, the cache is determined to be locked;

[0186] When the status data in the current entry indicates that the disk data is in the cache, the value of the read cache operation lock is valid, and the read cache is not completed, the value of the read cache operation lock is reset to invalid to obtain a new entry.

[0187] The status information bit "Read Cache Lock" is represented as R_L (Read Lock), indicating whether the dev_lba data is locked during the cache read. High indicates that the hash table entry is locked during the cache read operation and a cache read operation is about to be performed.

[0188] Specifically, in a hash entry, when V = 1, R_L = 1, and all other status bits are 0, it indicates that the data in dev_lba is in the cache and the read cache operation is locked, but the read cache operation is not completed. When reconstructing the entry, R_L is set to 0 (equivalent to resetting the value of the read cache lock to invalid), and all other status bits remain unchanged.

[0189] Through this implementation, the present application can achieve that when a read cache operation is locked and the read cache operation is not completed, the value of the status information bit that locks the read cache operation can be reset, and the values ​​of other status information bits remain unchanged, so as to reconstruct the hash table and respond to host commands with a new hash table. The data in the RAID Cache does not need to be flushed to the disk, thereby improving the response time of the RAID Controller to the host command.

[0190] In one embodiment, the state information bit further includes disk lock, the cache operation includes disk flushing, and the method may further include:

[0191] When the value of disk lock is valid, the cache is locked.

[0192] When the status data in the current entry indicates that the disk data is in the cache, the disk lock value is valid, and the disk lock operation is not completed, the disk lock value is reset to invalid to obtain a new entry.

[0193] The above-mentioned status information bit "Destage Lock" is represented as D_L: Destage Lock, which indicates whether the disk data is locked during the disk write operation. High is effective, indicating that the hash table entry is locked during the disk write operation and the disk write operation will be performed.

[0194] Specifically, in a hash entry, when V = 1, D_L = 1, and all other status bits are 0, the data in dev_lba is in the cache. The cache operation is locked, but not yet completed. When reconstructing the entry, D_L is set to 0 (equivalent to resetting the lock value to invalid). The other status bits in the entry remain unchanged, resulting in a new entry.

[0195] The present application reconstructs the hash table by reconstructing each table entry. Specifically, the application parses or analyzes each status information bit in each table entry, resets the value of each status information bit according to the parsing result, and reconstructs each representation, thereby reconstructing the hash table.

[0196] In one embodiment, the configuration information further includes configuration information of an abnormal event handling mode, and the method may further include:

[0197] When the status data in the current entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the abnormal state, an abnormal event is generated and reported;

[0198] When the status data in the current table entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the normal state, the values ​​of each status information bit in the current table entry are reset to invalid.

[0199] The configuration information of the above-mentioned abnormal event handling mode may include execution according to abnormal state and execution according to normal state. The abnormal event here refers to the situation where the value of the status information bit in the table entry is abnormal. Specifically, except for the following situations in the table entry, all other situations are abnormal events:

[0200] 1. In a hash table entry, when each status information bit is 0, it indicates an idle hash table entry.

[0201] 2. In the hash table entry, when V = 1 and other status information bits are 0, it means that the data of dev_lba is in the cache and the cache operation is completed.

[0202] 3. In the hash table entry, when V = 1, W_L = 1, and other status information bits are 0, it means that the data of dev_lba is in the cache, the write cache operation is locked, but the write cache operation is not completed.

[0203] 4. In the hash table entry, when W_L=1 and other status information bits are 0, it means that the data of dev_lba is not in the cache, the write cache operation is locked, but the write cache operation is not completed.

[0204] 5. In the hash table entry, when V = 1, R_L = 1, and other status information bits are 0, it means that the data of dev_lba is in the cache, the read cache operation is locked, but the read cache operation is not completed.

[0205] 6. In the hash table entry, if V = 1, D_L = 1, and other status information bits are 0, the data in dev_lba is in the cache. The cache operation is locked, but the cache operation is not completed.

[0206] In a hash table entry, when the status information bit is in other states, it indicates an abnormal state. That is, in addition to the above 6 situations, the hash table entry is in an abnormal state in other cases. When the status information bit in the hash table entry is detected as a situation other than the above 6 situations, the hash table entry is determined to be abnormal.

[0207] Specifically, when reading the status data in the hash table, before starting the bus read task, check whether there is an abnormal event. If so, jump to clear the original cache of the hash table entry. After completion, the hash table read task ends.

[0208] When reconstructing a hash table entry, you need to perform the following steps:

[0209] The hash entry is read and parsed from the original cache. If the hash entry is in a normal state, the hash entry is reconstructed and written to the reconstructed cache after reconstruction is complete.

[0210] If the hash table entry is in a normal state, based on the exception event handling mode in the register configuration information, if it is configured to "Execute as normal state," the hash table entry is reconstructed. After the reconstruction is complete, the hash table entry is written to the cache for reconstruction. If it is configured to "Execute as abnormal state," an exception event is generated. After the hash table reconstruction task is completed, the exception event is reported. Based on the register configuration information: If the exception event handling mode is configured to "Execute as abnormal state," an exception event is generated. After the hash table read task and the hash table write task are completed, the hash table reconstruction task is completed and the exception event is reported.

[0211] Through this implementation, the present application can implement software-configurable processing when the status information bit in the hash table indicates an abnormal state. When the software is configured to an abnormal state, an abnormal event is generated and notified to the software, which can report the abnormal situation and implement abnormal situation processing.

[0212] In one embodiment, the above method may further include:

[0213] When the values ​​of the status information bits in the current entry are all invalid, the step of resetting the status data of the current entry to obtain a new entry is not performed.

[0214] In this application, when each status information bit in a Hash table entry is 0, it indicates that the Hash table entry is idle. When the Hash table entry is idle, the operation of reconstructing the Hash table entry is not performed.

[0215] In one embodiment, the above-mentioned reading each new entry from the hash table entry reconstruction cache and writing it into the hash table to obtain a new hash table may include:

[0216] Determine the total number of times the hash table is written and the number of entries written each time according to the configuration information;

[0217] Determine whether the task of reading each new table entry from the hash table reconstruction cache and writing it into the hash table is completed;

[0218] When there are entries in the hash table reconstruction cache that have not been written into the hash table, a write task is initiated based on the number of entries written each time;

[0219] Return to the step of determining whether the task of reading each new table entry from the hash table entry reconstruction cache and writing it into the hash table is completed, until all the table entries in the hash table entry reconstruction cache are written into the hash table.

[0220] In this application, the disk array controller can calculate how many bus write tasks the hash table write task needs to be split into based on the hash table size, hash table item size and bus transmission characteristics, so that the entire hash table can be written within the limitations of the bus transmission characteristics.

[0221] The present application implements hash writing through this implementation, and implements the hash table reconstruction method of the present application through reading, reconstruction and writing of the hash table.

[0222] In one embodiment, the configuration information further includes bus characteristics for writing the hash table, including bus width and a transmission length supported by the bus. Determining the total number of times the hash table is written and the number of entries in each write based on the configuration information includes:

[0223] Determine a ratio of the size of the hash table to a second product to obtain a total number of writes to the hash table, where the second product is a product of a bus width and a transfer length supported by the bus in characteristics of a bus for writing the hash table;

[0224] The ratio of the second product to the size of the table entry is determined to obtain the number of table entries written each time.

[0225] In the present application, the configuration data may further include bus characteristics for writing the hash table, where the bus characteristics for writing the hash table may be the same as or different from the bus characteristics for reading the hash table.

[0226] The transmission length supported by the above-mentioned bus can be the burst size supported by the bus. For example, it is assumed that the above-mentioned bus width and the transmission length supported by the bus are E and F respectively. The hash table size is A, and the table item size is B. The total number of times the above-mentioned hash table is written is n. The number of table items written each time is n1. Among them, the units of C, D, n and n1 are all bytes. Then the above-mentioned n and n1 can be calculated by the following calculation formula:

[0227] n=A / (E*F)

[0228] n1=(E*F) / B

[0229] Wherein, E*F is an integer multiple of B. Here, E and F may be the same as or different from the above-mentioned C and D. Through this embodiment, the present application can implement writing and retrieving hash table entries under the limitation of bus transmission characteristics.

[0230] In one embodiment, the disk array controller is connected to a non-volatile memory, and the method may further include:

[0231] When the disk array controller experiences an abnormal power failure, the hash table is written to the non-volatile memory;

[0232] When power is cycled, the hash table is retrieved from the non-volatile memory.

[0233] In this application, when a RAID controller experiences an abnormal power outage, the hash table and cache data managed by the RAID cache are written to non-volatile memory via a backup capacitor for data protection. When the system powers back on, the hash table information and cache data in the external non-volatile memory are written to the RAID controller. This implementation achieves data protection.

[0234] In one embodiment, responding to the host's input and output commands according to the new hash table may include:

[0235] Determine the hash address corresponding to the input and output commands according to a preset hash algorithm;

[0236] Read the entry corresponding to the hash address from the new hash table;

[0237] Execute the cache search operation based on the state data of the table entry corresponding to the hash address;

[0238] When the status data in the table entry corresponding to the hash address indicates that the disk data is in the cache, it is determined that the result of the search operation is that the data corresponding to the input / output command is in the cache;

[0239] When the input / output command is a read command, the data corresponding to the read command is read from the cache and the execution result of the input / output command is generated;

[0240] Feedback the execution results of input and output commands to the host.

[0241] The hash address is the hash value obtained by hashing the input and output commands. The table entry is retrieved from the storage location specified by the hash value. The state data in the retrieved table entry is parsed, and based on the parsing result, a cache search operation is performed.

[0242] When the status data in the obtained table entry indicates that the disk data is in the cache, it is determined that the result of the search operation is that the data corresponding to the input / output command is hit in the cache.

[0243] Furthermore, the above table entry may also include pageIndex, which indicates the starting address of the dev_lba data stored in the Cache. The above data corresponding to the read command read from the Cache may include:

[0244] Writes the input at the space specified by pageIndex back to the host.

[0245] In one embodiment, the above method may further include:

[0246] When the input / output command is a write command, the data corresponding to the write command is written into the cache, and the corresponding execution result is generated and fed back to the host;

[0247] When the input / output command is a disk write command, the data corresponding to the disk write command is written back to the disk, and the corresponding execution result is generated and fed back to the host.

[0248] Specifically, the RAID Controller writes the data of the host write command to the space specified by pageIndex based on the search result.

[0249] Specifically, the RAID Controller writes the data in the space specified by pageIndex back to the disk based on the search result.

[0250] In one embodiment, before writing the data corresponding to the write command into the cache, the method further includes:

[0251] Set the write cache lock value in the entry corresponding to the hash address to valid;

[0252] After writing the data corresponding to the write command into the cache, the method further includes:

[0253] The write cache lock value in the entry corresponding to the hash address is set to invalid.

[0254] In this application, before writing the cache, the value of the write cache lock status information bit in the corresponding table entry needs to be set to valid to lock the write cache operation. After the write cache operation is executed, the value of the write cache lock status information bit is set to invalid to unlock the write cache operation, thereby updating the hash table.

[0255] In one embodiment, the process of reading the Hash table in this application is as follows: Figure 3 As shown. Figure 3 In the Hash table reading process, the following steps can be performed:

[0256] S0: Preparations before reading the hash table. The hash table reconstruction unit parses the register configuration information and splits the hash table read task into k (k ≥ 1) bus read tasks. Register configuration information includes but is not limited to the hash table starting address, hash table size, and bus transmission characteristics. After completion, jump to S1.

[0257] S1: Start the bus read task. Before starting the bus read task, check whether there are any abnormal events. If so, jump to S3. Otherwise, check whether the hash table read task is complete. If so, the hash table read task ends; otherwise, jump to S2.

[0258] S2: Initiate a bus read task and write the read hash table entry into the hash table entry original cache. Based on the hash table entry original cache resource size, register configuration information, and the number of read tasks, calculate the bus access interface characteristics and initiate a bus read task. Write the read hash table entry into the hash table entry original cache. After completion, jump to S1.

[0259] S3: Clear the original cache of the hash table entries. After completion, the hash table read task ends.

[0260] In one embodiment, the process of reconstructing the Hash table entry of this application is as follows: Figure 4 As shown. Figure 4 In the process of reconstructing the hash table entry, the process may include:

[0261] S0: Start the hash table entry refactoring task. The hash table reconstruction unit parses register configuration information and initiates the hash table reconstruction task. Register configuration information includes, but is not limited to, the hash table size and exception event handling mode. Before starting the hash table reconstruction task, it checks whether the hash table reconstruction is complete. If so, the hash table reconstruction task ends. Otherwise, it checks whether the hash table entry's original cache contains the hash table entry. If so, it jumps to S1. Otherwise, it waits in S0.

[0262] S1: Read and parse the hash entry from the original cache. When parsing the hash entry, the process analyzes the V, D_L, R_L, W_L, and M state information in the hash entry. If the hash entry is in a normal state, the process jumps to S2. Otherwise, based on the register configuration information (Exception Handling Mode), if the configuration is "Execute as Normal State," the process jumps to S2; otherwise, the process jumps to S3.

[0263] S2: Reconstruct the hash table entries. After reconstruction, write the hash table entries to reconstruct the cache. Reconstruct the hash table entries according to Table 2. After reconstruction, reconstruct the cache resource size based on the hash table entries, write the hash table entries to reconstruct the cache. After completion, jump to S0.

[0264] S3: Generate an exception event. After the hash table reconstruction task is completed, the exception event is reported. According to the register configuration information: Exception event handling mode, if it is configured as "Execute according to abnormal state", an exception event is generated. After the hash table read task and the hash table write task are completed, the hash table reconstruction task is completed and the exception event is reported.

[0265] In one embodiment, the process of writing the Hash table in this application is as follows: Figure 5 As shown. Figure 5 In the Hash table writing process, the following steps can be included:

[0266] S0: Preparations before reading the hash table. The hash table reconstruction unit parses the register configuration information and splits the hash table write task into n (n ≥ 1) bus write tasks. Register configuration information includes but is not limited to the hash table starting address, hash table size, hash table entry size, and bus transmission characteristics. After completion, jump to S1.

[0267] S1: Start the bus write task. Before starting the bus write task, check whether there are any abnormal events. If so, jump to S3; otherwise, check whether the hash table write task is completed. If so, the hash table write task ends. Otherwise, jump to S2.

[0268] S2: Initiate a bus write task, read the hash table entry, reconstruct the cache hash entry, and write it into the hash table. Based on the hash table entry, reconstruct the cache resource size, register configuration information, and the number of write tasks, calculate the interface characteristics of the bus access, and initiate a bus write task. After completion, jump to S1.

[0269] S3: Clear the hash table entries and rebuild the cache. Once completed, the hash table write task ends.

[0270] In one embodiment, Figure 6 As shown, a disk array cache hash table reconstruction system is provided. The system includes a disk array controller and a host. The disk array controller is connected to the host and includes a hash table reconstruction device, wherein:

[0271] The hash table reconstruction device is used to read the cache status data from the pre-built hash table when the disk array controller is powered on again. When the status data indicates that the cache is locked and the cache operation has not been completed, the status data is reset to reconstruct the hash table to obtain a new hash table.

[0272] The disk array controller is used to respond to input and output commands from the host according to the new hash table.

[0273] In one embodiment, the above-mentioned state data includes state data of multiple table entries, and the hash table reconstruction device includes a hash table reconstruction unit, a hash table entry original cache, a hash table entry reconstruction cache, and a register, and the hash table entry original cache, the hash table entry reconstruction cache, and the register are respectively connected to the hash table reconstruction unit, wherein,

[0274] The hash table reconstruction unit is configured to determine the number of entries to be read each time and the number of reads based on the configuration information in the register, read the status data of each entry from the hash table based on the number of entries to be read each time and the number of reads, write the status data of each entry into the hash table entry original cache, read each entry from the hash table entry original cache, reset the status data of each entry based on the status data of each entry, reconstruct a new entry, write the new entry into the hash table entry reconstruction cache, read each new entry from the hash table entry reconstruction cache, write the new entry into the hash table, and obtain a new hash table.

[0275] The above hash table entry original cache is used to store the status data of each entry read from the hash table;

[0276] The above-mentioned hash table entry reconstruction cache is used to store each new entry;

[0277] The above registers are used to store configuration information.

[0278] Specifically, the hash table entry original cache, the hash table entry reconstruction cache, and the register are respectively connected to the hash table reconstruction unit. The hash table reconstruction unit accesses the hash table and cache data through an external bus.

[0279] Please refer to Figure 7 , Figure 7 In one embodiment, a schematic diagram of the internal structure of a hash table reconstruction device. The RAIDCache hash table reconstruction device includes the following modules:

[0280] 1. Hash table reconstruction unit:

[0281] The Hash table reconstruction unit is used to read m (m≥1) Hash table entries each time according to the register file configuration information, write them into the Hash table entry original cache, read the Hash table entries from the Hash table entry original cache, rebuild new Hash table entries according to the Hash table entry status information, write the built new Hash table entries into the Hash table entry reconstruction cache, read (n≥1) Hash table entries from the Hash table entry reconstruction cache, and write them into the Hash table.

[0282] 2. Hash table entry original cache: used to save the original Hash table information read.

[0283] 3. Hash table entry reconstruction cache: used to store new hash table entries reconstructed by the hash table entry reconstruction unit.

[0284] 4. Register file:

[0285] (1) Provide the Hash table entry reconstruction unit with access to the Hash table starting address, Hash table size, and Hash table entry size information.

[0286] (2) Provide Hash table entry reconstruction unit with access to Hash table bus characteristics.

[0287] (3) Provide a mechanism for handling abnormal status of hash table entries.

[0288] The Hash conflict hardware processing device externally includes the following modules:

[0289] 1. BUS: external bus, used by the Hash table reconstruction unit to access the Hash table.

[0290] 2. Data Cache: Saves disk data maintained by RAID Cache.

[0291] In one embodiment, Figure 8 As shown, a disk array cache hash table reconstruction device is provided. The device is applied to a disk array controller, which is connected to a host and includes a cache. The device includes a reading module 11, a reconstruction module 12, and a response module 13, wherein:

[0292] The reading module 11 is used to read the cache status data from the pre-built hash table when the disk array controller is restarted after power failure;

[0293] A reconstruction module 12 is configured to reset the state data to reconstruct the hash table to obtain a new hash table when the state data indicates that the cache is locked and the cache operation is not completed;

[0294] The response module 13 is configured to respond to the input and output commands of the host according to the new hash table.

[0295] In one embodiment, the above-mentioned hash table includes multiple table entries, the above-mentioned status data includes status data corresponding to multiple table entries, and the above-mentioned reading module 11 can also obtain pre-set configuration information, the configuration information includes the size of the hash table, the size of the table entries and the bus characteristics of reading the hash table. According to the size of the hash table, the size of the table entries and the bus characteristics of reading the hash table, the number of table entries corresponding to each reading task and the total number of reading tasks are determined. The above-mentioned reading module 11 can read the cache status data from the hash table according to the number of table entries of each reading task and the total number of reading tasks.

[0296] In one embodiment, the bus characteristics of the above-mentioned read hash table include the bus bit width and the transmission length supported by the bus. The above-mentioned reading module 11 can also determine the ratio of the size of the hash table to the first product to obtain the total number of reading tasks. The first product is the product of the bus bit width and the transmission length supported by the bus in the bus characteristics of the read hash table. The ratio of the first product to the size of the table entry is determined to obtain the number of table entries corresponding to each reading task.

[0297] In one embodiment, the disk array controller includes a hash table item original cache, and the reading module 11 can also determine whether each reading task is completed. When there is an unfinished reading task, a reading task is initiated according to the number of table items in each reading task, and the status data corresponding to the read table items is written into the hash table item original cache, and the step of determining whether each reading task is completed is returned until each reading task is completed.

[0298] In one embodiment, the disk array controller includes a hash table item reconstruction cache, and the reading module 11 can also read the status data of the current item from the hash table item original cache. The reconstruction module 12 can reset the status data of the current item when the status data of the current item indicates that the cache is locked and the cache operation has not been completed, obtain a new item, write the new item into the hash table item reconstruction cache, read each new item from the hash table item reconstruction cache, write the new item into the hash table to reconstruct the hash table, and obtain a new hash table.

[0299] In one embodiment, the status data of each of the above-mentioned table entries includes multiple status information bits and the values ​​of each of the above-mentioned status information bits, the above-mentioned status information bits include the write cache operation lock and whether the disk data is in the cache, the above-mentioned cache operation includes the write cache operation, and the above-mentioned reconstruction module 12 can determine that the cache is locked when the value of the write cache operation lock is valid. When the status data in the current table entry indicates that the disk data is in the cache, the value of the write cache operation lock is valid, and the write cache has not been executed, the value of the write cache operation lock is reset to invalid to obtain a new table entry.

[0300] In one embodiment, the reconstruction module 12 can also reset the values ​​of all status information bits of the current entry to invalid to obtain a new entry when the status data in the current entry indicates that the disk data is not in the cache, the value of the write cache operation lock is valid, and the write cache has not been executed.

[0301] In one embodiment, the above-mentioned status information bit also includes a read cache operation lock, and the above-mentioned cache operation includes a read cache operation. The above-mentioned reconstruction module 12 can also determine that the cache is locked when the value of the read cache operation lock is valid. When the status data in the current table entry indicates that the disk data is in the cache, the value of the read cache operation lock is valid, and the read cache has not been executed, the value of the read cache operation lock is reset to invalid to obtain a new table entry.

[0302] In one embodiment, the above-mentioned status information bit also includes disk lock, the above-mentioned cache operation includes disk lock operation, and the above-mentioned reconstruction module 12 can also determine that the cache is locked when the value of disk lock is valid. When the status data in the current table entry indicates that the disk data is in the cache, the value of disk lock is valid, and the disk lock operation has not been completed, the value of disk lock is reset to invalid to obtain a new table entry.

[0303] In one of the embodiments, the above-mentioned configuration information also includes configuration information of the abnormal event handling mode. The above-mentioned reconstruction module 12 can also generate an abnormal event and report the abnormal event when the status data in the current table item indicates an abnormal state and the configuration information of the abnormal event handling mode is to execute according to the abnormal state. When the status data in the current table item indicates an abnormal state and the configuration information of the abnormal event handling mode is to execute according to the normal state, the values ​​of each status information bit in the current table item are reset to invalid.

[0304] In one embodiment, the reconstruction module 12 may not perform the step of resetting the state data of the current entry to obtain a new entry when the values ​​of the state information bits in the current entry are all invalid.

[0305] In one embodiment, the above-mentioned reading module 11 can also determine the total number of times the hash table is written and the number of entries written each time based on the configuration information, and judge whether the task of reading each new entry from the hash table entry reconstruction cache and writing it into the hash table is completed. When there are entries in the hash table entry reconstruction cache that have not been written into the hash table, a write task is initiated based on the number of entries written each time, and the step of judging whether the task of reading each new entry from the hash table entry reconstruction cache and writing it into the hash table is completed is returned until all the entries in the hash table entry reconstruction cache are written into the hash table.

[0306] In one embodiment, the above-mentioned configuration information also includes bus characteristics for writing the hash table, and the bus characteristics for writing the hash table include the bus bit width and the transmission length supported by the bus. The above-mentioned reading module 11 can also determine the ratio of the size of the hash table to the second product to obtain the total number of times the hash table is written. The second product is the product of the bus bit width and the transmission length supported by the bus in the bus characteristics for writing the hash table. The ratio of the second product to the size of the table entry is determined to obtain the number of table entries written each time.

[0307] In one embodiment, the disk array controller is connected to a non-volatile memory, and the reading module 11 can also write the hash table to the non-volatile memory when the disk array controller experiences an abnormal power outage, and retrieve the hash table from the non-volatile memory when the power is restored.

[0308] In one embodiment, the above-mentioned response module 13 can determine the hash address corresponding to the input and output command according to a preset hash algorithm, read the table item corresponding to the hash address from a new hash table, and perform a cache search operation according to the status data of the table item corresponding to the hash address. When the status data in the table item corresponding to the hash address indicates that the disk data is in the cache, it is determined that the result of the search operation is that the data corresponding to the input and output command is in the cache. When the input and output command is a read command, the data corresponding to the read command is read from the cache, and the execution result of the input and output command is generated, and the execution result of the input and output command is fed back to the host.

[0309] In one embodiment, the above-mentioned response module 13 can also write the data corresponding to the write command into the cache when the input / output command is a write command, and generate a corresponding execution result to feedback to the host; when the input / output command is a disk write command, the data corresponding to the disk write command is written back to the disk, and generate a corresponding execution result to feedback to the host.

[0310] In one embodiment, the above-mentioned response module 13 can also set the value of the write cache lock in the table entry corresponding to the hash address to be valid before writing the data corresponding to the write command into the cache, and set the value of the write cache lock in the table entry corresponding to the hash address to be invalid after writing the data corresponding to the write command into the cache.

[0311] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 9 As shown. The computer device includes a processor, memory, network interface and database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store data such as operating data of smart home devices. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements the hash table reconstruction method.

[0312] In one embodiment, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the following steps are implemented: when a disk array controller is restarted after power failure, cache status data is read from a pre-built hash table; when the status data indicates that the cache is locked and cache operations have not been completed, the status data is reset to reconstruct the hash table to obtain a new hash table; and input and output commands from a host are responded to according to the new hash table.

[0313] In one embodiment, the hash table includes multiple entries, the state data includes state data corresponding to the multiple entries, and the processor further implements the following steps when executing the computer program:

[0314] Obtaining pre-set configuration information, including the size of the hash table, the size of the table entries, and bus characteristics for reading the hash table;

[0315] Determine the number of entries corresponding to each read task and the total number of read tasks based on the size of the hash table, the size of the table entries, and the bus characteristics of the hash table read;

[0316] When the processor executes the computer program to implement the above-mentioned step of reading the cache status data from the pre-built hash table, the following steps are specifically implemented:

[0317] The cache status data is read from the hash table based on the number of entries in each read task and the total number of read tasks.

[0318] In one embodiment, the bus characteristics for reading the hash table include the bus width and the transmission length supported by the bus. When the processor executes the computer program to implement the above-mentioned step of determining the number of entries corresponding to each read task and the total number of read tasks based on the size of the hash table, the size of the entries, and the bus characteristics for reading the hash table, the following steps are specifically implemented:

[0319] Determine a ratio of the size of the hash table to a first product to obtain a total number of read tasks, where the first product is a product of a bus width and a transfer length supported by the bus in bus characteristics for reading the hash table;

[0320] The ratio of the first product to the size of the table entry is determined to obtain the number of table entries corresponding to each reading task.

[0321] In one embodiment, the disk array controller includes a hash table entry raw cache. When the processor executes a computer program to implement the above-mentioned step of reading cache status data from the hash table based on the number of entries read each time and the total number of reads, the following steps are specifically implemented:

[0322] Determine whether each reading task is completed;

[0323] When there is an unfinished read task, a read task is initiated based on the number of entries in each read task;

[0324] Write the state data corresponding to the read table entry into the hash table entry original cache;

[0325] Return to the step of determining whether each reading task is completed, until each reading task is completed.

[0326] In one embodiment, the disk array controller includes a hash table entry reconstruction cache, and the processor further implements the following steps when executing the computer program:

[0327] Read the current entry's state data from the hash table entry original cache;

[0328] When the processor executes the computer program to implement the above-mentioned step of resetting the state data to reconstruct the hash table to obtain a new hash table when the state data indicates that the cache is locked and the cache operation has not been completed, the following steps are specifically implemented:

[0329] When the status data of the current entry indicates that the cache is locked and the cache operation is not completed, the status data of the current entry is reset to obtain a new entry;

[0330] Write the new table entry into the hash table to reconstruct the cache;

[0331] Each new entry is read from the hash table entry reconstruction cache and written into the hash table to reconstruct the hash table to obtain a new hash table.

[0332] In one embodiment, the status data of each of the above-mentioned table entries includes multiple status information bits and values ​​of each status information bit, the above-mentioned status information bits include whether a write cache operation is locked and whether disk data is in the cache, the above-mentioned cache operation includes a write cache operation, and the processor executes a computer program to implement the above-mentioned step of resetting the status data of the current table entry to obtain a new table entry when the status data of the current table entry indicates that the cache is locked and the cache operation has not been completed, and specifically implements the following steps:

[0333] When the value of the write cache operation lock is valid, the cache is determined to be locked;

[0334] When the status data in the current entry indicates that the disk data is in the cache, the value of the write cache operation lock is valid, and the write cache is not completed, the value of the write cache operation lock is reset to invalid to obtain a new entry.

[0335] In one embodiment, when the processor executes the computer program, it further implements the following steps:

[0336] When the status data in the current entry indicates that the disk data is not in the cache, the value of the write cache operation lock is valid, and the write cache is not completed, the values ​​of all status information bits of the current entry are reset to invalid to obtain a new entry.

[0337] In one embodiment, the aforementioned status information bit further includes a cache read operation lock, and the aforementioned cache operation includes a cache read operation. When the processor executes the computer program, the processor further specifically implements the following steps:

[0338] When the value of the read cache operation lock is valid, the cache is determined to be locked;

[0339] When the status data in the current entry indicates that the disk data is in the cache, the value of the read cache operation lock is valid, and the read cache is not completed, the value of the read cache operation lock is reset to invalid to obtain a new entry.

[0340] In one embodiment, the aforementioned status information bit also includes disk lock, and the aforementioned cache operation includes a disk flush operation. When the processor executes the computer program, the processor further specifically implements the following steps:

[0341] When the value of disk lock is valid, the cache is locked.

[0342] When the status data in the current entry indicates that the disk data is in the cache, the disk lock value is valid, and the disk lock operation is not completed, the disk lock value is reset to invalid to obtain a new entry.

[0343] In one embodiment, the above configuration information also includes configuration information of the abnormal event handling mode. When the processor executes the computer program, the following steps are specifically implemented:

[0344] When the status data in the current entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the abnormal state, an abnormal event is generated and reported;

[0345] When the status data in the current table entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the normal state, the values ​​of each status information bit in the current table entry are reset to invalid.

[0346] In one embodiment, when the processor executes the computer program, it further implements the following steps:

[0347] When the values ​​of the status information bits in the current entry are all invalid, the step of resetting the status data of the current entry to obtain a new entry is not performed.

[0348] In one embodiment, when the processor executes the computer program to implement the above-mentioned steps of reading each new entry from the hash table entry reconstruction cache, writing it into the hash table, and obtaining a new hash table, the following steps are specifically implemented:

[0349] Determine the total number of times the hash table is written and the number of entries written each time according to the configuration information;

[0350] Determine whether the task of reading each new table entry from the hash table reconstruction cache and writing it into the hash table is completed;

[0351] When there are entries in the hash table reconstruction cache that have not been written into the hash table, a write task is initiated based on the number of entries written each time;

[0352] Return to the step of determining whether the task of reading each new table entry from the hash table entry reconstruction cache and writing it into the hash table is completed, until all the table entries in the hash table entry reconstruction cache are written into the hash table.

[0353] In one embodiment, the configuration information further includes bus characteristics for writing the hash table, and the bus characteristics for writing the hash table include the bus width and the transfer length supported by the bus. When the processor executes the computer program to implement the above-mentioned step of determining the total number of times the hash table is written and the number of entries written each time based on the configuration information, the following steps are specifically implemented:

[0354] Determine a ratio of the size of the hash table to a second product, and obtain data written into the hash table, where the second product is a product of a bus width and a transfer length supported by the bus in characteristics of a bus for writing the hash table;

[0355] The ratio of the second product to the size of the table entry is determined to obtain the number of table entries written each time.

[0356] In one embodiment, the disk array controller is connected to a non-volatile memory, and when the processor executes the computer program, the following steps are specifically implemented:

[0357] When the disk array controller experiences an abnormal power failure, the hash table is written to the non-volatile memory;

[0358] When power is cycled, the hash table is retrieved from the non-volatile memory.

[0359] In one embodiment, when the processor executes the computer program to implement the above-mentioned step of responding to the host's input and output commands according to the new hash table, the following steps are specifically implemented:

[0360] Determine the hash address corresponding to the input and output commands according to a preset hash algorithm;

[0361] Read the entry corresponding to the hash address from the new hash table;

[0362] Execute the cache search operation based on the state data of the table entry corresponding to the hash address;

[0363] When the status data in the table entry corresponding to the hash address indicates that the disk data is in the cache, it is determined that the result of the search operation is that the data corresponding to the input / output command is in the cache;

[0364] When the input / output command is a read command, the data corresponding to the read command is read from the cache and the execution result of the input / output command is generated;

[0365] Feedback the execution results of input and output commands to the host.

[0366] In one embodiment, when the processor executes the computer program, it further implements the following steps:

[0367] When the input / output command is a write command, the data corresponding to the write command is written into the cache, and the corresponding execution result is generated and fed back to the host;

[0368] When the input / output command is a disk write command, the data corresponding to the disk write command is written back to the disk, and the corresponding execution result is generated and fed back to the host.

[0369] In one embodiment, before the processor executes the computer program to implement the above-mentioned step of writing the data corresponding to the write command into the cache, the processor further specifically implements the following steps:

[0370] Set the write cache lock value in the entry corresponding to the hash address to valid;

[0371] After writing the data corresponding to the write command into the cache, the method further includes:

[0372] The write cache lock value in the entry corresponding to the hash address is set to invalid.

[0373] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the following steps are implemented: when a disk array controller is restarted after power failure, cache status data is read from a pre-built hash table; when the status data indicates that the cache is locked and the cache operation has not been completed, the status data is reset to reconstruct the hash table to obtain a new hash table; and input and output commands of the host are responded to according to the new hash table.

[0374] In one embodiment, the hash table includes multiple entries, the state data includes state data corresponding to the multiple entries, and when the computer program is executed by the processor, the following steps are specifically implemented:

[0375] Obtaining pre-set configuration information, including the size of the hash table, the size of the table entries, and bus characteristics for reading the hash table;

[0376] Determine the number of entries corresponding to each read task and the total number of read tasks based on the size of the hash table, the size of the table entries, and the bus characteristics of the hash table read;

[0377] When the computer program is executed by the processor to implement the above-mentioned step of reading the cache status data from the pre-built hash table, the following steps are specifically implemented:

[0378] The cache status data is read from the hash table based on the number of entries in each read task and the total number of read tasks.

[0379] In one embodiment, the bus characteristics for reading the hash table include the bus width and the transmission length supported by the bus. When the computer program is executed by the processor to implement the above-mentioned step of determining the number of entries corresponding to each read task and the total number of read tasks based on the size of the hash table, the size of the table entries, and the bus characteristics for reading the hash table, the following steps are specifically implemented:

[0380] Determine a ratio of the size of the hash table to a first product to obtain a total number of read tasks, where the first product is a product of a bus width and a transfer length supported by the bus in bus characteristics for reading the hash table;

[0381] The ratio of the first product to the size of the table entry is determined to obtain the number of table entries corresponding to each reading task.

[0382] In one embodiment, the disk array controller includes a hash table entry raw cache. When the computer program is executed by a processor to implement the above-mentioned step of reading cache status data from the hash table based on the number of entries read each time and the total number of reads, the computer program specifically implements the following steps:

[0383] Determine whether each reading task is completed;

[0384] When there is an unfinished read task, a read task is initiated based on the number of entries in each read task;

[0385] Write the state data corresponding to the read table entry into the hash table entry original cache;

[0386] Return to the step of determining whether each reading task is completed, until each reading task is completed.

[0387] In one embodiment, the disk array controller includes a hash table entry reconstruction cache, and when the computer program is executed by a processor, the computer program further implements the following steps:

[0388] Read the current entry's state data from the hash table entry original cache;

[0389] When the computer program is executed by the processor to implement the above-mentioned step of resetting the state data to reconstruct the hash table to obtain a new hash table when the state data indicates that the cache is locked and the cache operation has not been completed, the computer program specifically implements the following steps:

[0390] When the status data of the current entry indicates that the cache is locked and the cache operation is not completed, the status data of the current entry is reset to obtain a new entry;

[0391] Write the new table entry into the hash table to reconstruct the cache;

[0392] Each new entry is read from the hash table entry reconstruction cache and written into the hash table to reconstruct the hash table to obtain a new hash table.

[0393] In one embodiment, the status data of each of the above-mentioned table entries includes multiple status information bits and values ​​of each status information bit, the above-mentioned status information bits include whether a write cache operation is locked and whether disk data is in the cache, the above-mentioned cache operation includes a write cache operation, and the computer program is executed by the processor to implement the above-mentioned step of resetting the status data of the current table entry to obtain a new table entry when the status data of the current table entry indicates that the cache is locked and the cache operation is not completed, and specifically implementing the following steps:

[0394] When the value of the write cache operation lock is valid, the cache is determined to be locked;

[0395] When the status data in the current entry indicates that the disk data is in the cache, the value of the write cache operation lock is valid, and the write cache is not completed, the value of the write cache operation lock is reset to invalid to obtain a new entry.

[0396] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0397] When the status data in the current entry indicates that the disk data is not in the cache, the value of the write cache operation lock is valid, and the write cache is not completed, the values ​​of all status information bits of the current entry are reset to invalid to obtain a new entry.

[0398] In one embodiment, the aforementioned status information bit further includes a cache read operation lock, and the aforementioned cache operation includes a cache read operation. When the computer program is executed by the processor, the following steps are specifically implemented:

[0399] When the value of the read cache operation lock is valid, the cache is determined to be locked;

[0400] When the status data in the current entry indicates that the disk data is in the cache, the value of the read cache operation lock is valid, and the read cache is not completed, the value of the read cache operation lock is reset to invalid to obtain a new entry.

[0401] In one embodiment, the aforementioned status information bit also includes disk lock, and the aforementioned cache operation includes a disk write operation. When the computer program is executed by the processor, the following steps are specifically implemented:

[0402] When the value of disk lock is valid, the cache is locked.

[0403] When the status data in the current entry indicates that the disk data is in the cache, the disk lock value is valid, and the disk lock operation is not completed, the disk lock value is reset to invalid to obtain a new entry.

[0404] In one embodiment, the above configuration information also includes configuration information of the abnormal event handling mode. When the computer program is executed by the processor, the following steps are specifically implemented:

[0405] When the status data in the current entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the abnormal state, an abnormal event is generated and reported;

[0406] When the status data in the current table entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the normal state, the values ​​of each status information bit in the current table entry are reset to invalid.

[0407] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0408] When the values ​​of the status information bits in the current entry are all invalid, the step of resetting the status data of the current entry to obtain a new entry is not performed.

[0409] In one embodiment, when the computer program is executed by a processor to implement the above-mentioned steps of reading each new entry from the hash table entry reconstruction cache, writing it into the hash table, and obtaining a new hash table, the following steps are specifically implemented:

[0410] Determine the total number of times the hash table is written and the number of entries written each time according to the configuration information;

[0411] Determine whether the task of reading each new table entry from the hash table reconstruction cache and writing it into the hash table is completed;

[0412] When there are entries in the hash table reconstruction cache that have not been written into the hash table, a write task is initiated based on the number of entries written each time;

[0413] Return to the step of determining whether the task of reading each new table entry from the hash table entry reconstruction cache and writing it into the hash table is completed, until all the table entries in the hash table entry reconstruction cache are written into the hash table.

[0414] In one embodiment, the configuration information further includes bus characteristics for writing to the hash table, and the bus characteristics for writing to the hash table include the bus width and the transfer length supported by the bus. When the computer program is executed by the processor to implement the above-mentioned step of determining the total number of times the hash table is written and the number of entries written each time based on the configuration information, the following steps are specifically implemented:

[0415] Determine a ratio of the size of the hash table to a second product, and obtain data written into the hash table, where the second product is a product of a bus width and a transfer length supported by the bus in characteristics of a bus for writing the hash table;

[0416] The ratio of the second product to the size of the table entry is determined to obtain the number of table entries written each time.

[0417] In one embodiment, the disk array controller is connected to a non-volatile memory, and when the computer program is executed by a processor, the following steps are specifically implemented:

[0418] When the disk array controller experiences an abnormal power failure, the hash table is written to the non-volatile memory;

[0419] When power is cycled, the hash table is retrieved from the non-volatile memory.

[0420] In one embodiment, when the computer program is executed by a processor to implement the above-mentioned step of responding to the host's input and output commands according to the new hash table, the following steps are specifically implemented:

[0421] Determine the hash address corresponding to the input and output commands according to a preset hash algorithm;

[0422] Read the entry corresponding to the hash address from the new hash table;

[0423] Execute the cache search operation based on the state data of the table entry corresponding to the hash address;

[0424] When the status data in the table entry corresponding to the hash address indicates that the disk data is in the cache, it is determined that the result of the search operation is that the data corresponding to the input / output command is in the cache;

[0425] When the input / output command is a read command, the data corresponding to the read command is read from the cache and the execution result of the input / output command is generated;

[0426] Feedback the execution results of input and output commands to the host.

[0427] In one embodiment, when the computer program is executed by a processor, the following steps are further implemented:

[0428] When the input / output command is a write command, the data corresponding to the write command is written into the cache, and the corresponding execution result is generated and fed back to the host;

[0429] When the input / output command is a disk write command, the data corresponding to the disk write command is written back to the disk, and the corresponding execution result is generated and fed back to the host.

[0430] In one embodiment, before the computer program is executed by the processor to implement the above-mentioned step of writing the data corresponding to the write command into the cache, the computer program further specifically implements the following steps:

[0431] Set the write cache lock value in the entry corresponding to the hash address to valid;

[0432] After writing the data corresponding to the write command into the cache, the method further includes:

[0433] The write cache lock value in the entry corresponding to the hash address is set to invalid.

[0434] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0435] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0436] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A hash table reconstruction method, characterized in that: The method is applied to a disk array controller, the disk array controller is connected to a host, the disk array controller includes a cache, and the method includes: When the disk array controller is restarted after power failure, the cache status data is read from a pre-built hash table, the cache status data including whether the cache has been allocated and whether it has been locked. The status data includes multiple status information bits, including write cache operation lock, whether disk data is in the cache, and disk lock; When the status data indicates that the disk data is in the cache, the write cache operation lock is in a valid state, and the write cache operation is not completed, resetting the write cache operation lock to an invalid state to reconstruct the hash table to obtain a new hash table; When the state data indicates that the disk data is in the cache, the disk lock is in a valid state, and the disk lock operation is not completed, the disk lock is reset to an invalid state to reconstruct the hash table to obtain a new hash table; The host's input and output commands are responded to according to the new hash table.

2. The method according to claim 1, characterized in that The hash table includes a plurality of entries, the state data includes state data corresponding to the plurality of entries, and the method further includes: Acquire preset configuration information, wherein the configuration information includes the size of the hash table, the size of the table entry, and bus characteristics for reading the hash table; Determining the number of table entries corresponding to each read task and the total number of read tasks according to the size of the hash table, the size of the table entries, and the bus characteristics of the read hash table; The step of reading the cache status data from the pre-built hash table includes: The state data of the Cache is read from the hash table according to the number of entries of each reading task and the total number of the reading tasks.

3. The method according to claim 2, characterized in that The bus characteristics of the read hash table include a bus width and a transmission length supported by the bus. The determining, based on the size of the hash table, the size of the table items, and the bus characteristics of the read hash table, the number of table items corresponding to each read task and the total number of read tasks includes: Determine a ratio of the size of the hash table to a first product to obtain a total number of read tasks, where the first product is a product of a bus width and a transmission length supported by the bus in bus characteristics for reading the hash table; A ratio of the first product to the size of the table entry is determined to obtain the number of table entries corresponding to each reading task.

4. The method according to claim 2, characterized in that The disk array controller includes a hash table entry original cache, and reading the cache status data from the hash table according to the number of entries read each time and the total number of reads includes: Determine whether each reading task is completed; When there is an unfinished reading task, initiating a reading task according to the number of entries in each reading task; Writing the state data corresponding to the read table entry into the hash table entry original cache; Return to the step of determining whether each reading task is completed until each reading task is completed.

5. The method according to claim 4, characterized in that The disk array controller includes a hash table entry reconstruction cache, and the method further includes: Reading state data of the current entry from the hash table entry original cache; When the state data indicates that the cache is locked and the operation of the cache is not completed, resetting the state data to reconstruct the hash table to obtain a new hash table includes: When the status data of the current entry indicates that the cache is locked and the operation of the cache is not completed, the status data of the current entry is reset to obtain a new entry; Writing the new entry into the hash table entry reconstruction cache; Each of the new entries is read from the hash table entry reconstruction cache, and is written into the hash table to reconstruct the hash table, thereby obtaining the new hash table.

6. The method according to claim 5, characterized in that The method further comprises: When the status data in the current table entry indicates that the disk data is not in the cache, the value of the write cache operation lock is valid, and the write cache has not been executed, the values ​​of all status information bits of the current table entry are reset to invalid to obtain the new table entry.

7. The method according to claim 5, characterized in that The status information bit further includes a read cache operation lock, the cache operation includes a read cache operation, and the method further includes: When the value of the cache read operation lock is valid, determining that the cache is locked; When the status data in the current entry indicates that the disk data is in the cache, the value of the read cache operation lock is valid, and the read cache is not completed, the value of the read cache operation lock is reset to invalid to obtain the new entry.

8. The method according to claim 5, characterized in that The configuration information also includes configuration information of an abnormal event handling mode, and the method further includes: When the state data in the current entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the abnormal state, an abnormal event is generated and the abnormal event is reported; When the status data in the current table entry indicates an abnormal state, and the configuration information of the abnormal event processing mode is to execute according to the normal state, the values ​​of each status information bit in the current table entry are reset to invalid.

9. The method according to claim 5, characterized in that The method further comprises: When the values ​​of the status information bits in the current entry are all invalid, the step of resetting the status data of the current entry to obtain a new entry is not performed.

10. The method according to claim 5, characterized in that The step of reading each of the new entries from the hash table entry reconstruction cache and writing the new entries into the hash table to obtain the new hash table includes: Determine the total number of times the hash table is written and the number of entries written each time according to the configuration information; Determining whether the task of reading each of the new entries from the hash table entry reconstruction cache and writing them into the hash table is completed; When there are entries in the hash table reconstruction cache that have not been written into the hash table, initiating a write task according to the number of entries written each time; Return to the step of determining whether the task of reading each of the new entries from the hash table entry reconstruction cache and writing them into the hash table is completed, until all entries in the hash table entry reconstruction cache are written into the hash table.

11. The method according to claim 10, characterized in that The configuration information also includes bus characteristics for writing the hash table, where the bus characteristics for writing the hash table include bus bit width and a transmission length supported by the bus. Determining the total number of times the hash table is written and the number of entries in each write according to the configuration information includes: Determine a ratio of the size of the hash table to a second product to obtain the total number of times the hash table is written, where the second product is a product of a bus width and a transfer length supported by the bus in bus characteristics for writing the hash table; A ratio of the second product to the size of the entry is determined to obtain the number of entries written each time.

12. The method according to claim 1, characterized in that The disk array controller is connected to a non-volatile memory, and the method further includes: When the disk array controller experiences an abnormal power failure, writing the hash table to the non-volatile memory; When power is turned on again, the hash table is retrieved from the non-volatile memory.

13. The method according to claim 2, characterized in that The responding to the input and output commands of the host according to the new hash table includes: Determine the hash address corresponding to the input and output command according to a preset hash algorithm; Reading the entry corresponding to the hash address from the new hash table; Execute the cache search operation according to the status data of the entry corresponding to the hash address; When the status data in the table entry corresponding to the hash address indicates that the disk data is in the cache, determining as a result of the search operation that the data corresponding to the input / output command is in the cache; When the input / output command is a read command, reading data corresponding to the read command from the cache, and generating an execution result of the input / output command; Feedback the execution result of the input and output command to the host.

14. The method according to claim 13, wherein: The method further comprises: When the input / output command is a write command, the data corresponding to the write command is written into the cache, and a corresponding execution result is generated and fed back to the host; When the input / output command is a write-to-disk command, the data corresponding to the write-to-disk command is written back to the disk, and a corresponding execution result is generated and fed back to the host.

15. The method according to claim 14, characterized in that Before writing the data corresponding to the write command into the cache, the method further includes: Setting the write cache lock value in the entry corresponding to the hash address to valid; After writing the data corresponding to the write command into the cache, the method further includes: The write cache lock value in the entry corresponding to the hash address is set to invalid.

16. A disk array cache hash table reconstruction device, characterized in that: The device is applied to a disk array controller, the disk array controller is connected to a host, the disk array controller includes a cache, and the device includes: a reading module, configured to read the cache status data from a pre-built hash table when the disk array controller is restarted after power failure, the cache status data including whether the cache has been allocated and whether it has been locked, the status data including a plurality of status information bits including a write cache operation lock, whether disk data is in the cache, and a disk lock; a reconstruction module, configured to, when the status data indicates that the disk data is in the cache, the write cache operation lock is in a valid state, and the write cache operation has not been completed, reset the write cache operation lock to an invalid state to reconstruct the hash table to obtain a new hash table; and, when the status data indicates that the disk data is in the cache, the write to disk lock is in a valid state, and the write to disk operation has not been completed, reset the write to disk lock to an invalid state to reconstruct the hash table to obtain a new hash table; A response module is used to respond to the input and output commands of the host according to the new hash table.

17. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 15 are implemented.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 15 are implemented.

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