Circuit gate level logic simulation method and device, computer equipment and storage medium

Abstract

This application relates to a method, apparatus, computer device, and storage medium for simulating gate-level logic. The method includes: preprocessing a logic cell library of the simulation circuit to obtain a logic extended state table; performing parallel analysis on the simulation circuit according to a preset processing algorithm to obtain a target parallel computing scheme; and performing simulation based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation result. This method enables flexible and universal parallel gate-level logic simulation, saves simulation computation costs, and accelerates the execution efficiency of parallel computing.

Description

Technical Field

[0001] This application relates to the field of circuit design automation technology, and in particular to a circuit gate-level logic simulation method, apparatus, computer device, and storage medium. Background Technology

[0002] Gate-level logic simulation is a crucial step in chip design. In this step, chip design engineers use gate-level logic models to construct circuits based on the chip's functionality and specifications. They then utilize gate-level logic simulation tools to simulate the switching of logic levels in the circuit, taking into account the functions of the logic gates, the connections between them, and the propagation delays of signals in different parts of the circuit. This simulation yields the signal changes at each location within a given timeframe, enabling functional verification and performance analysis of the constructed circuit. Gate-level logic simulation can detect errors in the circuit, guiding the optimization of its structure and parameters, thereby improving chip reliability and efficiency. Gate-level logic simulation is typically performed in the mid-to-late stages of the chip design process, providing a basis for physical design and manufacturing.

[0003] In traditional technologies, gate-level logic simulation mainly employs serial computing or limited parallel computing methods.

[0004] However, serial computing or limited parallel computing relies on the modularity of the circuit itself. When dealing with large-scale, high-speed integrated circuits with dense interconnections and asynchronous signals, it often cannot fully utilize the parallel computing capabilities of multi-core processors (such as CPUs) and many-core processors (such as GPUs), resulting in low simulation speed. Summary of the Invention

[0005] Therefore, it is necessary to provide a circuit gate-level logic simulation method, apparatus, computer equipment, computer-readable storage medium, and computer program product that can improve the simulation speed by performing parallel computation simulation on logic gates, in order to address the above-mentioned technical problems.

[0006] Firstly, this application provides a circuit gate-level logic simulation method, including:

[0007] The logic unit library of the simulation circuit is preprocessed to obtain the logic extended state table;

[0008] The simulation circuit is analyzed in parallel according to the preset processing algorithm to obtain the target parallel computing scheme.

[0009] Simulations were performed based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation results.

[0010] In one embodiment, the logic unit library of the simulation circuit is preprocessed to obtain a logic extended state table, including:

[0011] By statistically analyzing the logic gates in the simulation circuit, various types of simulation logic gates can be obtained.

[0012] The logic gates of each type are analyzed using the input variation scheme to obtain the logic extension state table.

[0013] In one embodiment, the input variation scheme is used to analyze each type of simulated logic gate to obtain a logic extension state table, including:

[0014] The inputs and outputs of each type of simulation logic gate are analyzed to obtain input variation schemes;

[0015] Simulate each type of logic gate based on the input variation scheme to obtain the input-output mapping relationship of the simulation logic gate;

[0016] The logic extended state table is determined based on the input-output mapping relationship.

[0017] In one embodiment, the simulation circuit is analyzed in parallel according to a preset processing algorithm to obtain a target parallel computing scheme, including:

[0018] Directed graphs are generated based on simulated circuits;

[0019] The directed graph is traversed using the depth-first search algorithm in the preset processing algorithm to obtain the processed directed graph.

[0020] The topological sorting algorithm in the preset processing algorithm is used to perform statistics on the processed directed graph to obtain the target parallel computing scheme.

[0021] In one embodiment, simulation is performed based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation results, including:

[0022] Simulations were performed based on the target parallel computing scheme, the input flipping timing scheme, and the logic extended state table to obtain logic simulation results; among them, the logic simulation results include the signal stabilization time.

[0023] The logic simulation results are compared with the stability threshold to obtain the target logic simulation results.

[0024] In one embodiment, simulation is performed based on the target parallel computing scheme and the input flip timing scheme to obtain logic simulation results, including:

[0025] The input flipping scheme of the current logic gate is determined based on the target parallel computing scheme and the input flipping timing scheme.

[0026] Based on the input flipping scheme and logic extension state table, the logic simulation results are obtained.

[0027] In one embodiment, analysis is performed based on the input flipping scheme and the logic extended state table to obtain logic simulation results, including:

[0028] The input comparison result is obtained by comparing the value of the input signal after the flip in the input flip scheme with the value of the input signal in the logic extended state table.

[0029] When the input comparison result shows that the input signal has a flipped value in the logic extended state table, the output signal of the current logic gate is flipped to obtain the simulation output signal;

[0030] If the input comparison result is that the value of the input signal after the flip does not exist in the logic extended state table, record the stable duration of the current output signal.

[0031] Secondly, this application also provides a circuit gate-level logic simulation device, comprising:

[0032] The preprocessing module is used to preprocess the logic unit library of the simulation circuit to obtain the logic extended state table;

[0033] The scheme planning module is used to perform parallel analysis on the simulation circuit according to the preset processing algorithm to obtain the target parallel computing scheme.

[0034] The logic simulation module is used to perform simulations based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation results.

[0035] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0036] The logic unit library of the simulation circuit is preprocessed to obtain the logic extended state table;

[0037] The simulation circuit is analyzed in parallel according to the preset processing algorithm to obtain the target parallel computing scheme.

[0038] Simulations were performed based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation results.

[0039] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0040] The logic unit library of the simulation circuit is preprocessed to obtain the logic extended state table;

[0041] The simulation circuit is analyzed in parallel according to the preset processing algorithm to obtain the target parallel computing scheme.

[0042] Simulations were performed based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation results.

[0043] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0044] The logic unit library of the simulation circuit is preprocessed to obtain the logic extended state table;

[0045] The simulation circuit is analyzed in parallel according to the preset processing algorithm to obtain the target parallel computing scheme.

[0046] Simulations were performed based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation results.

[0047] The aforementioned gate-level logic simulation method, apparatus, computer equipment, storage medium, and computer program product extract the logic gates used in the simulation circuit, classify the extracted logic gates, and then analyze each type of logic gate to obtain a logic extended state table. Based on the input-to-output decision relationship of the logic gates, the simulation circuit is analyzed to obtain the circuit, and then the output direction of the circuit is statistically analyzed in combination with a preset processing algorithm to obtain the target parallel computing scheme. The signal flip timing scheme of each logic gate is preset, and each logic gate is simulated based on the target parallel computing scheme and the obtained logic extended state table to obtain the output flip timing result. Based on the output flip timing result, the target logic simulation result is obtained. This method can decouple the causal relationship caused by the circuit topology and feedback loop in the gate-level logic simulation process, realize flexible and universal parallel gate-level logic simulation, save simulation calculation costs, and accelerate the execution efficiency of parallel computing. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 This is a flowchart illustrating a circuit gate-level logic simulation method in one embodiment;

[0050] Figure 2(a) is a schematic diagram of the logic gate structure in one embodiment;

[0051] Figure 2(b) is a partial schematic diagram of the state table corresponding to the logic gate in one embodiment;

[0052] Figure 2(c) is a partial schematic diagram of the logical extended state table in one embodiment;

[0053] Figure 3(a) is a schematic diagram of the simulation circuit in one embodiment;

[0054] Figure 3(b) is a schematic diagram of the directed graph corresponding to the simulation circuit in one embodiment;

[0055] Figure 4(a) is a schematic diagram of the logic gate to be computed in one embodiment;

[0056] Figure 4(b) is a schematic diagram of the logic extended state table corresponding to the logic gate to be calculated in one embodiment;

[0057] Figure 4(c) is a schematic diagram of the signal flipping situation in one embodiment;

[0058] Figure 5 This is a block diagram of a circuit gate-level logic simulation device in one embodiment;

[0059] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0061] In one embodiment, such as Figure 1 As shown, a gate-level logic simulation method is provided. This embodiment illustrates the method by applying it to a terminal. It is understood that this method can also be applied to a server, and to a system including both a terminal and a server, and implemented through interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0062] Step 102: Preprocess the logic unit library of the simulation circuit to obtain the logic extended state table.

[0063] The logic unit library includes all types of logic gates used in simulation circuits.

[0064] For example, statistics are performed on logic gates in the simulation circuit to obtain all types of logic gates. Then, the input and output of each type of logic gate are analyzed to obtain a state table for each type of logic gate. Subsequently, based on the state table of the logic gate, the analog operation of changing the input signal is performed to determine the associated input and output relationships, that is, to determine the sensitivity dependency between the input and output of each type of logic gate. Based on the sensitivity dependency of the input and output of each type of logic gate, the logic extended state table is calculated.

[0065] Step 104: Perform parallel analysis on the simulation circuit according to the preset processing algorithm to obtain the target parallel computing scheme.

[0066] The preset processing algorithms include depth-first search algorithm and topology sorting algorithm.

[0067] For example, the simulation circuit is transformed to obtain a directed graph. The pins of the components in the circuit are used as nodes, and the directed graph is constructed through the connections between nodes and signal transmission. The directed graph is processed using a depth-first search algorithm from the preset processing algorithm: starting from each node in the directed graph, the algorithm traverses all other nodes pointed to by the current node through directed edges, recording the visited nodes; simultaneously, for each directed edge from the current node pointing to a previously visited node, the directed edge is marked as "disconnected". After traversal, a directed acyclic graph (DAG) is obtained. Then, the topology sorting algorithm from the preset processing algorithm is used to analyze the DAG to obtain the target parallel computing scheme.

[0068] Step 106: Perform simulation based on the target parallel computing scheme and logic extended state table to obtain the target logic simulation results.

[0069] For example, each logic gate is simulated sequentially according to the obtained target parallel computing scheme. The output is obtained by changing the input signal, and the output result is compared with the logic extended state table to obtain the target logic simulation result.

[0070] In the aforementioned gate-level logic simulation method, the logic gates used in the simulation circuit are extracted and classified. Then, an extended state table is obtained by analyzing each type of logic gate. Based on the input-to-output decision relationship of the logic gates, the simulation circuit is analyzed to obtain the circuit. A preset processing algorithm is then used to statistically analyze the output direction of the circuit, thereby obtaining the target parallel computing scheme. The signal flipping timing scheme for each logic gate is pre-set, and each logic gate is simulated based on the target parallel computing scheme and the obtained extended state table, thus obtaining the output flipping timing result. The target logic simulation result is obtained by analyzing the output flipping timing result. This method can decouple the causal relationships caused by circuit topology and feedback loops during gate-level logic simulation, achieving flexible and universal parallel gate-level logic simulation, saving simulation computation costs, and accelerating the execution efficiency of parallel computing.

[0071] In one exemplary embodiment, the logic unit library of the simulation circuit is preprocessed to obtain a logic extended state table, including:

[0072] The logic gates in the simulation circuit are statistically analyzed to obtain various types of simulation logic gates; the logic extended state table is obtained by analyzing each type of simulation logic gate using input variation schemes.

[0073] For example, after counting all logic gates in the simulation circuit, all logic gates are classified to obtain various types of simulation logic gates. Then, input combinations are set for the input signals of each type of logic gate, and the input signals are changed based on the input combinations to determine the sensitivity dependency between the change in the output signal and the input signal. Based on this sensitivity dependency, the logic extended state table is calculated.

[0074] In this embodiment, by analyzing various types of simulated logic gates in the simulation circuit, the state table of the logic gate is obtained. Then, input combinations are set, and the sensitivity dependency between input and output is obtained by combining the state table and input combinations. In turn, the logic extended state table of the simulated logic gate is calculated, which can achieve the effect of accelerating the efficiency of parallel computing simulation and saving computing costs.

[0075] In an exemplary embodiment, the input variation scheme is used to analyze each type of simulation logic gate to obtain a logic extended state table, including:

[0076] The inputs and outputs of each type of simulated logic gate are analyzed to obtain input variation schemes; each type of simulated logic gate is simulated based on the input variation schemes to obtain the input-output mapping relationship of the simulated logic gate; and the logic extension state table is determined based on the input-output mapping relationship.

[0077] Among them, the input variation scheme refers to the variation scheme of the input signal in each input combination, and the input-output mapping relationship refers to the sensitivity dependence relationship between the input and the output.

[0078] For example, after analyzing the simulated logic gates in the simulated circuit, the input signal is modified based on the input variation scheme to obtain the output result. Then, the sensitivity dependency between the input and output is obtained by analyzing the input combinations and their corresponding output results. Simultaneously, a specific input signal can be determined to produce a unique output signal, and the value of this specific input signal and the value of the output signal are set as a logic extended state table.

[0079] Taking a sequential logic gate as an example, as shown in Figure 2(a), this sequential logic gate is a D flip-flop. Next, the relationship between the inputs and outputs of this sequential logic gate, as well as the relationship between the current internal state and the next internal state, are listed, i.e., the state table of this sequential logic gate is enumerated. The corresponding state table of the sequential logic gate shown in Figure 2(a) is shown in Figure 2(b). Here, CLK_N, SET_B, RST_B, and D represent the four inputs of the logic gate, IQ represents the internal state of the logic gate, Q represents the output of the logic gate, and IQ' represents the next internal state of the logic gate.

[0080] Based on the four inputs of the sequential logic gate, input combinations are constructed, and then each input combination is simulated to obtain the corresponding output result. After completing the simulation of all input combinations, the input combinations and their corresponding output results are analyzed to determine the unique output result corresponding to a specific input combination, and the input combination and its corresponding unique output result are added to the logic extended state table, as shown in Figure 2(c).

[0081] In this setup, the input signals CLK_N, SET_B, RST_B, and the current internal state IQ are set to 0, 1, 1, and 0, respectively. When the value of input signal D is 0 or 1, the values ​​of output signal Q and the next internal state IQ' are both 0. Here, U represents the input signal, signifying an input that does not require a specific determination. This illustrates the ability of the D flip-flop to maintain its internal state when not triggered.

[0082] Similarly, if the input signal SET_B and the current internal state IQ are both set to 0, then the values ​​of the input signals CLK_N, RST_B, and D will not affect the output result. This demonstrates the ability of the D flip-flop to force its internal state to 1 when encountering a low-active asynchronous set signal.

[0083] In this embodiment, by analyzing the input and output signals, the input-output mapping relationship is found, and then the extended state table is calculated. This is beneficial for obtaining flexible and universal parallel gate-level logic simulation, reducing the computational difficulty of the simulation logic gate, thereby improving the efficiency of parallel simulation and saving computational costs.

[0084] In one exemplary embodiment, the simulation circuit is analyzed in parallel according to a preset processing algorithm to obtain a target parallel computing scheme, including:

[0085] A directed graph is generated based on the simulation circuit; the directed graph is traversed according to the depth-first search algorithm in the preset processing algorithm to obtain the processed directed graph; the processed directed graph is statistically analyzed according to the topology sorting algorithm in the preset processing algorithm to obtain the target parallel computing scheme.

[0086] The preset processing algorithms include depth-first search algorithm and topology sorting algorithm.

[0087] For example, component pins in the simulation circuit are designated as nodes, and directed edges in the circuit are determined based on the input-to-output relationships of the simulated logic gates. This process continues until all simulated logic gates in the simulation circuit are analyzed, resulting in a directed graph based on the simulation circuit. To avoid loops in the directed graph, a depth-first search algorithm is used to process the directed graph, resulting in a directed acyclic graph (DAG). Specifically, starting from each node in the directed graph, the system recursively traverses other nodes pointed to by the current node through directed edges in depth-first order. Visited nodes are marked to avoid repeated visits. If a directed edge from the current node points to a marked node, that edge is marked as disconnected, until a DAG is obtained.

[0088] The directed acyclic graph (DAG) is then processed using a topological sorting algorithm to obtain the target parallel computing scheme. Specifically, the in-degree of each node in the DAG is counted, and a hierarchical graph of the DAG is obtained using a topological sorting algorithm. This hierarchical graph represents the target parallel computing scheme.

[0089] Taking the simulation circuit shown in Figure 3(a) as an example, by taking the input and output pins of the components in the simulation circuit as nodes, we can obtain 6 nodes and 6 directed edges, and we can also find that there is a cycle, namely D->Q->A->O->D. By searching the simulation circuit using the depth-first search algorithm, we can determine that the directed edge represented by D->Q is marked as broken, which is represented by a dashed line, thus obtaining a directed acyclic graph, as shown in Figure 3(b). For the directed acyclic graph shown in Figure 3(b), the optimal parallel computing scheme, i.e., the target parallel computing scheme, is {Clk, B}, {Q}, {A}, {O}, {D}.

[0090] In this embodiment, the target parallel computing scheme, i.e. the optimal parallel computing scheme, is obtained by processing the simulation circuit using the depth-first search algorithm and the topology sorting algorithm in the preset processing algorithm. Based on the target parallel computing scheme, the calculation tasks of logic gates can be distributed to multiple threads for processing, thereby achieving the effect of saving computing costs and accelerating parallel computing efficiency.

[0091] In an exemplary embodiment, simulation is performed based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation results, including:

[0092] Simulations are performed based on the target parallel computing scheme, the input flipping timing scheme, and the logic extended state table to obtain logic simulation results. The logic simulation results include the signal stabilization duration. The logic simulation results are compared with the stabilization threshold to obtain the target logic simulation results.

[0093] The input flip timing scheme includes a preset flip scheme and the output timing scheme of the previous logic gate.

[0094] For example, after obtaining the target parallel computing scheme, the task of calculating the level signal toggling of logic gates is assigned to multiple threads. The input signal is toggled based on the input toggling timing scheme to obtain the modified input signal. The modified input signal is then searched in the logic extended state table to determine whether the output signal has changed, thus obtaining the logic simulation result. The signal stabilization time is then determined based on the logic simulation result until the signal stabilization time reaches a preset stabilization threshold, completing the simulation. The analysis results of the corresponding values ​​of the toggled input signal and the toggled output signal, respectively, compared with the corresponding values ​​of the output signal and the corresponding values ​​of the output signal in the logic extended state table, are used as the target logic simulation result.

[0095] In this embodiment, the input toggling timing scheme of the logic gate to be simulated is pre-set. Then, the value of the input signal after the toggling in the logic toggling timing scheme is found in the logic extended state table to determine the output result. The logic simulation result is determined based on the output result. By analyzing the sensitivity dependency between the input and output of the logic gate during the gate-level logic simulation process, that is, by finding the corresponding value of the input signal after the toggling in the logic extended state table, the duration of the level signal toggling is calculated and tracked. This achieves flexible and universal parallel gate-level logic simulation and saves the computational cost of integrated circuit gate-level logic simulation.

[0096] In an exemplary embodiment, simulation is performed based on the target parallel computing scheme and the input flip timing scheme to obtain logic simulation results, including:

[0097] The input switching scheme of the current logic gate is determined based on the target parallel computing scheme and the input switching timing scheme; the logic simulation results are obtained based on the input switching scheme and the logic extension state table.

[0098] The input flip timing scheme includes a preset flip scheme and the output timing scheme of the previous logic gate.

[0099] For example, it is determined whether the input signal of the current logic gate is the output signal of a simulated logic gate based on the target parallel computing scheme.

[0100] If the input signal of the current logic gate does not have an output signal of a simulated logic gate, the input toggling scheme of the current logic gate adopts the preset toggling scheme, that is, the preset toggling scheme is set as the current toggling scheme.

[0101] The input signal of the current logic gate has an output signal of a simulated logic gate. The preset flip scheme and the output timing scheme of the previous logic gate are integrated according to the timing sequence to obtain the integrated flip scheme, and the integrated flip scheme is set as the current flip scheme.

[0102] Based on the current flip scheme, the input signals of the current logic gate are subjected to timing flip operations in sequence. At the flip time, the corresponding values ​​of the input signals after flip are compared with the corresponding values ​​of the input signals in the logic extended state table to determine the flip status of the output signal, thereby determining the logic simulation results.

[0103] In this embodiment, the input signal of the current logic gate is determined according to the target parallel computing scheme to determine whether it is affected by other logic gates, thereby determining the input toggling scheme. Then, the value of the input signal after the toggling is found in the logic extended state table to determine the output result. Based on the output result, the logic simulation result is determined. Afterwards, the sensitivity dependency between the logic gate input and output can be analyzed, that is, the corresponding value of the input signal after the toggling is found in the logic extended state table, thereby calculating and tracking the duration of the level signal toggling. This achieves flexible and universal parallel gate-level logic simulation, saving the computational cost of integrated circuit gate-level logic simulation.

[0104] In an exemplary embodiment, analysis is performed based on the input flipping scheme and the logic extended state table to obtain logic simulation results, including:

[0105] The value of the input signal after inversion in the input inversion scheme is compared with the value of the input signal in the logic extended state table to obtain the input comparison result. When the input comparison result shows that the value of the input signal after inversion exists in the logic extended state table, the output signal of the current logic gate is inverted to obtain the simulation output signal. When the input comparison result shows that the value of the input signal after inversion does not exist in the logic extended state table, the stable duration of the current output signal is recorded.

[0106] For example, after determining the value of the input signal after the flip, the value is looked up in the logic extended state table. If the value exists, a signal flip event is performed on the output signal; otherwise, the stable duration of the current logic gate's output signal is recorded.

[0107] Taking the logic gate to be calculated shown in Figure 4(a) as an example, the logic extension state table of the logic gate to be calculated is shown in Figure 4(b), and the input signal flipping situation within a given time period is shown in Figure 4(c). Among them, the logic extension state query results corresponding to the discrete time represented by (1)~(6) in Figure 4(c) are shown in Figure 4(b). The specific simulation process is as follows:

[0108] Initial stage: Input signals A1 and A2 are at high level, input signal B is at low level, and output signal O is at low level.

[0109] First input signal toggle: Input signal A2 is pulled from high to low. At this time, the value of input signal A1 is 1, the value of input signal A2 is 0, and the value of input signal B is 0. The corresponding input signal value can be found in the logic extension state table, and then the output signal O is toggled, that is, the low level of output signal O is raised to high level.

[0110] The second input signal flip: the input signal A1 is first pulled to a low level and then raised to a high level. Since the input signals A1 and A2 are input to an AND gate, the output signal does not flip when the input signal A2 is at a low level. Then the input signal A1 enters a stable state S(A1).

[0111] The third input signal toggle: First, raise the input signal A2 to a high level. Based on the logic extended state table, it is known that a toggle operation needs to be performed on the output signal O, that is, raise the high level of the output signal O to a low level. Then, pull the input signal A2 to a low level. Based on the logic extended state table, it is known that a toggle operation needs to be performed on the output signal O, that is, raise the low level of the output signal O to a high level. After that, the input signal A2 enters the stable state S(A2).

[0112] The fourth input signal toggle: The input signal B is pulled high. Based on the extended state table, a toggle operation needs to be performed on the output signal O, that is, the high level of the output signal O is raised to a low level. Furthermore, since the input signal B is a NOR gate, it means that the output signal O will remain low while the input signal B is high.

[0113] Subsequently, when the input signal A2 is in a state event that does not require determination, the output signal O remains at a low level. Until the input signal B is pulled low, the state of the output signal B can no longer be determined based on the logic extended state table, and thus the period from discrete time (4) to discrete time (6) in Figure 4(c) is determined to be the stable duration.

[0114] The flip event propagation steps are repeated until the simulation reaches the preset calculation progress. The calculation progress is defined by the discrete time of the level signal flip. The simulation operation is completed when the stabilization period reaches the preset duration.

[0115] In this embodiment, the input signal is flipped according to the timing scheme based on a pre-set input flipping timing scheme. Then, the value of the input signal after flipping is found in the logic extended state table to determine the output result. The logic simulation result is determined based on the output result. Furthermore, the duration of the level signal flipping needs to be calculated and tracked to determine whether the simulation is completed. This achieves flexible and universal parallel gate-level logic simulation and saves the computational cost of integrated circuit gate-level logic simulation.

[0116] In one exemplary embodiment, a circuit gate-level logic simulation method is provided, the method comprising the following steps:

[0117] By statistically analyzing the logic gates in the simulation circuit, various types of simulation logic gates can be obtained.

[0118] The inputs and outputs of each type of simulation logic gate are analyzed to obtain input variation schemes.

[0119] Simulate each type of logic gate based on the input variation scheme to obtain the input-output mapping relationship of the simulation logic gate.

[0120] The logic extended state table is determined based on the input-output mapping relationship.

[0121] Directed graphs are generated based on simulated circuits.

[0122] The directed graph is traversed using the depth-first search algorithm in the preset processing algorithm to obtain the processed directed graph.

[0123] The topological sorting algorithm in the preset processing algorithm is used to perform statistics on the processed directed graph to obtain the target parallel computing scheme.

[0124] The input flipping scheme of the current logic gate is determined based on the target parallel computing scheme and the input flipping timing scheme.

[0125] The input signal value after inversion in the input inversion scheme is compared with the input signal value in the logic extended state table to obtain the input comparison result.

[0126] When the input comparison result shows that the input signal value exists in the logic extended state table after the flip, the output signal of the current logic gate is flipped to obtain the simulation output signal.

[0127] When the input comparison result indicates that the value of the input signal after the flip does not exist in the logic extended state table, the stabilization time of the current output signal is recorded. The logic simulation result includes the signal stabilization time.

[0128] The logic simulation results are compared with the stability threshold to obtain the target logic simulation results.

[0129] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0130] Based on the same inventive concept, this application also provides a circuit gate-level logic simulation device for implementing the circuit gate-level logic simulation method described above. The solution provided by this device is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more circuit gate-level logic simulation device embodiments provided below can be found in the limitations of the circuit gate-level logic simulation method described above, and will not be repeated here.

[0131] In one exemplary embodiment, such as Figure 5 As shown, a circuit gate-level logic simulation device is provided, including: a preprocessing module 502, a scheme planning module 504, and a logic simulation module 506, wherein:

[0132] The preprocessing module 502 is used to preprocess the logic unit library of the simulation circuit to obtain the logic extended state table.

[0133] The scheme planning module 504 is used to perform parallel analysis on the simulation circuit according to the preset processing algorithm to obtain the target parallel computing scheme.

[0134] The logic simulation module 506 is used to perform simulation based on the target parallel computing scheme and the logic extended state table to obtain the target logic simulation results.

[0135] In an exemplary embodiment, the preprocessing module 502 is further configured to perform statistical analysis on the logic gates in the simulation circuit to obtain various types of simulation logic gates; and to analyze each type of simulation logic gate based on the input variation scheme to obtain a logic extension state table.

[0136] In an exemplary embodiment, the preprocessing module 502 is further configured to analyze the inputs and outputs of each type of simulated logic gate to obtain an input variation scheme; simulate each type of simulated logic gate based on the input variation scheme to obtain the input-output mapping relationship of the simulated logic gate; and determine the logic extension state table based on the input-output mapping relationship.

[0137] In an exemplary embodiment, the scheme planning module 504 is further configured to generate a directed graph based on the simulation circuit; traverse the directed graph according to the depth-first search algorithm in the preset processing algorithm to obtain the processed directed graph; and perform statistics on the processed directed graph based on the topology sorting algorithm in the preset processing algorithm to obtain the target parallel computing scheme.

[0138] In an exemplary embodiment, the logic simulation module 506 is further configured to perform simulation based on the target parallel computing scheme, the input flip timing scheme, and the logic extended state table to obtain logic simulation results; wherein, the logic simulation results include the signal stabilization duration; and compare the logic simulation results with a stabilization threshold to obtain the target logic simulation results.

[0139] In an exemplary embodiment, the logic simulation module 506 is further configured to determine the input flipping scheme of the current logic gate based on the target parallel computing scheme and the input flipping timing scheme; and to analyze the input flipping scheme and the logic extended state table to obtain the logic simulation results.

[0140] In an exemplary embodiment, the logic simulation module 506 is further configured to compare the value of the flipped input signal in the input flip scheme with the value of the input signal in the logic extended state table to obtain an input comparison result; when the input comparison result indicates that the value of the flipped input signal exists in the logic extended state table, the output signal of the current logic gate is flipped to obtain a simulation output signal; when the input comparison result indicates that the value of the flipped input signal does not exist in the logic extended state table, the stable duration of the current output signal is recorded.

[0141] Each module in the aforementioned gate-level logic simulation device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0142] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operating system and computer programs stored in the non-volatile storage media. The database stores gate-level logic simulation data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a gate-level logic simulation method.

[0143] Those skilled in the art will understand that Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0144] In one embodiment, a computer device is also provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above method embodiments.

[0145] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the steps in the above method embodiments.

[0146] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0147] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0148] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0149] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0150] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method of circuit gate level logic simulation, characterized by, The method comprises: preprocessing a logic cell library of a simulation circuit to obtain a logic extension state table; wherein the logic cell library comprises all types of simulation logic gates in the simulation circuit; analyzing the input and output of each type of the simulation logic gate to obtain an input change scheme; simulating each type of the simulation logic gate based on the input change scheme to obtain an input-output mapping relationship of the simulation logic gate; and determining the logic extension state table based on the input-output mapping relationship; performing parallel analysis on the simulation circuit according to a preset processing algorithm to obtain a target parallel computing scheme; performing simulation based on the target parallel computing scheme and the logic extension state table to obtain a target logic simulation result.

2. The method of claim 1, wherein, The preprocessing of the logic cell library of the simulation circuit to obtain the logic extension state table comprises: counting the logic gates in the simulation circuit to obtain multiple types of simulation logic gates; analyzing each type of the simulation logic gate based on the input change scheme to obtain the logic extension state table.

3. The method of claim 1, wherein, The preset processing algorithm comprises a depth-first search algorithm and a topological sorting algorithm; and the parallel analysis on the simulation circuit according to the preset processing algorithm to obtain the target parallel computing scheme comprises: generating a directed graph based on the simulation circuit; performing traversal operation on the directed graph according to the depth-first search algorithm in the preset processing algorithm to obtain a processed directed graph; counting the processed directed graph based on the topological sorting algorithm in the preset processing algorithm to obtain the target parallel computing scheme.

4. The method of claim 1, wherein, The simulation based on the target parallel computing scheme and the logic extension state table to obtain the target logic simulation result comprises: performing simulation according to the target parallel computing scheme, an input flip timing scheme, and the logic extension state table to obtain a logic simulation result; wherein the logic simulation result comprises a signal stable duration, and the input flip timing scheme comprises a preset flip scheme and an output timing scheme of a previous logic gate; comparing the logic simulation result with a stable threshold to obtain the target logic simulation result.

5. The method of claim 4, wherein, The input flip timing scheme comprises a preset flip scheme and an output timing scheme of a previous logic gate. The simulation according to the target parallel computing scheme and the input flip timing scheme to obtain the logic simulation result comprises: determining an input flip scheme of a current logic gate according to the target parallel computing scheme and the input flip timing scheme; performing analysis based on the input flip scheme and the logic extension state table to obtain the logic simulation result.

6. The method of claim 5, wherein, The analysis based on the input flip scheme and the logic extension state table to obtain the logic simulation result comprises: comparing the value of the flipped input signal in the input flip scheme with the value of the input signal in the logic extension state table to obtain an input comparison result; when the input comparison result is that the value of the flipped input signal exists in the logic extension state table, flipping the output signal of the current logic gate to obtain a simulation output signal; when the input comparison result is that the value of the flipped input signal does not exist in the logic extension state table, recording the stable duration of the current output signal.

7. A circuit gate level logic simulation apparatus, characterized by, The device comprises: A preprocessing module is configured to preprocess a logic cell library of a simulation circuit to obtain a logic extension state table. The logic cell library includes all types of simulation logic gates in the simulation circuit. The input and output of each type of simulation logic gate are analyzed to obtain an input change scheme. Each type of simulation logic gate is simulated based on the input change scheme to obtain an input-output mapping relationship of the simulation logic gate. The logic extension state table is determined based on the input-output mapping relationship. A scheme planning module is configured to perform parallel analysis on the simulation circuit according to a preset processing algorithm to obtain a target parallel computing scheme. A logic simulation module is configured to perform simulation based on the target parallel computing scheme and the logic extension state table to obtain a target logic simulation result.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor executes the computer program to implement the steps of the method in any one of claims 1 to 6.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program is executed by the processor to implement the steps of the method in any one of claims 1 to 6.

Images