Automatic frequency correction circuit and method

Abstract

The present invention provides an automatic frequency correction circuit and method. The automatic frequency correction circuit comprises a first counting module, a second counting module, a counting comparison module, a high-frequency four-phase clock generating module, a high-frequency four-phase clock auxiliary judgment module, a composite judgment and optimal selection module, and a segment selection logic module. The high-frequency four-phase clock auxiliary judgment module samples and judges the lowest bit of a first counting value and the lowest bit of a second counting value under the control of four high-frequency clocks, judges the speed of a feedback frequency-dividing clock relative to the phase-locking clock, and obtains a second judgment result. Sampling and detection are performed based on the four introduced high-frequency out-of-phase clocks, thereby getting rid of the dependence of segment selection accuracy and time on the phase-locking clock frequency. Even in the application of low phase-locking frequency, the frequency difference between the phase-locking clock and the feedback frequency-dividing clock can be quickly and accurately distinguished. When applied to a phase-locked loop, the output frequency correction speed and accuracy of a phase-locked loop based on a multi-segment voltage-controlled oscillator are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loop frequency synthesis, and in particular to an automatic frequency correction circuit and method. Background Art

[0002] Phase-locked loop frequency synthesizers and clock generation circuits are widely used in analog, digital and RF chips. The phase-locked loop that combines multiple voltage-controlled oscillators (VCOs) and multi-segment voltage-controlled oscillators can achieve wide-band coverage and better spurious and phase noise performance. However, the output of the multi-segment voltage-controlled oscillator phase-locked loop inevitably requires automatic frequency correction to achieve the optimal voltage-controlled oscillator sub-segment selection for locking the frequency point to achieve optimal performance.

[0003] Due to process reasons, the frequency range covered by the voltage-controlled oscillator segment of each chip is different. In different chips, the voltage-controlled oscillator segments corresponding to the same frequency point are not necessarily the same. Therefore, there is no universal combination of frequency division value and voltage-controlled oscillator segment code that allows each chip to output the same frequency. The most effective solution is to use a dedicated automatic frequency correction module to select the voltage-controlled oscillator segment with the best performance for each chip.

[0004] The phase-locked loop is a feedback control system, in which the output frequency of the voltage-controlled oscillator is divided by a frequency divider to obtain a feedback divided clock. According to the frequency phase relationship between the phase-locked clock and the feedback divided clock, the control voltage of the voltage-controlled oscillator is adjusted, thereby adjusting the frequency of the feedback divided clock, which in turn affects the frequency phase relationship between the phase-locked clock and the feedback divided clock. After such a cyclic adjustment and feedback process, the phase-locked loop finally reaches a stable state. At this time, the phase-locked clock and the feedback divided clock have the same frequency and a relatively stable phase difference. The output frequency is equal to the phase-locked frequency multiplied by the set frequency division number of the divider, that is, the target frequency. For a multi-stage voltage-controlled oscillator phase-locked loop, in order to ensure continuous frequency coverage, there is an overlap in the frequency range between adjacent voltage-controlled oscillator segments. The frequency points in the overlapping range can be obtained by the output of multiple voltage-controlled oscillators participating in the overlap. Different voltage-controlled oscillator segments have different control voltages to achieve the same frequency output. When the control voltage is within a specific range, the voltage-controlled oscillator can achieve the best output performance. The work of the automatic frequency correction circuit is to find the voltage-controlled oscillator segment whose output frequency is closest to the target frequency under the set voltage. In other words, find the voltage-controlled oscillator segment whose feedback frequency division clock frequency is closest to the phase detection clock frequency.

[0005] The traditional automatic frequency correction algorithm uses a counting method, with the phase detection clock and the feedback frequency division clock as clock inputs, and counts them independently. The results of the two counters are compared to distinguish the speed of the two clocks. Then, the binary method is used to gradually approach the voltage-controlled oscillator segment corresponding to the target frequency point based on the comparison results. The accuracy of the comparison result depends on the number of comparison cycles. The larger the number of comparison cycles, the longer the comparison time is consumed, the more obvious the relative frequency difference between the two clocks is, and the more accurate the comparison result is.

[0006] However, in low phase-comparison frequency application scenarios, the phase-comparison clock itself has a long period, and it takes more total counting time to reflect the relative frequency difference with the counting period. Therefore, in this way, the speed of automatic frequency correction depends on the phase-comparison clock frequency. Summary of the invention

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide an automatic frequency correction technical solution for shortening the automatic frequency correction time, making the automatic frequency correction speed and accuracy not affected by the speed of the phase-locked frequency, and also for improving the recognition accuracy and speed of the frequency difference between the phase-locked clock and the feedback divided clock.

[0008] To achieve the above-mentioned purpose and other related purposes, the technical solution provided by the present invention is as follows.

[0009] An automatic frequency correction circuit, used for correcting the output frequency of a phase-locked loop based on a multi-segment voltage-controlled oscillator, comprises:

[0010] A first counting module is connected to the phase-locked loop phase-locked clock, and counts the phase-locked clock to obtain a first counting value;

[0011] A second counting module is connected to the feedback frequency-divided clock of the phase-locked loop, and counts the feedback frequency-divided clock to obtain a second count value;

[0012] a counting comparison module, connected to the first counting module and the second counting module respectively, comparing the first counting value and the second counting value, judging the speed of the feedback frequency-divided clock relative to the phase-detection clock, and obtaining a first judgment result;

[0013] A high-frequency four-phase clock generation module generates four high-frequency clocks with the same frequency but different phases, wherein the frequency of the high-frequency clock is higher than the frequency of the phase detection clock and the frequency of the feedback frequency division clock;

[0014] A high-frequency four-phase clock auxiliary judgment module is connected to the first counting module, the second counting module and the high-frequency four-phase clock generation module respectively, and under the control of the four high-frequency clocks, the lowest bit of the first count value and the lowest bit of the second count value are sampled and judged, and the speed of the feedback frequency-divided clock relative to the phase-detection clock is judged to obtain a second judgment result;

[0015] A composite judgment and optimal selection module is connected to the counting comparison module and the high-frequency four-phase clock auxiliary judgment module respectively, and obtains a composite judgment result according to the first judgment result and the second judgment result;

[0016] The segment selection logic module is connected to the composite judgment and optimal selection module, and uses a binary search method to find the next segment of the voltage-controlled oscillator according to the composite judgment result, until the final segment of the voltage-controlled oscillator is found.

[0017] Optionally, the second high-frequency clock lags behind the first high-frequency clock by 90°, the third high-frequency clock lags behind the second high-frequency clock by 90°, and the fourth high-frequency clock lags behind the third high-frequency clock by 90°.

[0018] Optionally, the high-frequency four-phase clock generation module includes four differential amplification units, the four differential amplification units are reversely cascaded in sequence, and the differential output end of the fourth differential amplification unit is fed back and forward cascaded to the differential input end of the first differential amplification unit.

[0019] Optionally, the phase shift contributed by the differential amplifier unit is 45°, and the first high-frequency clock is obtained at the negative differential output end of the second differential amplifier unit, the second high-frequency clock is obtained at the negative differential output end of the fourth differential amplifier unit, the third high-frequency clock is obtained at the positive differential output end of the second differential amplifier unit, and the fourth high-frequency clock is obtained at the positive differential output end of the fourth differential amplifier unit.

[0020] Optionally, the high-frequency four-phase clock auxiliary judgment module includes eight sampling units and a high-frequency counting unit.

[0021] The four sampling units are respectively connected to the first counting module and the high-frequency four-phase clock generating module, and under the one-to-one corresponding control of the four high-frequency clocks, the lowest bit of the first counting value is sampled to obtain a first sampling value and a second sampling value.

[0022] The other four sampling units are connected to the second counting module and the high-frequency four-phase clock generating module respectively, and under the one-to-one corresponding control of the four high-frequency clocks, the lowest bit of the second counting value is sampled to obtain a third sampling value and a fourth sampling value.

[0023] The high-frequency counting unit receives the first sampling value and the third sampling value, and controls the high-frequency counting unit with the first sampling value and the third sampling value as indication signals to obtain a high-frequency counting value.

[0024] Optionally, the high-frequency four-phase clock auxiliary judgment module further includes a high-frequency clock cycle level deviation calculation unit, a high-frequency clock phase level deviation correction calculation unit and two adding units.

[0025] The high-frequency clock cycle-level deviation calculation unit is connected to the high-frequency counting unit and the two sampling units, and uses the first sampling value and the third sampling value as indication signals to obtain the high-frequency counting value at the corresponding moment, and calculates the initial cycle-level phase difference and the current cycle-level phase difference between the feedback frequency-divided clock and the phase-detection clock.

[0026] The high-frequency clock phase level deviation correction calculation unit receives the second sampling value and the fourth sampling value, and calculates the initial phase deviation correction value and the current phase deviation correction value between the feedback frequency division clock and the phase detection clock according to the second sampling value and the fourth sampling value.

[0027] The first adding unit is connected to the high-frequency clock cycle level deviation calculation unit and the high-frequency clock phase level deviation correction calculation unit respectively, and calculates the initial clock phase difference between the feedback frequency division clock and the phase detection clock according to the initial cycle level phase difference and the initial phase deviation correction value.

[0028] The second adding unit is respectively connected to the high-frequency clock cycle level deviation calculation unit and the high-frequency clock phase level deviation correction calculation unit, and calculates the current clock phase difference between the feedback divided clock and the phase detection clock according to the current cycle level phase difference and the current phase deviation correction value.

[0029] Optionally, the high-frequency four-phase clock auxiliary judgment module further includes two storage units, a subtraction unit and a comparison unit.

[0030] The first storage unit is connected to the first adder, receives and stores the initial clock phase difference,

[0031] The second storage unit is connected to the second adder, receives and stores the current clock phase difference,

[0032] The subtraction unit is connected to the two storage units respectively, and calculates the difference between the current clock phase difference and the initial clock phase difference to obtain the current clock phase difference change.

[0033] The comparison unit is connected to the subtraction unit, and compares the current clock phase difference variation with a threshold value to obtain the second judgment result.

[0034] Optionally, the composite judgment and optimal selection module obtains the composite judgment result preferentially according to the second judgment result.

[0035] An automatic frequency correction method, applied to any one of the automatic frequency correction circuits described above, comprising:

[0036] Determine the initial segment of the voltage controlled oscillator using a dichotomy method;

[0037] By comparing with the high-frequency four-phase clock auxiliary judgment module, the speed of the feedback frequency-divided clock relative to the phase-detection clock is judged to obtain the second judgment result and the composite judgment result;

[0038] If the state of the composite judgment result is that a difference is judged within the preset period, then the comparison of this section is terminated and the current continuous period number when the difference is judged is recorded; if the state of the composite judgment result is that no difference is judged within the preset period, then the comparison of this section is terminated and the corresponding selected section is directly determined to be the final selected section of the voltage-controlled oscillator;

[0039] If the state of the composite judgment result is that a difference is judged within a preset period, then the best segment is updated according to the current number of continuous cycles, and the next segment of the voltage-controlled oscillator is determined by using a binary selection method according to the composite judgment result, the segment of the voltage-controlled oscillator is updated, and the above comparison and judgment steps are repeated until the state of the composite judgment result under all binary selections is that a difference is judged within a preset period, or until the state of the composite judgment result is that no difference is judged within a preset period;

[0040] If after traversing all binary selections, the states of the composite judgment results under all binary selections are judged to be different within a preset period, the best selection with the longest duration period is selected as the final selection of the voltage-controlled oscillator.

[0041] Optionally, the step of updating the best segment according to the current number of continuous cycles includes:

[0042] It is determined whether the current duration period number is greater than the previous duration period number, if so, the current segment is updated to the best segment, if not, the best segment is retained.

[0043] As described above, the automatic frequency correction circuit and method of the present invention have at least the following beneficial effects:

[0044] An automatic frequency correction circuit is designed by combining the first counting module, the second counting module, the counting comparison module, the high-frequency four-phase clock generation module, the high-frequency four-phase clock auxiliary judgment module, the composite judgment and optimal selection module, and the segment selection logic module. The high-frequency four-phase clock auxiliary judgment module samples and judges the lowest bit of the first counting value and the lowest bit of the second counting value under the control of four high-frequency clocks, judges the speed of the feedback frequency-dividing clock relative to the phase-detection clock, and obtains the second judgment result. Sampling and detection are performed based on the four high-frequency out-of-phase clocks introduced, which gets rid of the dependence of the segment selection accuracy and time on the phase-detection clock frequency. Even in the application of low phase-detection frequency, the frequency difference between the phase-detection clock and the feedback frequency-dividing clock can be quickly and accurately distinguished; the frequency of the high-frequency clock is higher than the frequency of the phase-detection clock and the frequency of the feedback frequency-dividing clock, which improves the sampling recognition accuracy. At the same time, the recognition accuracy also depends on the phase difference between the high-frequency four-phase clocks. The smaller the phase difference, the higher the accuracy, thereby effectively avoiding the timing limitations and power consumption problems faced by simply increasing the detection clock frequency, and has the advantages of accurate and efficient detection and low dependence on process. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Shown is a structural block diagram of the automatic frequency correction circuit in the present invention.

[0046] Figure 2 Shown is a structural block diagram of the high-frequency four-phase clock generation module in the present invention.

[0047] Figure 3 Shown is a structural block diagram of the high-frequency four-phase clock auxiliary judgment module of the present invention.

[0048] Figure 4 It is a timing diagram showing the deviation Φ between the phase detection clock fr and the feedback frequency division clock fv in an optional embodiment of the present invention.

[0049] Figure 5 It is a timing diagram showing the deviation Φ between the phase detection clock fr and the feedback frequency division clock fv in another optional embodiment of the present invention.

[0050] Figure 6 It shows a flow chart of comparison and judgment based on a high-frequency four-phase clock auxiliary judgment module and selection of the most preferred segment of a voltage-controlled oscillator VCO in an optional embodiment of the present invention.

[0051] Figure 7 Shown is a graph of an automatic frequency correction process using an automatic frequency correction circuit in an optional embodiment of the present invention. DETAILED DESCRIPTION

[0052] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] See also Figures 1 to 7 . It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation. The type, quantity and proportion of each component in actual implementation can be changed arbitrarily, and the component layout type may also be more complicated. The structure, proportion, size, etc. shown in the drawings attached to this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, it has no technical substantive significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effect and purpose that can be achieved by the present invention.

[0054] like Figure 1 As shown, the present invention provides an automatic frequency correction circuit for correcting the output frequency of a phase-locked loop based on a multi-stage voltage-controlled oscillator, which comprises:

[0055] A first counting module is connected to the phase-locked loop phase-locked clock fr, and counts the phase-locked clock fr to obtain a first counting value Dfr;

[0056] A second counting module is connected to the feedback frequency-divided clock fv of the phase-locked loop, and counts the feedback frequency-divided clock fv to obtain a second counting value Dfv;

[0057] The counting comparison module is connected to the first counting module and the second counting module respectively, compares the first counting value Dfr and the second counting value Dfv, determines the speed of the feedback frequency-divided clock fv relative to the phase-detection clock fr, and obtains a first determination result P1;

[0058] A high-frequency four-phase clock generation module generates four high-frequency clocks ck0-ck3 with the same frequency but different phases. The frequencies of the high-frequency clocks ck0-ck3 are higher than the frequencies of the phase detection clock fr and the feedback frequency division clock fv.

[0059] The high-frequency four-phase clock auxiliary judgment module is connected to the first counting module, the second counting module and the high-frequency four-phase clock generation module respectively, and under the control of the four high-frequency clocks ck0-ck3, the lowest bit of the first count value Dfr and the lowest bit of the second count value Dfv are sampled and judged, and the speed of the feedback frequency-divided clock fv relative to the phase-detection clock fr is judged to obtain the second judgment result P2;

[0060] The composite judgment and optimal selection module is connected to the counting comparison module and the high-frequency four-phase clock auxiliary judgment module respectively, and obtains the composite judgment result P0 according to the first judgment result P1 and the second judgment result P2;

[0061] The segment selection logic module is connected to the composite judgment and optimal selection module, and uses a binary search method to find the next segment of the voltage-controlled oscillator VCO according to the composite judgment result P0, until the final segment of the voltage-controlled oscillator VCO is found.

[0062] In detail, Figure 1 As shown, the segment selection logic module uses the binary search method to find the next segment of the voltage-controlled oscillator VCO according to the composite judgment result P0, and obtains the VCO segment code, that is, the automatic frequency correction circuit ( Figure 1 The VCO segment code is adjusted and controlled according to the comparison result between the feedback divided-frequency clock fv and the phase-detection clock fr in the phase-locked loop, thereby controlling the output frequency fvco of the multi-section voltage-controlled oscillator VCO in the phase-locked loop. The output frequency fvco of the multi-section voltage-controlled oscillator VCO is divided by the divider to generate the feedback divided-frequency clock fv.

[0063] In more detail, Figure 1 As shown, the first counting module counts the phase-detection clock fr, and the phase-detection clock fr serves as the input clock of the first counting module. Every time a rising edge of the phase-detection clock fr appears, the corresponding first counting value Dfr increases by 1; the second counting module counts the feedback frequency-divided clock fv, and the feedback frequency-divided clock fv serves as the input clock of the second counting module. Every time a rising edge of the feedback frequency-divided clock fv appears, the corresponding second counting value Dfv increases by 1.

[0064] Among them, the first counting module and the second counting module both start from zero and are started at the same time; the increment speed of the first counting value Dfr and the second counting value Dfv reflects the frequency of the two clocks. The higher the clock frequency, the faster the increment speed, and the larger the counting value reached at the same time.

[0065] In more detail, Figure 1 As shown, the counting comparison module performs a conventional counting method to compare the first counting value Dfr and the second counting value Dfv, and determines the speed of the feedback frequency-divided clock fv relative to the phase-detection clock fr to obtain a first judgment result P1.

[0066] In detail, in an optional embodiment of the present invention, the second high frequency clock ck1 lags behind the first high frequency clock ck0 by 90°, the third high frequency clock ck2 lags behind the second high frequency clock ck1 by 90°, and the fourth high frequency clock ck3 lags behind the third high frequency clock ck2 by 90°.

[0067] In detail, in an optional embodiment of the present invention, as Figure 2 As shown, the high-frequency four-phase clock generation module includes four differential amplifier units, which are reversely cascaded in sequence, and the differential output end of the previous differential amplifier unit is reversely connected to the differential input end of the next differential amplifier unit (that is, the differential output positive end of the previous differential amplifier unit is connected to the differential input negative end of the next differential amplifier unit, and the differential output negative end of the previous differential amplifier unit is connected to the differential input positive end of the next differential amplifier unit), and the differential output end of the fourth differential amplifier unit is fed back and forward cascaded to the differential input end of the first differential amplifier unit (that is, the differential output positive end of the fourth differential amplifier unit is connected to the differential input positive end of the first differential amplifier unit, and the differential output negative end of the fourth differential amplifier unit is connected to the differential input negative end of the first differential amplifier unit). In this way, the four differential amplifier units form a feedback loop to constitute a differential ring oscillator.

[0068] The positive power supply terminal of each differential amplifier unit is connected to the positive power supply VCC, and the negative power supply terminal of each differential amplifier unit is connected to the negative power supply VSS.

[0069] In more detail, Figure 2 The differential ring oscillator (i.e., high-frequency four-phase clock generation module) shown in the figure has a phase shift of 180° contributed by the four-stage differential amplifier (with a delay effect) during oscillation, i.e., the phase shift contributed by each stage of the differential amplifier unit is 180° / 4=45°, and the signal phase shift contributed by the two-stage differential amplifier unit is 90°. A high-frequency clock with a high frequency and a different phase can be obtained by taking the differential signal separated by two stages.

[0070] Specifically, the first high-frequency clock ck0 is obtained at the negative end of the differential output IP of the second differential amplifier unit, the second high-frequency clock ck1 is obtained at the negative end of the differential output QP of the fourth differential amplifier unit, the third high-frequency clock ck2 is obtained at the positive end of the differential output IN of the second differential amplifier unit, and the fourth high-frequency clock ck3 is obtained at the positive end of the differential output QN of the fourth differential amplifier unit. Taking the phase of the first high-frequency clock ck0 as the reference zero point, the phase of the first high-frequency clock ck0 is 0°, the phase of the second high-frequency clock ck1 is 90°, the phase of the third high-frequency clock ck2 is 180°, and the phase of the fourth high-frequency clock ck3 is 270°.

[0071] It can be understood that the four high-frequency clocks ck0~ck3 can also be obtained at the output end of the first differential amplifier unit and the output end of the third differential amplifier unit; at the same time, the high-frequency clocks are not limited to four, but can also be five, six, eight, etc., and the phase difference between two adjacent high-frequency clocks is not limited to 90°, but can also be 45°, 60°, etc., which can be flexibly adjusted according to the sampling judgment accuracy during frequency correction, and is not limited here.

[0072] In detail, in an optional embodiment of the present invention, as Figure 3 As shown, the high-frequency four-phase clock auxiliary judgment module includes eight sampling units and a high-frequency counting unit.

[0073] The four sampling units are connected to the first counting module and the high-frequency four-phase clock generating module respectively. Under the one-to-one correspondence control of the four high-frequency clocks ck0-ck3, the least significant bit LSB_Dfr of the first counting value Dfr is sampled to obtain the first sampling value fr_s0 and the second sampling value sample_fr.

[0074] The other four sampling units are connected to the second counting module and the high-frequency four-phase clock generation module respectively, and under the one-to-one control of the four high-frequency clocks ck0-ck3, the least significant bit LSB_Dfv of the second counting value Dfv is sampled to obtain the third sampling value fv_s0 and the fourth sampling value sample_fv.

[0075] The high frequency counting unit receives the first sampling value fr_s0 and the third sampling value fv_s0, uses the first sampling value fr_s0 and the third sampling value fv_s0 as indication signals, controls the high frequency counter inside the high frequency counting unit, and outputs the high frequency counting value Dfr&fv at the corresponding time point.

[0076] Among them, the sampling values ​​of the outputs of the first four sampling units are fr_s0, fr_s1, fr_s2 and fr_s3 respectively, and the second sampling value sample_fr is a combination of the sampling value fr_s1, the sampling value fr_s2 and the sampling value fr_s3; the sampling values ​​of the outputs of the last four sampling units are fv_s0, fv_s1, fv_s2 and fv_s3 respectively, and the fourth sampling value sample_fv is a combination of the sampling value fv_s1, the sampling value fv_s2 and the sampling value fv_s3, which will not be repeated here.

[0077] In detail, Figure 3 As shown, the high-frequency four-phase clock auxiliary judgment module also includes a high-frequency clock cycle level deviation calculation unit, a high-frequency clock phase level deviation correction calculation unit and two adding units.

[0078] The high-frequency clock cycle-level deviation calculation unit is connected to the high-frequency counting unit and the two sampling units, and uses the first sampling value fr_s0 and the third sampling value fv_s0 as indication signals to obtain the high-frequency counting value Dfr&fv at the corresponding moment, and calculates the initial cycle-level phase difference T0 and the current cycle-level phase difference T(t) between the feedback frequency-divided clock fv and the phase-detection clock fr according to the high-frequency counting value Dfr&fv.

[0079] The high-frequency clock phase level deviation correction calculation unit receives the second sampling value sample_fr and the fourth sampling value sample_fv, and calculates the initial phase deviation correction value between the feedback frequency division clock fv and the phase detection clock fr according to the second sampling value sample_fr and the fourth sampling value sample_fv. And the current phase deviation correction value

[0080] The first adding unit is connected to the high-frequency clock cycle level deviation calculation unit and the high-frequency clock phase level deviation correction calculation unit respectively, and calculates the initial cycle level phase difference T0 and the initial phase deviation correction value according to the initial cycle level phase difference T0 and the initial phase deviation correction value. The initial clock phase difference Φ0 between the feedback frequency division clock fv and the phase detection clock fr is calculated.

[0081] The second adding unit is connected to the high-frequency clock cycle level deviation calculation unit and the high-frequency clock phase level deviation correction calculation unit respectively, and calculates the current cycle level phase difference T(t) and the current phase deviation correction value according to the current cycle level phase difference T(t). The current clock phase difference Φ(t) between the feedback frequency-divided clock fv and the phase-detection clock fr is calculated.

[0082] In detail, Figure 3 As shown, the high-frequency four-phase clock auxiliary judgment module also includes two storage units, a subtraction unit and a comparison unit.

[0083] The first storage unit is connected to the first adder, receives and stores the initial clock phase difference Φ0,

[0084] The second storage unit is connected to the second adder to receive and store the current clock phase difference Φ(t).

[0085] The subtraction unit is connected to the two storage units respectively, and the difference between the current clock phase difference Φ(t) and the initial clock phase difference Φ0 is calculated to obtain the current clock phase difference change ΔΦ(t).

[0086] The comparison unit is connected to the subtraction unit, and compares the current clock phase difference variation ΔΦ(t) with the threshold value to obtain a second judgment result P2.

[0087] In more detail, Figure 3As shown, in the high-frequency four-phase clock auxiliary judgment module, two sampling units and a high-frequency counting unit are combined, and the high-frequency clock ck0 is used to identify the time difference between the change edge of the lowest bit LSB_Dfr of the first count value Dfr obtained by counting the phase-locked clock fr and the change edge of the lowest bit LSB_Dfv of the second count value Dfv obtained by counting the corresponding feedback divided-frequency clock fv. The high-frequency count value Dfr&fv represents the time difference, and this time difference is based on the clock cycle of the high-frequency clock ck0. Subsequently, the cycle-level deviation between the phase-locked clock fr and the feedback divided-frequency clock fv can be calculated based on the high-frequency count value Dfr&fv.

[0088] At the same time, in combination with the other six sampling units and the high-frequency clocks ck1, ck2 and ck3, the lowest bit LSB_Dfr of the first count value Dfr obtained by counting the phase detection clock fr and the lowest bit LSB_Dfv of the second count value Dfv obtained by counting the feedback frequency-divided clock fv are sampled respectively to obtain the second sampling value sample_fr and the fourth sampling value sample_fv. Due to the characteristics that the phases of the four-phase clocks ck0 to ck3 are arranged in sequence, the value of the second sampling value sample_fr can reflect the position where the change edge of the lowest bit LSB_Dfr of the first count value Dfr obtained by counting the phase detection clock fr is between the clock edges of the four-phase clocks ck0 to ck3, and the value of the fourth sampling value sample_fv can reflect the position where the change edge of the lowest bit LSB_Dfv of the second count value Dfv obtained by counting the feedback frequency-divided clock fv is between the clock edges of the four-phase clocks ck0 to ck3. Due to the characteristics of the phase delay of the four-phase clock ck0~ck3 being equally spaced, the sampling results will also show a specific pattern as the position of the change moment of LSB_Dfr or LSB_Dfv between the rising edges of the four-phase clock ck0~ck3 is different. According to this pattern, the position of the change moment between the rising edges of the four out-of-phase clocks ck0~ck3 can be calculated. This is equivalent to considering the four equally spaced rising edges of the high-frequency four-phase clock ck0~ck3 as four scales, and the change moment of LSB_Dfr or LSB_Dfv is placed in such a measurement system, and its measurement accuracy is one quarter of the high-frequency clock cycle.

[0089] In detail, Figure 3 As shown, when calculating the deviation between the phase detection clock fr and the feedback frequency division clock fv, the high-frequency clock cycle level deviation calculation unit calculates the cycle level deviation T between the phase detection clock fr and the feedback frequency division clock fv according to the high-frequency count value Dfr&fv, and the cycle level deviation T is based on the clock period of the high-frequency clock ck0; the high-frequency clock phase level deviation correction calculation unit calculates the phase level deviation between the feedback frequency division clock fv and the phase detection clock fr according to the second sampling value sample_fr and the fourth sampling value sample_fv. Phase level deviation Take one quarter of the clock cycle of the high-frequency clock ck0 as the unit; finally, superimpose the cycle level deviation T and the phase level deviation The deviation Φ between the phase detection clock fr and the feedback frequency division clock fv can be calculated.

[0090] In detail, in an optional embodiment of the present invention, as Figure 4 As shown, with the high-frequency clock ck0 for counting, by rounding up, the difference between the rising edge of LSB_Dfr and the rising edge of LSB_Dfv approximately spans 3 clock cycles of the high-frequency clock ck0; and then the phase level deviation is accurate to one quarter of the high-frequency clock cycle, the corresponding second sampling value sample_fr is 001, the fourth sampling value sample_fv is 001, and the phase level deviation correction value of the two is 0; thus, it can be obtained that the deviation Φ between the phase detection clock fr and the feedback frequency division clock fv is 3 clock cycles of the high-frequency clock ck0.

[0091] In detail, in an optional embodiment of the present invention, as Figure 5 As shown, with the high-frequency clock ck0 for counting, by rounding up, the difference between the rising edge of LSB_Dfr and the rising edge of LSB_Dfv approximately spans 2 clock cycles of the high-frequency clock ck0; and then the phase level deviation is accurate to one quarter of the high-frequency clock cycle, the corresponding second sampling value sample_fr is 000, the fourth sampling value sample_fv is 001, and the phase level deviation correction value of the two is -1; thus, it can be obtained that the deviation Φ between the phase detection clock fr and the feedback frequency division clock fv is (2-1 / 4) the clock cycle of the high-frequency clock ck0.

[0092] Thus, according to the value change from the second sampling value sample_fr to the fourth sampling value sample_fv, the time interval between the change edge of LSB_Dfr and the change edge of LSB_Dfv can be corrected. The correction accuracy can reach the accuracy of the phase difference between two adjacent phases in the four-phase clock, that is, one quarter of the high-frequency detection clock cycle.

[0093] In more detail, Figure 3 As shown, by setting the start flag, the initial cycle-level phase difference T0 between the feedback frequency-dividing clock fv and the phase-detection clock fr is calculated by the high-frequency clock cycle-level deviation calculation unit, and the initial phase deviation correction value between the feedback frequency-dividing clock fv and the phase-detection clock fr is calculated by the high-frequency clock phase-level deviation correction calculation unit. The initial periodic phase difference T0 and the initial phase deviation correction value are superimposed by the adding unit The initial phase difference between the feedback frequency division clock fv and the phase detection clock fr at the beginning of the comparison can be obtained (i.e., the initial clock phase difference Φ0, in units of one quarter of the high-frequency clock cycle). The same calculation is performed on each subsequent rising edge of LSB_Dfr and LSB_Dfv, and then subtracted from the initial phase difference to obtain the change in the phase difference (i.e., the current clock phase difference change ΔΦ(t)). This change comes from the accumulation of the period difference between the phase detection clock fr and the feedback frequency division clock fv, reflecting the frequency difference between the two. When the change in the phase difference exceeds the set threshold, the frequency of the phase detection clock fr and the feedback frequency division clock fv can be judged, and the second judgment result P2 can be obtained.

[0094] In more detail, Figure 1 As shown, the composite judgment and optimal selection module is connected to the counting comparison module and the high-frequency four-phase clock auxiliary judgment module respectively, and the composite judgment result P0 is obtained according to the first judgment result P1 and the second judgment result P2. That is to say, the composite judgment logic in the present invention supports the high-frequency four-phase clock auxiliary judgment of the high-frequency four-phase clock auxiliary judgment module or the traditional counting method judgment of the counting comparison module, and the composite judgment and optimal selection module preferentially supports the high-frequency four-phase clock auxiliary judgment of the high-frequency four-phase clock auxiliary judgment module. When the high-frequency four-phase clock auxiliary judgment function of the high-frequency four-phase clock auxiliary judgment module is turned off, the first count value Dfr and the second count value Dfv are directly compared by the counting comparison module to obtain the first judgment result P1, and the frequency speed of the phase detection clock fr and the feedback frequency division clock fv is judged. When the high-frequency four-phase clock auxiliary judgment function of the high-frequency four-phase clock auxiliary judgment module is turned on, the lowest bit LSB_Dfr of the first count value Dfr and the lowest bit LSB_Dfv of the second count value Dfv are introduced into the high-frequency four-phase clock auxiliary judgment module for clock speed judgment. The frequency of change of LSB_Dfr and LSB_Dfv is equal to the frequency divided by two of the input clock, thereby reducing the frequency requirement of the high-frequency detection clock. At the same time, the influence of the uncertainty of the duty cycle of the phase-locked clock fr and the feedback frequency-divided clock fv is also eliminated. The segment selection logic module searches for the next segment of the voltage-controlled oscillator VCO according to the conclusion drawn by the composite judgment (i.e., the composite judgment result P0) until the final segment of the voltage-controlled oscillator VCO is found.

[0095] In detail, Figure 6 The diagram shows the process of comparing and judging based on the high-frequency four-phase clock auxiliary judgment module and selecting the optimal segment of the voltage-controlled oscillator VCO.

[0096] In detail, Figure 6As shown, while the high-frequency four-phase clock auxiliary judgment module is working, the first counting module for counting the phase detection clock fr is also approaching the set maximum comparison cycle number. Before the first count value Dfr output by the first counting module reaches the maximum comparison cycle number, if the high-frequency four-phase clock auxiliary judgment module identifies the frequency difference between the phase detection clock fr and the feedback frequency division clock fv, the first count value Dfr at this time is recorded. This value represents the time required to identify the frequency deviation between the phase detection clock fr and the feedback frequency division clock fv. As mentioned above, the change in the phase difference between LSB_Dfr and LSB_Dfv is derived from the accumulation of the cycle difference between the phase detection clock fr and the feedback frequency division clock fv. The larger the difference between the two clock cycles, the faster the accumulation and the shorter the recognition time. The smaller the cycle difference, the slower the accumulation, the longer the recognition time, and the closer the selected segment output frequency fvco of the voltage-controlled oscillator VCO is to the target frequency. The segment value with the longest recognition time is saved as the best historical segment. When the segment selection logic module compares all possible segments in turn according to the binary search method, it will select the best historical segment as the final target segment.

[0097] Among them, after receiving the second judgment result P2 given by the high-frequency four-phase clock auxiliary judgment module, the composite judgment and optimal selection module records the count value of the current phase-locked clock fr (i.e., the first count value Dfr). In theory, the longer the time required to make a judgment, the smaller the frequency difference between the phase-locked clock fr and the feedback frequency-divided clock fv. This judgment time is reflected in the count value of the phase-locked clock fr. The longer the time to draw a judgment conclusion, the larger the count value of the phase-locked clock fr. Under the condition of a fixed control voltage, the smaller the frequency difference between the phase-locked clock fr and the feedback frequency-divided clock fv, the more it can represent the accuracy of the selected voltage-controlled oscillator VCO segment. After completing the comparison of all voltage-controlled oscillator VCO segments, if no two segments with completely consistent clock frequencies are found, the segment selection logic module will select the voltage-controlled oscillator VCO segment that has been identified with the longest difference.

[0098] That is to say: if the high-frequency four-phase clock auxiliary judgment module identifies the frequency difference between the phase-detection clock fr and the feedback frequency-divided clock fv before the count value of the phase-detection clock fr reaches the set maximum comparison cycle number (i.e., the preset cycle), then the comparison of this section is terminated and the count value of the phase-detection clock fr at this time is recorded, and the next selected section of the voltage-controlled oscillator is determined by using the binary selection method according to the composite judgment result, the selected section of the voltage-controlled oscillator is updated, and the above comparison and judgment steps are repeated until all binary selection sections are traversed or the count value of the phase-detection clock fr reaches the set maximum comparison cycle number and the high-frequency four-phase clock auxiliary judgment module still does not identify the frequency difference between the phase-detection clock fr and the feedback frequency-divided clock fv; after traversing all binary selection sections of the voltage-controlled oscillator, the high-frequency four-phase clock auxiliary judgment module still does not identify the frequency difference between the phase-detection clock fr and the feedback frequency-divided clock fv; after traversing all binary selection sections of the voltage-controlled oscillator, the high-frequency four-phase clock auxiliary judgment module Before the count value of r reaches the set maximum number of comparison cycles, if all selected segments can identify the frequency difference between the phase-locked clock fr and the feedback frequency-divided clock fv, the voltage-controlled oscillator segment whose difference has been identified the longest is selected; if the count value of the phase-locked clock fr (i.e., the first count value Dfr) reaches the set maximum number of comparison cycles, the high-frequency four-phase clock auxiliary judgment module still fails to identify the frequency difference between the phase-locked clock fr and the feedback frequency-divided clock fv, that is, the cumulative phase difference between the phase-locked clock fr and the feedback frequency-divided clock fv within the preset period is always less than the threshold (in units of one quarter of the period of the high-frequency clock ck0), then it means that the current selected segment is the best selected segment under the set maximum number of comparison cycles, and this is used as the final selected segment, and the automatic frequency correction process ends.

[0099] It should be emphasized that only the process of performing comparison and judgment through the high-frequency four-phase clock auxiliary judgment module is expanded here, and the process of performing conventional comparison and judgment through the counting comparison module can be analyzed with reference to the existing technology and will not be repeated here.

[0100] At the same time, the present invention is also based on Figure 1 and Figure 6 An automatic frequency correction method is proposed, which is applied to the above automatic frequency correction circuit, and comprises the steps of:

[0101] S1. Use the dichotomy method to determine the initial selection of the voltage controlled oscillator;

[0102] S2, using the high-frequency four-phase clock auxiliary judgment module to compare and judge whether the feedback frequency-divided clock fv is faster or slower than the phase-detection clock fr, and obtain a second judgment result P2 and a composite judgment result P0;

[0103] S3. If the state of the composite judgment result P0 is that a difference is judged within the preset period, then the comparison of this section is terminated and the current continuous period number when the difference is judged is recorded; if the state of the composite judgment result P0 is that no difference is judged within the preset period, then the comparison of this section is terminated and the corresponding selected section is directly determined to be the final selected section of the voltage-controlled oscillator;

[0104] S4. If the state of the composite judgment result P0 is that a difference is judged within a preset period, then the best segment is updated according to the current number of continuous cycles, and the next segment of the voltage-controlled oscillator is determined by using the binary selection method according to the composite judgment result P0, and the segment of the voltage-controlled oscillator is updated, and steps S2 to S3 are repeated until all binary selections are traversed and the state of the composite judgment result P0 under all binary selections is that a difference is judged within the preset period, or until the state of the composite judgment result P0 is found to be that no difference is judged within the preset period;

[0105] S5. If after traversing all binary selections, the states of the composite judgment results P0 under all binary selections are judged to be different within the preset period, then the best selection with the longest continuous period is selected as the final selection of the voltage-controlled oscillator.

[0106] Specifically, in step S4, the step of updating the best segment according to the current duration period number further includes:

[0107] Determine whether the current duration period is greater than the previous duration period. If so, update the current segment to the best segment. Otherwise, keep the best segment.

[0108] In an optional embodiment of the present invention, the technical effect of the above automatic frequency correction circuit is verified, and a curve diagram of the control voltage v_tune and the output frequency freq (ie, fvco) of the voltage controlled oscillator VCO changing with time during operation is obtained as shown in FIG. Figure 7 As shown. Figure 7 It can be seen that the curve can be divided into three stages according to the change of the control voltage v_tune: the first stage is the coding stage, which is to configure the frequency division value and other parameters; the second stage is the automatic frequency correction stage, at this time the control voltage v_tune is an open-loop fixed voltage; the third stage is the closed-loop phase-locked stage, the control voltage v_tune is switched from the open-loop fixed voltage to the closed-loop phase-locked voltage, and the final phase-locking work is completed. Among them, the automatic frequency correction process, with the assistance of the high-frequency four-phase clock auxiliary judgment module, can accurately identify the voltage-controlled oscillator segment with a small frequency deviation, and can quickly screen out the voltage-controlled oscillator segment with a large frequency deviation, thereby improving the correction speed and accuracy.

[0109] The above implementation results show that the automatic frequency correction circuit proposed by the present invention has the advantages of accuracy and high efficiency, and can be applied to multi-stage VCO clock phase-locked loop chips that need to quickly complete frequency hopping locking.

[0110] In summary, in the automatic frequency correction circuit and method provided by the present invention, the automatic frequency correction circuit is designed by combining the first counting module, the second counting module, the counting comparison module, the high-frequency four-phase clock generation module, the high-frequency four-phase clock auxiliary judgment module, the composite judgment and optimal selection module, and the segment selection logic module. The high-frequency four-phase clock auxiliary judgment module samples and judges the lowest bit of the first count value and the lowest bit of the second count value under the control of four high-frequency clocks, judges the speed of the feedback frequency division clock relative to the phase detection clock, and obtains the second judgment result. Based on the sampling detection of the four introduced high-frequency out-of-phase clocks, the swing It gets rid of the dependence of segment selection accuracy and time on the phase-locked clock frequency. Even in applications with low phase-locked frequencies, it can quickly and accurately distinguish the frequency difference between the phase-locked clock and the feedback frequency-divided clock, thereby improving the frequency correction speed and accuracy of the phase-locked loop. The frequency of the high-frequency clock is higher than that of the phase-locked clock and the feedback frequency-divided clock, thereby improving the sampling recognition accuracy. At the same time, the recognition accuracy also depends on the phase difference between the high-frequency four-phase clocks. The smaller the phase difference, the higher the accuracy. This can effectively avoid the timing limitations and power consumption problems faced by simply increasing the detection clock frequency, and has the advantages of accurate and efficient detection and low dependence on process.

[0111] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. An automatic frequency correction circuit for correcting the output frequency of a phase-locked loop based on a multi-stage voltage-controlled oscillator, characterized in that: include: A first counting module is connected to the phase-locked loop phase-locked clock, and counts the phase-locked clock to obtain a first counting value; A second counting module is connected to the feedback frequency-divided clock of the phase-locked loop, and counts the feedback frequency-divided clock to obtain a second count value; a counting comparison module, connected to the first counting module and the second counting module respectively, comparing the first counting value and the second counting value, judging the speed of the feedback frequency-divided clock relative to the phase-detection clock, and obtaining a first judgment result; A high-frequency four-phase clock generation module generates four high-frequency clocks with the same frequency but different phases, wherein the frequency of the high-frequency clock is higher than the frequency of the phase detection clock and the frequency of the feedback frequency division clock; A high-frequency four-phase clock auxiliary judgment module is connected to the first counting module, the second counting module and the high-frequency four-phase clock generation module respectively, and under the control of the four high-frequency clocks, the lowest bit of the first count value and the lowest bit of the second count value are sampled and judged, and the speed of the feedback frequency-divided clock relative to the phase-detection clock is judged to obtain a second judgment result; A composite judgment and optimal selection module is connected to the counting comparison module and the high-frequency four-phase clock auxiliary judgment module respectively, and obtains a composite judgment result according to the first judgment result and the second judgment result; The segment selection logic module is connected to the composite judgment and optimal selection module, and uses a binary search method to find the next segment of the voltage-controlled oscillator according to the composite judgment result, until the final segment of the voltage-controlled oscillator is found.

2. The automatic frequency correction circuit according to claim 1, characterized in that: The second high-frequency clock lags behind the first high-frequency clock by 90°, the third high-frequency clock lags behind the second high-frequency clock by 90°, and the fourth high-frequency clock lags behind the third high-frequency clock by 90°.

3. The automatic frequency correction circuit according to claim 2, characterized in that: The high-frequency four-phase clock generation module includes four differential amplifying units, which are reversely cascaded in sequence, and the differential output end of the fourth differential amplifying unit is fed back and forwardly cascaded to the differential input end of the first differential amplifying unit.

4. The automatic frequency correction circuit according to claim 3, characterized in that: The phase shift contributed by the differential amplifier unit is 45°, and the first high-frequency clock is obtained at the negative differential output end of the second differential amplifier unit, the second high-frequency clock is obtained at the negative differential output end of the fourth differential amplifier unit, the third high-frequency clock is obtained at the positive differential output end of the second differential amplifier unit, and the fourth high-frequency clock is obtained at the positive differential output end of the fourth differential amplifier unit.

5. The automatic frequency correction circuit according to claim 1, characterized in that: The high-frequency four-phase clock auxiliary judgment module includes eight sampling units and a high-frequency counting unit. The four sampling units are respectively connected to the first counting module and the high-frequency four-phase clock generating module, and under the one-to-one correspondence control of the four high-frequency clocks, the lowest bit of the first counting value is sampled to obtain a first sampling value and a second sampling value, wherein the four sampling units include a first sampling unit, a second sampling unit, a third sampling unit and a fourth sampling unit, the first sampling value is a sampling value of the first sampling unit, and the second sampling value is a combination of sampling values ​​of the second sampling unit, the third sampling unit and the fourth sampling unit; The other four sampling units are respectively connected to the second counting module and the high-frequency four-phase clock generating module, and under the one-to-one correspondence control of the four high-frequency clocks, the lowest bit of the second counting value is sampled to obtain a third sampling value and a fourth sampling value, wherein the other four sampling units include a fifth sampling unit, a sixth sampling unit, a seventh sampling unit and an eighth sampling unit, the third sampling value is the sampling value of the fifth sampling unit, and the fourth sampling value is a combination of the sampling values ​​of the sixth sampling unit, the seventh sampling unit and the eighth sampling unit; The high-frequency counting unit receives the first sampling value and the third sampling value, and controls the high-frequency counting unit with the first sampling value and the third sampling value as indication signals to obtain a high-frequency counting value.

6. The automatic frequency correction circuit according to claim 5, characterized in that: The high-frequency four-phase clock auxiliary judgment module also includes a high-frequency clock cycle level deviation calculation unit, a high-frequency clock phase level deviation correction calculation unit and two adding units. The high-frequency clock cycle-level deviation calculation unit is connected to the high-frequency counting unit, the first sampling unit and the fifth sampling unit, and the first sampling value and the third sampling value are used as indication signals to obtain the high-frequency counting value at the corresponding moment, and calculate the initial cycle-level phase difference and the current cycle-level phase difference between the feedback frequency-divided clock and the phase-detection clock. The high-frequency clock phase level deviation correction calculation unit receives the second sampling value and the fourth sampling value, and calculates the initial phase deviation correction value and the current phase deviation correction value between the feedback frequency division clock and the phase detection clock according to the second sampling value and the fourth sampling value. The first adding unit is connected to the high-frequency clock cycle level deviation calculation unit and the high-frequency clock phase level deviation correction calculation unit respectively, and calculates the initial clock phase difference between the feedback frequency division clock and the phase detection clock according to the initial cycle level phase difference and the initial phase deviation correction value. The second adding unit is respectively connected to the high-frequency clock cycle level deviation calculation unit and the high-frequency clock phase level deviation correction calculation unit, and calculates the current clock phase difference between the feedback divided clock and the phase detection clock according to the current cycle level phase difference and the current phase deviation correction value.

7. The automatic frequency correction circuit according to claim 6, characterized in that: The high-frequency four-phase clock auxiliary judgment module also includes two storage units, a subtraction unit and a comparison unit. The first storage unit is connected to the first adding unit, receives and stores the initial clock phase difference, The second storage unit is connected to the second adding unit, receives and stores the current clock phase difference, The subtraction unit is connected to the two storage units respectively, and calculates the difference between the current clock phase difference and the initial clock phase difference to obtain the current clock phase difference change. The comparison unit is connected to the subtraction unit, and compares the current clock phase difference variation with a threshold value to obtain the second judgment result.

8. The automatic frequency correction circuit according to claim 1, characterized in that: The composite judgment and optimal selection module obtains the composite judgment result preferentially according to the second judgment result.

9. An automatic frequency correction method, characterized in that: The automatic frequency correction circuit as claimed in any one of claims 1 to 8, comprising: Determine the initial segment of the voltage controlled oscillator using a dichotomy method; By comparing with the high-frequency four-phase clock auxiliary judgment module, the speed of the feedback frequency-divided clock relative to the phase-detection clock is judged to obtain the second judgment result and the composite judgment result; If the state of the composite judgment result is that a difference is judged within the preset period, then the comparison of this section is terminated and the current continuous period number when the difference is judged is recorded; if the state of the composite judgment result is that no difference is judged within the preset period, then the comparison of this section is terminated and the corresponding selected section is directly determined to be the final selected section of the voltage-controlled oscillator; If the state of the composite judgment result is that a difference is judged within a preset period, then the best segment is updated according to the current number of continuous cycles, and the next segment of the voltage-controlled oscillator is determined by using a binary selection method according to the composite judgment result, the segment of the voltage-controlled oscillator is updated, and the above comparison and judgment steps are repeated until the state of the composite judgment result under all binary selections is that a difference is judged within a preset period, or until the state of the composite judgment result is that no difference is judged within a preset period; If after traversing all binary selections, the states of the composite judgment results under all binary selections are judged to be different within a preset period, the best selection with the longest duration period is selected as the final selection of the voltage-controlled oscillator.

10. The automatic frequency correction method according to claim 9, characterized in that: The step of updating the best segment according to the current number of continuous cycles includes: It is determined whether the current duration period number is greater than the previous duration period number, if so, the current segment is updated to the best segment, if not, the best segment is retained.

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