Array substrate, array substrate fabrication method, and electronic paper display panel

Abstract

The present application discloses an array substrate, a method for preparing the array substrate, and an electronic paper display panel, comprising a substrate, a first signal line, a first insulating layer, a second signal line, a second insulating layer, and a pixel electrode layer, wherein the pixel electrode layer comprises a plurality of pixel electrodes, and the pixel electrodes correspond to the pixel regions one by one, and the array substrate further comprises a metal wire group and a third insulating layer, wherein the metal wire group and the third insulating layer are sequentially arranged between the second insulating layer and the pixel electrode layer; the orthographic projection of the metal wire group on the substrate is in a mesh shape, the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the second signal line on the substrate; and the orthographic projection of the metal wire group on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate. Through the above design, the parasitic capacitance between the data line and the pixel electrode, and between the scanning line and the pixel electrode is avoided, and the repair capability of the array substrate is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a method for preparing the array substrate, and an electronic paper display panel. Background Art

[0002] With the development of digital technology, more and more display devices have entered people's lives, such as electronic paper display panels. Electronic paper display panels evenly disperse charged particles in a medium solution with a certain viscosity, and use an electric field to make the charged particles move electrophoretically to display.

[0003] However, nowadays, electronic display panels require the area of ​​the pixel region to be large enough, which increases the coupling capacitance between the pixel electrode and the data line and the scan line. When the display surface is switched, the parasitic capacitance causes the movement speeds of charged particles in different areas of the same pixel region to be different, resulting in crosstalk. Therefore, how to avoid the generation of parasitic capacitance between the data line and the pixel electrode, between the scan line and the pixel electrode while ensuring that the area of ​​the pixel electrode in the pixel region is not reduced, while also improving the repair capability of the array substrate. Summary of the invention

[0004] The purpose of the present application is to provide an array substrate, a method for preparing the array substrate and an electronic paper display panel, so as to avoid parasitic capacitance between data lines and pixel electrodes, between scan lines and pixel electrodes, and to improve the repair capability of the array substrate.

[0005] The present application discloses an array substrate, comprising a substrate, and a first signal line, a first insulating layer, a second signal line, a second insulating layer and a pixel electrode layer sequentially arranged on the substrate, wherein the first signal line comprises a scan line and the second signal line comprises a data line or the first signal line comprises a data line and the second signal line comprises a scan line; the first signal line and the second signal line are arranged in a crisscross pattern to define a plurality of pixel regions, the pixel electrode layer comprises a plurality of pixel electrodes, and the plurality of pixel electrodes correspond to the plurality of pixel regions one by one, the array substrate further comprises a metal wire group and a third insulating layer, and the metal wire group and the third insulating layer are sequentially arranged between the second insulating layer and the pixel electrode layer;

[0006] The orthographic projection of the metal wire group on the substrate is in a mesh shape, the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the second signal line on the substrate;

[0007] Furthermore, an orthographic projection of the metal wire group on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate.

[0008] Optionally, the metal line group includes two metal lines, namely a first sub-metal line and a second sub-metal line, the first sub-metal line and the second sub-metal line are both located on the second insulating layer, and the first sub-metal line and the second sub-metal line are arranged in parallel between two adjacent pixel electrodes;

[0009] The orthographic projection of a portion of the first sub-metal line close to the second sub-metal line on the substrate partially overlaps with the orthographic projections of the first signal line and the second signal line on the substrate;

[0010] The orthographic projection of a portion of the first sub-metal line away from the second sub-metal line on the substrate overlaps with the orthographic projection of the pixel electrode close to the first sub-metal line in two adjacent pixel electrodes on the substrate;

[0011] The orthographic projection of a portion of the second sub-metal line close to the first sub-metal line on the substrate partially overlaps with the orthographic projections of the first signal line and the second signal line on the substrate;

[0012] The orthographic projection of a portion of the second sub-metal line away from the first sub-metal line on the substrate overlaps with the orthographic projection of the pixel electrode close to the second sub-metal line in two adjacent pixel electrodes on the substrate;

[0013] The line width of the first sub-metal line, the line width of the second sub-metal line, the line width of the first signal line and the line width of the second signal line are all equal; the spacing between the first sub-metal line and the second sub-metal line is smaller than the line width of the first signal line.

[0014] Optionally, the array substrate further includes a line group insulation layer, and the first sub-metal line, the line group insulation layer and the second sub-metal line are sequentially arranged between the second insulation layer and the third insulation layer.

[0015] Optionally, an orthographic projection of a portion of the first sub-metal line close to the second sub-metal line on the substrate overlaps with an orthographic projection of a portion of the second sub-metal line close to the first sub-metal line on the substrate.

[0016] Optionally, the metal line group includes three metal lines, namely a third sub-metal line, a fourth sub-metal line and a fifth sub-metal line, the third sub-metal line, the fourth sub-metal line and the fifth sub-metal line are all located on the second insulating layer, and the third sub-metal line, the fourth sub-metal line and the fifth sub-metal line are arranged in parallel between two adjacent pixel electrodes;

[0017] The orthographic projection of a portion of the third sub-metal line close to the fourth sub-metal line on the substrate partially overlaps with the orthographic projections of the first signal line and the second signal line on the substrate;

[0018] The orthographic projection of a portion of the third sub-metal line away from the fourth sub-metal line on the substrate overlaps with the orthographic projection of the pixel electrode close to the third sub-metal line in two adjacent pixel electrodes on the substrate;

[0019] The orthographic projection of the fourth sub-metal line on the substrate is covered by the projections of the first signal line and the second signal line on the substrate;

[0020] The orthographic projection of a portion of the fifth sub-metal line close to the fourth sub-metal line on the substrate partially overlaps with the orthographic projections of the first signal line and the second signal line on the substrate;

[0021] The orthographic projection of a portion of the fifth sub-metal line away from the fourth sub-metal line on the substrate overlaps with the orthographic projection of the pixel electrode of the two adjacent pixel electrodes close to the fifth sub-metal line on the substrate;

[0022] The line width of the third sub-metal line, the line width of the fifth sub-metal line, the line width of the first signal line and the line width of the second signal line are all equal; the spacing between the third sub-metal line and the fourth sub-metal line is smaller than the line width of the first signal line, and the spacing between the fourth sub-metal line and the fifth sub-metal line is smaller than the line width of the first signal line.

[0023] Optionally, the array substrate also includes a line group insulation layer, which is located on the side of the second insulation layer away from the substrate, the third sub-metal wire and the fifth sub-metal wire are arranged in the same layer and are both located between the second insulation layer and the line group insulation layer, and the fourth sub-metal wire is located on the side of the line group insulation layer away from the second insulation layer.

[0024] Optionally, the first signal line includes a scan line, the second signal line includes a data line, the array substrate further includes a line group insulation layer, the metal line group includes a longitudinal metal line group portion and a transverse metal line group portion, and the transverse metal line group portion, the line group insulation layer and the longitudinal metal line group portion are sequentially arranged between the second insulation layer and the third insulation layer;

[0025] The longitudinal metal line group part is arranged in parallel with the data line, and the transverse metal line group part is arranged in parallel with the scan line; the orthographic projection of the longitudinal metal line group part on the substrate covers the orthographic projection of the data line on the substrate, and the orthographic projection of the transverse metal line on the substrate covers the orthographic projection of the scan line on the substrate;

[0026] The orthographic projection of the longitudinal metal wire group portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate; the orthographic projection of the transverse metal wire group portion on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate.

[0027] Optionally, the first signal line includes a scan line, the second signal line includes a data line, and the second insulating layer is provided with a first through-groove and a second through-groove on both sides of the data line in a width direction, respectively, and the first through-groove and the second through-groove both penetrate the second insulating layer;

[0028] A third through groove and a fourth through groove are respectively provided on both sides of the second insulating layer and the first insulating layer in the width direction of the scanning line, the third through groove penetrates the second insulating layer and the first insulating layer at the same time, and the fourth through groove penetrates the second insulating layer and the first insulating layer at the same time;

[0029] The metal wire group includes a main body, a first side edge and a second side edge, wherein the first side edge and the second side edge are respectively connected to two sides of the main body in a width direction, and a distance between the first side edge and the second side edge is greater than a line width of the data line and also greater than a line width of the scan line;

[0030] At a position where the main body covers the data line, the first side edge portion and the second side edge portion are respectively located in the first through groove and the second through groove;

[0031] At a position where the main body covers the scanning line, the first side edge portion and the second side edge portion are respectively located in the third through groove and the fourth through groove.

[0032] The present application also discloses a method for preparing an array substrate, which is used to prepare the array substrate described above, comprising the steps of:

[0033] preparing a first signal line on a substrate;

[0034] preparing a first insulating layer on the first signal line;

[0035] preparing a second signal line on the first insulating layer;

[0036] preparing a second insulating layer on the second signal line;

[0037] preparing the metal wire group on the second insulating layer;

[0038] preparing the third insulating layer on the metal wire group;

[0039] Preparing the pixel electrode layer on the third insulating layer and forming a plurality of pixel electrodes;

[0040] The orthographic projection of the metal wire group on the substrate is in a mesh shape, the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the second signal line on the substrate;

[0041] Furthermore, an orthographic projection of the metal wire group on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate.

[0042] The present application also discloses an electronic paper display panel, which includes an electrophoretic layer and an array substrate. The array substrate drives the electrophoretic particles in the electrophoretic layer to move so as to display a picture.

[0043] Compared with the structure of the existing array substrate, the present application covers the data line and the scan line through a metal wire group, thereby avoiding the generation of parasitic capacitance between the data line and the pixel electrode, and avoiding the generation of parasitic capacitance between the scan line and the pixel electrode. In addition, the metal wire group also has an overlapping portion with two adjacent pixel electrodes. When one of the pixel electrodes fails to work, the pixel electrodes of the two adjacent pixel areas can be connected through the overlapping portion of the laser metal wire group and the pixel electrode, thereby repairing the pixel electrode that fails to work. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0045] Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of the present application;

[0046] Figure 2 is a schematic diagram of a plane of an array substrate according to the first embodiment of the present application;

[0047] Figure 3 is a schematic diagram of a cross section of an array substrate along a data line width direction according to the first embodiment of the present application;

[0048] Figure 4 is a schematic diagram of a cross section of an array substrate along a scan line width direction according to the first embodiment of the present application;

[0049] Figure 5 is a cross-sectional schematic diagram of a metal wire group corresponding to a data line in the first embodiment of the present application;

[0050] Figure 6 is a cross-sectional schematic diagram of a metal wire group corresponding to a scan line in the first embodiment of the present application;

[0051] Figure 7 is a schematic diagram of a metal wire group according to the first embodiment of the present application;

[0052] Figure 8 is a schematic diagram of a cross section of an array substrate along a data line width direction according to a second embodiment of the present application;

[0053] Fig. 9 is a schematic diagram of a cross section of an array substrate along a scan line width direction according to a second embodiment of the present application;

[0054] Fig.10 is a schematic diagram of different layers of a first sub-metal line and a second sub-metal line according to a second embodiment of the present application;

[0055] Fig.11 is a schematic diagram of a cross section of an array substrate along a data line width direction according to a third embodiment of the present application;

[0056] Fig.12 is a schematic diagram of a cross section of an array substrate along a scan line width direction according to a third embodiment of the present application;

[0057] Fig.13 is a schematic diagram of a third sub-metal line, a fourth sub-metal line, and a fifth sub-metal line according to a third embodiment of the present application;

[0058] Fig.14 is a schematic diagram of a preparation sequence of an array substrate according to an embodiment of the present application;

[0059] Fig.15 It is a schematic diagram of a preparation process of an array substrate according to an embodiment of the present application.

[0060] Among them, 10, electronic paper display panel; 20, electrophoretic layer; 30, array substrate; 100, substrate; 110, first signal line; 120, first insulating layer; 130, second signal line; 140, second insulating layer; 150, pixel electrode layer; 210, scan line; 220, data line; 300, metal wire group; 310, first sub-metal wire; 320, second sub-metal wire; 330, third sub-metal wire; 340, Fourth sub-metal wire; 350, fifth sub-metal wire; 360, wire group insulating layer; 371, longitudinal metal wire group portion; 372, transverse metal wire group portion; 381, main body portion; 382, ​​first side edge portion; 383, second side edge portion; 400, third insulating layer; 510, gate; 521, source; 522, drain; 610, first through groove; 620, second through groove; 630, third through groove; 640, fourth through groove. DETAILED DESCRIPTION

[0061] It should be understood that the terms used herein, the specific structures and functional details disclosed are only for describing specific embodiments and are representative, but the present application can be implemented in many alternative forms and should not be construed as being limited to only the embodiments described herein.

[0062] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating relative importance or implicitly indicating the number of technical features indicated. Therefore, unless otherwise specified, features defined as "first" and "second" may explicitly or implicitly include one or more of the features; "plurality" means two or more. The term "including" and any variation thereof means non-exclusive inclusion, and one or more other features, integers, steps, operations, units, components and / or combinations thereof may exist or be added.

[0063] In addition, terms indicating orientation or positional relationships, such as “center,” “lateral,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are described based on the orientation or relative positional relationships shown in the accompanying drawings and are merely simplified descriptions for the convenience of describing the present application. They do not indicate that the devices or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limitations on the present application.

[0064] In addition, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be internally connected between two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0065] The present application is described in detail below with reference to the accompanying drawings and optional embodiments.

[0066] Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of the present application, such as Figure 1 As shown, the present application discloses an electronic paper display panel 10 , which includes an electrophoretic layer 20 and an array substrate 30 . The array substrate 30 drives the electrophoretic particles in the electrophoretic layer 20 to move so as to display images.

[0067] The electrophoretic layer 20 may be a microcapsule or ink, which is not limited here; and the electrophoretic particles in the microcapsule may be black and white or colorful.

[0068] The present application also discloses an array substrate 30, which can be used in the electronic paper display panel 10 described above. For the array substrate 30, the present application provides the following design, which is specifically introduced through several embodiments:

[0069] Embodiment 1:

[0070] Figure 2 is a schematic diagram of a plane of an array substrate according to the first embodiment of the present application, Figure 3 is a schematic diagram of a cross section of an array substrate along the width direction of a data line according to the first embodiment of the present application, Figure 4 is a schematic diagram of a cross section of an array substrate along the width direction of a scan line according to the first embodiment of the present application, such as Figure 2-4 As shown, the present application discloses an array substrate 30, including a substrate 100, and a first signal line 110, a first insulating layer 120, a second signal line 130, a second insulating layer 140 and a pixel electrode layer arranged in sequence on the substrate 100, the first signal line 110 includes a scan line 210 and the second signal line 130 includes a data line 220 or the first signal line 110 includes a data line 220 and the second signal line 130 includes a scan line 210; the first signal line 110 and the second signal line 130 are arranged in a criss-cross manner to define a plurality of pixel areas, the pixel electrode layer includes a plurality of pixel electrodes 150, and the plurality of pixel electrodes 150 correspond one-to-one to the plurality of pixel areas.

[0071] The array substrate 30 also includes a metal wire group 300 and a third insulating layer 400, and the metal wire group 300 and the third insulating layer 400 are sequentially arranged between the second insulating layer 140 and the pixel electrode layer; the orthographic projection of the metal wire group 300 on the substrate 100 is in a mesh shape, the orthographic projection of the metal wire group 300 on the substrate 100 covers the orthographic projection of the first signal line 110 on the substrate 100, and the orthographic projection of the metal wire group 300 on the substrate 100 covers the orthographic projection of the second signal line 130 on the substrate 100; and the orthographic projection of the metal wire group 300 on the substrate 100 partially overlaps with the orthographic projection of the pixel electrode 150 on the substrate 100.

[0072] The active switch in the array substrate 30 of the present application may be a bottom gate structure or a top gate structure. When the active switch is a bottom gate structure, the first signal line 110 includes a gate 510 and a scan line 210, etc., and the second signal line 130 includes a source 521, a drain 522, and a data line 220, etc.; when the active switch is a top gate structure, the first signal line 110 includes a source 521, a drain 522, and a data line 220, etc., and the second signal line 130 includes a gate 510 and a scan line 210, etc. The present application takes the active switch as the bottom gate structure as an example for explanation.

[0073] The metal wire group 300 may have only one metal wire, or may include multiple metal wires arranged in parallel. In this embodiment, the metal wire group 300 is taken as an example of one metal wire, that is, metal wires are arranged above the data line 220 and the scan line 210 to cover them, and there is a partial overlap between the two adjacent pixel electrodes 150 on both sides in the width direction of the metal line.

[0074] Compared with the structure of the existing array substrate 30, the present application covers the data line 220 and the scan line 210 through the metal wire group 300, thereby avoiding the generation of parasitic capacitance between the data line 220 and the pixel electrode 150, and avoiding the generation of parasitic capacitance between the scan line 210 and the pixel electrode 150. In addition, the metal wire group 300 also has an overlapping portion with two adjacent pixel electrodes 150. When one of the pixel electrodes 150 fails to work, the two adjacent pixel electrodes 150 can be connected through the overlapping portion of the laser metal wire group 300 and the pixel electrode 150, thereby repairing the pixel electrode 150.

[0075] Furthermore, the orthographic projection of the metal wire group 300 on the substrate 100 also covers the orthographic projection of the active switch on the substrate 100, and can also avoid the generation of parasitic capacitance between the source 521 in the active switch and the pixel electrode 150, and avoid the generation of parasitic capacitance between the drain 522 and the pixel electrode 150. Thus, a single pixel electrode 150 occupies the entire pixel area, and there is no need to form a avoidance area above the gate 510, the source 521 and the drain 522.

[0076] Figure 5 is a cross-sectional schematic diagram of a metal wire group corresponding to a data line in the first embodiment of the present application, Figure 6 is a schematic cross-sectional view of a metal wire group corresponding to a scanning line in the first embodiment of the present application, such as Figure 5-6 As shown, in order to completely isolate the parasitic capacitance generated between the data line 220 and the pixel electrode 150 and the parasitic capacitance generated between the scan line 210 and the pixel electrode 150 , the present application further designs the metal line group 300 .

[0077] Exemplarily, the second insulating layer 140 is provided with a first through-groove 610 and a second through-groove 620 on both sides of the data line 220 in the width direction, respectively. Both the first through-groove 610 and the second through-groove 620 penetrate the second insulating layer 140 .

[0078] The second insulating layer 140 and the first insulating layer 120 are respectively provided with a third through groove 630 and a fourth through groove 640 on both sides of the width direction of the scanning line 210, and the third through groove 630 penetrates the second insulating layer 140 and the first insulating layer 120 at the same time, and the fourth through groove 640 penetrates the second insulating layer 140 and the first insulating layer 120 at the same time.

[0079] The metal wire group 300 includes a main body 381, a first side edge portion 382 and a second side edge portion 383, wherein the first side edge portion 382 and the second side edge portion 383 are respectively connected to two sides of the main body 381 in a width direction, and a spacing between the first side edge portion 382 and the second side edge portion 383 is greater than the line width of the data line 220 and also greater than the line width of the scan line 210.

[0080] And at the position where the main body 381 covers the data line 220, the first side edge portion 382 and the second side edge portion 383 are respectively located in the first through groove 610 and the second through groove 620; at the position where the main body 381 covers the scan line 210, the first side edge portion 382 and the second side edge portion 383 are respectively located in the third through groove 630 and the fourth through groove 640.

[0081] The cross section of the metal line group 300 is in a U-shape to completely cover the data line 220 and the scan line 210 , thereby preventing parasitic capacitance from being generated between the data line 220 and the pixel electrode 150 , and preventing parasitic capacitance from being generated between the scan line 210 and the pixel electrode 150 .

[0082] Figure 7 is a schematic diagram of a metal wire group according to the first embodiment of the present application. Figure 7 As shown, the first signal line 110 is a scan line 210, the second signal line 130 is a data line 220, the array substrate 30 also includes a wire group insulation layer 360, the metal wire group 300 includes a longitudinal metal wire group portion 371 and a transverse metal wire group portion 372, the transverse metal wire group portion 372, the wire group insulation layer 360 and the longitudinal metal wire group portion 371 are sequentially arranged between the second insulation layer 140 and the third insulation layer 400.

[0083] The longitudinal metal wire group portion 371 is arranged in parallel with the data line 220, and the transverse metal wire group portion 372 is arranged in parallel with the scan line 210; the orthographic projection of the longitudinal metal wire group portion 371 on the substrate 100 covers the orthographic projection of the data line 220 on the substrate 100, and the orthographic projection of the transverse metal line on the substrate 100 covers the orthographic projection of the scan line 210 on the substrate 100.

[0084] The orthographic projection of the longitudinal metal wire group portion 371 on the substrate 100 partially overlaps with the orthographic projection of the adjacent pixel electrode 150 on the substrate 100; the orthographic projection of the transverse metal wire group portion 372 on the substrate 100 partially overlaps with the orthographic projection of the adjacent pixel electrode 150 on the substrate 100.

[0085] In simple terms, the portion of the metal wire group 300 parallel to the data line 220 and the portion parallel to the scan line 210 are divided into two layers, upper and lower. In this way, when the data line 220 is broken, the corresponding longitudinal metal wire group portion 371 can be connected to the broken data line 220 by laser welding to repair the data line 220. When the scan line 210 is broken, the corresponding transverse metal wire group portion 372 can be connected to the broken data line 220 by laser welding to repair the data line 220. Since the transverse metal wire group portion 372 and the longitudinal metal wire group portion 371 are not connected, they can be repaired at the same time without causing interference.

[0086] Moreover, the horizontal metal wire group part 372 parallel to the scanning line 210 is below the vertical metal wire group part 371 parallel to the data line 220, so that the distance between the horizontal metal wire group part 372 and the scanning line 210 is closer, and the distance between the vertical metal wire group part 371 and the data line 220 is closer, and laser welding repair is also simpler.

[0087] Embodiment 2:

[0088] Figure 8 is a schematic diagram of a cross section of an array substrate along the width direction of a data line according to a second embodiment of the present application, Fig. 9 is a schematic diagram of a cross section of an array substrate along the scan line width direction according to the second embodiment of the present application, combined with Figure 8-9 As shown, different from the first embodiment, the metal wire group 300 of this embodiment includes two metal wires, namely a first sub-metal wire 310 and a second sub-metal wire 320, and the first sub-metal wire 310 and the second sub-metal wire 320 are both located on the second insulating layer 140, and the first sub-metal wire 310 and the second sub-metal wire 320 are arranged in parallel between two adjacent pixel electrodes 150.

[0089] An orthographic projection of a portion of the first sub-metal line 310 close to the second sub-metal line 320 on the substrate 100 partially overlaps with an orthographic projection of the first signal line 110 and the second signal line 130 on the substrate 100 .

[0090] The orthographic projection of a portion of the first sub-metal line 310 away from the second sub-metal line 320 on the substrate 100 partially overlaps with the orthographic projection of the pixel electrode 150 close to the first sub-metal line 310 of the two adjacent pixel electrodes 150 on the substrate 100 .

[0091] An orthographic projection of a portion of the second sub-metal line 320 close to the first sub-metal line 310 on the substrate 100 partially overlaps with an orthographic projection of the first signal line 110 and the second signal line 130 on the substrate 100 .

[0092] The orthographic projection of a portion of the second sub-metal line 320 away from the first sub-metal line 310 on the substrate 100 partially overlaps with the orthographic projection of the pixel electrode 150 close to the second sub-metal line 320 among the two adjacent pixel electrodes 150 on the substrate 100 .

[0093] The line widths of the first sub-metal line 310 , the second sub-metal line 320 , the first signal line 110 and the second signal line 130 are all equal; the spacing between the first sub-metal line 310 and the second sub-metal line 320 is smaller than the line width of the first signal line 110 .

[0094] Compared with the solution of the first embodiment, since the line width of the first sub-metal line 310, the line width of the second sub-metal line 320, the line width of the data line 220, and the line width of the scan line 210 are all equal, illustratively, taking the data line 220 as an example, after the data line 220 is broken, it can be repaired with the first sub-metal line 310, and the line width of the first sub-metal line 310 and the data line 220 are the same, which will not interfere with the transmission of the repaired signal.

[0095] Furthermore, the reduction between the first sub-metal line 310 and the second sub-metal line 320 is less than or equal to 1 / 3 of the line width of the data line 220. Thus, even if the metal line group 300 does not cover the data line 220 and the scan line 210, parasitic capacitance can be prevented from being generated between the pixel electrode 150 and the data line 220, and parasitic capacitance can be prevented from being generated between the pixel electrode 150 and the scan line 210. Moreover, after the first sub-metal line 310 is used as a repair line, the second sub-metal line 320 still plays a certain shielding role.

[0096] Fig.10 is a schematic diagram of different layers of a first sub-metal line and a second sub-metal line according to a second embodiment of the present application, such as Fig.10 As shown, the array substrate 30 further includes a line group insulating layer 360 , and the first sub-metal wire 310 , the line group insulating layer 360 and the second sub-metal wire 320 are sequentially arranged between the second insulating layer 140 and the third insulating layer 400 .

[0097] This is equivalent to increasing the thickness of the metal wire group 300 and avoiding the problem of increased process difficulty due to the fact that the first sub-metal wire 310 and the second sub-metal wire 320 are too close to each other and the channel cannot be completely etched out, thereby improving the yield.

[0098] Furthermore, the orthographic projection of the portion of the first sub-metal line 310 close to the second sub-metal line 320 on the substrate 100 may overlap with the orthographic projection of the portion of the second sub-metal line 320 close to the first sub-metal line 310 on the substrate 100, so as to ensure that the oblique electric field lines between the pixel electrode 150 and the data line 220 and between the pixel electrode 150 and the scan line 210 will not pass through the gap between the first sub-metal line 310 and the second sub-metal line 320, and no parasitic capacitance will be generated.

[0099] Embodiment 3:

[0100] Fig.11 is a schematic diagram of a cross section of an array substrate along the width direction of a data line according to a third embodiment of the present application, Fig.12 is a schematic diagram of a cross section of an array substrate along the scan line width direction according to the third embodiment of the present application, combined with Figure 11-12 As shown, different from the second embodiment, the metal wire group 300 in this embodiment includes three metal wires, namely a third sub-metal wire 330, a fourth sub-metal wire 340 and a fifth sub-metal wire 350, and the third sub-metal wire 330, the fourth sub-metal wire 340 and the fifth sub-metal wire 350 are all located on the second insulating layer 140, and the third sub-metal wire 330, the fourth sub-metal wire 340 and the fifth sub-metal wire 350 are arranged in parallel between two adjacent pixel electrodes 150.

[0101] The orthographic projection of a portion of the third sub-metal line 330 close to the fourth sub-metal line 340 on the substrate 100 partially overlaps with the orthographic projections of the first signal line 110 and the second signal line 130 on the substrate 100 .

[0102] The orthographic projection of a portion of the third sub-metal line 330 away from the fourth sub-metal line 340 on the substrate 100 partially overlaps with the orthographic projection of the pixel electrode 150 close to the third sub-metal line 330 of the two adjacent pixel electrodes 150 on the substrate 100 .

[0103] The orthographic projection of the fourth sub-metal line 340 on the substrate 100 is covered by the projections of the first signal line 110 and the second signal line 130 on the substrate 100 .

[0104] The orthographic projection of a portion of the fifth sub-metal line 350 close to the fourth sub-metal line 340 on the substrate 100 partially overlaps with the orthographic projections of the first signal line 110 and the second signal line 130 on the substrate 100 .

[0105] The orthographic projection of a portion of the fifth sub-metal line 350 away from the fourth sub-metal line 340 on the substrate 100 partially overlaps with the orthographic projection of the pixel electrode 150 close to the fifth sub-metal line 350 of the two adjacent pixel electrodes 150 on the substrate 100 .

[0106] The line width of the third sub-metal line 330, the line width of the fifth sub-metal line 350, the line width of the first signal line 110 and the line width of the second signal line 130 are all equal; the spacing between the third sub-metal line 330 and the fourth sub-metal line 340 is smaller than the line width of the first signal line 110, and the spacing between the fourth sub-metal line 340 and the fifth sub-metal line 350 is smaller than the line width of the first signal line 110.

[0107] Compared with the solution of the second embodiment, this embodiment divides the metal wire group 300 into three metal wires, and the line widths of the third sub-metal wire 330 and the fifth sub-metal wire 350 on the left and right sides, the line width of the data line 220 and the line width of the scan line 210 are equal; on the basis that the third sub-metal wire 330 partially overlaps with the adjacent pixel electrode 150 on the left, and overlaps with the data line 220 and the scan line 210 below on the right, and the fifth sub-metal wire 350 partially overlaps with the adjacent pixel electrode 150 on the right, and overlaps with the data line 220 and the scan line 210 below on the left, since the fourth sub-metal wire 340 is arranged in the middle, the distance between the three metal wires will not be too large, thereby not losing the effect of the shielding electrode.

[0108] Fig.13 Schematic diagram of a third sub-metal line, a fourth sub-metal line and a fifth sub-metal line according to the third embodiment of the present application. Fig.13 As shown, the array substrate 30 also includes a wire group insulation layer 360, which is located on the side of the second insulation layer 140 away from the substrate 100, the third sub-metal wire 330 and the fifth sub-metal wire 350 are arranged in the same layer, both of which are located between the second insulation layer 140 and the wire group insulation layer 360, and the fourth sub-metal wire 340 is located on the side of the wire group insulation layer 360 away from the second insulation layer 140.

[0109] In simple terms, the third sub-metal line 330 and the fifth sub-metal line 350 are arranged in the same layer, and the fourth sub-metal line 340 in the middle is located on the side of the line group insulating layer 360 away from the third sub-metal line 330 and the fifth sub-metal line 350; while ensuring that the metal line group 300 can overlap with both the data line 220 and the scan line 210, and can also overlap with the adjacent pixel electrode 150, and because there is a height difference between the fourth sub-metal line 340 and the third sub-metal line 330 and the fifth sub-metal line 350, it is not easy for the pixel electrode 150 to generate parasitic capacitance with the data line 220 and the scan line 210.

[0110] Furthermore, the orthographic projection of the portion of the first sub-metal line 310 close to the second sub-metal line 320 on the substrate 100 overlaps with the orthographic projection of the portion of the second sub-metal line 320 close to the first sub-metal line 310 on the substrate 100, so as to completely isolate the possibility of parasitic capacitance between the pixel electrode 150 and the data line 220 and the scan line 210.

[0111] Fig.14 is a schematic diagram of a preparation sequence of an array substrate according to an embodiment of the present application. Fig.15 is a schematic diagram of a preparation process of an array substrate according to an embodiment of the present application, such as Figure 14-15 The present application also discloses a method for preparing an array substrate 30, which is used to prepare the array substrate 30 described above, comprising the steps of:

[0112] S1: preparing a first signal line on a substrate;

[0113] S2: preparing a first insulating layer on the first signal line;

[0114] S3: preparing a second signal line on the first insulating layer;

[0115] S4: preparing a second insulating layer on the second signal line;

[0116] S5: preparing the metal wire group on the second insulating layer;

[0117] S6: preparing the third insulating layer on the metal wire group;

[0118] S7: preparing the pixel electrode layer on the third insulating layer, and forming a plurality of pixel electrodes;

[0119] Among them, the orthographic projection of the metal wire group 300 on the substrate 100 is in a mesh shape, the orthographic projection of the metal wire group 300 on the substrate 100 covers the orthographic projection of the first signal line 110 on the substrate 100, and the orthographic projection of the metal wire group 300 on the substrate 100 covers the orthographic projection of the second signal line 130 on the substrate 100; and the orthographic projection of the metal wire group 300 on the substrate 100 partially overlaps with the orthographic projection of the pixel electrode 150 on the substrate 100.

[0120] Compared with the structure of the existing array substrate 30, the present application covers the data line 220 and the scan line 210 through the metal wire group 300, thereby avoiding the generation of parasitic capacitance between the data line 220 and the pixel electrode 150, and avoiding the generation of parasitic capacitance between the scan line 210 and the pixel electrode 150. In addition, the metal wire group 300 also has an overlapping portion with two adjacent pixel electrodes 150. When one of the pixel electrodes 150 fails to work, the two adjacent pixel electrodes 150 can be connected through the overlapping portion of the laser metal wire group 300 and the pixel electrode 150, thereby repairing the pixel electrode 150 that fails to work.

[0121] Among them, the technical solution of the present application can be widely used in various display panels, such as TN (Twisted Nematic) display panel, IPS (In-Plane Switching) display panel, VA (Vertical Alignment) display panel, MVA (Multi-Domain Vertical Alignment) display panel, and of course, other types of display panels, such as OLED (Organic Light-Emitting Diode) display panel, can all be applicable to the above solution.

[0122] It should be noted that the limitations on the various steps involved in this solution, without affecting the implementation of the specific solution, are not deemed to limit the order of the steps. The steps written in front can be executed first, or later, or even simultaneously. As long as this solution can be implemented, it should be deemed to fall within the scope of protection of this application.

[0123] It should be noted that the inventive concept of the present application can form a large number of embodiments, but the length of the application document is limited and it is impossible to list them one by one. Therefore, under the premise of no conflict, the embodiments or technical features described above can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effects will be enhanced.

[0124] The above content is a further detailed description of the present application in combination with specific optional implementation methods, and it cannot be determined that the specific implementation of the present application is limited to these descriptions. For ordinary technicians in the technical field to which the present application belongs, several simple deductions or substitutions can be made without departing from the concept of the present application, which should be deemed to fall within the scope of protection of the present application.

Claims

1. An array substrate, comprising a substrate, and a first signal line, a first insulating layer, a second signal line, a second insulating layer and a pixel electrode layer sequentially arranged on the substrate, wherein the first signal line comprises a scan line and the second signal line comprises a data line or the first signal line comprises a data line and the second signal line comprises a scan line; the first signal line and the second signal line are arranged in a crisscross pattern to define a plurality of pixel regions, the pixel electrode layer comprises a plurality of pixel electrodes, and the plurality of pixel electrodes correspond to the plurality of pixel regions one by one, characterized in that: The array substrate further comprises a metal wire group and a third insulating layer, wherein the metal wire group and the third insulating layer are sequentially arranged between the second insulating layer and the pixel electrode layer; The orthographic projection of the metal wire group on the substrate is in a mesh shape, the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the second signal line on the substrate; and an orthographic projection of the metal wire group on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate; The metal line group includes two metal lines, namely a first sub-metal line and a second sub-metal line, the first sub-metal line and the second sub-metal line are both located on the second insulating layer, and the first sub-metal line and the second sub-metal line are arranged in parallel between two adjacent pixel electrodes; The orthographic projection of a portion of the first sub-metal line close to the second sub-metal line on the substrate partially overlaps with the orthographic projections of the first signal line and the second signal line on the substrate; The orthographic projection of a portion of the first sub-metal line away from the second sub-metal line on the substrate overlaps with the orthographic projection of the pixel electrode close to the first sub-metal line in two adjacent pixel electrodes on the substrate; The orthographic projection of a portion of the second sub-metal line close to the first sub-metal line on the substrate partially overlaps with the orthographic projections of the first signal line and the second signal line on the substrate; The orthographic projection of a portion of the second sub-metal line away from the first sub-metal line on the substrate overlaps with the orthographic projection of the pixel electrode close to the second sub-metal line in two adjacent pixel electrodes on the substrate; The line width of the first sub-metal line, the line width of the second sub-metal line, the line width of the first signal line and the line width of the second signal line are all equal; the spacing between the first sub-metal line and the second sub-metal line is smaller than the line width of the first signal line.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes a line group insulating layer, and the first sub-metal line, the line group insulating layer and the second sub-metal line are sequentially arranged between the second insulating layer and the third insulating layer.

3. The array substrate according to claim 2, characterized in that: An orthographic projection of a portion of the first sub-metal line close to the second sub-metal line on the substrate overlaps with an orthographic projection of a portion of the second sub-metal line close to the first sub-metal line on the substrate.

4. An array substrate, comprising a substrate, and a first signal line, a first insulating layer, a second signal line, a second insulating layer and a pixel electrode layer sequentially arranged on the substrate, wherein the first signal line comprises a scan line and the second signal line comprises a data line or the first signal line comprises a data line and the second signal line comprises a scan line; the first signal line and the second signal line are arranged in a crisscross pattern to define a plurality of pixel regions, the pixel electrode layer comprises a plurality of pixel electrodes, and the plurality of pixel electrodes correspond to the plurality of pixel regions one by one, characterized in that: The array substrate further comprises a metal wire group and a third insulating layer, wherein the metal wire group and the third insulating layer are sequentially arranged between the second insulating layer and the pixel electrode layer; The orthographic projection of the metal wire group on the substrate is in a mesh shape, the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the second signal line on the substrate; and an orthographic projection of the metal wire group on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate; The metal line group includes three metal lines, namely a third sub-metal line, a fourth sub-metal line and a fifth sub-metal line, the third sub-metal line, the fourth sub-metal line and the fifth sub-metal line are all located on the second insulating layer, and the third sub-metal line, the fourth sub-metal line and the fifth sub-metal line are arranged in parallel between two adjacent pixel electrodes; The orthographic projection of a portion of the third sub-metal line close to the fourth sub-metal line on the substrate partially overlaps with the orthographic projections of the first signal line and the second signal line on the substrate; The orthographic projection of a portion of the third sub-metal line away from the fourth sub-metal line on the substrate overlaps with the orthographic projection of the pixel electrode close to the third sub-metal line in two adjacent pixel electrodes on the substrate; The orthographic projection of the fourth sub-metal line on the substrate is covered by the projections of the first signal line and the second signal line on the substrate; The orthographic projection of a portion of the fifth sub-metal line close to the fourth sub-metal line on the substrate partially overlaps with the orthographic projections of the first signal line and the second signal line on the substrate; The orthographic projection of a portion of the fifth sub-metal line away from the fourth sub-metal line on the substrate overlaps with the orthographic projection of the pixel electrode of the two adjacent pixel electrodes close to the fifth sub-metal line on the substrate; The line width of the third sub-metal line, the line width of the fifth sub-metal line, the line width of the first signal line and the line width of the second signal line are all equal; the spacing between the third sub-metal line and the fourth sub-metal line is smaller than the line width of the first signal line, and the spacing between the fourth sub-metal line and the fifth sub-metal line is smaller than the line width of the first signal line.

5. The array substrate according to claim 4, characterized in that: The array substrate also includes a wire group insulation layer, which is located on a side of the second insulation layer away from the substrate. The third sub-metal wire and the fifth sub-metal wire are arranged in the same layer and are both located between the second insulation layer and the wire group insulation layer. The fourth sub-metal wire is located on a side of the wire group insulation layer away from the second insulation layer.

6. An array substrate, comprising a substrate, and a first signal line, a first insulating layer, a second signal line, a second insulating layer and a pixel electrode layer sequentially arranged on the substrate, wherein the first signal line comprises a scan line and the second signal line comprises a data line or the first signal line comprises a data line and the second signal line comprises a scan line; the first signal line and the second signal line are arranged in a crisscross pattern to define a plurality of pixel regions, the pixel electrode layer comprises a plurality of pixel electrodes, and the plurality of pixel electrodes correspond to the plurality of pixel regions one by one, characterized in that: The array substrate further comprises a metal wire group and a third insulating layer, wherein the metal wire group and the third insulating layer are sequentially arranged between the second insulating layer and the pixel electrode layer; The orthographic projection of the metal wire group on the substrate is in a mesh shape, the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the second signal line on the substrate; and an orthographic projection of the metal wire group on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate; The first signal line includes a scan line, the second signal line includes a data line, the array substrate further includes a wire group insulation layer, the metal wire group includes a longitudinal metal wire group portion and a transverse metal wire group portion, the transverse metal wire group portion, the wire group insulation layer and the longitudinal metal wire group portion are sequentially arranged between the second insulation layer and the third insulation layer; The longitudinal metal line group part is arranged in parallel with the data line, and the transverse metal line group part is arranged in parallel with the scan line; the orthographic projection of the longitudinal metal line group part on the substrate covers the orthographic projection of the data line on the substrate, and the orthographic projection of the transverse metal line on the substrate covers the orthographic projection of the scan line on the substrate; The orthographic projection of a portion of the longitudinal metal line group on the substrate partially overlaps with the orthographic projection of the pixel electrode on the substrate; An orthographic projection of a portion of the lateral metal line group on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate.

7. An array substrate, comprising a substrate, and a first signal line, a first insulating layer, a second signal line, a second insulating layer and a pixel electrode layer sequentially arranged on the substrate, wherein the first signal line comprises a scan line and the second signal line comprises a data line or the first signal line comprises a data line and the second signal line comprises a scan line; the first signal line and the second signal line are arranged in a crisscross pattern to define a plurality of pixel regions, the pixel electrode layer comprises a plurality of pixel electrodes, and the plurality of pixel electrodes correspond to the plurality of pixel regions one by one, characterized in that: The array substrate further comprises a metal wire group and a third insulating layer, wherein the metal wire group and the third insulating layer are sequentially arranged between the second insulating layer and the pixel electrode layer; The orthographic projection of the metal wire group on the substrate is in a mesh shape, the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the second signal line on the substrate; and an orthographic projection of the metal wire group on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate; The first signal line includes a scan line, the second signal line includes a data line, the second insulating layer is provided with a first through groove and a second through groove on both sides of the data line in a width direction, and the first through groove and the second through groove both penetrate the second insulating layer; A third through groove and a fourth through groove are respectively provided on both sides of the second insulating layer and the first insulating layer in the width direction of the scanning line, the third through groove penetrates the second insulating layer and the first insulating layer at the same time, and the fourth through groove penetrates the second insulating layer and the first insulating layer at the same time; The metal wire group includes a main body, a first side edge and a second side edge, wherein the first side edge and the second side edge are respectively connected to two sides of the main body in a width direction, and a distance between the first side edge and the second side edge is greater than a line width of the data line and also greater than a line width of the scan line; At a position where the main body covers the data line, the first side edge portion and the second side edge portion are respectively located in the first through groove and the second through groove; At a position where the main body covers the scanning line, the first side edge portion and the second side edge portion are respectively located in the third through groove and the fourth through groove.

8. A method for preparing an array substrate, characterized in that: The method for preparing the array substrate according to any one of claims 1 to 7 comprises the following steps: preparing a first signal line on a substrate; preparing a first insulating layer on the first signal line; preparing a second signal line on the first insulating layer; preparing a second insulating layer on the second signal line; preparing the metal wire group on the second insulating layer; preparing the third insulating layer on the metal wire group; Preparing the pixel electrode layer on the third insulating layer and forming a plurality of pixel electrodes; The orthographic projection of the metal wire group on the substrate is in a mesh shape, the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the first signal line on the substrate, and the orthographic projection of the metal wire group on the substrate covers the orthographic projection of the second signal line on the substrate; Furthermore, an orthographic projection of the metal wire group on the substrate partially overlaps with an orthographic projection of the pixel electrode on the substrate.

9. An electronic paper display panel, characterized in that: The electronic paper display panel comprises an electrophoretic layer and an array substrate as claimed in any one of claims 1 to 7, wherein the array substrate drives the electrophoretic particles in the electrophoretic layer to move so as to display images.

Images