127results about How to "Avoid Parasitic Capacitance" patented technology

A display device integrated with a touch screen panel, and a method of driving the same, can prevent parasitic capacitance that would otherwise increase the load during a touch operation, lower the accuracy of touch sensing, or make touch sensing impossible. The display device includes data lines, gate lines, and a plurality of electrodes spaced apart from each other. A common voltage is applied to the electrodes in a display driving mode and a touch drive signal is applied to one or more of the electrodes in a touch driving mode. A data voltage is applied to the data lines in the display driving mode. A scan signal is supplied sequentially to the gate lines in the display driving mode and the touch drive signal or a signal corresponding to the touch drive signal is applied to one or more of the gate lines in the touch driving mode.

The present invention provides a display device including a pixel array section, the pixel array section having pixels arranged in a matrix form, each of the pixels including: an electro-optical element; a write transistor; a holding capacitance; a drive transistor; and a switching transistor; a write scan line disposed for each of pixel rows of the pixel array section and adapted to convey a write signal to be applied to the gate electrode of the write transistor; and a correction scan line, wherein the wiring structure of the write scan line does not intersect with the wiring pattern connected to the gate electrode of the drive transistor.

An in-cell touch display device. A panel has a plurality of data lines, a plurality of gate lines and a plurality of touch electrodes disposed thereon. A touch driving signal is applied to the plurality of touch electrodes when a driving mode is a touch mode. A data driver drives the plurality of data lines. A gate driver drives the plurality of gate lines. The gate driver sequentially outputs a scanning signal for driving the plurality of gate lines to the plurality of gate lines when the driving mode is a display mode, and outputs a load-free driving signal corresponding to the touch driving signal to at least one gate line when the driving mode is the touch mode. A level shifter generates the load-free driving signal. A multiplexer inputs a scanning voltage or the load-free driving signal to the gate driver depending on the driving mode.

In a method of forming a device isolation layer for minimizing a parasitic capacitor and a non-volatile memory device using the same, a trench is formed on a substrate. A first insulation layer is formed on a top surface of the substrate and on inner surfaces of the trench, so that the trench is partially filled with the first insulation layer. A second insulation layer is formed on the first insulation layer to a thickness to fill up the trench, thereby forming a preliminary isolation layer. An etching rate of the second insulation layer is different from that of the first insulation layer. A recess is formed at a central portion of the preliminary isolation layer by partially removing the first and second insulation layers, thereby forming the device isolation layer including the recess. The recess in the device isolation layer reduces a parasitic capacitance in a non-volatile memory device.

An isolation structure of a semiconductor device is formed by forming a hard mask layer on a semiconductor substrate having active and field regions to expose the field region. A trench is defined by etching the exposed field region of the semiconductor substrate using the hard mask as an etch mask. An SOG layer is formed in the trench partially filling the trench. An amorphous aluminum oxide layer is formed on the resultant substrate including the SOG layer. An HDP layer is formed on the amorphous aluminum oxide layer to completely fill the trench. The HDP layer and the amorphous aluminum oxide layer are subjected to CMP to expose the hard mask. The hard mask and portions of the amorphous aluminum oxide layer that are formed on the HDP layer are removed. The amorphous aluminum oxide layer is crystallized.

In a drive method of a light-emitting display panel capable of emitting light in low luminance, the parasitic capacitances of the light-emitting elements disposed in the light-emitting display panel are precharged making use of a reverse bias voltage before they are lit. In this case, a reverse bias voltage created by a reverse bias voltage creation circuit or a peak current being precharged is controlled by selectively grounding control terminals based on dimmer control. In particular, when the light-emitting elements are emitted in low luminance, the reverse bias voltage is output in a low level, thereby the light-emitting elements are prevented from being precharged with an excessive voltage. The above arrangement can realize light emission control in low luminance.

A MEMS device (100) is provided that includes a handle layer (108) having a sidewall (138), a cap (132) overlying said handle layer (108), said cap (132) having a sidewall (138), and a conductive material (136) disposed on at least a portion of said sidewall of said cap (138) and said sidewall of said handle layer (138) to thereby electrically couple said handle layer (108) to said cap (132). A wafer-level method for manufacturing the MEMS device from a substrate (300) comprising a handle layer (108) and a cap (132) overlying the handle layer (108) is also provided. The method includes making a first cut through the cap (132) and at least a portion of the substrate (300) to form a first sidewall (138), and depositing a conductive material (136) onto the first sidewall (138) to electrically couple the cap (132) to the substrate (300).

The invention provides a manufacturing method of a Terahertz Schottky diode. The manufacturing method comprises: a high-concentration gallium arsenide-doped layer and a low-concentration gallium arsenide-doped layer are sequentially formed on a substrate of a gallium arsenide semiconductor; an Ohmic contact cathode and Ohmic contact metals are formed on the high-concentration gallium arsenide-doped layer; a silicon dioxide layer with small bores is formed on the low-concentration gallium arsenide-doped layer; a Schottky contact anode is formed; an Ohmic contact cathode pressure point, a Schottky contact anode extension pressure point and a suspending plating bridge are formed; and the Schottky contact anode extension pressure point is connected with the Schottky contact anode through the impending plating bridge. According to the Schottky diode manufactured by the manufacturing method provided by the invention, parasitic effects are reduced, thermionic noises existing in n+GaAs, the discontinuity of the anode pressure point to the impending plating bridge and the series resistance of the diode can be lowered, and the integration with peripheral circuits is easily realized by using flip chip bonding.

A display having a touch sensor comprises: a plurality of pixel areas disposed in a matrix manner on a substrate; a routing line running along a first direction on the substrate; a first passivation layer covering the routing line; a touch electrode covering the routing line and corresponding to a grouped pixel areas on the first passivation layer; a touch contact hole exposing some portions of the routing line by penetrating the touch electrode and the first passivation layer; a second passivation layer covering the touch electrode; a passivation contact hole exposing the touch contact hole and some portions of the touch electrode around the touch contact hole by penetrating the second passivation layer; and a touch terminal connecting the touch electrode and the routing line on the second passivation layer.

The present invention is to provide a power converter, which includes a half-bridge circuit parallel-connected to an input voltage and having two series-connected power switches, an LLC resonant circuit formed by a resonant inductor, magnetic inductance of a primary winding and a resonant capacitor, a current-circulating circuit parallel-connected to the half-bridge circuit and having two series-connected rectifiers, and a full-wave rectification circuit connected to a secondary winding for generating an output voltage across an output capacitor. The LLC resonant circuit is parallel-connected to one of the power switches, and the line between the two rectifiers is cross-connected to the line between the resonant inductor and the primary winding. Thus, since the current-circulating circuit is able to guide current through the resonant inductor into circulation in switching moment of the power switches, parasitic capacitance of the primary winding is prevented from being overcharged by the current through the resonant inductor accordingly.

An ESD protection device includes a Si substrate and a rewiring layer. The rewiring layer includes Ti/Cu/Ti electrodes are electrically connected through contact holes to an ESD protection circuit with Al electrodes films, which is formed at the surface of the Si substrate. The Al electrode film is electrically connected to the Ti/Cu/Ti electrode, whereas the Al electrode film is electrically connected to the Ti/Cu/Ti electrode. A diode forming region is formed between Al electrode films, whereas a diode forming region is formed between Al electrode films. The Ti/Cu/Ti electrode has no overlap with the diode forming region, whereas the Ti/Cu/Ti electrode has no overlap with the diode forming region. Thus, a semiconductor device is provided which is able to reduce the generation of parasitic capacitance, and able to be applied up to a higher frequency band.

The invention provides a liquid crystal pixel and the making method and LCD thereof. And the liquid crystal pixel comprises a data line, a doped polycrystalline layer and a shielding metal layer, where the doped polycrystalline silicon layer is located under the data line and the vertical projection of the polycrystalline silicon layer does not overlap the data line; the shielding metal layer is located between the data line and the doped polycrystalline silicon layer and form a storage capacitor together with the polycrystalline silicon layer. In addition, the invention also provides a liquid crystal pixel making method, which stores video data by the store capacitor and can not cause burden to the data line but can avoid possible parasitical capacitor between the pixel electrode and the data line.

An organic light emitting diodes display device includes a number of data lines, scan lines, and cathode electrodes. These scan lines are perpendicular to the data lines to form a number of pixels, each of which possess a pixel area respectively. All the pixels areas form a pixel area array. These cathode electrodes are parallel to the scan lines or data lines and partially cover the pixel area array. Spaces between each two cathode electrodes are above the scan lines or data lines to avoid the parasitic capacitance between the cathode electrodes and scan lines or data lines. And thus the resistance capacitance time delay is prevented.

A display substrate includes a base substrate, a first line, a second line, a bridge line, a thin-film transistor (TFT), a storage line, and a pixel electrode. The first line extends in a first direction on the base substrate. The second line extends in a second direction on the base substrate and is divided into two portions with respect to the first line. The bridge line makes contact with the two portions of the second line in first and second bridge contact regions. The TFT includes a source electrode making contact with one of the first and second lines in a data contact region. The storage line is formed on the one of the first and second lines. The pixel electrode is formed on the storage line and is electrically connected to the TFT. The display substrate reduces formation of parasitic capacitance between pixel electrode and data line.

An in-cell touch display device. A panel has a plurality of data lines, a plurality of gate lines and a plurality of touch electrodes disposed thereon. A touch driving signal is applied to the plurality of touch electrodes when a driving mode is a touch mode. A data driver drives the plurality of data lines. A gate driver drives the plurality of gate lines. The gate driver sequentially outputs a scanning signal for driving the plurality of gate lines to the plurality of gate lines when the driving mode is a display mode, and outputs a load-free driving signal corresponding to the touch driving signal to at least one gate line when the driving mode is the touch mode. A level shifter generates the load-free driving signal. A multiplexer inputs a scanning voltage or the load-free driving signal to the gate driver depending on the driving mode.

The invention discloses an array substrate, a display and electronic equipment. The array substrate comprises a public electrode layer and a pixel electrode layer which are opposite to each other, wherein the pixel electrode layer comprises a plurality of arrayed pixel electrodes, and the public electrode layer comprises a plurality of public electrode blocks; the array substrate further comprises a plurality of switch devices, a plurality of data lines extending along the column direction of the array, and a plurality of public routings electrically connected with the public electrode blocks in a one-to-one correspondence manner; projections of the public routings in the pixel electrode layer are not superposed with the pixel electrodes in the direction vertical to the pixel electrode layer; a pixel clearance is reserved between every two adjacent pixel electrodes; projections of the public routings in the pixel electrode layer and projections of the data lines in the pixel electrode layer are positioned in different pixel clearances in the direction vertical to the pixel electrode layer; two data lines of which the projections are positioned in the same pixel clearance are positioned on different layers. The array substrate is higher in touch detection precision.

The invention provides a three-dimensional NAND memory device structure and a preparation method thereof. The method comprises the following steps: forming a first laminated structure and a second laminated structure with communicated channel holes on a support substrate; forming a functional layer, a channel layer and a filling dielectric on the surface of the channel hole; forming a gate gap; filling a gap insulating layer in the gate gap; removing the support substrate, and forming a third laminated structure on the back surface of the first laminated structure; etching the third laminatedstructure to form a first etching window, and removing the functional layer at the bottom of the first channel hole based on the first etching window; and filling a channel connection layer in the first etching window. The channel connection layer is formed at the corresponding position of the back surface of the channel hole, so that the risk that the functional layer at the connecting part of the upper channel hole and the lower channel hole is damaged when the channel connection layer and the channel layer are connected through a process of punching from the front surface of the channel hole is avoided; and in addition, the process for forming the channel connection layer is low in complexity, easy to control and high in yield.

The invention provides a fin type field effect transistor and a manufacture method of the fin type field effect transistor. The method comprises the steps that a fin is formed on a semiconductor substrate, a virtual grid electrode is formed on the semiconductor substrate with the formed fin and stretches across the fin, first side walls are formed on two sides of the virtual grid electrode, ions are implanted in the fin so as to form a source electrode and a drain electrode of the fin type field effect transistor, the virtual grid electrode is eliminated, an opening is formed in the position of the virtual grid electrode, a high-K-grid medium layer and a metal grid electrode material layer are sequentially deposited so as to fill the opening, and a metal grid electrode is formed, and the first side walls and the high-K-grid medium layer on the side wall of the metal grid electrode are eliminated. According to the fin type field effect transistor, the high-K-grid medium layer on two sides of the metal grid electrode are effectively eliminated in sequence, stray capacitance is prevented from generating between the metal grid electrode and the source electrode or the drain electrode, other semiconductor structures are prevented from being damaged during the eliminating process, and the fin type field effect transistor is enabled to be good in electrical properties.

The invention discloses an array substrate and a preparation method therefor, a display panel and a display apparatus, and belongs to the display field. The array substrate comprises multiple pixel units, a reading signal line, a first gate electrode signal line, a second gate electrode signal line, a data line and a shielding signal line, wherein each pixel unit comprises three sub pixel units; each sub pixel unit comprises a display sub unit; at least one pixel unit also comprises a palmprint recognition sub unit; the shielding signal line is parallel to the reading signal line; one end of the shielding signal line is grounded while the other end of the shielding signal line is connected with the input end of the first gate electrode signal line; the corresponding display sub units are connected with the first gate electrode signal line and the data line; and the palmprint recognition unit is connected with the second gate electrode signal line and the reading signal line. According to the array substrate, due to the addition of the shielding signal line, the interference on the reading signal line from the grid electrode signal lines can be reduced, stray capacitance can be prevented from being generated on the reading signal line, and the palmprint recognition effect is improved.

The invention provides an array baseplate, a preparation method of the array baseplate, and a display panel, and relates to the technical field of display. The array baseplate, the preparation method and the display panel can reduce stray capacitance between a transparent conducting layer and an active layer. The array baseplate comprises a substrate, a thin film transistor arranged on the substrate, and a common electrode arranged on one side, far away from the substrate, of the thin film transistor, wherein the common electrode comprises a first hollow part; an active layer of the thin film transistor comprises a source electrode region, a drain electrode region and a channel region; and orthographic projection of the first hollow part on the substrate at least covers orthographic projection of the channel region on the substrate.