Minimum pulse width violation repair circuit and minimum pulse width violation repair method

Abstract

The present disclosure relates to a minimum pulse width violation repair circuit and a minimum pulse width violation repair method. The circuit comprises a pulse delay module that delays the generation time of a pulse input signal transition edge that causes a minimum pulse width violation to obtain a delayed pulse signal; and a widening module that obtains a widened pulse signal that meets pulse design rules according to the pulse input signal and the delayed pulse signal. The technical solution of the present disclosure can eliminate the pulse width violation of the pulse signal that causes the minimum pulse width violation. The circuit of the present disclosure has a simple structure, is easy to implement, and has a good effect of improving the minimum pulse width violation. The data model of the circuit of the present disclosure can be stored in advance and called during the repair of the minimum pulse width violation. A plurality of circuits of the present disclosure can be connected in series to further enhance the repair effect of the minimum pulse width violation and finally completely repair the minimum pulse width violation.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a minimum pulse width violation repair circuit and a minimum pulse width violation repair method. Background Art

[0002] Modern digital integrated circuits contain a large number of sequential circuit units, including various flip-flops and latches. All of these units require the clock signal to meet a certain minimum pulse width to function properly. A minimum pulse width violation occurs when the clock signal pulse width is less than the minimum pulse width required by the sequential unit. Because sequential units require sufficient pulse width to accurately capture and process signals, a minimum pulse width violation can cause the sequential units to malfunction. Summary of the Invention

[0003] In view of this, the present disclosure provides a minimum pulse width violation repair circuit and a minimum pulse width violation repair method to solve the minimum pulse width violation problem occurring in a sequential circuit.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] According to one aspect of the present disclosure, a minimum pulse width violation repair circuit is provided, comprising:

[0006] A pulse delay module, which delays the generation time of the transition edge of the pulse input signal that causes the minimum pulse width violation to obtain a delayed pulse signal;

[0007] A widening module is configured to obtain a widened pulse signal that complies with pulse design rules according to the pulse input signal and the delayed pulse signal.

[0008] In one possible implementation, the time delay of the pulse delay module for the transition edge of the pulse input signal is smaller than the pulse width of the pulse input signal.

[0009] In one possible embodiment, the pulse delay module includes at least one buffer. When the number of the buffers is at least two, the pulse delay module includes at least one pulse delay branch connected between the pulse signal input line and the widening module, and each of the pulse delay branches includes at least one buffer; wherein the time delay of each buffer to the transition edge of the input signal of the buffer itself is less than the pulse width of the input signal of the buffer itself, and wherein the pulse signal input line is used to transmit the pulse input signal.

[0010] In one possible implementation, the pulse delay module includes an even number of first inverters connected in series between a pulse signal input line and the widening module, wherein the pulse signal input line is used to transmit the pulse input signal.

[0011] In one possible implementation, the widening module includes an OR gate unit, one input end of the OR gate unit receives the pulse input signal, the other input end of the OR gate unit receives the delayed pulse signal, and the output end of the OR gate unit outputs the widened pulse signal.

[0012] In one possible implementation, the number of the other input terminals of the OR gate unit is equal to the number of the output terminals of the pulse delay module, and the other input terminals of the OR gate unit are respectively connected one-to-one with the output terminals of the pulse delay module.

[0013] In one possible implementation, the minimum pulse width violation repair circuit further includes:

[0014] a second inverter, wherein the second inverter obtains the pulse input signal according to the inverted pulse signal;

[0015] The widening module includes a NAND gate unit, one input end of the NAND gate unit receives the pulse input signal, the other input end of the NAND gate unit receives the delayed pulse signal, and the output end of the NAND gate unit outputs the widening pulse signal.

[0016] In one possible implementation, the widening module includes an AND gate unit, one input end of the AND gate unit receives the pulse input signal, the other input end of the AND gate unit receives the delayed pulse signal, and the output end of the AND gate unit outputs the widening pulse signal.

[0017] In one possible implementation, the number of the other input terminals of the AND gate unit is equal to the number of the output terminals of the pulse delay module, and the other input terminals of the AND gate unit are respectively connected one-to-one with the output terminals of the pulse delay module.

[0018] In one possible implementation, the minimum pulse width violation repair circuit further includes:

[0019] a second inverter, wherein the second inverter obtains the pulse input signal according to the inverted pulse signal;

[0020] The widening module includes a NOR gate unit, one input end of the NOR gate unit receives the pulse input signal, the other input end of the NOR gate unit receives the delayed pulse signal, and the output end of the NOR gate unit outputs the widening pulse signal.

[0021] According to another aspect of the present disclosure, a minimum pulse width violation repair method is provided, comprising:

[0022] From the pulse width violation information, a circuit generating the pulse width violation is obtained;

[0023] In the circuit for generating pulse width violation, a minimum pulse width violation repair circuit as described in any one of the above items is added.

[0024] According to another aspect of the present disclosure, there is provided an electronic device, comprising:

[0025] processor;

[0026] a memory for storing executable instructions for the processor;

[0027] The processor is configured to execute the executable instructions to implement the minimum pulse width violation repair method as described above.

[0028] According to another aspect of the present disclosure, a computer-readable storage medium is provided. When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device can implement the minimum pulse width violation repair method as described above.

[0029] According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the minimum pulse width violation repair method as described above is implemented.

[0030] As can be seen from the above scheme, the minimum pulse width violation repair circuit and minimum pulse width violation repair method disclosed in the present invention first delay the generation time of the transition edge of the pulse input signal that causes the minimum pulse width violation, and then refer to the transition edge of the pulse input signal and the transition edge of the delayed pulse signal, select one transition edge of the pulse input signal as the rising edge of the widened pulse signal that complies with the pulse design rules, and select the other transition edge of the delayed pulse signal as the falling edge of the widened pulse signal, thereby obtaining a widened pulse signal. One transition edge in the widened pulse signal is consistent with one transition edge of the pulse input signal, and the other transition edge in the widened pulse signal is consistent with the other transition edge of the delayed pulse signal, because the other transition edge of the delayed pulse signal is delayed from the other transition edge of the pulse input signal that causes the minimum pulse width violation. Therefore, compared with the pulse input signal, the pulse width of the widened pulse signal is larger. Using the minimum pulse width violation repair circuit and minimum pulse width violation repair method disclosed in the present invention, the pulse width violation of the pulse signal that causes the minimum pulse width violation can be eliminated.

[0031] The minimum pulse width violation repair circuit and the minimum pulse width violation repair method disclosed in the present invention have a simple circuit structure, are easy to implement, and have a good effect in improving the minimum pulse width violation. By using the minimum pulse width violation repair circuit and the minimum pulse width violation repair method disclosed in the present invention, before performing the minimum pulse width violation repair, the data model of the minimum pulse width violation repair circuit disclosed in the present invention can be stored in advance, and called when performing the minimum pulse width violation repair. Compared with the relevant minimum pulse width violation repair scheme, the minimum pulse width violation can be repaired by using the minimum pulse width violation repair circuit and the minimum pulse width violation repair method disclosed in the present invention, which can obtain a basically determined pulse width improvement and benefit. In the case where the difference between the pulse width value of the minimum pulse width violation and the pulse width specified by the pulse design rules is large, the repair effect of the minimum pulse width violation can be further enhanced by connecting multiple minimum pulse width violation repair circuits disclosed in series, and finally the minimum pulse width violation can be completely repaired. The structure of the minimum pulse width violation repair circuit disclosed in the present invention can be packaged or customized into a standard minimum pulse width violation repair unit module, which can be directly called using the general ECO method and quantitatively analyzed through the STA tool, and can achieve full compatibility with related timing sign-off processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic diagram showing the timing difference between an ideal clock signal and an actual transmission clock signal according to an exemplary embodiment;

[0033] Figure 2 is a schematic diagram showing the logical structure of a minimum pulse width violation repair circuit according to an exemplary embodiment;

[0034] Figure 3A is a circuit diagram showing a pulse delay module including a buffer according to an exemplary embodiment;

[0035] Figure 3B is a circuit diagram showing a pulse delay module including a pulse delay branch according to an exemplary embodiment;

[0036] Figure 3C is a circuit diagram showing a pulse delay module including two pulse delay branches according to an exemplary embodiment;

[0037] Figure 4 is a circuit diagram showing a pulse delay module including two first inverters connected in series according to an exemplary embodiment;

[0038] Figure 5 is a circuit diagram showing a widening module including an OR gate unit according to an exemplary embodiment;

[0039] Figure 6 is a schematic diagram showing a minimum pulse width violation repair circuit including a second inverter and a NAND gate unit according to an exemplary embodiment;

[0040] Figure 7 is a circuit diagram showing an expansion module including an AND gate unit according to an exemplary embodiment;

[0041] Figure 8 is a schematic diagram of a minimum pulse width violation repair circuit including a second inverter and a NOR gate unit according to an exemplary embodiment;

[0042] Figure 9A is a first specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment;

[0043] Figure 9B yes Figure 9A A signal timing diagram of the circuit shown;

[0044] Figure 9C This is a schematic diagram of the signal timing where glitches occur;

[0045] Figure 10 is a second specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment;

[0046] Figure 11 is a third specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment;

[0047] Figure 12A is a fourth specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment;

[0048] Figure 12B yes Figure 12A A signal timing diagram of the circuit shown;

[0049] Figure 13A is a fifth specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment;

[0050] Figure 13B yes Figure 13A A signal timing diagram of the circuit shown;

[0051] Figure 14 is a sixth specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment;

[0052] Figure 15Ais a seventh specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment;

[0053] Figure 15B yes Figure 15A A signal timing diagram of the circuit shown;

[0054] Figure 16 yes Figure 9A A simulation waveform diagram of a first specific circuit structure;

[0055] Figure 17 It is a structural diagram of an electronic device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0057] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the numbers used in this manner are interchangeable where appropriate so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure as detailed in the appended claims.

[0058] Figure 1 FIG. 1 is a schematic diagram showing the timing difference between an ideal clock signal and an actual transmission clock signal according to an exemplary embodiment. Figure 1 As shown in FIG, in an ideal state, in the ideal clock signal clk0, the positive pulse width Ton and the negative pulse width Toff are equal. However, in practice, due to the influence of various aspects in the integrated circuit, the rising edge and the falling edge of the actual transmission clock signal clk1 may be delayed or advanced, and the rising edge and the falling edge of the actual transmission clock signal clk1 may also have different degrees of inclination. This causes the positive pulse width Ton and the negative pulse width Toff in the actual transmission clock signal clk1 to be unequal, for example Figure 1 As shown, the positive pulse width Ton in the actual transmission clock signal clk1 is smaller than the negative pulse width Toff.

[0059] Among them, the positive pulse can also be called a high pulse, and the negative pulse can also be called a low pulse. Furthermore, the positive pulse width can be called a high pulse width, and the negative pulse width can be called a low pulse width. A logic level that is originally logic 0, which is converted from logic 0 to logic 1, and then converted from logic 1 to logic 0 to form a pulse signal is called a positive pulse or a high pulse; a logic level that is originally logic 1, which is converted from logic 1 to logic 0, and then converted from logic 0 to 1 to form a pulse signal is called a negative pulse or a low pulse. The square wave and rectangular wave in the logic circuit are composed of alternating high pulses and low pulses. In the implementation of the present disclosure, positive pulses, negative pulses, positive pulse widths and negative pulse widths are used for description.

[0060] Take the rising edge triggered D flip-flop as an example. For the rising edge triggered D flip-flop, it has a minimum positive pulse width requirement. Figure 1 For example, if the positive pulse width Ton of the actual transmission clock signal clk1 is less than the minimum positive pulse width required by the rising-edge-triggered D flip-flop, the rising-edge-triggered D flip-flop will not work properly. Similarly, for the falling-edge-triggered D flip-flop, there is a corresponding minimum negative pulse width requirement. If the negative pulse width Toff of the actual transmission clock signal clk1 is less than the minimum negative pulse width required by the falling-edge-triggered D flip-flop, the falling-edge-triggered D flip-flop will not work properly.

[0061] The solution to fixing minimum pulse width violations is to try to eliminate factors that cause clock signal degradation in the clock tree, including crosstalk between signal lines; or to use engineering change orders (ECOs) to reshape degraded clock signals; or to use higher-quality clock sources, such as phase-locked loops (PLLs) with less jitter. A clock tree is a special network structure used to distribute clock signals in digital circuit design. Its primary function is to evenly distribute the clock signal generated by a clock source to various clock load points (such as triggers, registers, and other sequential circuit units) across the entire chip or circuit board.

[0062] Each of the above methods generally has limitations. In some cases, clock signal degradation may not be corrected, for example, in densely wired areas where resource constraints make it difficult to reduce interference on the clock signal lines, or when the clock source has already been selected and cannot be changed. In other cases, the improvement of clock signal degradation is limited and insufficient to completely correct minimum pulse width violations. For example, using ECO methods, such as inserting a buffer with strong drive capability to shape the clock signal, can be used.

[0063] In view of this, the concept of the embodiments of the present disclosure is to widen the positive or negative pulse width by introducing a delay by adding a logic circuit unit to resolve the pulse width violation problem. When performing minimum pulse width repair, the minimum pulse width violation can be improved and repaired by directly utilizing the minimum pulse width violation repair circuit and minimum pulse width violation repair method of the embodiments of the present disclosure.

[0064] Figure 2 FIG. 1 is a schematic diagram showing a logic structure of a minimum pulse width violation repair circuit according to an exemplary embodiment. Figure 2 As shown, the minimum pulse width violation repair circuit mainly includes a pulse delay module 201 and a pulse width expansion module 202. The pulse delay module 201 delays the generation time of the transition edge of the pulse input signal A that causes the minimum pulse width violation, generating a delayed pulse signal B. The pulse width expansion module 202 generates a widened pulse signal X that complies with pulse design rules based on the pulse input signal A and the delayed pulse signal B. Pulse design rules refer to a series of design criteria and standards that must be followed in integrated circuit design, particularly in pulse circuit design, to ensure that the circuit can correctly generate, transmit, and process pulse signals. These rules cover multiple aspects of the circuit, including pulse signal generation, shaping, propagation, and synchronization. The purpose of pulse design rules is to ensure that integrated circuits can meet specific performance requirements in practical applications, such as signal stability, timing accuracy, and circuit reliability. The width of the pulse signal, such as the positive pulse width and the negative pulse width, is one of the criteria in the pulse design rules. Therefore, the widened pulse signal X refers to a pulse signal that complies with the pulse design rules after the pulse width is widened relative to the pulse input signal A that causes the minimum pulse width violation.

[0065] In an exemplary embodiment, the pulse input signal A is a pulse signal with a pulse width violation. In an exemplary embodiment, the pulse width violation refers to a minimum pulse width violation.

[0066] In the exemplary embodiment, the input terminal of pulse delay module 201 is electrically connected to the pulse signal input line to receive pulse input signal A, which is transmitted on the pulse signal input line. The first input terminal of widening module 202 is electrically connected to the pulse signal input line, and the second input terminal of widening module 202 is electrically connected to the output terminal of pulse delay module 201. The output terminal of widening module 202 is electrically connected to the pulse signal output line. Pulse delay module 201 transmits delayed pulse signal B via its output terminal to the second input terminal of widening module 202, and widening module 202 outputs widened pulse signal X via the pulse signal output line.

[0067] The minimum pulse width violation repair circuit of the embodiment of the present disclosure first uses the pulse delay module 201 to delay the generation time of the jump edge of the pulse input signal A that causes the minimum pulse width violation to obtain a delayed pulse signal B, and then the jump edge of the delayed pulse signal B is delayed compared to the jump edge of the pulse input signal A. Then, the widening module 202 is used to refer to the jump edge of the pulse input signal A and the jump edge of the delayed pulse signal B (delayed from the jump edge of the pulse input signal A), and selects a jump edge (for example, a rising edge) of the pulse input signal A as a jump edge (for example, a rising edge) of the widened pulse signal X that complies with the pulse design rules, and selects another jump edge (for example, a falling edge) of the delayed pulse signal B as another jump edge (for example, a falling edge) of the widened pulse signal X, thereby obtaining the widened pulse signal X. One transition edge (e.g., a rising edge) in the widened pulse signal X is consistent with one transition edge (e.g., a rising edge) of the pulse input signal A, and another transition edge (e.g., a falling edge) in the widened pulse signal X is consistent with another transition edge (e.g., a falling edge) of the delayed pulse signal B, and another transition edge (e.g., a falling edge) of the delayed pulse signal B is delayed from another transition edge (e.g., a falling edge) of the pulse input signal A. Based on this, one transition edge (e.g., a rising edge) in the widened pulse signal X is consistent with one transition edge (e.g., a rising edge) of the pulse input signal A, and another transition edge (e.g., a falling edge) in the widened pulse signal X is delayed from another transition edge (e.g., a falling edge) of the pulse input signal A, so that the pulse width (e.g., a positive pulse width) of the widened pulse signal X is larger than that of the pulse input signal A that causes the minimum pulse width violation. In the case where the pulse input signal A is a pulse signal with a pulse width violation (for example, the positive pulse width is too small), the pulse width (for example, the positive pulse width) of the widened pulse signal X obtained by using the minimum pulse width violation repair circuit of the embodiment of the present disclosure is greater than the pulse width of the pulse input signal A (for example, the positive pulse width is too small), so that the obtained widened pulse signal X may comply with the corresponding pulse design rules, thereby eliminating the pulse width violation.

[0068] To avoid the problem of glitches in the widened pulse signal X, in an exemplary embodiment, the pulse delay module 201 delays the transition edge of the pulse input signal A by a time delay that is smaller than the pulse width of the pulse input signal A.

[0069] In an illustrative embodiment, the pulse delay module 201 includes at least one buffer. The buffer is a basic circuit element, and its main function is to receive an input signal and convert it into an output signal of the same form, while providing a certain current driving capability. Although the buffer is intended to provide signal transmission without changing its logical state, in actual applications, the buffer will produce a certain delay, which can be called propagation delay. The embodiment of the present disclosure introduces pulse delay by adding a buffer. Depending on the pulse delay requirements, the number of buffers can be more than one. In an illustrative embodiment, when the number of buffers is at least two, the pulse delay module 201 includes at least one pulse delay branch connected between the pulse signal input line and the widening module, and each pulse delay branch includes at least one buffer. The time delay of each buffer to the input signal jump edge of the buffer itself is less than the pulse width of the input signal of the buffer itself. The pulse signal input line is used to transmit the pulse input signal.

[0070] Figure 3A is a circuit diagram showing a pulse delay module including a buffer according to an exemplary embodiment. Figure 3B is a circuit diagram showing a pulse delay module including a pulse delay branch according to an exemplary embodiment. Figure 3C FIG. 1 is a circuit diagram showing a pulse delay module including two pulse delay branches according to an exemplary embodiment. Figure 3A 、 Figure 3B and Figure 3C The following are only several schematic circuit structures of the pulse delay module 201 composed of buffers BUF. In actual applications, different numbers of buffers BUF and their connection structures can be set to form the pulse delay module 201 to meet the pulse delay module 201's delay requirements for the pulse input signal A. In order to avoid the problem of burrs S in the widened pulse signal X, the pulse delay module 201's time delay for the pulse input signal A's transition edge is less than the pulse width of the pulse input signal A. Figure 3B In the embodiment shown, the pulse delay module 201 has only one pulse delay branch, which constitutes the entire pulse delay module 201. Figure 3B In the embodiment, the pulse delay branch or the pulse delay module 201 is composed of two buffers BUF connected in series between the pulse signal input line and the widening module 202. The number of buffers BUF connected in series can be greater as needed. Figure 3C In the illustrated embodiment, the pulse delay module 201 is composed of two pulse delay branches. Figure 3CIn the figure, the upper pulse delay branch of the two pulse delay branches includes a buffer BUF, which is connected between the pulse signal input line and the widening module 202; the lower pulse delay branch of the two pulse delay branches includes two buffers BUF, which are connected in series between the pulse signal input line and the widening module 202; as needed, the number of pulse delay branches in the pulse delay module 201 can be set to more, and the number of buffers BUF in each pulse delay branch can also be set as needed.

[0071] In an exemplary embodiment, when the pulse delay module 201 includes at least two pulse delay branches, the numbers of buffers between the pulse delay branches are unequal.

[0072] In an illustrative embodiment, in the pulse delay module 201, an inverter can also be used to replace the buffer BUF. Among them, the inverter is a basic logic gate, and its main function is to flip the logic state of the signal, that is, to change the high level of the input signal to a low level, and vice versa. In actual applications, the inverter will produce a certain delay to the input signal due to the size, working area, switching time, etc. of its internal transistors. This delay is determined by the internal circuit characteristics of the inverter. In the related art, in order to avoid violations of the pulse signal, certain means are usually used to avoid the generation of delays in circuit units such as inverters. In the embodiment of the present disclosure, contrary to the related art, this delay is used to achieve the repair of pulse width violations.

[0073] Figure 4 is a circuit diagram showing a pulse delay module including two first inverters connected in series according to an exemplary embodiment. Figure 4 In the illustrated embodiment, the pulse delay module 201 includes two first inverters NOT1 connected in series between the pulse signal input line and the widening module 202. Because the function of the inverter is to flip the logic state of the signal, the pulse input signal A needs to be inverted an even number of times in order to obtain the delayed pulse signal B. Based on this, in the exemplary embodiment, the pulse delay module 201 includes an even number of first inverters NOT1 connected in series between the pulse signal input line and the widening module 202, wherein the pulse signal input line is used to transmit the pulse input signal A. Figure 4 and Figure 3A By comparison, it can be seen that, from the perspective of the delay effect of the pulse input signal A, the two first inverters NOT1 can be equivalent to a buffer BUF, that is, a buffer BUF can be replaced by two first inverters NOT1, and then Figure 3B 、 Figure 3C Each buffer BUF in can be replaced by two inverters.

[0074] Figure 5 FIG. 1 is a circuit diagram showing a widening module including an OR gate unit according to an exemplary embodiment, as shown in FIG. Figure 5 As shown, in the exemplary embodiment, the widening module 202 includes an OR gate unit OR, one input end of the OR gate unit OR receives the pulse input signal A, the other input end of the OR gate unit OR receives the delayed pulse signal B, and the output end of the OR gate unit OR outputs the widening pulse signal X. In the exemplary embodiment, one input end of the OR gate unit OR is electrically connected to the pulse signal input line to receive the pulse input signal A, and the other input end of the OR gate unit OR is electrically connected to the output end of the pulse delay module 201 to receive the delayed pulse signal B.

[0075] In the exemplary embodiment, the number of the other input terminals of the OR gate unit OR is equal to the number of the output terminals of the pulse delay module 201, and the other input terminals of the OR gate unit OR are connected one-to-one with the output terminals of the pulse delay module 201. Figure 3A 、 Figure 3B 、 Figure 4 The pulse delay module 201 shown includes an embodiment of an output terminal, and the other input terminal of the OR gate unit OR is one, thereby, the OR gate unit OR adopts a two-input OR gate unit; Figure 3C The pulse delay module 201 shown includes an embodiment with two output terminals, and the other input terminals of the OR gate unit OR are two. Therefore, the OR gate unit OR adopts a three-input OR gate unit.

[0076] Figure 6 FIG is a schematic diagram of a minimum pulse width violation repair circuit including a second inverter and a NAND gate unit according to an exemplary embodiment. Figure 6 As shown, in an illustrative embodiment, the minimum pulse width violation repair circuit of the embodiment of the present disclosure may further include a second inverter NOT2. The second inverter NOT2 obtains a pulse input signal A based on the inverted pulse signal A′, wherein the input end of the pulse delay module 201 is electrically connected to the output end of the second inverter NOT2. In an illustrative embodiment, the input end of the second inverter NOT2 is electrically connected to the pulse signal input line. Wherein, the widening module 202 includes a NAND gate unit NAND, one input end of the NAND gate unit NAND receives the pulse input signal A, the other input end of the NAND gate unit NAND receives the delayed pulse signal B, and the output end of the NAND gate unit NAND outputs the widened pulse signal X. In an illustrative embodiment, one input end of the NAND gate unit NAND is electrically connected to the output end of the second inverter NOT2 to receive the pulse input signal A, and the other input end of the NAND gate unit NAND is electrically connected to the output end of the pulse delay module 201 to receive the delayed pulse signal B.

[0077] above Figure 5 and Figure 6The embodiment shown can be used to widen the positive pulse width in a pulse signal that violates the minimum pulse width. Figure 5 The embodiment shown utilizes the cooperation of the OR gate unit OR and the pulse delay module 201 to achieve the widening of the positive pulse width in the pulse input signal A. Figure 6 The embodiment shown utilizes the cooperation of the second inverter NOT2 and the NAND gate unit NAND with the pulse delay module 201 to achieve the expansion of the positive pulse width in the inverted pulse signal A′ that violates the minimum pulse width.

[0078] Figure 7 FIG. 1 is a circuit diagram showing an expansion module including an AND gate unit according to an exemplary embodiment. Figure 7 As shown, in the exemplary embodiment, the widening module 202 includes an AND gate unit AND. One input terminal of the AND gate unit AND receives the pulse input signal A, the other input terminal of the AND gate unit AND receives the delayed pulse signal B, and the output terminal of the AND gate unit AND outputs the widening pulse signal X. In the exemplary embodiment, one input terminal of the AND gate unit AND is electrically connected to the pulse signal input line to receive the pulse input signal A, and the other input terminal of the AND gate unit AND is electrically connected to the output terminal of the pulse delay module 201 to receive the delayed pulse signal B.

[0079] In the exemplary embodiment, the number of the other input terminals of the AND gate unit AND is equal to the number of the output terminals of the pulse delay module 201, and the other input terminals of the AND gate unit AND are connected one-to-one with the output terminals of the pulse delay module 201. Figure 3A 、 Figure 3B 、 Figure 4 The pulse delay module 201 shown includes an embodiment of an output terminal, and the other input terminal of the AND gate unit AND is one, thereby, the AND gate unit AND adopts a two-input AND gate unit; Figure 3C The pulse delay module 201 shown includes an embodiment with two output terminals, and the other input terminals of the AND gate unit AND are two. Therefore, the AND gate unit AND adopts a three-input AND gate unit.

[0080] Figure 8 FIG is a schematic diagram of a minimum pulse width violation repair circuit including a second inverter and a NOR gate unit according to an exemplary embodiment. Figure 8As shown, in an illustrative embodiment, the minimum pulse width violation repair circuit of the embodiment of the present disclosure may further include a second inverter NOT2. The second inverter NOT2 obtains a pulse input signal A according to the inverted pulse signal A′, wherein the input end of the pulse delay module 201 is electrically connected to the output end of the second inverter NOT2. In an illustrative embodiment, the input end of the second inverter NOT2 is electrically connected to the pulse signal input line. Wherein, the widening module 202 includes a NOR gate unit NOR, one input end of the NOR gate unit NOR receives the pulse input signal A, the other input end of the NOR gate unit NOR receives the delayed pulse signal B, and the output end of the NOR gate unit NOR outputs the widened pulse signal X. In an illustrative embodiment, one input end of the NOR gate unit NOR is electrically connected to the output end of the NOT gate circuit to receive the pulse input signal A, and the other input end of the NOR gate unit NOR is electrically connected to the output end of the pulse delay module 201 to receive the delayed pulse signal B.

[0081] above Figure 7 and Figure 8 The embodiment shown can be used to widen the negative pulse width in a pulse signal that violates the minimum pulse width. Figure 7 The embodiment shown utilizes the cooperation of the AND gate unit AND and the pulse delay module 201 to achieve the widening of the negative pulse width in the pulse input signal A. Figure 8 The embodiment shown utilizes the cooperation of the second inverter NOT2 and the NOR gate unit NOR with the pulse delay module 201 to achieve the expansion of the negative pulse width in the inverted pulse signal A′ that violates the minimum pulse width.

[0082] The above is a description of the various components of the minimum pulse width violation repair circuit according to the embodiment of the present disclosure. The following is a supplementary description of the minimum pulse width violation repair circuit according to the present disclosure in combination with several specific circuit structures.

[0083] Figure 9A is a first specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment. Figure 9B yes Figure 9A The signal timing diagram of the circuit shown is as follows: Figure 9C This is a schematic diagram of the signal timing when glitches occur. Figure 9A As shown, the first specific circuit structure includes a buffer BUF and an OR gate unit OR, wherein the number of the buffer BUF is one, the input end of the buffer BUF (equivalent to the input end of the pulse delay module 201) is electrically connected to the pulse signal input line to receive the pulse input signal A that causes the minimum pulse width violation; the first input end of the OR gate unit OR, for example Figure 9AThe upper input terminal of the OR gate unit OR (equivalent to the first input terminal of the widening module 202) is electrically connected to the pulse signal input line to receive the pulse input signal A; the second input terminal of the OR gate unit OR, for example Figure 9A The lower input end of the OR gate unit OR (equivalent to the second input end of the widening module 202) is electrically connected to the output end of the buffer BUF (equivalent to the output end of the pulse delay module 201); the output end of the OR gate unit OR (equivalent to the output end of the widening module 202) is electrically connected to the pulse signal output line to output the widened pulse signal X that complies with the pulse design rules.

[0084] like Figure 9A 、 Figure 9B As shown, the delayed pulse signal B obtained by the pulse input signal A passing through the buffer BUF has a delayed rising and falling edge compared to the pulse input signal A. The pulse input signal A and the delayed pulse signal B are input to the OR gate unit OR. According to the truth table of the OR gate unit OR, when either the pulse input signal A or the delayed pulse signal B is at a high level, the widened pulse signal X is at a high level. Only when both the pulse input signal A and the delayed pulse signal B are at a low level, the widened pulse signal X is at a low level. Therefore, at the rising edge of the pulse input signal A (ahead of the rising edge of the delayed pulse signal B), the widened pulse signal X jumps from a low level to a high level. At the falling edge of the delayed pulse signal B (delayed from the falling edge of the pulse input signal A), the widened pulse signal X jumps from a high level to a low level. Therefore, compared to the pulse input signal A, the rising edge of the widened pulse signal X is substantially synchronized with the rising edge of the pulse input signal A, and the falling edge of the widened pulse signal X is delayed from the falling edge of the pulse input signal A. Therefore, the positive pulse width of the expanded pulse signal X is greater than the positive pulse width of the pulse input signal A. Figure 9A The first specific circuit shown plays a role in widening the positive pulse width of the pulse input signal A. When the positive pulse width of the pulse input signal A is too small and a minimum pulse width violation occurs, the minimum pulse width violation can be repaired by adding the first specific circuit.

[0085] Figure 9A In the first specific circuit shown, in order to avoid the problem of glitches in the widened pulse signal X, the time delay of the buffer BUF to the transition edge of the pulse input signal A is less than the positive pulse width of the pulse input signal A. Figure 9C This is the timing diagram obtained when the time delay of the pulse input signal A jump edge of the buffer BUF exceeds the positive pulse width of the pulse input signal A, as shown in Figure 9CAs shown, when the time delay of buffer BUF for the transition edge of pulse input signal A exceeds the positive pulse width of pulse input signal A, the rising edge of delayed pulse signal B is delayed after the falling edge of pulse input signal A. Consequently, between the falling edge of pulse input signal A and the rising edge of delayed pulse signal B, the widened pulse signal X will experience a brief level change, resulting in a glitch S. In addition to the positive pulse width, the problem of glitch generation in the widened pulse signal X can also occur when the time delay of buffer BUF for the transition edge of pulse input signal A exceeds the negative pulse width of pulse input signal A. Therefore, the time delay of buffer BUF for the transition edge of pulse input signal A must also be less than the negative pulse width of pulse input signal A. Therefore, it is necessary to control the time delay of buffer BUF for the transition edge of pulse input signal A to be less than the pulse width of pulse input signal A (including both the positive and negative pulse widths) to avoid the problem of glitch S in the widened pulse signal X.

[0086] Figure 10 FIG. 1 is a second specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment. Figure 10 As shown, the second specific circuit structure includes a buffer BUF and an OR gate unit OR, wherein the number of the buffer BUF is three, one buffer BUF constitutes a pulse delay branch in the pulse delay module 201, and the other two buffers BUF are connected in series to constitute another pulse delay branch in the pulse delay module 201. Figure 10 The OR gate unit OR in the second specific circuit needs to connect the two branches of the pulse delay module 201 and the pulse signal input line. The OR gate unit OR in the second specific circuit is a three-input OR gate unit OR. Among them, the first input terminal of the OR gate unit OR, for example Figure 10 The upper input terminal of the middle OR gate unit OR is electrically connected to the pulse signal input line to receive the pulse input signal A that causes the minimum pulse width violation; the second input terminal of the OR gate unit OR, for example Figure 10 The middle input terminal of the OR gate unit OR is electrically connected to a pulse delay branch formed by a buffer BUF; the third input terminal of the OR gate unit OR, for example Figure 10The lower input end of the OR gate unit OR is electrically connected to a pulse delay branch composed of two buffers BUF connected in series. In the exemplary embodiment, the pulse delay branches can be further increased as needed. Accordingly, the number of input ends of the OR gate unit OR needs to be determined according to the number of pulse signal input lines and pulse delay branches. In order to avoid the problem of glitches in the widened pulse signal X, the time delay of the pulse input signal A jump edge by a single buffer BUF in each pulse delay branch must be less than the pulse width of the pulse input signal A. Since multiple pulse delay branches are used and the delay of a single buffer BUF in each pulse delay branch is less than the pulse width of the input signal A, the generation of glitches is avoided. At the same time, the overall delay of the multiple pulse delay branches is increased (the width of the final pulse widening depends on the pulse delay branch with the largest delay).

[0087] Figure 11 FIG. 3 is a schematic diagram of a third specific circuit structure of a minimum pulse width violation repair circuit according to an exemplary embodiment. Figure 11 As shown, the third specific circuit structure includes a first inverter NOT1 and an OR gate unit OR, wherein the number of the first inverter NOT1 is two, and the two first inverters NOT1 are connected in series to the pulse signal input line and the second input end of the OR gate unit OR (for example Figure 11 The lower input terminal of the OR gate unit OR in the OR gate unit OR), the first input terminal of the OR gate unit OR (for example Figure 11 The upper input terminal of the OR gate unit OR in the circuit is electrically connected to the pulse signal input line to receive the pulse input signal A that causes the minimum pulse width violation. The output terminal of the OR gate unit OR is electrically connected to the pulse signal output line to output the widened pulse signal X that complies with the pulse design rule. In this third specific circuit, the pulse input signal A that causes the minimum pulse width violation is inverted twice by two first inverters NOT1 before entering the OR gate unit OR. The two first inverters NOT1 act as a buffer BUF, delaying the pulse input signal A. Based on this, in other circuit embodiments using buffers BUF, each buffer BUF can be replaced by two first inverters NOT1.

[0088] Figure 12A FIG. 4 is a schematic diagram of a fourth specific circuit structure of a minimum pulse width violation repair circuit according to an exemplary embodiment. Figure 12AAs shown, the fourth specific circuit structure includes a second inverter NOT2, a buffer BUF and a NAND gate unit NAND. The input end of the second inverter NOT2 is electrically connected to the pulse signal input line to receive the inverted pulse signal A' that causes the minimum pulse width violation in the pulse signal input line and obtain the pulse input signal A according to the inverted pulse signal A'. Because the second inverter NOT2 only performs an inverting operation on the inverted pulse signal, the obtained pulse input signal A is also the pulse input signal A that causes the minimum pulse width violation; the input end of the buffer BUF is electrically connected to the output end of the second inverter NOT2 to receive the pulse input signal A and delay the pulse input signal A to obtain the delayed pulse signal B; the first input end of the NAND gate unit NAND (for example Figure 12A The upper input terminal of the NAND gate unit NAND) is electrically connected to the output terminal of the second inverter NOT2 to receive the pulse input signal A. The second input terminal of the NAND gate unit NAND (for example Figure 12A The lower input terminal of the NAND gate unit (NAND) is electrically connected to the output terminal of the buffer BUF to receive the delayed pulse signal B. The output terminal of the NAND gate unit (NAND) is electrically connected to the pulse signal output line. The NAND gate unit (NAND) generates an expanded pulse signal X that complies with the pulse design rules based on the pulse input signal A and the delayed pulse signal B, and outputs the expanded pulse signal X through the pulse signal output line. To avoid glitches in the expanded pulse signal X, the time delay of the transition edge of the pulse input signal A by the buffer BUF must be less than the positive pulse width of the inverted pulse signal A′ (i.e., the negative pulse width of the pulse input signal A).

[0089] Figure 12B yes Figure 12A The signal timing diagram of the circuit shown is as follows: Figure 12A 、 Figure 12BAs shown, the inverted pulse signal A' passes through the second inverter NOT2 to generate the pulse input signal A. The pulse input signal A passes through the buffer BUF to generate the delayed pulse signal B, which has both its rising and falling edges delayed compared to the pulse input signal A. The pulse input signal A and the delayed pulse signal B are input to the NAND gate unit NAND. According to the truth table of the NAND gate unit NAND, the output signal of the NAND gate unit NAND is low only when all input signals of the NAND gate unit NAND are high. As long as at least one input signal is low, the output signal of the NAND gate unit NAND is high. Therefore, when either the pulse input signal A or the delayed pulse signal B is low, the widened pulse signal X is high. Only when both the pulse input signal A and the delayed pulse signal B are high does the widened pulse signal X go low. Therefore, at the rising edge of the inverted pulse signal A', that is, the falling edge of the pulse input signal A (ahead of the falling edge of the delayed pulse signal B), the widened pulse signal X jumps from a low level to a high level. At the rising edge of the delayed pulse signal B (delayed from the falling edge of the inverted pulse signal A' and the rising edge of the pulse input signal A), the widened pulse signal X jumps from a high level to a low level. Therefore, compared with the inverted pulse signal A', the rising edge of the widened pulse signal X is basically synchronized with the rising edge of the inverted pulse signal A', and the falling edge of the widened pulse signal X is delayed from the falling edge of the inverted pulse signal A'. Therefore, the positive pulse width of the widened pulse signal X is greater than the positive pulse width of the inverted pulse signal A'. Figure 12A The fourth specific circuit shown plays a role in widening the positive pulse width of the inverted pulse signal A′. When the positive pulse width of the inverted pulse signal A′ is too small and a minimum pulse width violation occurs, the minimum pulse width violation can be repaired by adding the fourth specific circuit.

[0090] The first specific circuit, the second specific circuit, the third specific circuit and the fourth specific circuit are aimed at widening the positive pulse width.

[0091] Figure 13A is a fifth specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment. Figure 13B yes Figure 13A The signal timing diagram of the circuit shown in Figure 1 is as follows. Figure 13A As shown, the fifth specific circuit structure includes a buffer BUF and an AND gate unit AND, wherein the number of the buffer BUF is one, the input end of the buffer BUF (equivalent to the input end of the pulse delay module 201) is electrically connected to the pulse signal input line to receive the pulse input signal A that causes the minimum pulse width violation; the first input end of the AND gate unit AND, for example Figure 13AThe upper input terminal of the AND gate unit AND (equivalent to the first input terminal of the widening module 202) is electrically connected to the pulse signal input line to receive the pulse input signal A; the second input terminal of the AND gate unit AND, for example Figure 13A The lower input end of the AND gate unit AND (equivalent to the second input end of the widening module 202) is electrically connected to the output end of the buffer BUF (equivalent to the output end of the pulse delay module 201); the output end of the AND gate unit AND (equivalent to the output end of the widening module 202) is electrically connected to the pulse signal output line to output the widened pulse signal X that complies with the pulse design rules.

[0092] like Figure 13A 、 Figure 13B As shown in the figure, the delayed pulse signal B obtained by the pulse input signal A passing through the buffer BUF has a delayed falling edge and a delayed rising edge compared to the pulse input signal A. The pulse input signal A and the delayed pulse signal B are input to the AND gate unit AND. According to the truth table of the AND gate unit AND, the output signal of the AND gate unit AND is high only when all the input signals of the AND gate unit AND are high. As long as at least one input signal is low, the output signal of the AND gate unit AND is low. Therefore, the expanded pulse signal X is high only when both the pulse input signal A and the delayed pulse signal B are high. When either the pulse input signal A or the delayed pulse signal B is low, the expanded pulse signal X is low. Therefore, at the falling edge of the pulse input signal A (ahead of the falling edge of the delayed pulse signal B), the expanded pulse signal X drops from a high level to a low level. At the rising edge of the delayed pulse signal B (delayed from the rising edge of the pulse input signal A), the expanded pulse signal X jumps from a low level to a high level. Thus, compared to the pulse input signal A, the falling edge of the expanded pulse signal X is substantially synchronized with the falling edge of the pulse input signal A, and the rising edge of the expanded pulse signal X is delayed from the rising edge of the pulse input signal A. Therefore, the negative pulse width of the expanded pulse signal X is greater than the negative pulse width of the pulse input signal A. Figure 13A The fifth specific circuit shown plays a role in widening the negative pulse width of the pulse input signal A. When the negative pulse width of the pulse input signal A is too small and a minimum pulse width violation occurs, the minimum pulse width violation can be repaired by adding the fifth specific circuit. Figure 13A In the fifth specific circuit shown, in order to avoid the problem of burrs S in the widened pulse signal X, the time delay of the buffer BUF to the transition edge of the pulse input signal A is less than the negative pulse width of the pulse input signal A.

[0093] Figure 14 FIG. 6 is a sixth specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment. Figure 14As shown, the sixth specific circuit structure includes a buffer BUF and an AND gate unit AND, wherein the number of the buffer BUF is three, one buffer BUF constitutes a pulse delay branch in the pulse delay module 201, and the other two buffers BUF are connected in series to constitute another pulse delay branch in the pulse delay module 201. Figure 14 The AND gate unit AND in the sixth specific circuit needs to connect the two branches of the pulse delay module 201 and the pulse signal input line. The AND gate unit AND in the sixth specific circuit is a three-input AND gate unit AND. Among them, the first input terminal of the AND gate unit AND, for example Figure 14 The upper input terminal of the AND gate unit AND is electrically connected to the pulse signal input line to receive the pulse input signal A that causes the minimum pulse width violation; the second input terminal of the AND gate unit AND, for example Figure 14 The middle input terminal of the AND gate unit AND is electrically connected to a pulse delay branch formed by a buffer BUF; the third input terminal of the AND gate unit AND, for example Figure 14 The lower input end of the AND gate unit AND is electrically connected to a pulse delay branch composed of two buffers BUF connected in series. In the exemplary embodiment, the pulse delay branches can be further increased as needed. Accordingly, the number of input ends of the AND gate unit AND needs to be determined according to the number of pulse signal input lines and pulse delay branches. In order to avoid the problem of glitches in the widened pulse signal X, the time delay of each pulse delay branch to the transition edge of the pulse input signal A must be less than the pulse width of the pulse input signal A. Since multiple pulse delay branches are used and each pulse delay branch has a single buffer BUF, the overall delay of the multiple pulse delay branches is increased (the width of the final pulse widening depends on the pulse delay branch with the largest delay), thereby avoiding the generation of glitches.

[0094] Figure 15A FIG. 7 is a seventh specific circuit structure diagram of a minimum pulse width violation repair circuit according to an exemplary embodiment. Figure 15A As shown, the fourth specific circuit structure includes a second inverter NOT2, a buffer BUF and a NOR gate unit NOR. The input end of the second inverter NOT2 is electrically connected to the pulse signal input line to receive the inverted pulse signal A' that causes the minimum pulse width violation in the pulse signal input line and obtain the pulse input signal A according to the inverted pulse signal A'. Because the second inverter NOT2 only performs an inverting operation on the inverted pulse signal, the obtained pulse input signal A is also the pulse input signal A that causes the minimum pulse width violation; the input end of the buffer BUF is electrically connected to the output end of the second inverter NOT2 to receive the pulse input signal A and delay the pulse input signal A to obtain the delayed pulse signal B; the first input end of the NOR gate unit NOR (for example Figure 15AThe upper input terminal of the NOR gate unit NOR) is electrically connected to the output terminal of the second inverter NOT2 to receive the pulse input signal A. The second input terminal of the NOR gate unit NOR (eg Figure 15A The lower input terminal of the NOR gate unit (NOR) is electrically connected to the output terminal of the buffer BUF to receive the delayed pulse signal B. The output terminal of the NOR gate unit NOR is electrically connected to the pulse signal output line. The NOR gate unit NOR generates an expanded pulse signal X that complies with the pulse design rules based on the pulse input signal A and the delayed pulse signal B, and outputs the expanded pulse signal X through the pulse signal output line. To avoid glitches in the expanded pulse signal X, the time delay of the transition edge of the pulse input signal A by the buffer BUF must be less than the negative pulse width of the inverted pulse signal A′ (i.e., the positive pulse width of the pulse input signal A).

[0095] Figure 15B yes Figure 15A The signal timing diagram of the circuit shown is as follows: Figure 15A 、 Figure 15B As shown, the inverted pulse signal A' passes through the second inverter NOT2 to generate the pulse input signal A. The pulse input signal A passes through the buffer BUF to generate the delayed pulse signal B, which has both its falling and rising edges delayed compared to the pulse input signal A. The pulse input signal A and the delayed pulse signal B are then input to the NOR gate unit NOR. According to the truth table for the NOR gate unit NOR, the output signal of the NOR gate unit NOR is high only when all input signals are low. As long as at least one input signal is high, the output signal of the NOR gate unit NOR is low. Therefore, when either the pulse input signal A or the delayed pulse signal B is high, the widened pulse signal X is low. The widened pulse signal X is high only when both the pulse input signal A and the delayed pulse signal B are low. Therefore, at the falling edge of the inverted pulse signal A', that is, the rising edge of the pulse input signal A (ahead of the rising edge of the delayed pulse signal B), the widened pulse signal X jumps from a high level to a low level. At the falling edge of the delayed pulse signal B (delayed from the rising edge of the inverted pulse signal A' and the falling edge of the pulse input signal A), the widened pulse signal X jumps from a low level to a high level. Thus, compared with the inverted pulse signal A', the falling edge of the widened pulse signal X is substantially synchronized with the falling edge of the inverted pulse signal A', and the rising edge of the widened pulse signal X is delayed from the rising edge of the inverted pulse signal A'. Therefore, the negative pulse width of the widened pulse signal X is greater than the negative pulse width of the inverted pulse signal A'. Figure 15A The seventh specific circuit shown plays a role in widening the negative pulse width of the inverted pulse signal A′. When the negative pulse width of the inverted pulse signal A′ is too small and a minimum pulse width violation occurs, the minimum pulse width violation can be repaired by adding the seventh specific circuit.

[0096] The fifth, sixth and seventh specific circuits are designed to extend the negative pulse width.

[0097] The minimum pulse width violation repair circuit of the disclosed embodiment first delays the generation time of the transition edge of the pulse input signal A that causes the minimum pulse width violation. Then, referring to the transition edge of the pulse input signal A and the transition edge of the delayed pulse signal B, it selects one transition edge of the pulse input signal A as the rising edge of the widened pulse signal X that complies with the pulse design rules, and selects another transition edge of the delayed pulse signal B as the falling edge of the widened pulse signal X, thereby obtaining the widened pulse signal X. One transition edge in the widened pulse signal X coincides with one transition edge of the pulse input signal A, and another transition edge in the widened pulse signal X coincides with another transition edge of the delayed pulse signal B. Because the other transition edge of the delayed pulse signal B is delayed from the other transition edge of the pulse input signal A that causes the minimum pulse width violation, the pulse width of the widened pulse signal X is larger than that of the pulse input signal A. The minimum pulse width violation repair circuit of the disclosed embodiment can eliminate the pulse width violation of the pulse signal that causes the minimum pulse width violation.

[0098] The minimum pulse width violation repair circuit of the embodiment of the present disclosure has simple circuit structure, is easy to implement, and has good effect in repairing minimum pulse width violation. When the minimum pulse width violation repair circuit of the embodiment of the present disclosure is used, the data model of the minimum pulse width violation repair circuit of the embodiment of the present disclosure can be stored in advance before the minimum pulse width violation repair is performed, and is called when the minimum pulse width violation repair is performed. Compared with the related minimum pulse width violation repair scheme, the minimum pulse width violation repair circuit of the embodiment of the present disclosure can obtain basically determined pulse width improvement and benefit in repairing the minimum pulse width violation. In the case that the difference between the pulse width value of the minimum pulse width violation and the pulse width specified by the pulse design rule is large, the repair effect of the minimum pulse width violation can be further enhanced by connecting multiple minimum pulse width violation repair circuits of the embodiment of the present disclosure, and the minimum pulse width violation can be completely repaired. The structure of the minimum pulse width violation repair circuit of the embodiment of the present disclosure can be packaged or customized as a standard minimum pulse width violation repair unit module, which can be directly called by using a general ECO method and quantitatively analyzed by using a static timing analysis (STA) tool, and can be completely compatible with a related timing sign-in process. The static timing analysis is an important timing verification technology in digital circuit design, which is used to evaluate and verify whether there is a timing problem in a data path of an integrated circuit, such as a setup time violation, a hold time violation, a clock skew, and a clock period problem.

[0099] In the illustrative embodiment, the embodiment of the present disclosure also provides a minimum pulse width violation repair method, which comprises:

[0100] Obtaining the circuit causing the pulse width violation from the pulse width violation information;

[0101] Adding the minimum pulse width violation repair circuit in any of the above embodiments to the circuit causing the pulse width violation.

[0102] Figure 16 is Figure 9A the simulation waveform diagram of the first specific circuit structure of Figure 9A The first specific circuit structure is simulated, and the simulation is under a 6nm process, wherein a related semiconductor device uses an ultra-low threshold voltage field effect transistor (ULVT MOSFET). Under the conditions of a typical process angle, a power supply voltage of 0.7V, and a temperature of 85℃, the simulation waveform is Figure 16As shown, the positive pulse width of the pulse input signal A is 375 ps (picoseconds), and the positive pulse width of the obtained expanded pulse signal X is 390 ps, ​​and the positive pulse width is expanded by 15 ps.

[0103] In integrated circuit technology, process corners refer to the varying performance variations of transistors caused by fluctuations in process parameters during semiconductor manufacturing. Process corners are used to help designers account for these performance variations during IC design, ensuring that the designed circuit will function properly under a wide range of possible performance conditions. A typical process corner is TT (Typical NMOS and Typical PMOS), representing the combination of typical NMOS and typical PMOS transistors and representing an average performance level. In addition to TT, process corners typically include SS (Slow NMOS and Slow PMOS) and FF (Fast NMOS and Fast PMOS). SS, representing the combination of slow NMOS and slow PMOS, represents the worst-case scenario for transistor performance; FF, representing the combination of fast NMOS and fast PMOS, represents the best-case scenario for transistor performance. During IC design, simulations are performed for different process corners to ensure that the circuit meets performance requirements under both worst-case and best-case scenarios. This approach can mitigate the impact of process fluctuations on circuit performance to a certain extent, improving the robustness, yield, and reliability of integrated circuits.

[0104] Figure 17 1 is a structural diagram of an electronic device provided by an embodiment of the present disclosure. In some embodiments, the electronic device is a server. The electronic device 1700 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 1701 and one or more memories 1702, wherein at least one program code is stored in the memory 1702, and the at least one program code is loaded and executed by the processor 1701 to implement the minimum pulse width violation repair method provided by the above-mentioned various embodiments. Of course, the electronic device 1700 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The electronic device 1700 may also include other components for implementing device functions, which will not be described in detail here.

[0105] In an exemplary embodiment, a computer-readable storage medium including at least one instruction is also provided, such as a memory including at least one instruction. The at least one instruction can be executed by a processor in a computer device to complete the minimum pulse width violation repair method in the above embodiment.

[0106] Optionally, the above-mentioned computer-readable storage medium may be a non-temporary computer-readable storage medium. For example, the non-temporary computer-readable storage medium may include ROM (Read-Only Memory), RAM (Random-Access Memory), CD-ROM (Compact Disc Read-Only Memory), magnetic tape, floppy disk and optical data storage device, etc.

[0107] In an exemplary embodiment, a computer program product is further provided, including a computer program. When the computer program is executed by a processor, the minimum pulse width violation repair method provided by each of the above embodiments is implemented.

[0108] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A method for repairing a minimum pulse width violation, comprising: The structure of the minimum pulse width violation repair circuit is packaged or custom-designed into a minimum pulse width violation repair unit module for pre-storage, wherein the minimum pulse width violation repair circuit includes: a pulse delay module, which delays the generation time of the pulse input signal jump edge causing the minimum pulse width violation to obtain a delayed pulse signal; and a widening module, which obtains a widened pulse signal that complies with pulse design rules based on the pulse input signal and the delayed pulse signal; wherein the data model of the minimum pulse width violation repair circuit is pre-stored and called when the minimum pulse width violation is repaired; wherein the pulse design rules are design criteria and standards followed in the integrated circuit design process and are not restrictions on the use stage of the integrated circuit; From the pulse width violation information, a circuit generating the pulse width violation is obtained; In the circuit generating the pulse width violation, the minimum pulse width violation repair unit module is added using an ECO method call.

2. The minimum pulse width violation repair method according to claim 1, wherein: The time delay of the pulse delay module for the transition edge of the pulse input signal is smaller than the pulse width of the pulse input signal.

3. The minimum pulse width violation repair method according to claim 2, wherein: The pulse delay module includes at least one buffer. When the number of the buffers is at least two, the pulse delay module includes at least one pulse delay branch connected between the pulse signal input line and the widening module, and each of the pulse delay branches includes at least one buffer; wherein, the time delay of each buffer to the transition edge of the input signal of the buffer itself is less than the pulse width of the input signal of the buffer itself, wherein the pulse signal input line is used to transmit the pulse input signal.

4. The minimum pulse width violation repair method according to claim 1, wherein: The pulse delay module includes an even number of first inverters connected in series between a pulse signal input line and the widening module, wherein the pulse signal input line is used to transmit the pulse input signal.

5. The minimum pulse width violation repair method according to claim 1, wherein: The widening module includes an OR gate unit, one input end of the OR gate unit receives the pulse input signal, the other input end of the OR gate unit receives the delayed pulse signal, and the output end of the OR gate unit outputs the widened pulse signal.

6. The minimum pulse width violation repair method according to claim 5, wherein: The number of the other input terminals of the OR gate unit is equal to the number of the output terminals of the pulse delay module, and the other input terminals of the OR gate unit are respectively connected one-to-one with the output terminals of the pulse delay module.

7. The minimum pulse width violation repair method according to claim 1, wherein: The minimum pulse width violation repair circuit further includes: a second inverter, wherein the second inverter obtains the pulse input signal according to the inverted pulse signal; The widening module includes a NAND gate unit, one input end of the NAND gate unit receives the pulse input signal, the other input end of the NAND gate unit receives the delayed pulse signal, and the output end of the NAND gate unit outputs the widening pulse signal.

8. The minimum pulse width violation repair method according to claim 1, wherein: The widening module includes an AND gate unit, one input end of the AND gate unit receives the pulse input signal, the other input end of the AND gate unit receives the delayed pulse signal, and the output end of the AND gate unit outputs the widening pulse signal.

9. The minimum pulse width violation repair method according to claim 8, wherein: The number of the other input terminals of the AND gate unit is equal to the number of the output terminals of the pulse delay module, and the other input terminals of the AND gate unit are respectively connected one-to-one with the output terminals of the pulse delay module.

10. The minimum pulse width violation repair method according to claim 1, wherein: The minimum pulse width violation repair circuit further includes: a second inverter, wherein the second inverter obtains the pulse input signal according to the inverted pulse signal; The widening module includes a NOR gate unit, one input end of the NOR gate unit receives the pulse input signal, the other input end of the NOR gate unit receives the delayed pulse signal, and the output end of the NOR gate unit outputs the widening pulse signal.

11. An electronic device, characterized in that: include: processor; a memory for storing executable instructions for the processor; The processor is configured to execute the executable instructions to implement the minimum pulse width violation repair method according to any one of claims 1 to 10.

12. A computer-readable storage medium, characterized in that When at least one instruction in the computer-readable storage medium is executed by a processor of an electronic device, the electronic device is enabled to implement the minimum pulse width violation repair method according to any one of claims 1 to 10.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the minimum pulse width violation repair method according to any one of claims 1 to 10 is implemented.

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