Conversion circuit

Abstract

To provide a conversion circuit that can reduce the layout area occupied by a latch circuit.SOLUTION: An A / D conversion circuit 1 converts an analog input signal Vin into numerical data using a pulse delay circuit 2, which is made up of multiple delay units DU connected in series, each of which inverts and delays a pulse signal to output it. Master latch circuits 21m, ..., and 24m hold the states of the delayed pulse group outputs P1, P2, P3, ..., and Pn output from the pulse delay circuit 2 using different clocks CK1, ..., and CK4. The slave latch circuits 21s, ..., and 24s hold the outputs of the master latch circuits 21m, ..., and 24m using a clock CK1.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a conversion circuit that converts an analog input signal into numerical data using a pulse delay circuit that is made up of a plurality of connected pulse delay units that delay and output pulse signals. [Background technology]

[0002] Conventionally, A / D conversion circuits have been developed to acquire high-resolution digital values ​​and numerical data while simplifying their configuration (see, for example, Patent Document 1). The A / D conversion device described in Patent Document 1 forms a pulse delay circuit consisting of a plurality of delay units, each consisting of various gate circuits, connected in cascade, and supplies an analog input signal to be A / D converted to this delay unit as a power supply voltage, thereby forming a time-domain processing A / D conversion circuit.

[0003] In the A / D conversion method employed in Patent Document 1, a pulse delay circuit with delay units arranged in a ring transmits a pulse signal, with the pulse signal propagating at a speed corresponding to the pulse signal delay time, which depends on the power supply voltage of each delay unit.The analog input signal is converted into numerical data by counting the number of delay units through which the pulse signal passes within a predetermined sampling time.The A / D conversion circuit described in Patent Document 1 is called a clock edge shift (CKES) type TAD (Time-A / D converter) A / D conversion circuit, sometimes abbreviated as CKES-TAD. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-007385 Summary of the Invention [Problem to be solved by the invention]

[0005] The A / D conversion circuit described in Patent Document 1 is configured to have multiple latch circuits that operate on multiple m (e.g., four) sampling clocks as pulse position reading and holding units, and each of these latch circuits controls the address of an encoder that digitizes the pulse position.

[0006] This A / D conversion circuit uses master-slave D flip-flops as latch circuits, which operate independently using multiple sampling clocks. However, each operates using an independent clock signal. This increases the number of clock wires, which increases the layout area occupied by the latch circuit. As a result, the circuit area occupied on the IC chip increases.

[0007] In other words, the large layout area occupied by the latch circuit results in longer read wiring for the delayed pulse group, which increases the parasitic components due to parasitic capacitance and parasitic resistance. As a result, the rise time of the latch input signal increases, dulling the delayed pulse output waveform and causing the latch circuit to operate unstably. The miniaturization of CMOS process manufacturing technology can sometimes hinder the performance improvement effect of the A / D conversion circuit.

[0008] An object of the present invention is to provide a conversion circuit that can reduce the layout area occupied by a latch circuit. [Means for solving the problem]

[0009] The invention described in claim 1 is a conversion circuit that converts an analog input signal into numerical data using a pulse delay circuit that is configured by connecting multiple delay units in series to delay and output pulse signals, and outputs a group of delayed pulses from the delay units.

[0010] Each of the plurality of latch circuits includes a master latch circuit and a slave latch circuit. The master latch circuit holds the output states of the delayed pulse groups output from the pulse delay circuit using first clocks that are different from each other. The slave latch circuit holds the output of the master latch circuit using a second clock. The conversion unit converts the output data of the multiple slave latch circuits into numerical data.

[0011] Since multiple latch circuits are used, increases in circuit area and power consumption can be suppressed without increasing the number of pulse delay circuits or the number of delay units within the pulse delay circuits. At this time, at least two of the multiple slave latch circuits commonly input a second clock based on the first clock to hold output data. Because the slave latch circuits commonly input a second clock based on the first clock and output data, wiring for the second clock based on the wiring for the first clock can be used, significantly reducing the number of clock wirings. This allows the layout area occupied by the latch circuits to be reduced. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a block diagram showing a partial configuration of an A / D conversion circuit according to a first embodiment; [Figure 2] FIG. 1 is an electrical configuration diagram illustrating a clock generation circuit used in a first embodiment. [Figure 3] 2 is a block diagram showing a partial configuration of the A / D conversion circuit according to the first embodiment; [Figure 4] Electrical configuration and connection wiring diagram of a latch circuit according to a first embodiment [Figure 5] Electrical configuration diagram of a master-slave latch circuit used in the first embodiment [Figure 6] 1 is a timing chart illustrating the operation of a latch circuit according to a first embodiment; [Figure 7] Electrical configuration and connection wiring diagram of a latch circuit according to a comparative example [Figure 8] Electrical configuration diagram of a master-slave latch circuit used in the second embodiment [Figure 9]FIG. 1 is a block diagram showing a partial configuration of an A / D conversion circuit according to a third embodiment; [Figure 10] 10 is a time chart illustrating the operation of the latch circuit according to the third embodiment; [Figure 11] 2 is a block diagram showing a partial configuration of an A / D conversion circuit according to the third embodiment; DETAILED DESCRIPTION OF THE INVENTION

[0013] Several embodiments of the conversion circuit will be described below with reference to the drawings. In each embodiment, substantially identical or similar parts are designated by the same or similar reference numerals, for example, the same reference numerals are assigned to the ones and tens digits and a different reference numeral is assigned to the hundreds digit, and descriptions thereof will be omitted as necessary. In each embodiment, the description will focus on the characteristic parts.

[0014] (First embodiment) A first embodiment will be described with reference to Fig. 1 to Fig. 7. Fig. 1 to Fig. 5 schematically show a time A / D (Time Analog to Digital Converter) type A / D conversion circuit 1. The A / D conversion circuit 1 is configured using a CMOS manufacturing process inside a semiconductor integrated circuit device such as a microcomputer mounted on an automotive electronic control unit (hereinafter referred to as ECU) or a sensor product having a digital communication function with the ECU, an SoC (System On Chip) of a 5G communication device, or an IoT application system.

[0015] 1 and 3, the A / D conversion circuit 1 includes a pulse delay circuit 2, a clock generation circuit 3, a pulse position digitization unit 4, and an adder 5. The A / D conversion circuit 1 receives an analog input signal Vin output from a sensor or the like, converts the analog input signal Vin into digital numerical data DTA, and outputs the digital numerical data DTA. The pulse position digitization unit 4 is called an L&E / S (Latch-&-Encoder and Subtractor).

[0016] <Configuration of pulse delay circuit 2> The pulse delay circuit 2 is called a ring delay line and is configured by serially arranging n delay units DU, which invert and delay pulses in a ring shape and output them, where n is an odd number, for example 15.

[0017] The delay units DU are composed of gates G1 to Gn, which each delay a pulse by a predetermined delay time Td and output the pulse. Therefore, in the following description, one or more delay units will be referred to as "DU," or as "G1" ... "Gn." The pulse delay circuit 2 is configured to output the output of each delay unit DU to a pulse position digitization unit 4.

[0018] An analog input signal Vin to be A / D converted is input as a power supply voltage to each of the gates G1 to Gn, and each of the gates G1 to Gn outputs a signal that changes in accordance with this analog input signal Vin. Any gates whose delay time Td changes in accordance with the analog input signal Vin can be used for each of the gates G1 to Gn, but it is preferable to configure each of the gates G1 to Gn using a NAND gate G1 and NOT gates G2...Gn, as shown in Figure 1.

[0019] An even number of NOT gates G2 to Gn shown in FIG. 1 are connected in cascade, and the NAND gate G1 receives the signal EN as an input and is connected so as to receive the output of the NOT gate Gn at the final stage.

[0020] The NOT gates G2 to G15 are configured using a single-stage CMOS inverter in order to simplify the circuit configuration and to shorten the delay time Td as much as possible to increase the time resolution.

[0021] When the signal EN is switched from L level to H level, the outputs of the odd-numbered NAND gate G1, NOT gates G3, G5, etc. are switched from H level to L level, and the outputs of the even-numbered NOT gates G2, G4, etc. are switched from L level to H level.

[0022] The delay units DU are configured in a loop with an odd number of stages in total, so the timing of switching from L level to H level and from H level to L level moves sequentially. By using this configuration, the circulation speed of the pulse can be changed in response to changes in the analog input signal Vin.

[0023] <Configuration of clock generation circuit 3> As shown in Fig. 2, the clock generation circuit 3 is configured with an inverter M1 connected in the front stage and inverters M2a...M2d connected in parallel in the rear stage, thereby outputting multiple sampling clocks CK1...CKm. Hereinafter, the sampling clocks CK1...CKm will be abbreviated as "clocks CK1...CKm." Note that this embodiment shows a configuration where m=4. In the configuration of Fig. 2, the inverter M1 is the first stage and the inverters M2a...M2d are the second stage.

[0024] An analog input signal Vin is applied as a power supply voltage to these multiple stages of inverters M1, M2a...M2d. A clock generation circuit 3 generates multiple clocks CK1...CKm based on a sampling clock reference signal CKs input as a reference clock / master clock. The sampling clock reference signal CKs is the main sampling clock input from outside.

[0025] The first-stage inverter M1 receives the sampling clock reference signal CKs, transmits pulses, and outputs them to the second-stage inverters M2a...M2d, which also transmit and output pulses. The inverters M2a...M2d have p-channel and n-channel transistors with different gate widths and lengths, which relatively changes the rise delay time difference ΔTs of the clock edges. The clocks CK1, CK2...CKm are adjusted so that the rise times of the clock edges are delayed in this order.

[0026] Furthermore, the period Ts of the clocks CK1...CKm is set to a time longer than the delay time Td of each delay unit DU, for example, a constant time several times or more the delay time Td of one delay unit DU. Each clock CK1...CKm is set so that four times (=m times) the phase difference time Δt (see FIG. 6) between adjacent clocks is equal to the delay time Td.

[0027] <Configuration of pulse position digitization unit 4> 1, the pulse position digitizing unit 4 includes a NOT gate 20, latch circuits 21...24, and encoders 31...34. Also, as shown in FIG. 3, the pulse position digitizing unit 4 includes latches 41...44 and subtractors 51...54.

[0028] 1 is provided with n NOT gates 20, each receiving outputs P1...Pn from n delay units DU. The inputs of latch circuits 21...24 are commonly connected to the outputs of the NOT gates 20, and n sets of latch circuits 21...24 are provided, the same number as the outputs P1...Pn of the delayed pulse groups from the delay units DU. M latch circuits 21...24 are provided per set.

[0029] By providing m sets of latch circuits 21...24 in parallel for each of the outputs P1...Pn, it is possible to hold each output P1...Pn at the timing of +Δt, +Δt×2, +Δt×3, or +Δt×4, which is obtained by further dividing the delay time Td of the delay unit DU by 1 / m. Therefore, by parallelizing the latch circuits 21...24 and holding the outputs P1...Pn at the generation timing of each different clock CK1...CK4, it is possible to improve the time resolution without increasing the number of pulse delay circuits 2 or the number n of delay units DU within the pulse delay circuit 2.

[0030] The plurality of latch circuits 21...24 are configured to hold the outputs P1...Pn of the n delay units DU via a NOT gate 20. These plurality of latch circuits 21...24 are configured by cascading master latch circuits 21m...24m and slave latch circuits 21s...24s, respectively, and latch the states of the outputs P1, P2,..., Pn of the delayed pulse group output from the pulse delay circuit 2 via the NOT gate 20 at the generation timings of m clocks CK1...CKm.

[0031] In particular, the master latch circuits 21m...24m hold the states of the outputs P1, P2,..., Pn of the delayed pulse group using different clocks CK1...CK4. These clocks CK1...CK4 correspond to the first clock. The slave latch circuits 21s...24s hold the outputs Dm1...Dm4 of the master latch circuits 21m...24m at the generation timing of the clock CK1. That is, the slave latch circuits 21s...24s hold the outputs at the generation timing of the clock CK1, which is included as part of the clocks CK1...CK4. The clock CK1 used by the slave latch circuits 21s...24s corresponds to the second clock. Specific examples will be described later.

[0032] A total of m encoders 31...34 are provided. In this embodiment, four encoders 31...34 are provided. The encoder 31 encodes output data Do1, which is obtained by holding the outputs P1...Pn in the latch circuit 21, at the generation timing of the sampling clock reference signal CKs. The encoder 32 encodes output data Do2, which is obtained by holding the outputs P1...Pn in the latch circuit 22, at the generation timing of the sampling clock reference signal CKs. The encoder 33 encodes output data Do3, which is obtained by holding the outputs P1...Pn in the latch circuit 23, at the generation timing of the sampling clock reference signal CKs.

[0033] The encoder 34 encodes the output data Do4, which is obtained by holding the outputs P1...Pn in the latch circuit 24, at the timing of generation of the sampling clock reference signal CKs. At this time, the encoders 31...34 use the sampling clock reference signal CKs, which is the source of generating the clocks CK1...CKm, as the clock for reading the output data Do1...Do4 of the latch circuits 21...24. This allows the encoders 31...34 to digitize and output the arrival position of the pulse transmitted through the delay unit DU based on the outputs P1...Pn.

[0034] 3, latches 41...44 are provided downstream of the encoders 31...34, respectively, and the latches 41...44 hold the output data O1...O4 of the encoders 31...34 at the timing of generation of the sampling clock reference signal CKs. The latches 41...44 latch the data O1...O4 output from the encoders 31...34 and store them as previous values.

[0035] Subtractors 51...54 are provided downstream of the encoders 31...34, respectively. The subtractors 51...54 subtract the previous values ​​held in the latches 41...44 from the current values ​​of the encoders 31...34 output from the encoders 31...34, and output the difference as numerical data DT1...DT4 to the adder 5. The adder 5 adds these numerical data DT1...DT4 and outputs the result as numerical data DTA. The adder 5 adds the m pieces of numerical data DT1...DT4 output by the pulse position digitizing unit 4 to generate numerical data DTA of "n+log2m" bits. Note that various processing units may be provided instead of the adder 5, as long as these processing units are configured to output some kind of numerical data DTA based on the subtraction results of the subtractors 51...54.

[0036] The conversion unit 60 is made up of the above-mentioned encoders 31...34, latches 41...44, and subtractors 51...54. The conversion unit 60 subtracts the previous output data from the current output data for the output data Do1...Do4 of the slave latch circuits 21s...24s, and outputs the result to the adder 5 as numeric data DT1...DT4.

[0037] In the A / D conversion circuit 1 configured in this manner, the delay time Td of each delay unit DU changes according to the magnitude of the signal voltage level of the analog input signal Vin. The higher the signal voltage level of the analog input signal Vin, the lower the on-resistance of the transistors constituting each delay unit DU, resulting in a shorter delay time Td. Conversely, the lower the signal voltage level of the analog input signal Vin, the higher the on-resistance of the transistors constituting each delay unit DU, resulting in a longer delay time Td. Therefore, the numerical data DT1...DT4 digitized by the pulse position digitizing unit 4 also changes according to the magnitude of the signal voltage level of the analog input signal Vin, and numerical data DTA based on the numerical data DT1...DT4 corresponding to the analog input signal Vin can be obtained as A / D conversion data.

[0038] <Explanation of the significance of this embodiment> This embodiment is characterized by the configuration of the latch circuits 21...24, and the significance of the configuration of the latch circuits 21...24 will be explained here. An enlarged view of the configuration of the latch circuits 21...24 is shown in FIG. 4, and a specific example is shown in FIG. 5. Here, the output level of the NOT gate 20 will be referred to as level Din. As shown in FIGS. 4 and 5, each of the multiple latch circuits 21...24 is configured as a master-slave type, and includes a master latch circuit 21m...24m in the preceding stage and a slave latch circuit 21s...24s in the succeeding stage. Level Din is input to the master latch circuits 21m...24m.

[0039] The master latch circuits 21m...24m in the preceding stage are configured as static types that include a feedback circuit using a NOT gate Gb and hold outputs Dm1...Dm4. The master latch circuits 21m...24m have the same element configuration as one another, and are therefore given the same reference numerals in FIG. 5. In this embodiment, the slave latch circuits 21s...24s in the succeeding stage are also configured as static types that include a feedback circuit and hold output data Do1...Do4. The ..., and are therefore given the same reference numerals in FIG. 5.

[0040] In the following, the wiring of the master latch circuit 21m and the slave latch circuit 21s will be described as representative, and the wiring of the other master latch circuits 22m...24m and slave latch circuits 22s...24s will be omitted.

[0041] The master latch circuit 21m includes switches SW1 and SW2 and NOT gates Ga and Gb. One end of the switch SW1 receives a level Din, and the other end of the switch SW1 is connected to the input of the NOT gate Ga. The output of the NOT gate Ga is connected to the input of the NOT gate Gb and is also input to one end of the switch SW3 of the subsequent slave latch circuit 21s.

[0042] The output of the NOT gate Gb of the master latch circuit 21m is connected to one end of a switch SW2, and the other end of the switch SW2 is connected to the input of a NOT gate Ga. The switch SW1 is turned on by the negative edge CK1n of the clock CK1 and turned off by the positive edge CK1p. The switch SW2 is turned on by the positive edge CK1p of the clock CK1 and turned off by the negative edge CK1n.

[0043] Therefore, the switches SW1 and SW2 operate complementarily, and when the switch SW1 is turned on, it outputs an inverted level of the level Din to the slave latch circuit 21s in the subsequent stage, and when the switch SW2 is turned on, it turns off the switch SW1. Therefore, while the switch SW1 is turned off, the master latch circuit 21m can maintain the level of the output Dm1 regardless of changes in the level Din.

[0044] On the other hand, the slave latch circuit 21s includes switches SW3 and SW4 and NOT gates Gc and Gd. One end of the switch SW3 receives the output Dm1 of the preceding master latch circuit 21m, and the other end of the switch SW3 is connected to the input of the NOT gate Gc. The output of the NOT gate Gc is connected to the input of the NOT gate Gd, and its output is input to the encoder 31 as output data Do1.

[0045] The output of the NOT gate Gd of the slave latch circuit 21s is connected to one end of a switch SW4, and the other end of the switch SW4 is connected to the input of a NOT gate Gc. The switch SW3 is turned on by the positive edge CK1p of the clock CK1 and turned off by the negative edge CK1n. The switch SW4 is turned on by the negative edge CK1n of the clock CK1 and turned off by the positive edge CK1p.

[0046] Therefore, switches SW3 and SW4 operate complementarily, and when switch SW3 is turned on, the output data Do1 is an inverted level of the output Dm1 of the preceding master latch circuit 21m, and when switch SW4 is turned on, switch SW3 is turned off. Therefore, while switch SW3 is turned off, the level of output data Do1 of slave latch circuit 21s can be maintained regardless of changes in the output of master latch circuit 21m. The wiring of the other master latch circuits 22m...24m and slave latch circuits 22s...24s is the same as described above, so a description thereof will be omitted.

[0047] 5, a common clock CK1 is input to the switches SW3 and SW4 of all the slave latch circuits 21s to 24s, so that all the switches SW3 and SW4 of the slave latch circuits 21s to 24s turn on and off synchronously. On the other hand, different clocks CK1 to CK4 are input to the switches SW1 and SW2 of the master latch circuits 21m to 24m, respectively.

[0048] Specifically, the switch SW1 of the master latch circuit 22m is turned on by the negative edge CK2n of the clock CK2 and turned off by the positive edge CK2p, and the switch SW2 of the master latch circuit 22m is turned on by the positive edge CK2p of the clock CK2 and turned off by the negative edge CK2n.

[0049] The switch SW1 of the master latch circuit 23m is turned on by the negative edge CK3n of the clock CK3 and turned off by the positive edge CK3p, and the switch SW2 of the master latch circuit 23m is turned on by the positive edge CK3p of the clock CK3 and turned off by the negative edge CK3n.

[0050] The switch SW1 of the master latch circuit 24m is turned on by the negative edge CK4n of the clock CK4 and turned off by the positive edge CK4p, and the switch SW2 of the master latch circuit 24m is turned on by the positive edge CK4p of the clock CK4 and turned off by the negative edge CK4n.

[0051] The master latch circuits 21m...24m in the preceding stages input the level Din at the timings of the negative edges CK1n...CK4n of the clocks CK1...CK4. Then, as shown in Figure 6, the master latch circuits 21m...24m hold the level Din at the timings tlm1...tlm4 of the positive edges CK1p...CK4p of the clocks CK1...CK4. After that, the slave latch circuits 21s...24s of the latch circuits 21...24 simultaneously latch the output data Do1...Do4 at the timing tls.

[0052] Since the master latch circuits 21m...24m hold the level Din at the timings tlm1...tlm4 of the positive edges CK1p...CK4p of the clocks CK1...CK4, which are different from one another, even if all the subsequent slave latch circuits 21s...24m receive a common input of the clock CK1, they can hold the level Din at the different timings +Δt, +Δt×2, +Δt×3, and +Δt×4. This allows each latch circuit 21...24 to operate stably.

[0053] As mentioned above, the encoders 31...34 use the sampling clock reference signal CKs, which is the source of multiple clocks CK1...CKm, as the read clock. The output data Do1...Do4 of the slave latch circuits 21s...24s is determined at timing tls. This allows the encoders 31...34 to stably read the output data Do1...Do4 at the subsequent timing tEn, and to stably encode the output data Do1...Do4. All processing of the output data Do1...Do4 in the stages subsequent to the encoders 31...34 can be performed using the sampling clock reference signal CKs.

[0054] <Explanation of Comparative Example> 7 shows a comparative example corresponding to FIG. 4. In this example, clocks CK1 to CK4, which are the same as the operating clocks of the master latch circuits 21m to 24m, are used as clocks that determine the latch timing of the slave latch circuits 21s to 24s. In this configuration, four (=m) wires must be provided to connect the clock generation circuit 3 to the slave latch circuits 21s to 24s. This results in a large number of long wires connecting the clock generation circuit 3 to the latch circuits 21s to 24, and the layout area required to provide these connection wires must be large.

[0055] In particular, in recent miniaturized CMOS process technology, when using, for example, three-dimensional transistors (e.g., FinFET, GAA, etc.), the proportion of the clock wiring area to the entire circuit increases as the CMOS process manufacturing technology becomes finer. As a result, the area occupied by the latch circuits 21...24 becomes larger relative to the circuit area of ​​the pulse delay circuit 2, which may result in a decrease in operating performance and an increase in manufacturing costs.

[0056] <Present Embodiment> In contrast, in this embodiment, the clock CK1 is supplied as a common input to all of the slave latch circuits 21s...24s that make up the multiple latch circuits 21...24. This allows the single clock CK1 to be shared by all of the slave latch circuits 21s...24s. A single wire can be used to connect the output node of the clock CK1 to the slave latch circuits 21s...24s.

[0057] This reduces the number of clock wirings extending from the clock generation circuit 3 to the latch circuits 21...24, thereby reducing the layout area occupied by the clock wirings, enabling miniaturization and effectively improving pulse delay characteristics. This also improves yield and reduces costs. Furthermore, it prevents adverse effects of parasitic elements on the transmission wiring of the clocks CK1...CK4, maintaining high operational reliability. It also reduces or prevents the effects of parasitic elements associated with the read wiring for the delayed pulse group outputs P1...Pn of the pulse delay circuit 2, allowing the latch circuit 21 to stably read the state of the delayed pulse group outputs P1...Pn.

[0058] According to this embodiment, the pulse delay circuit is configured as a ring delay line in a ring shape, which allows for miniaturization and improved pulse delay characteristics.

[0059] Furthermore, the encoders 31...34 read using the sampling clock reference signal CKs that is the source of the clocks CK1...CK4, and therefore can stably read and encode the output data Do1...Do4 of the slave latch circuits 21s...24s.

[0060] (Second embodiment) The second embodiment will be described with reference to Fig. 8. The latch circuits 221...224 shown in Fig. 8 include master latch circuits 21m...24m and slave latch circuits 221a...224a. In this embodiment, the subsequent slave latch circuits 221s...224s are configured as dynamic types that hold output data Do1...Do4 without including a feedback circuit.

[0061] Each of the slave latch circuits 221s...224s includes a switch SW3, a capacitor C1, and a NOT gate Gc. One end of the switch SW3 receives the output of the preceding master latch circuit 21m, and the other end of the switch SW3 is connected to the input of the NOT gate Gc. The output of the NOT gate Gc in each of the slave latch circuits 221s...224s is input as output data Do1...Do4 to the succeeding encoders 31...34, respectively.

[0062] Here, the NOT gate Gc is configured, for example, by a CMOS inverter, and therefore has parasitic capacitance at its input. Although a symbol for capacitor C1 is clearly illustrated in Figure 8, capacitor C1 is actually a capacitance based on the gate input capacitance of the NOT gate Gc and the parasitic capacitance occurring in the wiring from switch SW3 to the input of the NOT gate Gc. Therefore, there is no need to provide a large additional layout area to intentionally configure capacitor C1.

[0063] This allows for a reduction in the number of elements constituting the slave latch circuits 221s...224s compared to the previous embodiment. That is, the layout area can be reduced by the components of the NOT gate Gd and switch SW4 described in the first embodiment. Moreover, the layout area can be reduced by the wiring connecting these components compared to the configuration of the first embodiment. This improves yield and reduces costs. Furthermore, it is possible to prevent adverse effects of parasitic components on the transmission wiring of the clocks CK1...CK4, thereby maintaining high operational reliability. Conversely, if there is ample layout area, the circuit arrangement can be devised to increase the capacitance of capacitor C1 and stabilize the voltage of the output level.

[0064] (Third embodiment) The third embodiment will be described with reference to Figures 9 to 11. In the first embodiment described above, the pulse delay circuit 2 has a configuration in which delay units DU each consisting of a NAND gate G1 and NOT gates G2 to G15 are connected in a ring shape, but the present invention is not limited to this.

[0065] The delay units DU may be connected in series, and may not be connected in a ring shape. That is, as shown in the pulse delay circuit 302 in Fig. 9, the pulse delay circuit 302 may be configured as an open delay line in which the delay units DU are arranged in a non-ring shape. The pulse delay circuit 302 is configured by cascading NOT gates G1a, G2...Gn, and the analog input signal Vin is supplied to these NOT gates G1a, G2...Gn as a power supply voltage.

[0066] When such a pulse delay circuit 302 is used, as illustrated in FIG. 10, a pulse signal PA is transmitted from the first-stage delay unit DU for each cycle Ts of the clock reference signal CKs.

[0067] In this embodiment, each of the encoders 31...34 of the pulse position digitizing unit 304 digitizes and outputs the number of delay units DU through which the pulse signal PA has passed, depending on the phase difference between the generation timing of the input pulse signal PA that activates the pulse delay circuit 302 and the generation timing of each of the clocks CK1...CK4.

[0068] Therefore, as shown in Figure 11, there is no need to provide the latches 41...44 and subtractors 51...54 described in the first embodiment in the pulse position digitization unit 304, allowing for a simpler circuit configuration. The other components are the same as those in the first or second embodiment, so a description of the configuration will be omitted. Note that the conversion unit 360 in this embodiment is made up of encoders 31...34. As a result, the number of elements can be further reduced compared to the previous embodiments, and the layout area for mounting the elements can be reduced.

[0069] According to this embodiment, the pulse delay circuit is configured as an open delay line, so that components (e.g., NAND gates, subtractors) that are used in a ring configuration are not required, allowing for miniaturization and improved pulse delay characteristics. This provides the same effects as the previous embodiment, as well as additional advantageous effects.

[0070] (Other embodiments) The present invention is not limited to the above-described embodiment, and the following modifications or extensions are possible. In the above-described embodiment, the gates G2 to G15 are configured with a single-stage CMOS inverter, but the CMOS inverters may be cascaded in two stages. In this case, the variation in the A / D conversion results can be suppressed compared to a configuration in which a single stage of CMOS inverters is connected.

[0071] In the first to third embodiments described above, one clock CK1 is selected from a plurality of clocks CK1...CKm (where m=4) and is input as a common "second clock" to all slave latch circuits 21s...24m, 221s...224s. However, it is also possible to provide a plurality of clocks to be input in common and supply them to slave latch circuits 21s...24s, 221s...224s.

[0072] That is, for example, one clock CK1 may be supplied to a plurality of slave latch circuits 21s and 22s, and another clock CK2 may be supplied to a further plurality of slave latch circuits 23s and 24s.

[0073] Alternatively, one clock (e.g., CK1) may be supplied to m-1 slave latch circuits (e.g., 21s, 22s, 23s), and another clock (e.g., CK2) may be supplied to another slave latch circuit (e.g., 24s). In other words, one clock (e.g., CK1) can be supplied to a maximum of m-1 slave latch circuits.

[0074] In the first embodiment, the master latch circuits 21m...24m hold the states of the outputs P1, P2,..., Pn of the delayed pulse group using different clocks CK1...CK4, and the slave latch circuits 21s...24s hold the outputs of the master latch circuits 21m...24m using clock CK1. However, this is not limiting. Any clock based on the clocks CK1...CK4 can be used as the "second clock" for the common input according to the present application. In other words, the "second clock" according to the present application can be a clock obtained by performing a shaping process, such as inversion, on any one of the clocks CK1...CK4.

[0075] In other words, any configuration may be applied as long as at least two or more slave latch circuits (e.g., 21s, 22s) are configured to commonly input a "second clock" based on a "first clock" and hold output data Do1...Do4.

[0076] When the number of parallel connections of the latch circuits 21...24 per delay unit DU, i.e., m, is increased, the configuration of the above-described embodiment can be realized by shortening the time Δt corresponding to the phase difference of the clocks CK1...CKm according to the value of m. The larger m is set, the better the resolution and accuracy, so the larger m is set, the better.

[0077] As in the technology described in Patent Document 1, a circulation counter that counts the number of pulse circulations may be provided downstream of the pulse delay circuits 2, 302, and the difference between the numerical value of the previous pulse position and the numerical value of the current pulse position may be calculated using subtractors 51...54, taking into account the value of the circulation counter, to obtain the numerical data DTA.

[0078] The configurations and functions of the above-described embodiments may be combined. Aspects in which parts of the above-described embodiments are omitted as long as they can solve the problem can also be considered embodiments. Furthermore, any conceivable aspect can also be considered an embodiment, as long as it does not deviate from the essence of the invention as defined by the wording of the claims.

[0079] Although the present disclosure has been described based on the above-described embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including one, more, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0080] In the drawing, 2 is a pulse delay circuit, 3 is a clock generation circuit, 4 is a pulse position digitization unit, 60 and 360 are conversion units, CK1 to CK4 are sampling clocks, CKs is a sampling clock reference signal (master clock), and DU is a delay unit.

Claims

1. A conversion circuit for converting a voltage (Vin) into numerical data (DTA) using a pulse delay circuit (2) configured by serially connecting a plurality of delay units (DU) that delay and output pulse signals, and outputting a group of delayed pulses from the plurality of delay units, a plurality of latch circuits (21, 22, 23, 24) each including a master latch circuit (21m...24m) that holds the state of the output (P1, P2, P3,..., Pn) of the delayed pulse group output from the pulse delay circuit using first clocks (CK1...CK4) that are different from each other, and a slave latch circuit (21s...24s) that holds the output of the master latch circuit using a second clock (CK1); a conversion unit (60; 360) that includes an encoder at a subsequent stage of the plurality of slave latch circuits and converts the output data of the plurality of slave latch circuits into the numerical data, At least two of the plurality of slave latch circuits receive the second clock based on the first clock in common and hold the output data; The plurality of latch circuits are a conversion circuit in which the slave latch circuit is connected in cascade immediately after the master latch circuit.

2. 2. The conversion circuit according to claim 1, wherein the master latch circuit is configured as a static type having a feedback circuit to hold an output, and the slave latch circuit is configured as a dynamic type not having the feedback circuit to hold the output data.

3. 3. The conversion circuit according to claim 1, wherein the pulse delay circuit is configured by a ring delay line in which the plurality of delay units are arranged in a ring shape.

4. 3. The conversion circuit according to claim 1, wherein the pulse delay circuit is configured by an open delay line in which the plurality of delay units are arranged in a non-ring shape.

5. 5. The conversion circuit according to claim 1, wherein the second clock is commonly input and supplied to all of the slave latch circuits that constitute the plurality of latch circuits.

6. A conversion circuit as claimed in any one of claims 1 to 5, wherein the encoder uses a master clock (CKs) that is the source of the first clock (CK1, CK2, ..., CKm) or the second clock (CK1) as the clock for reading the output data.

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