Chip internal comparator threshold calibration method, system and computer program product

Abstract

The present application relates to a method, system and computer program product for calibrating the threshold value of a chip internal comparator. The method includes: configuring each threshold value to be calibrated to each chip, and the threshold value to be calibrated is used to obtain the input value of the first input terminal of the internal comparator in each channel in each chip; configuring the target source initial value to the target source, indicating the target source to generate a target signal as the input value of the second input terminal of the internal comparator of each chip; obtaining the output state of the chip internal comparator in each channel in parallel; updating the target signal according to the scanning step and the first update direction, and the updated target signal is used to input the second input terminal of the chip internal comparator in each channel; when the output state of the chip internal comparator jumps, the first correlation relationship between the target signal corresponding to the first jump moment and the threshold value to be calibrated is recorded; and the first correlation relationship is used as calibration information. The use of this method can ensure calibration accuracy and improve calibration efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, system and computer program product for calibrating a comparator threshold inside a chip. Background Art

[0002] In traditional technology, the channel resources of ATE equipment use the characteristics of PE chips to set the levels of VIH, VIL, VOH, and VOL of the output waveform to meet the requirements of the chip under test for different noise tolerances. The VOH and VOL parameters correspond to the comparator threshold voltage inside the PE chip and must be calibrated before use. There are currently two commonly used calibration methods:

[0003] The first is the direct voltage measurement method, which means that the output voltage of the DAC corresponding to VOH and VOL is led out to the Monitor module of the PE chip through the diagnostic circuit inside the PE chip, and then the output signal of the Monitor is sampled using the ADC reference outside the PE chip to achieve the purpose of indirect calibration.

[0004] The second is the DCF detection method, which refers to detecting the output level of the comparator through the DCF (Duty Cycle Filter) module inside the PE chip, triggering the comparator output jump through the external precise excitation voltage scanning method, and then obtaining the actual output flip state of the comparator after DCF integration processing, and then calibrating the set voltage of VOH or VOL with the precise excitation voltage corresponding to the flip state moment.

[0005] However, although the direct voltage measurement method is direct and efficient, it measures the direct output of the DAC inside the PE and cannot reflect the output of the comparator. In addition, the output signal of the comparator inside the PE will pass through multiple stages of circuits before being output to the outside of the PE chip. Other offsets will be introduced in the middle, and the final accuracy is not high.

[0006] The DCF detection method detects the comparator output signal, has a signal integration function, has a good recognition of the comparator metastable state, and has a relatively high calibration accuracy. However, DCF also reflects the direct output signal of the comparator and does not include the characteristics of the subsequent circuit. Before calibration, it is usually necessary to calibrate the DCF module in each channel itself to calibrate the actual flip state of the comparator through the zero calibration value. On a multi-channel resource board, the VOH / VOL calibration time will account for a large proportion, reducing the calibration efficiency. Summary of the invention

[0007] Based on this, it is necessary to provide a chip internal comparator threshold calibration method, system and computer program product that can ensure calibration accuracy and improve calibration efficiency in response to the above technical problems.

[0008] In a first aspect, the present application provides a method for calibrating a comparator threshold value within a chip, which is applied to a parallel calibration module, and the method comprises:

[0009] Allocating each threshold value to be calibrated to each chip, wherein the threshold value to be calibrated is used to obtain an input value of a first input terminal of an internal comparator in each channel in the chip;

[0010] configuring the target source initial value to the target source to instruct the target source to generate a target signal, wherein the target signal is an input value of the second input terminal of each internal comparator of the chip;

[0011] Acquire the output states of the internal comparators of the chip in each of the channels in parallel;

[0012] The target signal is updated according to the scanning step length and the first updating direction, and the updated target signal is used to be input to the second input end of the internal comparator of the chip in each of the channels;

[0013] When the output state of the comparator inside the chip changes, a first correlation relationship between the target signal corresponding to the first change moment and the threshold to be calibrated is recorded;

[0014] The first association relationship is used as calibration information.

[0015] In one embodiment, the method further comprises:

[0016] When the output states of the comparators inside each chip change, the next threshold to be calibrated is obtained, and the step of configuring the target source initial value to the target source to instruct the target source to generate a target signal is continued until the association between each threshold to be calibrated and the corresponding target signal is obtained.

[0017] In one embodiment, the chip includes at least two internal comparators of the chip; and the step of obtaining the output states of the internal comparators of the chip in each channel in parallel includes:

[0018] The output states of the internal comparators of each chip in each channel are acquired in parallel, respectively, wherein the output states of the internal comparators of each chip in each channel are acquired in parallel.

[0019] In one embodiment, after obtaining the output state of the internal comparator of the chip in each channel, the method further includes:

[0020] When the output states of the internal comparators of the chip in each of the channels are different, the target signal is updated according to a second update direction until the output states of the internal comparators of the chip in each of the channels are the same; the updated target signal is used to input into the internal comparators of the chip in each of the channels, and the second update direction is opposite to the first update direction.

[0021] In one embodiment, the internal comparator of the chip is a comparator with hysteresis characteristics or metastable characteristics; after recording the first correlation relationship between the target signal corresponding to the first jump moment and the threshold to be calibrated, the method includes:

[0022] The target signal is updated according to a scanning step length and a second updating direction, wherein the second updating direction is opposite to the first updating direction, and the updated target signal is used to be input to a second input terminal of the internal comparator of the chip in each of the channels;

[0023] When the output state of the comparator inside the chip changes, a second correlation relationship between the target signal corresponding to a second change time and the threshold to be calibrated is recorded, wherein the change of the comparator with a metastable characteristic refers to that the duty cycle of the output state of the comparator is greater than a preset ratio;

[0024] Calculating mathematical statistics of the target signal corresponding to the first transition time and the target signal corresponding to the second transition time;

[0025] A third association relationship between the mathematical statistic value and the threshold value to be calibrated is recorded, and the third association relationship is used as calibration information.

[0026] In one embodiment, the transition of the comparator with metastable characteristics refers to the output state duty cycle of the comparator being greater than a preset ratio, which includes:

[0027] In the first update direction, the high level duty cycle of the output state of the comparator is greater than the preset ratio, and in the second update direction, the low level duty cycle of the output state of the comparator is greater than the preset ratio; or,

[0028] In the first update direction, the low level duty cycle of the output state of the comparator is greater than a preset ratio, and in the second update direction, the high level duty cycle of the output state of the comparator is greater than a preset ratio.

[0029] In one embodiment, before configuring each threshold to be calibrated to the chip in each channel, the method includes:

[0030] Initialization processing is performed on each of the channels in parallel, and the initialization processing includes shutting down the function of each target channel and configuring the output state acquisition information of the comparator inside the chip.

[0031] In a second aspect, the present application further provides a chip internal comparator threshold calibration method, which is applied to a terminal, and the method includes:

[0032] Sending a calibration start instruction, wherein the calibration start instruction is used to instruct the parallel calibration module to execute the above-mentioned chip internal comparator threshold calibration method to obtain calibration information;

[0033] A calibration fit is performed on the calibration information.

[0034] In one embodiment, before sending the calibration start instruction, the method includes:

[0035] Calibration configuration parameters are sent to the parallel calibration module, wherein the calibration configuration parameters include each threshold to be calibrated, a target source initial value, a first update direction, and a scanning step size.

[0036] In one embodiment, before sending the calibration start instruction, the method includes:

[0037] A calibration initialization instruction is sent, where the calibration initialization instruction is used to instruct the parallel calibration module to perform initialization processing on each of the channels in parallel.

[0038] In a third aspect, the present application further provides a chip internal comparator threshold calibration system, the system comprising:

[0039] A chip including a plurality of channels, each channel including at least one internal comparator of the chip;

[0040] At least one channel FPGA module, used for parallel acquisition of the output state of the chip internal comparator in each channel of the chip, wherein each of the channels is calibrated in parallel, and each of the chip internal comparators in each of the channels is calibrated in parallel;

[0041] A target source, used to generate a target signal;

[0042] The parallel calibration module is used to execute the above-mentioned chip internal comparator threshold calibration method to obtain calibration information.

[0043] In one embodiment, the parallel calibration module includes a parallel calibration unit, a first main control unit and a first peripheral unit, wherein the first main control unit is communicatively connected with the channel FPGA module, the first peripheral unit and the parallel calibration unit; the first peripheral unit is communicatively connected with the target source, and the target source is communicatively connected with the second input end of the chip internal comparator in each of the channels in each of the chips;

[0044] The parallel calibration unit is used to execute the chip internal comparator threshold calibration method described in any one of the above embodiments to obtain calibration information;

[0045] The first peripheral unit is used to be controlled by the first main control unit, and to control the target source to output a corresponding target signal to an internal comparator of the chip in each channel of each chip;

[0046] The first main control unit is used to initialize each channel of each chip, configure the calibration parameters of the parallel calibration unit, forward the calibration-related instructions provided by the parallel calibration unit to the channel FPGA module, forward the output status of the internal comparator of the chip returned by the channel FPGA module to the parallel calibration unit, and forward the calibration information generated by the parallel calibration unit.

[0047] In one optional embodiment, the channel FPGA module includes a second main control unit, a second peripheral unit and an acquisition unit, the second main control unit is communicatively connected with the parallel calibration module, the second peripheral unit and the acquisition unit, the second peripheral unit is communicatively connected with the chip, and the acquisition unit is communicatively connected with the internal comparator of the chip respectively;

[0048] The second main control unit is used to receive calibration related instructions sent by the parallel calibration module;

[0049] The second peripheral unit is used for initializing each channel of each chip based on the calibration initialization instruction in the calibration related instruction;

[0050] The acquisition unit is used to acquire the output state of the chip internal comparator in each channel of each chip based on the calibration start instruction in the calibration related instructions, and send the output state of the chip internal comparator to the parallel calibration module through the second main control unit.

[0051] In one embodiment, the system further comprises:

[0052] The terminal communicates with the parallel calibration module, and is used to obtain the calibration information from the parallel calibration module and perform calibration fitting on the calibration information.

[0053] In a fourth aspect, the present application also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of the method described in any one of the above embodiments.

[0054] The above-mentioned chip internal comparator threshold calibration method, system and computer program product configure each threshold to be calibrated to each chip, and the threshold to be calibrated is used to obtain the input value of the first input end of each chip internal comparator of each channel of the chip; the target source initial value is configured to the target source to instruct the target source to generate a target signal, the target signal is the input value of the second input end of each chip internal comparator, and the output state of the chip internal comparator in each channel is obtained in parallel, and the target signal is updated according to the scanning step and the first update direction. The updated target signal is used to input the second input end of the chip internal comparator in each channel. In this way, when the output state of the chip internal comparator jumps, the target signal corresponding to the first jump moment and the first correlation relationship between the threshold to be calibrated are recorded and used as calibration information, so as to directly collect the output signal of the comparator, which can ensure the accuracy of calibration, and the output state of the chip comparator in each channel is collected in parallel to improve efficiency, thereby ensuring both the calibration accuracy and the calibration efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the related technical descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 A block diagram of a comparator threshold calibration system inside a chip in one embodiment;

[0057] Figure 2 A schematic diagram of a comparator threshold calibration system inside a chip in one embodiment;

[0058] Figure 3 It is an architecture diagram of a comparator threshold calibration system inside a chip in one embodiment;

[0059] Figure 4 A schematic diagram of a flow chart of a method for calibrating a threshold value of a comparator inside a chip in one embodiment;

[0060] Figure 5 A schematic diagram of a flow chart of a method for calibrating a threshold value of a comparator inside a chip in one embodiment;

[0061] Figure 6 A timing diagram of a comparator threshold calibration method inside a chip in one embodiment;

[0062] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0064] Regarding the detection methods of the prior art, there is also a software query method, which refers to a method of querying the comparator output state through software. Compared with the second method, this method is used when there is no DCF module inside the PE chip. The software counts the number of high and low states of the comparator output within a certain time window to determine the actual flip state, and also calibrates the set voltage of VOH or VOL with the precise excitation voltage corresponding to the flip state. The software query method is an alternative method for calibrating the VOH / VOL of PE chips without DCF function. Its query rate will seriously affect the calibration efficiency, and it is difficult to accurately identify the metastable state of the comparator output, and it is easy to miss the flip state, resulting in poor accuracy.

[0065] Specifically, combined Figure 1 As shown, the present application provides a chip internal comparator threshold calibration system, the system comprising: a chip to be calibrated, a channel FPGA module, a target source and a parallel calibration module.

[0066] Among them combined Figure 2 As shown, the chip to be calibrated includes multiple channels. Figure 2 Only one channel is shown in the figure. One channel includes at least one comparator, and the output of each comparator is connected to the channel FPGA module. Each channel of each chip to be calibrated includes at least one internal comparator of the chip. The channel FPGA module is used to collect the output state of the corresponding internal comparator of the chip; the target source is used to generate the target signal; and the parallel calibration module is used to execute the threshold calibration method of the internal comparator of the chip to obtain the calibration information. Among them, the chip to be calibrated refers to the PE chip (Pin electronic IC, pin unit or pin electronics), and the chips appearing below are all PE chips.

[0067] For ease of understanding, combined Figure 3As shown, the chip internal comparator threshold calibration system includes a terminal and a resource board, wherein the resource board includes a first subcard and several second subcards, wherein the first subcard includes a target source and a parallel calibration module, and the parallel calibration module includes a first main control unit, a first peripheral unit and a parallel calibration unit, wherein the first main control unit is communicatively connected with the channel FPGA module, the first peripheral unit and the parallel calibration unit; the first peripheral unit is communicatively connected with the target source, and the target source is communicatively connected with the second input end of the chip internal comparator in each of the channels in each chip; wherein the first main control unit is communicatively connected with the terminal. The parallel calibration unit is used to execute the chip internal comparator threshold calibration method of the present application to obtain calibration information. The first peripheral unit is used to be controlled by the first main control unit, and control the target source to output the corresponding target signal to the chip internal comparator in each channel in each chip. The first main control unit serves as a communication unit of the resource board, and is used to initialize each channel of each chip, configure the calibration parameters of the parallel calibration unit, forward each calibration-related instruction provided by the parallel calibration unit to the channel FPGA module, forward the output state of the chip internal comparator returned by the channel FPGA module to the parallel calibration unit, and forward the calibration information generated by the parallel calibration unit to the terminal. Specifically, the first main control unit can receive the calibration-related instructions set by the terminal for this calibration, and the calibration-related instructions include calibration start instructions, calibration initialization instructions, calibration parameter configuration instructions, etc. The first main control unit initializes several second sub-cards based on the calibration initialization instructions to initialize all chip channels in each second sub-card. The first main control unit also configures the corresponding calibration parameters for the first sub-card based on the calibration parameter configuration instructions, including each threshold to be calibrated, the target source initial value, the first update direction, and the scanning step size. The first main control unit also controls the parallel calibration unit to start executing the chip internal comparator threshold calibration method of the present application based on the calibration start instruction. The first main control unit also receives the output state of the internal comparator of the chip returned by the channel FPGA module, and forwards the output state to the parallel calibration unit; the first main control unit forwards the calibration information of the cyclic calibration of all comparators with different thresholds to be calibrated provided by the parallel calibration unit, and sends the calibration information to the terminal. The first main control unit also controls the target source through the first peripheral unit so that the target source outputs a precise target signal to the internal comparator of each chip. Among them, the terminal can be a host computer, that is, a PC or an industrial computer.

[0068] Each second subcard includes a chip to be calibrated (PE chip) and a channel FPGA module, wherein each chip to be calibrated may include at least one channel, and each channel may be calibrated in parallel. Optionally, each channel may include at least one internal comparator of the chip, and each internal comparator of the chip may be calibrated in parallel. The channel FPGA module includes a second main control unit, a second peripheral unit, and a collection unit, the second main control unit is communicatively connected with the parallel calibration module, the second peripheral unit, and the collection unit, the second peripheral unit is communicatively connected with the chip, and the collection unit is communicatively connected with the internal comparator of the chip respectively. The second main control unit is used to receive calibration-related instructions sent by the parallel calibration module; the second peripheral unit is used to initialize each of the channels of each chip based on the calibration initialization instructions in the calibration-related instructions; the collection unit is used to collect the output state of the internal comparator of the chip in each of the channels of each chip based on the calibration start instruction in the calibration-related instructions, and send the output state of the internal comparator of the chip to the parallel calibration module through the second main control unit. Specifically, the second main control unit is used to communicate with the parallel calibration module, receive and forward the calibration-related instructions sent by the parallel calibration module, and forward the output state of the chip internal comparator collected by the acquisition unit to the parallel calibration module, specifically to the first main control unit of the parallel calibration module. Specifically, the second main control unit can receive the broadcast initialization output by the first main control unit to initialize each channel of the chip to be calibrated through the second peripheral unit, and configure the sampling frequency and number of sampling points of the acquisition unit. In addition, the second main control unit is also used to receive the output state of the internal chip internal comparator of each chip to be calibrated collected by the acquisition unit, and forward the output state to the first main control unit, and the first main control unit outputs the output state to the parallel calibration unit. Finally, the parallel calibration unit determines whether the output state jumps. If it jumps, the target signal corresponding to the first jump moment and the first correlation relationship of the threshold to be calibrated are recorded, and the first correlation relationship is used as calibration information.

[0069] Among them, the terminal can communicate with the parallel calibration module, and optionally, communicate with the first main control unit of the parallel calibration module to send a calibration start instruction to the parallel calibration module, so as to control the parallel calibration module to start calibration, execute the chip internal comparator threshold calibration method to obtain calibration information, and return the calibration information of the comparator output state in all channels to the terminal, so as to facilitate the terminal to perform calibration fitting.

[0070] Before sending the calibration start instruction, the terminal also sends calibration configuration parameters to the parallel calibration module. The calibration configuration parameters include each threshold to be calibrated, the target source initial value, the first update direction and the scanning step size, so that the parallel calibration module can configure the calibration parameters of the first subcard based on these calibration configuration parameters.

[0071] In addition, before sending the calibration start instruction, the terminal also sends a calibration initialization instruction, and the calibration initialization instruction is used to instruct the parallel calibration module to perform initialization processing on each channel in parallel, that is, to configure a plurality of second subcards.

[0072] In an exemplary embodiment, Figure 4 As shown, a method for calibrating the threshold value of a comparator inside a chip is provided. Figure 3 The parallel calibration module in FIG. 1 is taken as an example to illustrate, and the steps include the following steps 402 to 412. Among them:

[0073] S402: configuring each threshold value to be calibrated to a chip in each channel, wherein the threshold value to be calibrated is used to obtain an input value of a first input terminal of a comparator inside the chip.

[0074] Among them, each threshold to be calibrated is the corresponding threshold of the internal comparator of the chip, and the threshold to be calibrated includes but is not limited to VOH / VOL, differential VOH / VOL, digital CA, CB parameters, PMU (power management unit) Go-No-Go parameters, which correspond to the comparison terminal voltage of the internal comparator of the chip. Taking VOL and / or VOH as an example, Figure 2 As shown in , a chip includes a channel, and a channel may include two chip internal comparators, wherein the threshold corresponding to one chip internal comparator is VOL, and the threshold corresponding to the other chip internal comparator is VOH. In other embodiments, the number of chip internal comparators in a channel may be other values, which are not specifically limited here, and only the thresholds to be calibrated of each chip internal comparator need to be configured. Optionally, the thresholds to be calibrated corresponding to the chip internal comparators in each channel may be the same or different, which are not specifically limited here.

[0075] The threshold to be calibrated corresponds to the input value of the first input terminal of the internal comparator of the chip, wherein each threshold to be calibrated corresponds to a DAC code value, and the corresponding voltage value is obtained after DAC processing, which is used as the input value of the first input terminal of the internal comparator of the chip. For example, assuming that the threshold to be calibrated is code0, the corresponding voltage value is V0, and the voltage value V0 is used as the input value of the first input terminal of the internal comparator of the chip, that is, the threshold of the internal comparator of the chip. When the target signal of the input of the internal comparator of the chip is less than the threshold, the internal comparator of the chip outputs the first output state, and when the target signal of the input of the internal comparator of the chip is greater than the threshold, the internal comparator of the chip outputs the second output state.

[0076] In this embodiment, the threshold to be calibrated corresponding to each chip is configured through the terminal, and then the DAC in each chip performs digital-to-analog conversion on the threshold to be calibrated to obtain the input value of the first input terminal of the corresponding chip internal comparator, and input it to the first input terminal of the corresponding chip internal comparator.

[0077] S404: configuring the target source initial value to the target source to instruct the target source to generate a target signal, where the target signal is the input value of the second input terminal of the internal comparator of each chip.

[0078] The target source is a signal source for generating a precise signal, and the target source initial value is configured, which can instruct the target source to generate a target signal corresponding to the target source initial value. Optionally, the target source is a high-precision DAC device, and a resource board can have only one, so that the target source initial value is configured to the DAC device, and the DAC device obtains the corresponding target signal based on the input target source initial value, and then inputs the target signal to the input value of the second input terminal of the chip internal comparator, wherein in order to achieve synchronous calibration of the chip internal comparators in multiple chips, the input value of the second input terminal of each chip internal comparator is the same in each clock cycle.

[0079] S406: Obtain the output status of the internal comparator of each channel in parallel.

[0080] In this embodiment, the acquisition unit is used to acquire the output state of the internal comparator of the chip in the channel, wherein each channel corresponds to an acquisition unit, so each channel can realize parallel acquisition. The acquisition unit in each channel acquires the output state of the internal comparator of the chip in the channel in parallel and returns it to the parallel calibration module, for example, in combination with Figure 3 As shown, each acquisition unit acquires the output state of the internal comparator of the chip in the channel in parallel.

[0081] In one of the optional embodiments, the chip includes at least two internal chip comparators; and the output states of the internal chip comparators in each channel are acquired in parallel, including: acquiring the output states of the internal chip comparators in each channel in parallel, wherein the output states of the internal chip comparators in each channel are acquired in parallel.

[0082] Wherein a channel inside the chip includes at least two chip internal comparators. In order to realize parallel acquisition, the acquisition unit in a channel in this embodiment can parallelly acquire the output states of the internal comparators of each chip in the channel, thereby realizing parallel acquisition of the output states of the internal comparators of each chip.

[0083] Therefore, the parallel acquisition in the present application includes the parallel acquisition of each channel and the parallel acquisition of the output state of each chip internal comparator in each channel, thereby improving the acquisition efficiency.

[0084] In addition, the acquisition unit in the present application is implemented through FPGA, which directly acquires the output of the comparator inside the chip, and can calibrate the voltage bias offset introduced by the internal link of the chip, thereby improving the overall calibration accuracy.

[0085] S408: updating the target signal according to the scanning step length and the first updating direction, and the updated target signal is used to input into the second input terminal of the internal comparator of the chip in each channel.

[0086] The scanning step length is the step length of the change of the target signal, wherein the scanning step length may be related to the calibration accuracy of the threshold to be calibrated. The higher the calibration accuracy of the threshold to be calibrated, the smaller the scanning step length. For example, when the calibration accuracy of the threshold to be calibrated is 1V, the corresponding scanning step length should be less than 1V. When the calibration accuracy of the threshold to be calibrated is 0.1V (the accuracy becomes higher), the corresponding scanning step length should be less than 0.1V.

[0087] The first update direction is also the update direction of the pre-configured target signal. Optionally, the size of the target signal is updated in a certain direction, so that the target signal input to the second input terminal of the chip internal comparator in each channel can be changed, and the output state of the chip internal comparator can be changed. The first update direction can be from small to large, or from large to small, and there is no specific limitation here. It only requires that the target signal of the chip internal comparator input to each channel changes synchronously.

[0088] Optionally, in the present application, the target source only outputs voltage, and the actual voltage value corresponding to the threshold to be calibrated in each channel is determined by continuously adjusting the voltage value.

[0089] The scanning step size, the first update direction, the threshold to be calibrated, and the target source initial value may be pre-configured calibration parameters, and the calibration parameters may be configured in the terminal and sent to the parallel calibration unit.

[0090] S410: When the output state of the internal comparator of the chip changes, a first correlation relationship between a target signal corresponding to a first change time and a threshold to be calibrated is recorded.

[0091] Among them, when the target signal of the input of the internal comparator of the chip is less than the threshold value to be calibrated, the output of the internal comparator of the chip is a first output state, and when the target signal of the input of the internal comparator of the chip is greater than the threshold value to be calibrated, the output of the internal comparator of the chip is a second output state. Therefore, there is a moment when the output state of the internal comparator of the chip jumps, for example, from the first output state to the second output state, or from the second output state to the first output state. At the moment of the jump, the target signal of the input of the internal comparator of the chip is equal to the threshold value to be calibrated. For this reason, the acquisition unit can acquire the output state of the internal comparator of the chip and return it to the second main control unit. The second main control unit returns the output state to the first main control unit. The first main control unit returns the output state to the parallel calibration unit. The parallel calibration unit determines whether the output state jumps, and obtains the target signal corresponding to the first jump moment and the first correlation relationship between the threshold value to be calibrated when the jump occurs.

[0092] S412: Use the first association relationship as calibration information.

[0093] The parallel calibration unit uses the target signal of the corresponding internal comparator of the chip in the corresponding channel and the first correlation relationship between the threshold value to be calibrated as calibration information.

[0094] Optionally, when the output state of the comparators inside each chip changes, the next threshold to be calibrated is obtained, and the step of configuring the target source initial value to the target source to instruct the target source to generate a target signal is continued until the correlation between each threshold to be calibrated and the corresponding target signal is obtained.

[0095] The internal comparator of each chip includes a plurality of thresholds to be calibrated, so after the calibration of one of the thresholds to be calibrated is completed, the next threshold to be calibrated is obtained and calibrated.

[0096] Since it is a synchronous calibration of the internal comparators of each chip, it is necessary to obtain the next threshold to be calibrated corresponding to each chip internal comparator in each channel when the output state of each chip internal comparator in each channel jumps, that is, when the calibration of the threshold to be calibrated corresponding to each chip internal comparator in each channel is completed, and input the next threshold to be calibrated into the corresponding DAC to obtain the input of the corresponding first input end of each chip internal comparator in each channel. As mentioned above, the thresholds to be calibrated corresponding to each chip internal comparator in each channel can be the same or different. Optionally, in order to simplify the operation, the change direction of each threshold to be calibrated corresponding to each chip internal comparator in each channel is the same, that is, the thresholds to be calibrated corresponding to each chip internal comparator in each channel are changed synchronously in one direction in sequence. In some optional embodiments, the determination of each threshold to be calibrated corresponding to each chip internal comparator in each channel can be repeated multiple times to take the average value as the calibration value of each threshold to be calibrated corresponding to each chip internal comparator in each channel.

[0097] The above-mentioned chip internal comparator threshold calibration method configures each threshold to be calibrated to each chip, and the threshold to be calibrated is used to obtain the input value of the first input terminal of the chip internal comparator; the target source initial value is configured to the target source to indicate the target source to generate a target signal, the target signal is the input value of the second input terminal of each chip internal comparator, and the output state of the chip internal comparator in each channel is obtained in parallel, and the target signal is updated according to the scanning step and the first update direction. The updated target signal is used to input the second input terminal of the chip internal comparator in each channel. In this way, when the output state of the chip internal comparator jumps, the target signal corresponding to the first jump moment and the first correlation relationship between the threshold to be calibrated are recorded and used as calibration information, so as to directly collect the output signal of the chip internal comparator, which can ensure the accuracy of calibration, and the output state of the chip internal comparator in each channel in parallel can improve efficiency, thereby ensuring both the calibration accuracy and the calibration efficiency.

[0098] In one of the optional embodiments, after obtaining the output state of the internal chip comparator in each channel, it also includes: when the output state of the internal chip comparator in each channel is different, updating the target signal according to the second update direction until the output state of the internal chip comparator in each channel is the same; the updated target signal is used to input into the internal chip comparator in each channel, and the second update direction is opposite to the first update direction.

[0099] After the first target signal is input to the chip internal comparator in each channel, the output state of each chip internal comparator in each channel is obtained. If the output states of each chip internal comparator in each channel are different, for example, some are the first output state and some are the second output state, the output states of each chip internal comparator in each channel need to be adjusted to be consistent. The specific adjustment method is to update the target signal according to the second update direction, so that the output states of the chip internal comparators in each channel can be the same. The second update direction is opposite to the first update direction.

[0100] For ease of understanding, assume that there are 2 channels and 4 internal comparators of the chip. After the first target signal is input, the output states of 3 internal comparators of the chip are the first output state, and the output state of the other internal comparator of the chip is the second output state. The first output state is output because the input target signal of the internal comparator of the chip is less than the threshold, and the second output state is output because the input target signal of the internal comparator of the chip is greater than the threshold. Therefore, the first update direction is to increase the target signal to make the states of the 3 internal comparators of the chip that output the first output state jump. Therefore, the second update direction is to decrease the target signal until the state of the internal comparator of the chip that outputs the second output state changes, and then update the target signal according to the first update direction. It should be noted that when the target signal is updated in the second update direction, its scanning step length can be the same as the scanning step length of updating the target signal in the first update direction.

[0101] In this way, under the premise of ensuring that the output states of the internal comparators of each chip in each channel are consistent, the target signal can be adjusted so that the output states of the internal comparators of each chip in each channel can jump, thereby realizing the calibration of the thresholds to be calibrated of the internal comparators of each chip in each channel.

[0102] In one of the optional embodiments, for a special type of internal chip comparator, for example, a transition state of an internal PE chip comparator having a metastable characteristic or a hysteresis characteristic means that all states of the output state points of the internal chip comparator collected by the FPGA (points sampled under a specified sampling rate and sampling point configuration) are after the transition.

[0103] For the internal comparator of the PE chip with metastable characteristics or hysteresis characteristics, it is necessary to let the target source scan the calibration values ​​of the thresholds to be calibrated in all channels in the reverse direction again, and take the mathematical statistical value, such as the average value, from the two calibration values ​​to participate in the fitting of the subsequent steps as the true value. In one optional embodiment, the internal comparator of the chip is an internal comparator of the chip with hysteresis characteristics or metastable characteristics; after recording the first correlation relationship between the target signal corresponding to the first jump moment and the threshold to be calibrated, it includes: updating the target signal according to the scanning step and the second update direction, the second update direction is opposite to the first update direction, and the updated target signal is used to input to the second input end of the internal comparator of the chip in each channel; when the output state of the internal comparator of the chip jumps, the second correlation relationship between the target signal corresponding to the second jump moment and the threshold to be calibrated is recorded; the mathematical statistical value of the target signal corresponding to the first jump moment and the target signal corresponding to the second jump moment is calculated; the third correlation relationship between the mathematical statistical value and the threshold to be calibrated is recorded, and the third correlation relationship is used as calibration information. Among them, the comparator with metastable characteristics has the following characteristics: when the target signal is updated in the first update direction or the second update direction and the target signal gradually approaches the threshold to be calibrated, within a certain range approaching the threshold to be calibrated, the output state of the comparator will have glitches, that is, jumps will occur. If the glitches that appear are directly regarded as jumps, it will be inaccurate. Therefore, this article proposes that the jump of the comparator with metastable characteristics refers to the output state duty cycle of the comparator being greater than a preset ratio. The preset ratio may not be fixed and may be set according to actual conditions, such as a preset ratio of 80%.

[0104] Specifically, in this embodiment, the target signal is first updated according to the first update direction, and the target signal corresponding to the first jump moment when the output state of the internal comparator of each chip in each channel jumps is recorded. After the output state of the internal comparator of each chip in each channel jumps, the target signal is updated according to the scanning step and the second update direction. Similarly, the second correlation relationship between the target signal corresponding to the second jump moment and the threshold to be calibrated is recorded in the same processing method as the first update direction, and finally the mathematical statistics of the target signal corresponding to the first jump moment and the target signal corresponding to the second jump moment are calculated, for example, the average value of the two target signals is calculated, and then the third correlation relationship between the mathematical statistics (such as the calculated average value) and the threshold to be calibrated is recorded, and the third correlation relationship is used as calibration information.

[0105] Specifically, the transition of a comparator with a metastable characteristic refers to the fact that the duty cycle of the output state of the comparator is greater than a preset ratio, including the following two situations: in the first update direction, the high level duty cycle of the output state of the comparator is greater than the preset ratio, and in the second update direction, the low level duty cycle of the output state of the comparator is greater than the preset ratio; or, in the first update direction, the low level duty cycle of the output state of the comparator is greater than the preset ratio, and in the second update direction, the high level duty cycle of the output state of the comparator is greater than the preset ratio.

[0106] In one of the optional embodiments, before configuring each threshold to be calibrated to each chip, it includes: performing initialization processing on each channel in parallel, and the initialization processing includes turning off the function of each target channel and configuring the output state collection information of the internal comparator of the chip.

[0107] Among them, before calibration, each channel needs to be initialized. The specific initialization mainly includes two parts: the first part is to turn off the target channel function of the chip, that is, to turn off other functions, such as outputting other channel functions to high impedance state, where other channel functions include but are not limited to Drive, PMU, Active-load. In this application, the output is turned off by function according to different chip models. The second part is to configure the output state acquisition information of the internal comparator of the chip, such as configuring the acquisition information of the acquisition unit of each channel FPGA module, which is not limited to the sampling frequency and / or the number of sampling points.

[0108] In an exemplary embodiment, Figure 5 As shown, a method for calibrating the threshold value of a comparator inside a chip is provided. Figure 3 The terminal in is taken as an example to illustrate, including the following steps 502 to 504. Among them:

[0109] S502: Send a calibration start instruction, where the calibration start instruction is used to instruct the parallel calibration module to execute the chip internal comparator threshold calibration method in any one of the above embodiments to obtain calibration information.

[0110] The calibration start instruction is sent by the terminal to the parallel calibration module, for example, to the first control unit of the parallel calibration module. The first control unit forwards the calibration start instruction to the parallel calibration unit, so that the parallel calibration unit can execute the above-mentioned chip internal comparator threshold calibration method, obtain calibration information, and send the calibration information to the terminal through the first control unit.

[0111] S504: Perform calibration fitting on the calibration information.

[0112] The process of fitting the calibration information is to obtain the corresponding relationship between the threshold to be calibrated of the comparator inside the chip and the target signal (such as voltage value). The threshold to be calibrated here refers to the code of the DAC on which the VOH / VOL setting inside the chip depends.

[0113] The calibration fitting operation is executed by the terminal driver and belongs to the software algorithm level; the channel FPGA module and the parallel calibration module are only responsible for high-speed feedback of the corresponding relationship between the threshold to be calibrated and the target signal of all channels, which can be a curve relationship.

[0114] Optionally, the calibration fitting operation may be to select an appropriate calibration model to perform calibration fitting on each channel respectively, wherein the calibration model includes but is not limited to a straight line model, a curve model, a piecewise straight line, a piecewise curve or a piecewise mixed model, etc.

[0115] In one optional embodiment, before sending the calibration start instruction, it includes: sending calibration configuration parameters to the parallel calibration module, the calibration configuration parameters including each threshold to be calibrated, the target source initial value, the first update direction and the scanning step size.

[0116] Among them, the calibration configuration parameters are used to control the calibration process, which include various thresholds to be calibrated, wherein the calibration thresholds can be arranged in a certain order, or can be arranged in a chaotic manner, and the calibration thresholds in each channel can be the same or different. Optionally, the calibration thresholds in each channel are the same, and no specific restrictions are made here.

[0117] The target source initial value is pre-set, wherein the target source initial value may be related to the voltage or current corresponding to each calibration threshold, and the target source initial values ​​corresponding to different calibration thresholds are different. For example, the voltage value range corresponding to the threshold to be calibrated is known, and the target source initial value may be any voltage value within the voltage value range.

[0118] The first update direction is related to the target source initial value. When the target source initial value is smaller than the voltage value corresponding to the threshold to be calibrated, the first update direction can be from small to large. When the target source initial value is greater than the voltage value corresponding to the threshold to be calibrated, the first update direction can be from large to small.

[0119] The scanning step length is the step length of the change of the target signal, wherein the scanning step length may be related to the calibration accuracy of the threshold to be calibrated. The higher the calibration accuracy of the threshold to be calibrated, the smaller the scanning step length.

[0120] In one of the optional embodiments, before sending the calibration start instruction, the method includes sending a calibration initialization instruction, where the calibration initialization instruction is used to instruct the parallel calibration module to perform initialization processing on each channel in parallel.

[0121] Among them, before calibration, the channels of each chip need to be initialized. The terminal sends a calibration initialization instruction to the parallel calibration module, so that the parallel calibration module initializes each channel in parallel to improve the efficiency of initialization. The specific initialization of each channel mainly includes two parts: the first part is to turn off the target channel function of the chip, that is, to turn off other channel functions, such as outputting other channel functions as high impedance, where other channel functions include but are not limited to Drive, PMU, Active-load. In this application, the output is turned off by function according to different chip models. The second part is to configure the output state acquisition information of the internal comparator of the chip, such as configuring the acquisition information of the acquisition unit of each channel FPGA module, and the acquisition information includes but is not limited to the sampling frequency and / or the number of sampling points.

[0122] For ease of understanding, combined Figure 6 As shown, Figure 6This is a simplified timing diagram of a chip internal comparator threshold calibration method in an embodiment. The complete process is described here. The complete process of the calibration initialization instruction is as follows: the calibration initialization instruction sent by the terminal is first sent to the parallel calibration unit through the first main control unit, and then the parallel calibration unit triggers the parallel calibration initialization instruction and feeds back to the first main control unit. The first main control unit then broadcasts the calibration initialization instruction to the second main control unit, and the second main control unit initializes the acquisition unit. The initialization of the acquisition unit mainly configures the sampling frequency and / or sampling points of the acquisition unit. The second main control unit will also pass the parallel calibration initialization instruction to the second peripheral unit, thereby initializing all chip channels, that is, according to different chip models, the output is closed according to the channel function. The complete process of configuring calibration parameters is as follows: the terminal sends a calibration parameter configuration instruction, which is first sent to the parallel calibration unit through the first main control unit, and then fed back to the first main control unit by the parallel calibration unit, wherein each threshold value to be calibrated in the calibration configuration parameter is configured by the first main control unit through the second main control unit and the acquisition unit in turn to the first input end of all comparators in each channel of each chip; wherein the target source initial value, the first update direction, the second update direction and the scanning step length in the calibration configuration parameter are configured to the target source in turn by the first main control unit and the first peripheral unit. After the initialization and calibration configuration parameters are sent, the complete process of the calibration start instruction is as follows: the terminal sends a calibration start instruction, which is first sent to the parallel calibration unit through the first main control unit, and then fed back to the first main control unit by the parallel calibration unit, and the threshold value to be calibrated is configured in parallel to each chip through the first main control unit and the second main control unit, so that the first input end of the chip internal comparator in each channel of each chip is input to the corresponding threshold value to be calibrated. The parallel calibration unit also configures the target source based on the target source initial value so that the target source outputs a corresponding target signal to the second input terminal of the comparator inside each chip. The subsequent parallel calibration unit updates the target signal based on the first update direction and the scanning step size.

[0123] Each acquisition unit acquires the output state of the internal comparator of the chip, and forwards the output state to the parallel calibration unit through the second main control unit and the first main control unit, wherein the parallel calibration unit records the first jump time when the output state of the internal comparator of the chip jumps.

[0124] Optionally, at the beginning of calibration, each acquisition unit acquires the output state of the comparator inside the chip. After the parallel calibration unit obtains the output state of the comparator inside the chip acquired by each acquisition unit, it determines whether the output states are the same. If they are not the same, the target signal is updated according to a second update direction (opposite to the first update direction) and a scanning step size until the output states of the comparators inside the chip acquired by each acquisition unit are the same.

[0125] After the output states of the internal comparators of the collected chips by the various acquisition units are the same, the target signal is updated according to the first update direction and the scanning step length, that is, the initial value of the target source is updated according to the first update direction and the scanning step length, so that the target source outputs a target signal, and the output states of the internal comparators of the chip are collected in parallel by the various acquisition units. After the parallel calibration unit obtains the output states of the internal comparators of the chips collected by the various acquisition units, the calibration information at the first jump moment is recorded, that is, the threshold to be calibrated of the internal comparators of each chip at the first jump moment and the corresponding target signal are recorded.

[0126] If there are other thresholds to be calibrated, the thresholds to be calibrated are changed synchronously in one direction in sequence, and the above process is repeated for each threshold to be calibrated, and the target signal corresponding to the threshold to be calibrated of each chip internal comparator in each channel is recorded.

[0127] The parallel calibration unit sends the recorded calibration information to the terminal through the first control unit, and the terminal fits the calibration information recorded by each channel based on the recorded calibration information.

[0128] In the above embodiment, the actual output of the internal comparator of the chip is collected, and the offset introduced by the internal link of the chip is calibrated together, which can truly reflect the actual signal; in addition, through FPGA high-frequency sampling, narrow pulse leakage in the metastable state is avoided, and the overall accuracy is higher. Moreover, the calibration in all channels is performed through FPGA parallel sampling, and the software is uniformly calculated, so the overall calibration efficiency is higher.

[0129] It should be understood that, although the steps in the flowcharts involved in the above embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above embodiments may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0130] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 7As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and the external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be realized through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a method for calibrating the threshold of a comparator inside a chip is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0131] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0132] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0133] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0134] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0135] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0136] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0137] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for calibrating a comparator threshold inside a chip, characterized in that: Applied to a parallel calibration module, the method comprises: Allocating each threshold value to be calibrated to each chip, wherein the threshold value to be calibrated is used to obtain an input value of a first input terminal of an internal comparator in each channel in the chip; configuring the target source initial value to the target source to instruct the target source to generate a target signal, wherein the target signal is an input value of the second input terminal of each internal comparator of the chip; Acquire the output states of the internal comparators of the chip in each of the channels in parallel; The target signal is updated according to the scanning step length and the first updating direction, and the updated target signal is used to be input to the second input end of the internal comparator of the chip in each of the channels; When the output state of the comparator inside the chip changes, a first correlation relationship between the target signal corresponding to the first change moment and the threshold to be calibrated is recorded; Using the first association relationship as calibration information; When the output states of the internal comparators of the chip in each of the channels are different, the target signal is updated according to a second update direction until the output states of the internal comparators of the chip in each of the channels are the same; the updated target signal is used to input into the internal comparators of the chip in each of the channels, and the second update direction is opposite to the first update direction.

2. The method according to claim 1, characterized in that The method further comprises: When the output states of the comparators inside each chip change, the next threshold to be calibrated is obtained, and the step of configuring the target source initial value to the target source to instruct the target source to generate a target signal is continued until the association between each threshold to be calibrated and the corresponding target signal is obtained.

3. The method according to claim 1, characterized in that The chip includes at least two internal comparators of the chip; and the step of obtaining the output states of the internal comparators of the chip in each channel in parallel includes: The output states of the internal comparators of each chip in each channel are acquired in parallel, respectively, wherein the output states of the internal comparators of each chip in each channel are acquired in parallel.

4. The method according to claim 1, characterized in that: The internal comparator of the chip is a comparator with hysteresis characteristics or metastable characteristics; after recording the first correlation relationship between the target signal corresponding to the first jump moment and the threshold to be calibrated, it includes: The target signal is updated according to a scanning step length and a second updating direction, wherein the second updating direction is opposite to the first updating direction, and the updated target signal is used to be input to a second input terminal of the internal comparator of the chip in each of the channels; When the output state of the comparator inside the chip changes, a second correlation relationship between the target signal corresponding to a second change time and the threshold to be calibrated is recorded, wherein the change of the comparator with a metastable characteristic refers to that the duty cycle of the output state of the comparator is greater than a preset ratio; Calculating mathematical statistics of the target signal corresponding to the first transition time and the target signal corresponding to the second transition time; A third association relationship between the mathematical statistic value and the threshold value to be calibrated is recorded, and the third association relationship is used as calibration information.

5. The method according to claim 4, characterized in that The transition of the comparator with metastable characteristics refers to the output state duty cycle of the comparator being greater than a preset ratio, including: In the first update direction, the high level duty cycle of the output state of the comparator is greater than the preset ratio, and in the second update direction, the low level duty cycle of the output state of the comparator is greater than the preset ratio; or, In the first update direction, the low level duty cycle of the output state of the comparator is greater than a preset ratio, and in the second update direction, the high level duty cycle of the output state of the comparator is greater than a preset ratio.

6. The method according to any one of claims 1 to 5, characterized in that: Before configuring each threshold value to be calibrated to each chip, the method includes: Initialization processing is performed on each of the channels in parallel, and the initialization processing includes shutting down the function of each target channel and configuring the output state acquisition information of the comparator inside the chip.

7. A method for calibrating a comparator threshold inside a chip, characterized in that: Applied to a terminal, the method comprises: Sending a calibration start instruction, wherein the calibration start instruction is used to instruct the parallel calibration module to execute the chip internal comparator threshold calibration method according to any one of claims 1 to 6 to obtain calibration information; A calibration fit is performed on the calibration information.

8. The method according to claim 7, characterized in that Before sending the calibration start instruction, the method includes: Calibration configuration parameters are sent to the parallel calibration module, wherein the calibration configuration parameters include each threshold to be calibrated, a target source initial value, a first update direction, and a scanning step size.

9. The method according to claim 7, characterized in that: Before sending the calibration start instruction, the method includes: A calibration initialization instruction is sent, where the calibration initialization instruction is used to instruct the parallel calibration module to perform initialization processing on each of the channels in parallel.

10. A chip internal comparator threshold calibration system, characterized in that: The system comprises: A chip including a plurality of channels, each channel including at least one internal comparator of the chip; At least one channel FPGA module, used for parallel acquisition of the output state of the chip internal comparator in each channel of the chip, wherein each of the channels is calibrated in parallel, and each of the chip internal comparators in each of the channels is calibrated in parallel; A target source, used to generate a target signal; A parallel calibration module is used to execute the chip internal comparator threshold calibration method described in any one of claims 1 to 6 to obtain calibration information.

11. The system according to claim 10, characterized in that The parallel calibration module includes a parallel calibration unit, a first main control unit and a first peripheral unit, wherein the first main control unit is communicatively connected with the channel FPGA module, the first peripheral unit and the parallel calibration unit; the first peripheral unit is communicatively connected with the target source, and the target source is communicatively connected with the second input end of the chip internal comparator in each of the channels in each of the chips; The parallel calibration unit is used to execute the chip internal comparator threshold calibration method according to any one of claims 1 to 6 to obtain calibration information; The first peripheral unit is used to be controlled by the first main control unit, and to control the target source to output a corresponding target signal to an internal comparator of the chip in each channel of each chip; The first main control unit is used to initialize each channel of each chip, configure the calibration parameters of the parallel calibration unit, forward the calibration-related instructions provided by the parallel calibration unit to the channel FPGA module, forward the output status of the internal comparator of the chip returned by the channel FPGA module to the parallel calibration unit, and forward the calibration information generated by the parallel calibration unit.

12. The system according to claim 10, characterized in that The channel FPGA module includes a second main control unit, a second peripheral unit and an acquisition unit, the second main control unit is communicatively connected with the parallel calibration module, the second peripheral unit and the acquisition unit, the second peripheral unit is communicatively connected with the chip, and the acquisition unit is communicatively connected with the internal comparator of the chip respectively; The second main control unit is used to receive calibration related instructions sent by the parallel calibration module; The second peripheral unit is used for initializing each channel of each chip based on the calibration initialization instruction in the calibration related instruction; The acquisition unit is used to acquire the output state of the chip internal comparator in each channel of each chip based on the calibration start instruction in the calibration related instructions, and send the output state of the chip internal comparator to the parallel calibration module through the second main control unit.

13. The system according to claim 10, characterized in that The system further comprises: The terminal communicates with the parallel calibration module, and is used to obtain the calibration information from the parallel calibration module and perform calibration fitting on the calibration information.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 or 7 to 9 are implemented.

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