T-type gate planar superjunction MOSFET and preparation method and chip thereof

Abstract

The present application belongs to the technical field of power devices, and provides a T-type gate planar super junction MOSFET and a preparation method and chip thereof, wherein a gate dielectric layer is formed on the groove sidewalls, the groove bottom, the first P-type base region, and the second P-type base region of an N-type drift layer, and the gate dielectric layer wraps the gate polysilicon layer, the gate polysilicon layer is a T-type structure, and the vertical portion of the gate polysilicon layer extends deep into between adjacent first P columns and second P columns, thereby forming an electron current high-speed channel in the N-type drift layer, greatly improving the electron current density in the JFET region, successfully eliminating the JFET effect, increasing the saturation current of the device, and solving the problem of the JFET effect existing in the traditional planar SJ MOS.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to a T-type gate planar super junction MOSFET and a preparation method and chip thereof. Background Art

[0002] Planar SJ MOSFET Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor (SJMOSFET) is widely used in many electrical fields due to its excellent high-voltage resistance.

[0003] However, the traditional planar SJ MOS has an inevitable JFET effect, and the JFET resistance will increase the conduction loss of the device and reduce the saturation current. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a T-gate planar super junction MOSFET and a preparation method and chip thereof, which can solve the problem of JFET effect existing in traditional planar SJ MOS.

[0005] A first aspect of an embodiment of the present application provides a T-type gate planar super junction MOSFET, wherein the T-type gate planar super junction MOSFET comprises:

[0006] N-type substrate;

[0007] A first P column, an N-type drift layer, and a second P column are formed on the front surface of the N-type substrate; wherein the N-type drift layer is located between the first P column and the second P column;

[0008] A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P-pillar, and the second P-type base region is formed on the second P-pillar;

[0009] A first N-type source region and a second N-type source region, wherein the first N-type source region is formed in a groove of the first P-type base region, and the second N-type source region is formed in a groove of the second P-type base region;

[0010] A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the groove sidewalls and the groove bottom of the N-type drift layer and the first P-type base region and the second P-type base region, and the gate dielectric layer wraps the gate polysilicon layer, the gate polysilicon layer is a T-shaped structure, and the vertical portion of the gate polysilicon layer extends deep into between the adjacent first P column and the second P column;

[0011] A source layer formed on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region and a portion of the gate dielectric layer;

[0012] The drain layer is formed on the back side of the N-type substrate.

[0013] In some embodiments, the vertical portion of the gate polysilicon layer is disposed opposite to a portion of the first P column and the second P column.

[0014] In some embodiments, the length of a partial area where the first P column is relatively set to the gate polysilicon layer is 1%-10% of the length of the first P column; and / or the length of a partial area where the second P column is relatively set to the gate polysilicon layer is 1%-10% of the length of the second P column.

[0015] In some embodiments, a distance between a vertical portion of the gate polysilicon layer and the first P-type base region and the second P-type base region is greater than one tenth of a width of the N-type drift layer and less than one quarter of a width of the N-type drift layer.

[0016] In some embodiments, the widths of the first P-type base region and the second P-type base region gradually increase in a direction from the drain layer to the source layer.

[0017] In some embodiments, the width of the vertical portion of the gate polysilicon layer gradually decreases in a direction from the drain layer to the source layer.

[0018] In some embodiments, the gate polysilicon layer has a trapezoidal structure.

[0019] In some embodiments, the first P-type base region and the second P-type base region are symmetrically disposed with respect to a vertical portion of the gate polysilicon layer.

[0020] A second aspect of the embodiment of the present application further provides a method for preparing a T-type gate planar super junction MOSFET, the method comprising:

[0021] An N-type drift region is generated by epitaxy on the front side of the N-type substrate;

[0022] A first P column, an N-type drift layer, and a second P column are formed in a partial area of ​​the N-type drift region by using trenching and epitaxial processes; wherein the N-type drift layer is located between the first P column and the second P column;

[0023] Continue epitaxially growing an N-type drift region on the first P column, the N-type drift layer, and the second P column, and implant P-type doping ions into a portion of the N-type drift region to form a first P-type base region and a second P-type base region; wherein the first P-type base region is formed on the first P column, and the second P-type base region is formed on the second P column;

[0024] Implanting N-type doping ions into partial regions on the first P-type base region and the second P-type base region to form a first N-type source region and a second N-type source region, so that the first N-type source region is formed in a groove of the first P-type base region, and the second N-type source region is formed in the groove of the second P-type base region;

[0025] Etching a groove on the N-type drift layer, and epitaxially growing a gate oxide material to form a gate dielectric layer; wherein the gate dielectric layer is formed on the groove sidewalls and bottom of the N-type drift layer and on the first P-type base region and the second P-type base region;

[0026] Depositing polysilicon material on the gate dielectric layer to form a gate polysilicon layer, and continuing to epitaxially grow a gate oxide material to form the gate dielectric layer wrapping the gate polysilicon layer; wherein the gate polysilicon layer is a T-shaped structure, and the vertical portion of the gate polysilicon layer extends deep into between the adjacent first P column and the second P column;

[0027] A source layer is formed on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region and a portion of the gate dielectric layer, and a drain layer is formed on the back side of the N-type substrate.

[0028] A third aspect of the embodiments of the present application further provides a chip, comprising a T-gate planar super junction MOSFET as described in any of the above embodiments.

[0029] The beneficial effects of the embodiments of the present application are as follows: a gate dielectric layer is formed on the groove sidewalls, the groove bottom, the first P-type base region, and the second P-type base region of the N-type drift layer, and the gate dielectric layer wraps the gate polysilicon layer, the gate polysilicon layer is a T-shaped structure, and the vertical portion of the gate polysilicon layer extends deep into between the adjacent first P column and the second P column, thereby forming an electron current high-speed channel in the N-type drift layer, greatly improving the electron current density in the JFET region, successfully eliminating the JFET effect, increasing the saturation current of the device, and solving the problem of the JFET effect existing in the traditional planar SJ MOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic diagram of the structure of a T-gate planar superjunction MOSFET provided in an embodiment of the present application;

[0031] Figure 2 It is a schematic diagram of the simulation structure of a T-type gate planar super junction MOSFET in an embodiment of the present application;

[0032] Figure 3 It is a schematic diagram of output characteristic simulation of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application;

[0033] Figure 4 It is a schematic diagram of simulation of the breakdown voltage of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application;

[0034] Figure 5 It is a simulation schematic diagram of transfer characteristic curves of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application;

[0035] Figure 6a Schematic diagram of the electron current density at the position of x=-0.5um for a conventional planar super junction MOSFET and a T-gate planar super junction MOSFET in an embodiment of the present application;

[0036] Figure 6b Schematic diagram of the electron current density at the position of y=0.3um for a conventional planar super junction MOSFET and a T-gate planar super junction MOSFET in an embodiment of the present application;

[0037] Figure 7a It is a schematic diagram of current density simulation of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application;

[0038] Figure 7b Schematic diagram of current density in the drift region of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application in the horizontal direction y=0um;

[0039] Figure 8 Another schematic diagram of the structure of a T-type gate planar super junction MOSFET device provided in an embodiment of the present application;

[0040] Fig. 9 It is a schematic flow chart of a method for preparing a T-type gate planar super junction MOSFET provided in an embodiment of the present application;

[0041] Fig.10 is a schematic diagram of forming an N-type drift layer on an N-type substrate provided by an embodiment of the present application;

[0042] Fig.11 is a schematic diagram of forming a first P column and a second P column provided in an embodiment of the present application;

[0043] Fig.12 is a schematic diagram of an N-type drift layer of a T-type structure provided in an embodiment of the present application;

[0044] Fig.13 It is a schematic diagram of forming a first P-type base region, a second P-type base region, a first N-type source region, and a second N-type source region provided by an embodiment of the present application;

[0045] Fig.14 is a schematic diagram of etching a groove on an N-type drift layer provided in an embodiment of the present application;

[0046] Fig.15 It is a schematic diagram of forming a gate dielectric layer provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0048] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0049] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0051] Traditional planar SJ MOS has an inevitable JFET effect, and the JFET resistance will increase the conduction loss of the device and reduce the saturation current.

[0052] In order to solve the above technical problems, the present application embodiment provides a T-type gate planar super junction MOSFET, see Figure 1 As shown, the T-type gate planar super junction MOSFET in this embodiment includes: an N-type substrate 110, a first P column 121, an N-type drift layer 124, a second P column 122, a first P-type base region 125, a second P-type base region 127, a first N-type source region 126, a second N-type source region 128, a gate dielectric layer 130, a gate polysilicon layer 131, a source layer 132, a drain layer 133, the first P column 121, the N-type drift layer 124, the second P column 122, the first P-type base region 125, the second P-type base region 127, the first N-type source region 126, the second N-type source region 128, the gate dielectric layer 130, the gate polysilicon layer 131, the source layer 132, the drain layer 133, 4. The second P column 122 is formed on the front surface of the N-type substrate 110; wherein the N-type drift layer 124 is located between the first P column 121 and the second P column 122; the first P-type base region 125 is formed on the first P column 121, and the second P-type base region 127 is formed on the second P column 122; the first N-type source region 126 is formed in the groove of the first P-type base region 125, and the second N-type source region 128 is formed in the groove of the second P-type base region 127. The gate dielectric layer 130 is formed on the sidewall and bottom of the groove of the N-type drift layer 124, and on the first P-type base region 125 and the second P-type base region 127, and the gate dielectric layer 130 wraps the gate polysilicon layer 131, and the gate polysilicon layer 131 is a T-shaped structure, and the vertical portion of the gate polysilicon layer 131 extends deep into the space between the adjacent first P column 121 and the second P column 122. The source layer 132 is formed on the first N-type source region 126 , the second N-type source region 128 , the first P-type base region 125 , the second P-type base region 127 and a portion of the gate dielectric layer 130 ; the drain layer 133 is formed on the back side of the N-type substrate 110 .

[0053] In this embodiment, a gate dielectric layer 130 is formed on the sidewalls of the groove, the bottom of the groove, the first P-type base region 125, and the second P-type base region 127 of the N-type drift layer 124, and the gate dielectric layer 130 wraps the gate polysilicon layer 131, the gate polysilicon layer 131 is a T-shaped structure, and the vertical portion of the gate polysilicon layer 131 extends deep into the adjacent first P column 121 and the second P column 122, the N-type drift layer 124 is a concave structure, and a portion of the N-type drift layer 124 is provided between the first P-type base region 125 and the gate polysilicon layer 131. A side portion, another side portion of the N-type drift layer 124 is provided between the second P-type base region 127 and the gate polysilicon layer 131, and the gate dielectric layer 130 isolates the gate polysilicon layer 131 from the N-type drift layer 124. When an appropriate gate voltage is applied to the gate polysilicon layer 131, an electron current high-speed channel can be formed in the N-type drift layer 124, and the electron current density in the JFET region is greatly improved, thereby successfully eliminating the JFET effect, increasing the saturation current of the device, and solving the problem of the JFET effect existing in the traditional planar SJMOS.

[0054] Figure 2is a schematic diagram of the simulation structure of a T-type gate planar super junction MOSFET in the embodiment of the present application. Table 1 shows the characteristic parameters of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in the embodiment of the present application. Figure 1 and Figure 2 As shown in the figure, by using T-shaped gate polysilicon to adjust the JFET region in the planar superjunction MOSFET, a high-speed electron current channel can be formed in the JFET region. The electron current density in the JFET region is increased by 2 orders of magnitude (as shown in Table 1), and the on-resistance Ron of the device is reduced from 205mΩ to 160mΩ, a decrease of 22%. The saturated drain current I Dsat It increased from 48.8A to 76.7A, an increase of 57%. The JFET effect was successfully eliminated through the optimization of gate polysilicon and the saturation current of the device was increased.

[0055] Table 1:

[0056]

[0057] In some embodiments, the vertical portion of the gate polysilicon layer 131 is disposed opposite to a portion of the first P-pillar 121 and the second P-pillar 122 .

[0058] In the present embodiment, the vertical portion of the gate polysilicon layer 131 penetrates into the N-type drift layer 124, and a part of the vertical portion of the gate polysilicon layer 131 is located between the first P column 121 and the second P column 122. Such a design can avoid the first P-type base region 125 and the second P-type base region 127 being directly opposite to each other, and the current of the drain layer 133 can enter the first P-type base region 125 and the second P-type base region 127 respectively through the two side portions of the N-type drift layer 124, thereby forming an electron current high-speed channel in the N-type drift layer 124, and the electron current density in the JFET region is greatly improved, thereby successfully eliminating the JFET effect, increasing the drain saturation current of the device, and solving the problem of the JFET effect existing in the traditional planar SJ MOS.

[0059] In some embodiments, the length of a portion of the first P column 121 that is disposed opposite to the gate polysilicon layer 131 is 1%-10% of the length of the first P column 121 .

[0060] In this embodiment, a partial area of ​​the first P-pillar 121 is arranged opposite to the top area of ​​the vertical portion of the gate polysilicon layer 131. By setting the length of the partial area where the first P-pillar 121 and the gate polysilicon layer 131 are arranged opposite to each other to be 1%-10% of the length of the first P-pillar 121, it is possible to avoid the first P-type base region 125 and the second P-type base region 127 being opposite to each other, and to avoid the problem of a decrease in breakdown voltage due to the excessive length of the vertical portion of the gate polysilicon layer 131.

[0061] In some embodiments, the length of a portion of the second P column 122 disposed opposite to the gate polysilicon layer 131 is 1%-10% of the length of the second P column 122 .

[0062] In this embodiment, a partial area of ​​the second P-column 122 is arranged opposite to the top area of ​​the vertical portion of the gate polysilicon layer 131. By setting the length of the partial area of ​​the second P-column 122 that is arranged opposite to the gate polysilicon layer 131 to 1%-10% of the length of the first P-column 121, it is possible to avoid the first P-type base region 125 and the second P-type base region 127 being opposite to each other, and to avoid the problem of a decrease in breakdown voltage due to the length of the vertical portion of the gate polysilicon layer 131 being too long.

[0063] In some embodiments, the distance between the vertical portion of the gate polysilicon layer 131 and the first and second P-type base regions 125 and 127 is greater than one tenth of the width of the N-type drift layer 124 and less than one quarter of the width of the N-type drift layer 124 .

[0064] In this embodiment, a side portion of the N-type drift layer 124 is provided between the vertical portion of the gate polysilicon layer 131 and the first P-type base region 125 , and another side portion of the N-type drift layer 124 is provided between the vertical portion of the gate polysilicon layer 131 and the second P-type base region 127 , and the current of the drain layer 133 can flow to the source layer 132 via the two side portions of the N-type drift layer 124 .

[0065] In some embodiments, the widths of the first P-type base region 125 and the second P-type base region 127 gradually increase in a direction from the drain layer 133 to the source layer 132 .

[0066] Figure 3 1 is a schematic diagram of output characteristic simulation of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application, wherein curve 1 represents the output characteristic curve of the T-type gate planar super junction MOSFET in an embodiment of the present application, and curve 2 represents the output characteristic curve of the conventional planar super junction MOSFET. Figure 3 The horizontal axis is the source-drain voltage VDS, and the vertical axis is the source-drain current IDS. Figure 3 As shown in FIG. 1 , the on-resistance (Ron) of the T-type gate planar superjunction MOSFET decreases by 22%. Since the drift region in the N-type drift layer 124 is not changed, the decrease in on-resistance is entirely due to the decrease in JFET resistance. The saturated drain current (I Dsat ) increased by 57%, which is due to the decrease in on-resistance (Ron). The high-speed electron current channel of the T-gate also increases the current density in the drift region, so the saturation drain current (I Dsat ) has been greatly improved.

[0067] Figure 4 3 is a simulation diagram of the breakdown voltage of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application. Curve 3 is a curve of the breakdown voltage of the T-type gate planar super junction MOSFET in an embodiment of the present application. Figure 4 is the breakdown voltage curve of the traditional planar superjunction MOSFET. Figure 4 The horizontal axis is the source-drain voltage VDS, and the vertical axis is the source-drain current IDS. Figure 4 As shown in Table 1, compared with the traditional planar super junction MOSFET, the breakdown voltage of the T-gate planar super junction MOSFET in the embodiment of the present application is slightly reduced, and the change rate of the breakdown voltage is less than 1%, which will not affect the normal use of the device.

[0068] Figure 5 : is a simulation schematic diagram of the transfer characteristic curves of the traditional planar super junction MOSFET and the T-type gate planar super junction MOSFET in the embodiment of the present application, curve 5 is the transfer characteristic curve of the T-type gate planar super junction MOSFET in the embodiment of the present application, and curve 6 is the transfer characteristic curve of the traditional planar super junction MOSFET. Figure 5 The horizontal axis is the gate-source voltage VGS, and the vertical axis is the source-drain current IDS. Figure 5 As shown in Table 1, the source-drain current of the T-gate planar super junction MOSFET in the embodiment of the present application is greatly increased when Vgs is consistent.

[0069] Figure 6a Schematic diagram of the electron current density at the position of x=-0.5um of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application, Figure 6a The vertical axis represents the electron current density. Figure 6a The abscissa in represents the horizontal direction of the device, and Curve 7 is the electron current density curve of the T-type gate planar super junction MOSFET in the embodiment of the present application. Figure 8 This is the electron current density curve of the traditional planar superjunction MOSFET. Figure 6b Schematic diagram of the electron current density at the position of y=0.3um of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application, Figure 6b The vertical axis represents the electron current density. Figure 6b The abscissa in represents the vertical direction of the device, and Curve 9 is the electron current density curve of the T-type gate planar super junction MOSFET in the embodiment of the present application. Fig.10 This is the electron current density curve of the traditional planar superjunction MOSFET. Figure 6a , Figure 6bAs shown in Table 1, the T-type gate planar super junction MOSFET in the embodiment of the present application forms an electron current high-speed channel (such as Figure 6b ), the electron current density in the JFET region increased by 2 orders of magnitude (as shown in Table 1), successfully eliminating the JFET effect and increasing the saturation current of the device.

[0070] Figure 7a : is a schematic diagram of current density simulation of a conventional planar super junction MOSFET and a T-type gate planar super junction MOSFET in an embodiment of the present application, wherein: Figure 7a The diagram (a) is a schematic diagram of the current density simulation of a conventional planar superjunction MOSFET. Figure 7a Schematic diagram (b) is a current density simulation schematic diagram of a T-type gate planar super junction MOSFET in an embodiment of the present application, Figure 7b 1 is a schematic diagram of the current density of the drift region of the conventional planar super junction MOSFET and the T-type gate planar super junction MOSFET in the embodiment of the present application in the horizontal direction y=0um, curve 11 is the electron current density curve of the T-type gate planar super junction MOSFET in the embodiment of the present application, Fig.12 This is the electron current density curve of the traditional planar superjunction MOSFET. Figure 7a , Figure 7b As shown in Table 1, the I Dsat Combined with the above simulation diagram ( Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6a , Figure 6b , Figure 7a , Figure 7b ) and Table 1 show that the T-gate planar super junction MOSFET in the embodiment of the present application successfully eliminates the JFET resistance of the traditional planar SJ MOS without reducing the static characteristics of the device, reduces the on-resistance, and greatly improves the saturation drain current. It is used in high-voltage and high-current application scenarios, and is expected to greatly expand the application range of the planar super junction MOSFET.

[0071] In some embodiments, see Figure 8 As shown, the width of the vertical portion of the gate polysilicon layer 131 gradually decreases in the direction from the drain layer 133 to the source layer 132 .

[0072] In this embodiment, the vertical portion of the gate polysilicon layer 131 is gradually reduced in the direction from the drain layer 133 to the source layer 132, so that the bottom area of ​​the vertical portion of the gate polysilicon layer 131 begins to gradually widen until the horizontal portion of the gate polysilicon layer 131 reaches the minimum width at the interface position with the horizontal portion of the gate polysilicon layer 131. With such a design, the vertical portion of the gate polysilicon layer 131 is related to the depth of the drift region where it is located, and is matched with the first P-type base region 125 and the second P-type base region 127 on both sides of the vertical portion of the gate polysilicon layer 131, so as to avoid a large sudden change in the electron current density in the electron current high-speed channel, reduce the negative effect of the increase in the electron current density, ensure the stability of the device, and help eliminate the JEFT effect in the device and increase the saturation current of the device.

[0073] In some embodiments, the gate polysilicon layer 131 has a trapezoidal structure.

[0074] In some embodiments, the first P-type base region 125 and the second P-type base region 127 are symmetrically disposed with respect to a vertical portion of the gate polysilicon layer 131 .

[0075] The present application also provides a method for preparing a T-type gate planar super junction MOSFET, see Fig. 9 As shown, the preparation method in this embodiment includes steps S100 to S900.

[0076] In step S100 , an N-type drift region is epitaxially grown on the front surface of the N-type substrate 110 .

[0077] Combination Fig.10 As shown, an N-type drift region can be formed on the front side of the N-type substrate 110 by an epitaxial growth process, and the thickness of the N-type drift region is greater than the thickness of the N-type substrate 110 .

[0078] In some embodiments, the thickness of the N-type substrate 110 may be 3-10 um.

[0079] In some embodiments, the doping concentration of N-type doping ions in the N-type substrate 110 may be 1e 20 cm-3.

[0080] In some embodiments, the thickness of the N-type drift region epitaxially grown on the front side of the N-type substrate 110 in step S100 may be 20-60 um.

[0081] In some embodiments, the doping concentration of N-type doping ions in the N-type drift region epitaxially generated on the front side of the N-type substrate 110 in step S100 may be 1e 15 ~1e 17 cm -3 .

[0082] In step S200 , a first P column 121 , an N-type drift layer 124 , and a second P column 122 are formed in a partial area of ​​the N-type drift region by using trenching and epitaxial processes.

[0083] In this embodiment, combined with Fig.11 As shown, deep grooves are formed by etching the two side areas of the N-type drift region, and then P-type semiconductor materials are epitaxially grown in the deep grooves to form a first P column 121 and a second P column 122 respectively, and the N-type drift layer 124 is located between the first P column 121 and the second P column 122.

[0084] In some embodiments, the widths of the N-type drift layer 124 , the first P column 121 , and the second P column 122 are the same.

[0085] In some embodiments, the doping concentration of the P-type doping ions in the first P column 121 and the second P column 122 may be 1e 15 ~1e 17 cm -3 .

[0086] In step S300 , an N-type drift region is epitaxially grown on the first P column 121 , the N-type drift layer 124 , and the second P column 122 , and P-type dopant ions are implanted into a portion of the N-type drift region to form a first P-type base region 125 and a second P-type base region 127 .

[0087] In this embodiment, combined with Fig.12 As shown, the N-type drift region is epitaxially grown on the first P column 121, the N-type drift layer 124, and the second P column 122 to form a T-shaped N-type drift layer 124. The thickness of the N-type drift region on the first P column 121 and the second P column 122 can be 1-5 um, and the doping concentration of the N-type drift region on the first P column 121 and the second P column 122 can be 1e 15 ~1e 17 cm -3 .

[0088] In some embodiments, in combination Fig.13 As shown, P-type doping ions are implanted into the first P column 121 and the second P column 122 to form a first P-type base region 125 and a second P-type base region 127, respectively. The doping concentration of the first P-type base region 125 and the second P-type base region 127 is 1e 17 ~5e 18 cm -3 , a first P-type base region 125 is formed on the first P-column 121 , and a second P-type base region 127 is formed on the second P-column 122 .

[0089] In step S400, N-type dopant ions are implanted into partial regions on the first P-type base region 125 and the second P-type base region 127 to form a first N-type source region 126 and a second N-type source region 128, so that the first N-type source region 126 is formed in a groove of the first P-type base region 125, and the second N-type source region 128 is formed in a groove of the second P-type base region 127.

[0090] In this embodiment, combined with Fig.13 As shown, N-type dopant ions are implanted into a portion of the first P-type base region 125 and the second P-type base region 127 to form a first N-type source region 126 and a second N-type source region 128. The doping concentration of the N-type dopant ions in the first N-type source region 126 and the second N-type source region 128 is 1e 19 ~5e 20 cm -3 .

[0091] In step S500 , a groove is formed by etching on the N-type drift layer 124 , and a gate oxide material is epitaxially grown to form a gate dielectric layer 130 ; wherein the gate dielectric layer 130 is formed on the groove sidewalls, the groove bottom, the first P-type base region 125 , and the second P-type base region 127 of the N-type drift layer 124 .

[0092] In this embodiment, combined with Fig.14 As shown, a groove is etched on the N-type drift layer 124, the width of the groove is 0.1-1 um, the depth of the groove is 1-4 um, and the width of the entire device is 8-16 um. Fig.15 As shown, a groove is formed by etching on the N-type drift layer 124 between the first P-type base region 125 and the second P-type base region 127 , and then a gate oxide material is epitaxially grown to form a gate dielectric layer 130 covering the groove sidewalls and bottom of the N-type drift layer 124 and the first P-type base region 125 and the second P-type base region 127 .

[0093] In some embodiments, the thickness of the gate dielectric layer 130 is 50-100 nm.

[0094] In step S600 , polysilicon material is deposited on the gate dielectric layer 130 to form a gate polysilicon layer 131 , and gate oxide material is continuously epitaxially grown to form the gate dielectric layer 130 that wraps the gate polysilicon layer 131 .

[0095] In this embodiment, combined with Figure 1As shown, after forming a gate dielectric layer 130 at the bottom and sidewall of the groove on the N-type drift layer 124, polysilicon material is deposited on the gate dielectric layer 130 to form a gate polysilicon layer 131. The polysilicon material is located on the groove of the N-type drift layer 124, the first P-type base region 125, and the second P-type base region 127, so that the gate polysilicon layer 131 is a T-shaped structure, and the vertical portion of the gate polysilicon layer 131 extends deep into the space between the adjacent first P column 121 and the second P column 122. Figure 1 As shown, after depositing the polysilicon material, the polysilicon material on the first P-type base region 125 and the second P-type base region 127 and the gate dielectric layer 130 are etched, and then the gate oxide material is epitaxially grown so that the gate dielectric layer 130 can wrap the gate polysilicon layer 131 .

[0096] In some embodiments, the width of the vertical portion of the gate polysilicon layer 131 is 4-8 um.

[0097] In some embodiments, after etching the polysilicon material and the gate dielectric layer 130 on the first P-type base region 125 and the second P-type base region 127 , the polysilicon material may be oxidized to form a gate dielectric layer 130 wrapping the gate polysilicon layer 131 .

[0098] In some embodiments, in combination Figure 8 As shown, after the polysilicon material is deposited, the polysilicon material may be etched so that the width of the vertical portion of the gate polysilicon layer 131 gradually decreases in the direction from the drain layer 133 to the source layer 132 .

[0099] In this embodiment, the vertical portion of the gate polysilicon layer 131 is gradually reduced in the direction from the drain layer 133 to the source layer 132, so that the bottom area of ​​the vertical portion of the gate polysilicon layer 131 begins to gradually widen until the horizontal portion of the gate polysilicon layer 131 reaches the minimum width at the interface position with the horizontal portion of the gate polysilicon layer 131. With such a design, the vertical portion of the gate polysilicon layer 131 is related to the depth of the drift region where it is located, and is matched with the first P-type base region 125 and the second P-type base region 127 on both sides of the vertical portion of the gate polysilicon layer 131, so as to avoid a large sudden change in the electron current density in the electron current high-speed channel, reduce the negative effect of the increase in the electron current density, ensure the stability of the device, and help eliminate the JEFT effect in the device and increase the saturation current of the device.

[0100] In some embodiments, the gate polysilicon layer 131 has a trapezoidal structure.

[0101] In step S700 , a source layer 132 is formed on the first N-type source region 126 , the second N-type source region 128 , the first P-type base region 125 , the second P-type base region 127 and a portion of the gate dielectric layer 130 , and a drain layer 133 is formed on the back side of the N-type substrate 110 .

[0102] In this embodiment, combined with Figure 1 As shown, electrode material is deposited on and on both sides of the gate dielectric layer 130 to form a source layer 132, and the source layer 132 is in contact with the first N-type source region 126, the second N-type source region 128, the first P-type base region 125, the second P-type base region 127, and a portion of the gate dielectric layer 130. An electrode material is deposited on the back side of the N-type substrate 110 to form a drain layer 133.

[0103] An embodiment of the present application also provides a chip, including a T-gate planar super junction MOSFET as described in any of the above embodiments.

[0104] In this embodiment, the chip includes a chip substrate, on which one or more T-type gate planar super junction MOSFETs are arranged. The T-type gate planar super junction MOSFET can be prepared by the preparation method in any of the above embodiments, or the T-type gate planar super junction MOSFET in any of the above embodiments can be arranged on the chip substrate.

[0105] In a specific application embodiment, other related semiconductor devices may also be integrated on the chip substrate to form an integrated circuit with the T-gate planar super junction MOSFET.

[0106] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0107] The beneficial effects of the embodiments of the present application are as follows: a gate dielectric layer is formed on the groove sidewalls, the groove bottom, the first P-type base region, and the second P-type base region of the N-type drift layer, and the gate dielectric layer wraps the gate polysilicon layer, the gate polysilicon layer is a T-shaped structure, and the vertical portion of the gate polysilicon layer extends deep into between the adjacent first P column and the second P column, thereby forming an electron current high-speed channel in the N-type drift layer, greatly improving the electron current density in the JFET region, successfully eliminating the JFET effect, increasing the saturation current of the device, and solving the problem of the JFET effect existing in the traditional planar SJ MOS.

[0108] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0109] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0110] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0111] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0112] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A T-type gate planar super junction MOSFET, characterized in that: include: N-type substrate; A first P column, an N-type drift layer, and a second P column are formed on the front surface of the N-type substrate; wherein the N-type drift layer is located between the first P column and the second P column; A first P-type base region and a second P-type base region, wherein the first P-type base region is formed on the first P-pillar, and the second P-type base region is formed on the second P-pillar; A first N-type source region and a second N-type source region, wherein the first N-type source region is formed in a groove of the first P-type base region, and the second N-type source region is formed in a groove of the second P-type base region; A gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the groove sidewalls and the groove bottom of the N-type drift layer and the first P-type base region and the second P-type base region, and the gate dielectric layer wraps the gate polysilicon layer, the gate polysilicon layer is a T-shaped structure, and the vertical portion of the gate polysilicon layer extends deep into between the adjacent first P column and the second P column; A source layer formed on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region and a portion of the gate dielectric layer; A drain layer is formed on the back side of the N-type substrate; a partial area of ​​the vertical portion of the gate polysilicon layer is located between the first P column and the second P column; the width of the first P-type base region and the second P-type base region gradually increases from the drain layer to the source layer; and the width of the vertical portion of the gate polysilicon layer gradually decreases from the drain layer to the source layer.

2. The T-gate planar superjunction MOSFET according to claim 1, characterized in that: The vertical portion of the gate polysilicon layer is disposed opposite to a portion of the first P column and the second P column.

3. The T-gate planar super junction MOSFET according to claim 2, characterized in that: The length of the partial area where the first P column is arranged opposite to the gate polysilicon layer is 1%-10% of the length of the first P column; and / or, The length of a partial area of ​​the second P column that is arranged opposite to the gate polysilicon layer is 1%-10% of the length of the second P column.

4. The T-gate planar super junction MOSFET according to claim 1, characterized in that: A distance between a vertical portion of the gate polysilicon layer and the first P-type base region and the second P-type base region is greater than one tenth of a width of the N-type drift layer and less than one quarter of a width of the N-type drift layer.

5. The T-gate planar super junction MOSFET according to claim 1, characterized in that: The gate polysilicon layer has a trapezoidal structure.

6. The T-gate planar super junction MOSFET according to claim 1, characterized in that: The first P-type base region and the second P-type base region are symmetrically disposed about a vertical portion of the gate polysilicon layer.

7. A method for preparing a T-type gate planar super junction MOSFET, characterized in that: The preparation method comprises: An N-type drift region is generated by epitaxy on the front side of an N-type substrate; A first P column, an N-type drift layer, and a second P column are formed in a partial area of ​​the N-type drift region by using trenching and epitaxial processes; wherein the N-type drift layer is located between the first P column and the second P column; Continue epitaxially growing an N-type drift region on the first P column, the N-type drift layer, and the second P column, and implant P-type doping ions into a portion of the N-type drift region to form a first P-type base region and a second P-type base region; wherein the first P-type base region is formed on the first P column, and the second P-type base region is formed on the second P column; Implanting N-type doping ions into partial regions on the first P-type base region and the second P-type base region to form a first N-type source region and a second N-type source region, so that the first N-type source region is formed in a groove of the first P-type base region, and the second N-type source region is formed in the groove of the second P-type base region; Etching a groove on the N-type drift layer, and epitaxially growing a gate oxide material to form a gate dielectric layer; wherein the gate dielectric layer is formed on the groove sidewalls and bottom of the N-type drift layer and on the first P-type base region and the second P-type base region; Depositing polysilicon material on the gate dielectric layer to form a gate polysilicon layer, and continuing to epitaxially grow a gate oxide material to form the gate dielectric layer wrapping the gate polysilicon layer; wherein the gate polysilicon layer is a T-shaped structure, and the vertical portion of the gate polysilicon layer extends deep into between the adjacent first P column and the second P column; A source layer is formed on the first N-type source region, the second N-type source region, the first P-type base region, the second P-type base region, and a partial area of ​​the gate dielectric layer, and a drain layer is formed on the back side of the N-type substrate; the width of the first P-type base region and the second P-type base region gradually increases from the drain layer to the source layer; the width of the vertical portion of the gate polysilicon layer gradually decreases from the drain layer to the source layer.

8. A chip, characterized in that: It comprises a T-gate planar super junction MOSFET as described in any one of claims 1 to 6.

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