A method for constructing a ferroelectric transistor simulation model

By constructing a ferroelectric transistor simulation model, using nonlinear functions and logic Sty functions to fit the polarization change rate of the ferroelectric transistor, and adding a truncated Gaussian distribution function to represent the random factor, the problem that the existing technology is difficult to meet the simulation requirements of ferroelectric transistors in the integrated circuit design of existing computing is achieved, and the accurate simulation and stability analysis of ferroelectric transistors are achieved.

CN118798105BActive Publication Date: 2025-04-15GUANGDONG JINGTIE STORAGE TECHNOLOGY CO LTD
View PDF 2 Cites 0 Cited by

Patent Information

Application Number
CN202410777088.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2024-06-17
Publication Date
2025-04-15
Estimated Expiration
2044-06-17

AI Technical Summary

Technical Problem

The prior art is difficult to meet the simulation needs of ferroelectric transistors in the design of integrated circuits of storage and computing, especially in describing physical characteristics such as size scaling effect and switching probability accumulation.

Method used

The simulation model is constructed by calculating the voltage, gate voltage, body voltage, drain voltage and source voltage across the ferroelectric layer in a ferroelectric transistor. The dynamic change rate of the polarization of the ferroelectric transistor is fitted using the logic Stie function and the nonlinear function, and a truncated Gaussian distribution function is added to represent the random factor.

Benefits of technology

It realizes the satisfaction of the simulation requirements of ferroelectric transistors in the integrated memory circuit, can accurately simulate the influence of polarization state, voltage and time, and is suitable for the simulation of continuous writing, erasing and reading FeFET circuits, and demonstrates the stability performance of FeFET in large-scale integrated memory arrays.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN118798105B_ABST
    Figure CN118798105B_ABST
Patent Text Reader

Abstract

The present invention discloses a method for constructing a ferroelectric transistor simulation model, including: calculating a first nonlinear function based on the voltage across a ferroelectric layer in a ferroelectric transistor at a certain moment, the gate voltage of the ferroelectric transistor, the body voltage of the ferroelectric transistor, the drain voltage of the ferroelectric transistor, and the source voltage of the ferroelectric transistor; obtaining each parameter value in a simulation model formula through a logistic function and the first nonlinear function; obtaining the upper limit and lower limit of the polarization of the ferroelectric transistor, and fitting a second nonlinear function based on the voltage of the ferroelectric polarization layer, the upper limit and lower limit of the polarization of the ferroelectric transistor, and deriving a ferroelectric transistor simulation model based on the first nonlinear function, the second nonlinear function, the truncated Gaussian distribution function, and each parameter value in the simulation model formula. The ferroelectric transistor simulation model provided by the present application can meet the simulation requirements of ferroelectric transistors in storage-computation integrated circuit design.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a method for constructing a ferroelectric transistor simulation model. Background Art

[0002] A ferroelectric transistor is a transistor made of special materials with ferroelectric properties. Compared with traditional transistors, the ferroelectric layer in it has the ability to maintain polarization, which can maintain the internal polarization voltage to a certain extent, thereby achieving the function of storage. In the storage-computing integrated circuit based on ferroelectric transistors, we write the polarization state into the ferroelectric layer of the ferroelectric transistor to change its conductivity, thereby storing multi-bit data, or simply storing data "1" and "0" based on whether it can be turned on or off. After writing the data, the ferroelectric transistor can multiply the data expressed in the form of voltage input at the drain, and the ferroelectric transistor has the characteristic of maintaining polarization, so the multiplier can be saved for a long time while performing multiplication calculations. This is its storage-computing integrated circuit design.

[0003] At present, the modeling of ferroelectric transistors still stays at the physical characteristics of randomness of written polarization and multi-domain structure, and focuses on reflecting one or several characteristics in a single simulation result. Although these modelings describe physical characteristics such as size scaling effect and switching probability accumulation in detail, simple circuit applications such as random generators can also be produced through this. However, these models cannot meet the simulation needs of ferroelectric transistors in storage and computing integrated circuit design.

[0004] Therefore, how to provide a ferroelectric transistor simulation model that can meet the simulation requirements of ferroelectric transistors in the design of integrated storage and computing circuits is a technical problem that needs to be solved. Summary of the invention

[0005] The purpose of the present invention is to provide a method for constructing a ferroelectric transistor simulation model to solve the problems existing in the prior art.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions:

[0007] The present invention provides a method for constructing a ferroelectric transistor simulation model, comprising:

[0008] Calculating a first nonlinear function based on a voltage across a ferroelectric layer in the ferroelectric transistor at a certain moment, a gate voltage of the ferroelectric transistor, a body voltage of the ferroelectric transistor, a drain voltage of the ferroelectric transistor, and a source voltage of the ferroelectric transistor;

[0009] Obtaining each parameter value in the simulation model formula through the logistic function and the first nonlinear function;

[0010] Obtaining an upper limit value and a lower limit value of the polarization of the ferroelectric transistor, and fitting a second nonlinear function based on the voltage of the ferroelectric polarization layer and the upper limit value and the lower limit value of the polarization of the ferroelectric transistor, wherein the first nonlinear function and the second nonlinear function are used to represent the dynamic polarization change rate during the polarization change process of the ferroelectric transistor;

[0011] A ferroelectric transistor simulation model is derived based on the first nonlinear function, the second nonlinear function, the truncated Gaussian distribution function and the parameter values ​​in the simulation model formula.

[0012] Optionally, the calculation of the first nonlinear function based on the voltage across the ferroelectric layer in the ferroelectric transistor at a certain moment, the gate voltage of the ferroelectric transistor, the body voltage of the ferroelectric transistor, the drain voltage of the ferroelectric transistor and the source voltage of the ferroelectric transistor is implemented according to the following formulas (1) and (2):

[0013] dV fe (t) = NLF(ΔV(t)) (1)

[0014] ΔV(t)=V G -V B -k(V D +V s ) / twenty two)

[0015] Among them, V fe represents the voltage across the ferroelectric layer, t represents time, ΔV(t) represents the equivalent voltage applied to the four ports of the ferroelectric transistor on the ferroelectric layer, NLF(ΔV(t)) represents the first nonlinear function with ΔV(t) as the independent variable, k represents the influence factor, V G Represents the gate voltage, V B Represents the body voltage, V D Represents the drain voltage, V S represents the source voltage, and d represents the differential sign.

[0016] Optionally, the parameter values ​​in the simulation model formula are obtained by using the logistic function and the first nonlinear function according to the following formula (3):

[0017]

[0018] Among them, V 1 represents the first parameter value, b represents the second parameter value, k 1 represents the third parameter value, k 2 represents the fourth parameter value, L represents the fifth parameter value, V 0 represents the sixth parameter value, and e represents the base of natural logarithm.

[0019] Optionally, fitting the second nonlinear function based on the voltage of the current ferroelectric polarization layer, the upper limit value and the lower limit value of the polarization of the ferroelectric transistor is implemented according to the following formula (4):

[0020]

[0021] Among them, NLPV (V FE ) indicates V FE is the second nonlinear function of the independent variable, V FE represents the voltage of the ferroelectric polarization layer, V -MAX Represents the upper limit of polarization, V mAX represents the lower limit of polarization, and α represents the material deviation coefficient.

[0022] Optionally, the truncated Gaussian distribution function is obtained by the following formula (5):

[0023]

[0024] Wherein, TG(t) represents the truncated Gaussian function, t′ represents the time from polarization change to measurement, φ() represents the probability density function of the standard Gaussian distribution, Φ() represents the cumulative distribution function of the standard Gaussian distribution, and L 1 represents the lower limit of the Gaussian distribution, U represents the upper limit of the Gaussian distribution, μ represents the mean of the Gaussian distribution, and σ represents the standard deviation of the Gaussian distribution.

[0025] Optionally, deriving a ferroelectric transistor simulation model based on the first nonlinear function, the second nonlinear function, the truncated Gaussian distribution function and the parameter values ​​in the simulation model formula is implemented according to the following formula (6):

[0026]

[0027] Among them, V FE represents the voltage of the ferroelectric polarization layer, t 0 represents the starting time of integration, t 1 represents the current time of integration, τ represents the integral variable, NLF(ΔV(τ)) represents the nonlinear function with ΔV(τ) as the independent variable, ΔV(t) represents the equivalent voltage applied to the ferroelectric layer by the voltage on the four ports of the ferroelectric transistor, NLPV(V FE (τ)) represents V FE (τ) is a nonlinear function of the independent variable, V FE (τ) represents the voltage of the ferroelectric polarization layer at the time of the integral variable, TG(τ) represents the truncated Gaussian function, V FE (t 0 ) represents the voltage of the ferroelectric polarization layer at the beginning of integration.

[0028] Optionally, the method further includes:

[0029] Acquire the ferroelectric layer voltage at the current moment based on the ferroelectric transistor simulation model;

[0030] The source-drain output current of the ferroelectric transistor is obtained based on the ferroelectric layer voltage, the gate voltage of the ferroelectric transistor and the source-drain voltage difference at the current moment.

[0031] Optionally, the truncated Gaussian distribution function is used to represent a random factor in a simulation model, and the random factor gradually approaches 0 as time increases.

[0032] Beneficial effects:

[0033] The ferroelectric transistor simulation model of this application fits the laboratory data to the actual performance of the ferroelectric transistor FeFET. It also uses the approximation model to limit the upper and lower limits of the polarization of the ferroelectric transistor FeFET, and fits the nonlinear function to represent the dynamic polarization change rate in different polarization change processes. For the randomness of the actual polarization process, a truncated Gaussian function is added as a random factor. This allows our simulation model to be used for the simulation of continuous writing, erasing, and reading of FeFET circuits, and obtains the stability performance of FeFET in large-scale storage and computing integrated arrays. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings constituting a part of this application are used to provide a further understanding of this application, so that other features, purposes and advantages of this application become more obvious. The schematic embodiment drawings and their descriptions of this application are used to explain this application and do not constitute an improper limitation on this application. In the drawings:

[0035] Figure 1 A schematic diagram of a flow chart of a method for constructing a ferroelectric transistor simulation model provided in an embodiment of the present application;

[0036] Figure 2 A diagram of the operation process of a simulation model provided in an embodiment of the present application;

[0037] Figure 3 A diagram showing the relationship between polarization speed and voltage difference of a ferroelectric transistor fitted by a simulation model provided in an embodiment of the present application;

[0038] Figure 4 A diagram showing the relationship between the maximum polarization change and the polarization voltage fitted by a simulation model provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0040] It should be understood that although the terms first, second, etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another unit. For example, a first unit can be referred to as a second unit, and similarly, a second unit can be referred to as a first unit without departing from the scope of the exemplary embodiments of the present invention.

[0041] It should be understood that the term "and / or" that may appear in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, B exists alone, and A and B exist at the same time. The term " / and" that may appear in this article describes another type of association object relationship, indicating that two relationships may exist. For example, A / and B can represent two situations: A exists alone, and A and B exist alone. In addition, the character " / " that may appear in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0042] Example:

[0043] like Figure 1 FIG. 1 is a flow chart of a method for constructing a ferroelectric transistor simulation model according to an embodiment of the present invention.

[0044] S1, calculating a first nonlinear function based on the voltage across the ferroelectric layer in the ferroelectric transistor, the gate voltage of the ferroelectric transistor, the body voltage of the ferroelectric transistor, the drain voltage of the ferroelectric transistor and the source voltage of the ferroelectric transistor at a certain moment.

[0045] Specifically, it is generally believed that the process of polarization reversal consists of the nucleation of polarized electric domains along the direction of the electric field, the longitudinal extension (parallel to the direction of the electric field) and the lateral growth (perpendicular to the direction of the electric field) of the nucleated electric domains. The nucleation process and the growth process are dominant in different situations. The most widely used kinetic analysis of polarization reversal is the Kolmogorov-Avrami-Ishibashi (KAI) model. The specific model formula is:

[0046]

[0047] Among them, f(t) represents the area ratio of the domain area flipped at time t, f 0 represents the area ratio of the flipped domain, A represents the total area ratio of the rotational domain, t 0 Represents the nucleation time of the rotation domain, and τ represents the relaxation time of the rotation domain. With the increase of the polarization bias, the final stable reversal domain area ratio f0 is allowed to gradually increase, while the total area ratio A of the rotation domain gradually decreases. The nucleation time t0 of the rotation domain does not change with the change of the polarization bias. τ is the relaxation time of the rotation domain, which is determined by the total area of ​​the rotation domain, the speed of domain wall movement and the growth dimension of the rotation domain. This formula describes the relationship between the reversal domain and time, the final stable reversal domain area ratio f0 and the total area ratio A of the rotation domain. The simulation model of the present application is built on this formula as one of the foundations. The KAI model describes the relationship between the stability of the polarization reversal of a domain and time. The longer the time, the closer the reversal state of the domain is to stability. The present application uses a nonlinear function (NLF) to represent the reversal rate, thereby obtaining a model in which the longer the voltage difference action time, the closer the reversal state of the domain is to stability.

[0048] In a preferred embodiment of the present scheme, the first nonlinear function is calculated based on the voltage across the ferroelectric layer in the ferroelectric transistor at a certain moment, the gate voltage of the ferroelectric transistor, the body voltage of the ferroelectric transistor, the drain voltage of the ferroelectric transistor and the source voltage of the ferroelectric transistor according to the following formulas (1) and (2):

[0049] dV fe (t) = NLF(ΔV(t)) (1)

[0050] ΔV(t)=V G -V B -k(V D +V S ) / twenty two)

[0051] Among them, V fe represents the voltage across the ferroelectric layer, t represents time, ΔV(t) represents the equivalent voltage applied to the four ports of the ferroelectric transistor on the ferroelectric layer, NLF(ΔV(t)) represents the first nonlinear function with ΔV(t) as the independent variable, k represents the influence factor, V G Represents the gate voltage, V B Represents the body voltage, V D Represents the drain voltage, V S represents the source voltage, and d represents the differential sign.

[0052] NLF(x) is a nonlinear function fitted by the hysteresis curve of the laboratory ferroelectric transistor, k is the influence factor of the source and drain on the writing of the polarization state of the ferroelectric layer, which is calibrated by laboratory data. k represents the influence of VD and VS on the voltage.

[0053] For the simulation of ferroelectric transistors, the macroscopic characteristics of the transistor are important, and the transconductance and equivalent capacitance of a specific ferroelectric transistor need to be accurately described. Specifically, it is necessary to accurately give the internal polarization state of the ferroelectric transistor and the transconductance at this time when a specific voltage is applied to the four ports (source, gate, drain, and body) of the ferroelectric transistor device within a certain period of time.

[0054] Due to the material characteristics of ferroelectric transistors, the microscopic description is very complex. First of all, there are many random factors that need to be set for modeling, and there is a certain correlation between the random quantities of different factors, which are not independent probability distributions. In addition, the polarization retention properties of ferroelectric materials are also closely related to the process, and it is difficult to make a complete physical model to describe all the properties of ferroelectric materials that have been observed. However, for the application of FeFET in storage and computing integrated circuits, only the macroscopic performance of FeFET needs to be considered, because its macroscopic performance has a certain stability and is gradually improving with the advancement of the process. Therefore, it can be expressed by formulas (1) and (2), which can describe the rate of polarization change.

[0055] S2, obtaining each parameter value in the simulation model formula through the logistic function and the first nonlinear function.

[0056] Specifically, in order to express the polarization retention characteristics of the transistor, when the voltage difference between the two ends of the ferroelectric layer and the internal equivalent electric field is small, the polarization state can hardly be changed. This rule is no longer applicable as the voltage difference gradually increases, so the logistic function is used to fit. After the voltage difference gradually increases, the difference between the polarization writing and the voltage difference remains basically unchanged, so the proportion of this difference to the voltage difference gradually decreases, and it can be approximately fitted with a linear function to obtain the following formula (3), and then the parameter values ​​of the model formula are obtained by fitting the laboratory data.

[0057]

[0058] Among them, V 1 represents the first parameter value, b represents the second parameter value, k 1 represents the third parameter value, k 2 represents the fourth parameter value, L represents the fifth parameter value, V 0 represents the sixth parameter value, e represents the base of the natural logarithm, and other is not within the range of (-V1, V1). Each parameter value needs to be calculated by fitting the data measured in the laboratory. The specific parameter value can be obtained by fitting the data curve actually measured in the laboratory using this formula (3).

[0059] S3, obtaining an upper limit value and a lower limit value of polarization of the ferroelectric transistor, and fitting a second nonlinear function based on the voltage of the ferroelectric polarization layer, the upper limit value and the lower limit value of polarization of the ferroelectric transistor.

[0060] Specifically, the upper limit of polarization is obtained through laboratory data. Even if the voltage difference between the external environment and the ferroelectric layer is still large near the upper limit, writing is almost impossible. Therefore, a function with the current voltage of the ferroelectric layer as the independent variable can be used to fit. Formula (4), formula (1) and (2) determine that the polarization rate depends not only on the NLF function with the variable △V(t), but also on the NLPV function with the variable VFE. The two functions jointly determine the polarization rate.

[0061] The second nonlinear function is fitted based on the voltage of the current ferroelectric polarization layer, the upper limit value and the lower limit value of the polarization of the ferroelectric transistor according to the following formula (4):

[0062]

[0063] Among them, NLPV (V FE ) indicates V FE is the second nonlinear function of the independent variable, V FE represents the voltage of the ferroelectric polarization layer, V -MAX Represents the upper limit of polarization, V MAX It represents the lower limit of polarization, α represents the material deviation coefficient, and α is a material deviation coefficient obtained through actual laboratory measurements of different ferroelectric transistors, which affects its performance to external voltage at different polarization strength positions.

[0064] In the preferred embodiment of this scheme, for single write or erase, the writing of the polarization state of the ferroelectric layer has a certain randomness, which is determined by the properties of the ferroelectric material itself. Specifically, the polarization switching of each ferroelectric domain has a certain randomness, and the process of polarization reversal is composed of the nucleation of the electric domain along the direction of the electric field, the longitudinal extension (parallel to the electric field direction) and the lateral growth (perpendicular to the electric field direction) of the nucleated electric domain. The nucleation of the electric domain requires a large activation energy and the direction has randomness, and the longitudinal extension and lateral growth also have the randomness of position and length. At the same time, ferroelectric materials have a size scaling effect, and the size reduction leads to a reduction in the number of ferroelectric domains, which further leads to greater overall randomness. Therefore, for actual single write and erase, a random factor should be added, and its standard deviation is related to the process and external conditions. Therefore, the truncated Gaussian distribution function is selected to represent the random factor, and the random factor gradually tends to 0 as time increases.

[0065] The truncated Gaussian distribution function is obtained by the following formula (5):

[0066]

[0067] Wherein, TG(t) represents the truncated Gaussian function, t′ represents the time from polarization change to measurement, that is, the time difference between the voltage measurement moment and the polarization completion moment, φ() represents the probability density function of the standard Gaussian distribution, Φ() represents the cumulative distribution function of the standard Gaussian distribution, L 1 represents the lower limit of the Gaussian distribution, U represents the upper limit of the Gaussian distribution, μ represents the mean of the Gaussian distribution, and σ represents the standard deviation of the Gaussian distribution.

[0068] Where φ(x) is the probability density function of the standard Gaussian distribution, Φ(x) is the cumulative distribution function of the standard Gaussian distribution, and the above formula represents the distribution in (L 1 ,U), the truncated Gaussian distribution function between can be used to simulate the randomness of different materials by adjusting μ and σ. Therefore, the model has a certain adaptability, which makes it possible to effectively give circuit simulation results by simply adjusting parameters as the process advances.

[0069] S4, deriving a ferroelectric transistor simulation model based on the first nonlinear function, the second nonlinear function, the truncated Gaussian distribution function and the parameter values ​​in the simulation model formula.

[0070] Specifically, according to the function described above, the voltage of the ferroelectric layer at any time can be calculated by integration, and then according to the voltage of each pole of the transistor, the formula can be calculated to be consistent with the average curve of multiple writes and erases measured in the laboratory, that is, the ferroelectric transistor simulation model.

[0071] The ferroelectric transistor simulation model is derived based on the first nonlinear function, the second nonlinear function, the truncated Gaussian distribution function and the parameter values ​​in the simulation model formula, which is implemented according to the following formula (6):

[0072]

[0073] Among them, V FE represents the voltage of the ferroelectric polarization layer, t 0 represents the starting time of integration, t 1 represents the current time of integration, τ represents the integral variable, NLF(ΔV(τ)) represents the nonlinear function with ΔV(τ) as the independent variable, ΔV(t) represents the equivalent voltage applied to the ferroelectric layer by the voltage on the four ports of the ferroelectric transistor, NLPV(V FE (τ)) represents V FE (τ) is a nonlinear function of the independent variable, V FE (τ) represents the voltage of the ferroelectric polarization layer at the time of the integral variable, TG(τ) represents the truncated Gaussian function, VFE (t 0 ) represents the voltage of the ferroelectric polarization layer at the beginning of integration.

[0074] This application can achieve:

[0075] (1) Accurate polarization state simulation: The simulation model can clearly set the upper and lower limits of polarization and fit the upper and lower limits with approximation functions, ensuring the accuracy of the simulation results, which reflects the physical behavior of ferroelectric transistors in actual operation.

[0076] (2) Accurate fitting of voltage and time effects: The simulation model can accurately simulate the voltage changes of the four ports (gate, source, drain, and body) and the influence of voltage application time on the polarization of the internal ferroelectric layer, which is crucial to understanding the performance of ferroelectric transistors under real working conditions.

[0077] (3) Suitable for simulation of integrated storage and computing circuits: This simulation model is particularly suitable for the simulation and design of integrated storage and computing circuits based on ferroelectric transistors, which provides a powerful tool for the application of ferroelectric transistors in new computing architectures.

[0078] (4) Accuracy of crosstalk analysis: The simulation model can accurately obtain the polarization voltage inside a specific ferroelectric transistor device under the influence of different times, external voltages, and initial states from a macroscopic perspective, thereby accurately analyzing the write crosstalk and read crosstalk problems in the array. This problem is a major difficulty in the storage and computing integrated circuit based on ferroelectric transistors, which is of great significance for improving the design quality of transistor arrays and optimizing circuit performance.

[0079] As an embodiment of the present application, the operation process of the model is as follows Figure 2 As shown:

[0080] Process: Start simulation (left 1), and set the initial polarization voltage of a ferroelectric polarization layer to 0.5V (right 1). Calculate VDS through the voltage of the device port (left 2), and update V FE (Left 3), the right box shows the specific operation of updating VFE. Take the current time t=t0, calculate the value of NFF function (right 2), calculate the value of NLPV function (right 3), add random factor, multiply the above two values ​​and then multiply them by random function TG (right 4), calculate V FE (Right 5), return to V FE Take the value, and take the calculation time t as t0, re-enter the next calculation cycle, and restart the calculation from right 2. After the model obtains the VFE value, the output current IDS (left 4) can be obtained according to VDS.

[0081] The relationship between the polarization speed and voltage difference of the ferroelectric transistor fitted by the model is as follows: Figure 3The punctuation points are measured data, and the curves are the results of model fitting. The process of fitting the model with the data actually measured in the laboratory is Figure 3 The correctness of the model was verified, and the specific parameter values ​​of the model (k1, k2, L and other parameters in the above formula) were obtained. The relationship between the maximum polarization change and the polarization voltage fitted by the model is shown in the figure. Figure 4 , and the punctuation marks are measured data. The correctness of the model can also be verified, and the data of the actual device is consistent with the results of the model.

[0082] This application has: 1. Innovative model formula: The change in polarization is represented by three internal functions, which respectively include the influence of the four-port voltage difference and time, the influence of the internal polarization state, and the influence of random factors. 2. Innovative treatment of the polarization saturation state: The model's approach function treatment of the polarization saturation state (implemented by the NLPV function) ensures the authenticity of the simulation results for the device. 3. Special optimization of storage-computing integrated circuits: The model is specially optimized for storage-computing integrated circuits, and the macroscopic performance is fitted in detail, which provides special support for the application of ferroelectric transistors in new computing architectures.

[0083] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods of each embodiment or some parts of the embodiment.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

[0085] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for constructing a ferroelectric transistor simulation model, characterized in that: include: Calculating a first nonlinear function based on a voltage across a ferroelectric layer in the ferroelectric transistor at a certain moment, a gate voltage of the ferroelectric transistor, a body voltage of the ferroelectric transistor, a drain voltage of the ferroelectric transistor, and a source voltage of the ferroelectric transistor; Obtaining each parameter value in the simulation model formula through the logistic function and the first nonlinear function; Obtaining an upper limit value and a lower limit value of the polarization of the ferroelectric transistor, and fitting a second nonlinear function based on the voltage of the ferroelectric polarization layer and the upper limit value and the lower limit value of the polarization of the ferroelectric transistor, wherein the first nonlinear function and the second nonlinear function are used to represent the dynamic polarization change rate during the polarization change process of the ferroelectric transistor; derive a ferroelectric transistor simulation model based on the first nonlinear function, the second nonlinear function, the truncated Gaussian distribution function and the parameter values ​​in the simulation model formula; The ferroelectric transistor simulation model is derived based on the first nonlinear function, the second nonlinear function, the truncated Gaussian distribution function and the parameter values ​​in the simulation model formula, which is implemented according to the following formula (6): Among them, V FE represents the voltage of the ferroelectric polarization layer, t0 represents the starting time of integration, t1 represents the current time of integration, τ represents the integral variable, NLF(ΔV(τ)) represents the nonlinear function with ΔV(τ) as the independent variable, ΔV(t) represents the equivalent voltage of the voltage applied to the four ports of the ferroelectric transistor on the ferroelectric layer, NLPV(V FE (τ)) represents V FE (τ) is a nonlinear function of the independent variable, V FE (τ) represents the voltage of the ferroelectric polarization layer at the time of the integral variable, TG(τ) represents the truncated Gaussian function, V FE (t0) represents the voltage of the ferroelectric polarization layer at the beginning of integration.

2. The method according to claim 1, characterized in that The calculation of the first nonlinear function based on the voltage across the ferroelectric layer in the ferroelectric transistor at a certain moment, the gate voltage of the ferroelectric transistor, the body voltage of the ferroelectric transistor, the drain voltage of the ferroelectric transistor and the source voltage of the ferroelectric transistor is implemented according to the following formulas (1) and (2): dV fe (t)=NLF(ΔV(t)) (1) ΔV(t)=V G -V B -k(V D +V S ) / 2 (2) Among them, V fe represents the voltage across the ferroelectric layer, t represents time, ΔV(t) represents the equivalent voltage applied to the four ports of the ferroelectric transistor on the ferroelectric layer, NLF(ΔV(t)) represents the first nonlinear function with ΔV(t) as the independent variable, k represents the influence factor, V G Represents the gate voltage, V B Represents the body voltage, V D Represents the drain voltage, V S represents the source voltage, and d represents the differential sign.

3. The method according to claim 2, characterized in that The parameter values ​​in the simulation model formula are obtained by the logistic function and the first nonlinear function according to the following formula (3): Among them, V1 represents the first parameter value, b represents the second parameter value, k1 represents the third parameter value, k2 represents the fourth parameter value, L represents the fifth parameter value, V0 represents the sixth parameter value, and e represents the base of the natural logarithm.

4. The method according to claim 3, characterized in that The second nonlinear function is fitted based on the voltage of the current ferroelectric polarization layer, the upper limit value and the lower limit value of the polarization of the ferroelectric transistor according to the following formula (4): Among them, NLPV (V FE ) indicates V FE is the second nonlinear function of the independent variable, V FE represents the voltage of the ferroelectric polarization layer, V -MAX Represents the upper limit of polarization, V MAX represents the lower limit of polarization, and α represents the material deviation coefficient.

5. The method according to claim 1, characterized in that The truncated Gaussian distribution function is obtained by the following formula (5): Wherein, TG(t') represents a truncated Gaussian function, t' represents the time from polarization change to measurement, φ() represents the probability density function of a standard Gaussian distribution, Φ() represents the cumulative distribution function of a standard Gaussian distribution, L1 represents the lower limit value of the Gaussian distribution, U represents the upper limit value of the Gaussian distribution, μ represents the mean value of the Gaussian distribution, and σ represents the standard deviation of the Gaussian distribution.

6. The method according to claim 1, characterized in that The method further comprises: Acquire the ferroelectric layer voltage at the current moment based on the ferroelectric transistor simulation model; The source-drain output current of the ferroelectric transistor is obtained based on the ferroelectric layer voltage, the gate voltage of the ferroelectric transistor and the source-drain voltage difference at the current moment.

7. The method according to claim 5, characterized in that The truncated Gaussian distribution function is used to represent the random factor in the simulation model. As time increases, the random factor gradually approaches 0.

Citation Information

Patent Citations

  • Transistor model capable of describing high temperature and low temperature mismatching characteristics and simulation method

    CN103838905A

  • Circuit simulation model of ferroelectric negative capacitance transistor and modeling method

    CN116205192A