Integrated circuit expansion method, device, equipment and storage medium

Abstract

The present application discloses an integrated circuit expansion method, device, equipment and storage medium, which relates to the field of communication technology and is applied to an ASIC chip that integrates multiple virtual ports and has multiple built-in PCIe Endpoints. The configuration space of the virtual port and the PCIe Endpoint is located in the ECAM of the ASIC chip. The PCIe Endpoint is connected to the virtual port to communicate with the uplink port; including: obtaining a Config configuration transaction request through the uplink port to access the configuration space in the ECAM, and returning a response message to the Config configuration transaction request to the uplink port; the PCIe Endpoint simulates the physical layer link building behavior so that the PCIe enumeration software recognizes it as an Endpoint device to achieve data transmission. In this way, the latency performance is better, it can be compatible with the PCIe protocol, and the reliability and efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an integrated circuit expansion method, device, equipment and storage medium. Background Art

[0002] The traditional external PCIe Endpoint is the final device on the PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus) bus, usually various devices inside the computer, such as graphics cards, network cards, sound cards, etc. Endpoint is responsible for receiving and sending data, and transferring data to other devices or host memory. Endpoint can flexibly connect PCIe devices with different functions. Endpoint can flexibly connect PCIe devices with different functions, but the hardware cost is high, and there are problems such as latency performance and protocol compatibility.

[0003] It can be seen that how to optimize the reliability and efficiency of Endpoint transaction processing is a problem to be solved in this field. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide an integrated circuit expansion method, device, equipment and storage medium, which has better latency performance of built-in PCIe Endpoint, is easy to expand, is compatible with PCIe standard protocol, and can improve the reliability and efficiency of processing transactions. The specific scheme is as follows:

[0005] In a first aspect, the present application provides an integrated circuit expansion method, which is applied to an ASIC chip that integrates multiple virtual ports and has multiple PCIe Endpoints built in, wherein the configuration spaces of the virtual ports and the PCIe Endpoints are both located in the ECAM of the ASIC chip, and each of the PCIe Endpoints communicates with an upstream port by connecting to a corresponding virtual port; wherein the method comprises:

[0006] Obtaining a Config configuration transaction request for the ECAM through the uplink port, so as to access the configuration space of the virtual port and / or the PCIe Endpoint in the ECAM through the Config configuration transaction request, and returning a response message for the Config configuration transaction request to the uplink port, thereby completing the expansion operation of the configuration space;

[0007] The PCIe Endpoint simulates the physical layer link establishment behavior so that the PCIe enumeration software recognizes the PCIe Endpoint as an Endpoint device, completing the expansion process of the integrated circuit to achieve data transmission based on the PCIe protocol.

[0008] Optionally, obtaining a Config configuration transaction request for the ECAM through the uplink port, accessing the configuration space of the virtual port and / or the PCIe Endpoint in the ECAM through the Config configuration transaction request, and returning a response message to the Config configuration transaction request to the uplink port to complete the configuration space expansion operation, includes:

[0009] Acquire a Config configuration transaction request for the ECAM through the uplink port, and convert the Config configuration transaction request into a local request through a first preset conversion interface;

[0010] Accessing the configuration space of the corresponding virtual port and / or PCIe Endpoint in the ECAM using the local request to generate a corresponding local response message;

[0011] The local reply message is converted into a response message for the Config configuration transaction request through a second preset conversion interface, and the response message is returned to the uplink port to complete the expansion operation of the configuration space.

[0012] Optionally, the registers in the configuration space of the ECAM are connected to the Wishbone bus by means of wiring, so that when data is transmitted through the Wishbone bus, information comparison operations are performed based on the registers, and corresponding data forwarding operations are performed according to the information comparison results; the Wishbone bus includes a master line and a slave line.

[0013] Optionally, the data transmission based on the PCIe protocol includes:

[0014] Acquire the data to be sent for the Wishbone bus through the uplink port, and convert the data to be sent into a Wishbone format through a third preset interface to obtain converted sent data, so as to transmit the converted sent data to the Wishbone bus to complete the corresponding data transmission operation;

[0015] The data to be sent includes response data for responding to a bus request of the Wishbone bus and request data for initiating a request to the Wishbone bus.

[0016] Optionally, performing an information comparison operation based on the register when transmitting data through the Wishbone bus, and performing a corresponding data forwarding operation according to the information comparison result, includes:

[0017] If the data to be sent is response data sent by the upstream port to respond to a bus request of the Wishbone bus, an information comparison operation is performed on the bus number corresponding to the data to be sent and the bus number of the register corresponding to the virtual port, so as to determine the target virtual port corresponding to the data to be sent and the corresponding target Wishbone bus port according to the corresponding information comparison result;

[0018] If the data to be sent is request data initiated by the upstream port to the Wishbone bus, an information comparison operation is performed on the address corresponding to the data to be sent and the address range of the register corresponding to the PCIe Endpoint, so as to determine the target PCIe Endpoint corresponding to the data to be sent and the corresponding target Wishbone bus port according to the corresponding information comparison result;

[0019] The data to be sent is forwarded to the corresponding target Wishbone bus port to complete the corresponding data forwarding operation.

[0020] Optionally, the data transmission based on the PCIe protocol includes:

[0021] Acquire the data to be uploaded for the upstream port through the Wishbone bus, and convert the data to be uploaded into a PCIe message format through a fourth preset interface to obtain converted uploaded data, so as to transmit the converted uploaded data to the upstream port to complete the corresponding data transmission operation;

[0022] The data to be uploaded includes response data for responding to request data initiated by the upstream port and a bus request for initiating a request to the upstream port.

[0023] Optionally, the data transmission based on the PCIe protocol includes:

[0024] The address conversion is performed on the data stream of the data transmission process through the internal address conversion unit to achieve address isolation between the address domain corresponding to the uplink port and the address domain corresponding to the PCIe Endpoint.

[0025] In a second aspect, the present application provides an integrated circuit expansion device, which is applied to an ASIC chip that integrates multiple virtual ports and has multiple PCIe Endpoints built in, wherein the configuration space of the virtual port and the PCIe Endpoint are both located in the ECAM of the ASIC chip, and each of the PCIe Endpoints communicates with the upstream port by connecting to the corresponding virtual port; wherein the device comprises:

[0026] A first expansion module is used to obtain a Config configuration transaction request for the ECAM through the uplink port, so as to access the configuration space of the virtual port and / or the PCIeEndpoint in the ECAM through the Config configuration transaction request, and return a response message to the Config configuration transaction request to the uplink port to complete the expansion operation of the configuration space;

[0027] The second expansion module is used to simulate the physical layer link establishment behavior through the PCIe Endpoint so that the PCIe enumeration software recognizes the PCIe Endpoint as an Endpoint device, completes the expansion process of the integrated circuit, and realizes data transmission based on the PCIe protocol.

[0028] In a third aspect, the present application provides an electronic device, including:

[0029] Memory, used to store computer programs;

[0030] A processor is used to execute the computer program to implement the integrated circuit expansion method as described above.

[0031] In a fourth aspect, the present application provides a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the integrated circuit expansion method as described above.

[0032] It can be seen that the present application is applied to an ASIC chip that integrates multiple virtual ports and has multiple PCIe Endpoints built in. The configuration spaces of the virtual ports and the PCIe Endpoints are both located in the ECAM of the ASIC chip, and each of the PCIe Endpoints communicates with the upstream port by hanging the corresponding virtual port; wherein the method includes: obtaining a Config configuration transaction request for the ECAM through the upstream port, so as to access the configuration space of the virtual port and / or the PCIe Endpoint in the ECAM through the Config configuration transaction request, and returning a response message to the Config configuration transaction request to the upstream port to complete the expansion operation of the configuration space; and, by simulating the physical layer link establishment behavior through the PCIe Endpoint, the PCIe enumeration software identifies the PCIe Endpoint as an Endpoint device, thereby completing the expansion process of the integrated circuit, so as to realize data transmission based on the PCIe protocol. In this way, the application can access the configuration space of the customized ECAM through the configuration request of the upstream port and realize the sending and receiving of PCIe configuration transactions and completed transactions; the PCIe Endpoint is inside the chip, and can connect to the upstream port to send and receive data by hanging a virtual port; and the built-in PCIe Endpoint can be enumerated by the standard PCIe enumeration software by simulating the physical layer link building behavior, and can process and route various transaction layer data packets. This reduces the hardware cost, and the built-in PCIe Endpoint has better latency performance, is easy to expand, is compatible with the PCIe standard protocol, and can improve the reliability and efficiency of transaction processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0034] Figure 1 A flow chart of an integrated circuit expansion method disclosed in this application;

[0035] Figure 2 A schematic diagram of a configuration space disclosed in this application;

[0036] Figure 3 A flowchart of a Config configuration transaction process disclosed in this application;

[0037] Figure 4 A specific data transmission flow chart disclosed in this application;

[0038] Figure 5 Another specific data transmission flow chart disclosed in this application;

[0039] Figure 6 A schematic diagram of an address domain disclosed in this application;

[0040] Figure 7 A schematic diagram of an address processing bus architecture disclosed in this application;

[0041] Figure 8 A specific address schematic diagram disclosed in this application;

[0042] Fig. 9 This is a schematic diagram of the structure of an integrated circuit expansion device disclosed in this application;

[0043] Fig.10 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0044] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0045] See also Figure 1 As shown, an embodiment of the present invention discloses an integrated circuit expansion method, which is applied to an ASIC (Application Specific Integrated Circuit) chip that integrates multiple virtual ports and has multiple PCIe Endpoints built in. The configuration space of the virtual port and the PCIe Endpoint are both located in the ECAM (Enhanced Configuration Access Mechanism, which is used herein to refer to the configuration space using the mechanism) of the ASIC chip. Each of the PCIe Endpoints communicates with the upstream port by connecting to the corresponding virtual port. The method includes:

[0046] Step S11: obtaining a Config configuration transaction request for the ECAM through the uplink port, so as to access the configuration space of the virtual port and / or the PCIe Endpoint in the ECAM through the Config configuration transaction request, and returning a response message to the Config configuration transaction request to the uplink port, thereby completing the expansion operation of the configuration space.

[0047] In this embodiment, the configuration space of each iDP (integration Downstream Port, denoted as a virtual port in the embodiment) or iEP (integration Endpoint) occupies 4KB of address resources. i-ECAM (integration Enhanced Configuration Access Mechanism) corresponds to the enhanced access mechanism of the configuration space in the PCIe standard protocol. Figure 2As shown in the figure, the configuration space is arranged in sequence from iDP0, iEP0, iDP1, iEP1…iDPn, iEPn, and the access address increases in sequence. The address range of the configuration space register of each iEP or iDP is 12'h000~12'hfff. The ECAM space of the iDP or iEP contains configuration registers that meet the requirements of the PCIe standard protocol, where iDP is a Type 1 configuration space and iEP is a Type 0 configuration space. The registers of the i-ECAM configuration space can act on the module that routes the TLP (Transaction Layer Packet) in the system to the iEP through wires, thereby realizing the control of the system-related functions by the i-ECAM registers. For example, the system's TLP address routing and ID (Identification) routing involve the (Prefetchable) Memory Base / Limit Register (prefetchable or non-prefetchable memory base address register, prefetchable or non-prefetchable memory address limit register) and Primary / Secondary / Subordinary BusNumber Register (primary, secondary and sub-level bus number registers) in the iDP configuration space respectively. In a specific embodiment, the registers in the configuration space in the ECAM are connected to the Wishbone (Y-shaped) bus by pulling wires, so that when data is transmitted through the Wishbone bus, information comparison operations are performed based on the registers, and corresponding data forwarding operations are performed according to the information comparison results; the Wishbone bus includes a master line and a slave line. Specifically, these registers can act on the routing module in the system in the form of pulling wires to realize the routing and forwarding of TLP.

[0048] In a specific embodiment, the Config configuration transaction request for the ECAM is obtained through the uplink port, so as to access the configuration space of the virtual port and / or the PCIe Endpoint in the ECAM through the Config configuration transaction request, and a response message for the Config configuration transaction request is returned to the uplink port to complete the configuration space expansion operation, including: obtaining the Config configuration transaction request for the ECAM through the uplink port, and converting the Config configuration transaction request into a local request (a request that matches the local chip custom interface) through a first preset conversion interface; using the local request to access the configuration space of the corresponding virtual port and / or PCIe Endpoint in the ECAM to generate a corresponding local response message; converting the local response message into a response message for the Config configuration transaction request through a second preset conversion interface, and returning the response message to the uplink port to complete the configuration space expansion operation. Specifically, as Figure 3 As shown in the figure, the Config configuration transaction accessing i-ECAM is first converted into a simple local request for register access to the local interface, where CFG is the abbreviation of Config, representing the configuration transaction. i-ECAM routes and distributes local requests based on the system device number and the bus number mounted on the iDP, obtains the data returned by the local, converts it into a Completion (completion transaction), that is, a local response message, and then forwards it to the USP (UpStream Port) to enable the system to send a configuration request to access the i-ECAM.

[0049] Furthermore, the loacl interface contains the address address[31:0] (32-bit address), data data[31:0] (21-bit data), read / write indication write_enable (write enable), and enable signal enable; when write_enable is valid, it indicates a write operation, and data[31:0] is the write operation data, otherwise it indicates a read operation and read data; the address, data, and read / write indication are valid only when the enable signal is valid. When Config converts the local interface, it first identifies the Format field of the Config message to identify whether it is a configuration read or configuration write, thereby determining whether the state of the local interface write_enable is 0 or 1. The Bus Number, Device Number, and Function Number fields (BDF, the identification number of each device) of the Config message are converted to address[27:12] of the local interface; the External Register Number+Register Number of the Config message is converted to address[11:2], and address[1:0] is fixed to 2'b00, corresponding to the configuration space register offset of each iDP or iEP (in DW, Double Word); the local interface address[31:28] is a reserved field. Secondly, identify the Type field of the Config message to determine whether it is a Type1 or Type0 configuration transaction. If it is a Type0 configuration transaction, the Device Number in address[27:12] is used to determine which iDP's configuration space is accessed. The correspondence between the Device Number and the iDP is pre-set by the system. For example, the Device Number can be set to 0, 1, 2...31, which correspond to the configuration space of iDP0, iDP1, iDP2...iDP31 respectively. If it is a Type 1 configuration transaction, the BusNumber in address[27:12] is compared with the Second Bus Number of each iDP. If it is equal to the Second Bus Number of a certain iDP, it means that the configuration transaction is to access the configuration space of the iEP corresponding to the iDP. If the above two scenarios are met, the configuration transaction request needs to be converted into a local request. After the loacl request passes through the routing module inside the i-ECAM, it accesses the configuration space of the corresponding iDP or iEP.In all other cases, the configuration transaction request is discarded, and the local-to-cpl module is notified to generate a Completion message of the Unsupported Request type and return it to the system.

[0050] Correspondingly, in the Completion message returned by i-ECAM, the Payload data is returned by i-ECAM through the local interface Data[31:0], the Completer id is equal to the BDF in the Config request, and the Requester id, Tag (message tag number, used to associate request and completion messages) and other fields are equal to the Requester id, Tag and other fields of the Config request.

[0051] Step S12: The PCIe Endpoint simulates the physical layer link establishment behavior so that the PCIe enumeration software identifies the PCIe Endpoint as an Endpoint device, thereby completing the expansion process of the integrated circuit to achieve data transmission based on the PCIe protocol.

[0052] It should be pointed out that the PCIe basic protocol clearly stipulates that Endpoint type devices cannot be directly connected to the Second Bus Number of USP. In this application, iEP is connected to virtual iDP to achieve logical connection of iDP under USP, and then iEP is connected under iDP to achieve communication between iEP and USP. It should be noted that for system software, iEP is not an RCiEP (root complex integrated endpoint) device type defined in the PCIe4.0, 5.0 or 6.0 protocol, but a standard Endpoint device type. In terms of device initialization, iEP is no different from a standard Endpoint device and fully complies with the PCIe protocol. Furthermore, in the present application, iEP can simulate the link establishment behavior of the physical layer; specifically, after resetting and unresetting to make all internal modules ready, the status flag of the successful link establishment of iDP and iEP configuration space is set, so that the system software can read the successful link establishment status. This step only simulates the behavior of the standard Endpoint device from unresetting to the successful physical layer link establishment. The actual link establishment process of iEP and iDP does not involve the negotiation and handshake actions of the physical layer high-speed serial interface, thus saving the physical layer link establishment time, that is, the theoretical value of the physical layer link establishment time of iEP and iDP is zero, so that the physical layer link establishment time of iEP is less than the 100 millisecond link establishment timeout specified by the PCIe basic protocol, and meets the condition that the normal physical layer link establishment must be completed normally within 100 milliseconds as constrained by the PCI basic protocol. Accordingly, iEP can be identified as an Endpoint device by the standard PCIe enumeration software. Specifically, due to the existence of i-ECAM, as long as the necessary functions and optional functions are implemented in the configuration space registers of each iDP or iEP device of i-ECAM, during the PCIe device enumeration phase of the system, the behavior of iEP will fully comply with the provisions of the PCIe protocol and can be enumerated by the standard PCIe device enumeration software. For device management, it is only necessary to implement the registers of the relevant management functions of i-ECAM and the registers to control the iEP system functions. For example, for power management, the iEP power management register can be set to different power consumption states such as D0 / D1 / D2, and the actual power state of the iEP working module can be customized to be off or on. This method can be used to simulate the device management related functions specified by the PCIe protocol.

[0053] In a specific embodiment, the data transmission based on the PCIe protocol may include: obtaining the data to be sent for the Wishbone bus through the upstream port, and converting the data to be sent into the Wishbone format through the third preset interface to obtain the converted data to be sent, so as to transmit the converted data to the Wishbone bus to complete the corresponding data transmission operation; wherein the data to be sent includes response data for responding to the bus request of the Wishbone bus and request data for initiating a request to the Wishbone bus. Specifically, for the request initiated by the Wishbone bus, the upstream port will return the corresponding Completion data, that is, the data to be sent; wherein the request initiated by the Wishbone bus includes the request issued by the Wishbone Slave (slave line), and the Wishbone request initiated by the upstream port to the Wishbone Master (master line) of the Wishbone bus.

[0054] like Figure 4In the data transmission process shown, the TLP to WB (Wishbone, Y-shaped bus) and CPL (Completion, completion of the transaction) to WB modules convert the data to be sent into the Wishbone format and transmit the converted data to the Wishbone bus. For the Wishbone request issued by the Wishbone Master. By identifying the Format field of the TLP message header, it is identified whether the TLP message is a read operation type or a write operation type. The TLP address is converted to the Wishbone address. Because the address domain of the PCIe TLP is DW-aligned, and the Wishbone address can be any value, it is necessary to combine the Length (length), First be (first double word byte enable), and Last be (last double word byte enable) in the TLP to judge the lower 2 bits of the converted Wishbone address, and determine the value of the lower 2 bits of the address to be 2'b00 or 2'b01 or 2'b10 or 2'b11 according to the situation. The Length, First be, and Last be in TLP are converted to the SEL_O (output selection) field of Wishbone. Note that the Length of PCIeTLP is in units of DW. For TLP with Payload, the Payload carried by TLP needs to be placed on the data signal of Wishbone, and the impact of the address, Length, First be, and Last be of PCIe TLP on data alignment and shifting needs to be considered. The Attr (feature), Poison (characterization of poison), TH (transaction hint), Relax Order (weak order preservation) and other fields in TLP can be placed in the user-defined signal TAGN_O (user-defined signal output) of the Wishbone bus to indicate the operation attribute information carried by TLP. In the TLP to WB and CPL to WB modules, the Posted (transaction request with postmark, which does not require a reply to complete the message) packets that exceed the amount of data that Wishbone can send at one time need to be disassembled into multiple packets and then sent to the Wishbone bus separately. The condition for splitting is that, based on the comprehensive judgment of the Address, Length, First be and Last be of TLP, when the TLP cannot be forwarded by Wishbone in one shot, the TLP needs to be split into two or more smaller packets so that each packet can be transmitted by Wishbone in one shot. After the data packet is split, except for the address and Length, the other fields such as Attr, Poison, TH, Relax Order mapped in the TAGN_O signal remain the same as the original packet, and the packets are sent in the order of increasing addresses.

[0055] It should be pointed out that for Non-Posted (transaction requests without postmarks that require a reply to a completion message) requests, because the PCIe basic protocol specifies that the Max Read Request Size is 4KB at most, and the Wishbone bus can carry a maximum of 64Bytes of data in one beat. Therefore, when a PCIe Non-Posted request is converted to a Wishbone bus read request, for Non-Posted requests whose expected returned Completion carries data that exceeds the bit width of the Wishbone data signal, the request needs to be split into two or more requests before being forwarded to the Wishbone bus. In addition, for Memory requests whose address and length combination cross the 4KB address boundary, they are directly discarded according to the PCIe protocol rules and a CPL of the Unsupported Request type is returned.

[0056] Furthermore, for each Non-Posted request sent by the Wishbone Slave port, the upstream port may return multiple corresponding Completion messages, so the CPL to WB module is required to collect and accumulate the length of the Completion messages with the same Requester ID and the same Tag. When the accumulated Completion Length (i.e., the Payload length carried by the Completion) is equal to or greater than the length of the Non-Posted request, it means that all the Completions are returned, and these Completion data need to be merged, disassembled into data adapted to the Wishbone bus, and sent to the Wishbone bus.

[0057] In another specific embodiment, the data transmission based on the PCIe protocol may include: obtaining the data to be uploaded for the upstream port through the Wishbone bus, and converting the data to be uploaded into a PCIe message format through a fourth preset interface to obtain the converted uploaded data, so as to transmit the converted uploaded data to the upstream port to complete the corresponding data transmission operation; wherein the data to be uploaded includes response data for responding to the request data initiated by the upstream port and a bus request for initiating a request to the upstream port. Specifically, the request issued by the Wishbone bus includes the request issued by the Wishbone Slave port, and the response data returned by the Wishbone Master port of the Wishbone bus in response to the request data of the upstream port.

[0058] like Figure 4In the data transmission process shown, the Format, Type, Attr, Poison, TH, RelaxOrder and other fields in TLP are mapped to the Wishbone bus user-defined signal TAGN_O to indicate the type and operation attribute information of TLP. When Wishbone TAGN_O is identified, it indicates that it is a TLP of Message type with Memory, IO or address routing. The Wishbone address is converted to the TLP address. Because the Wishbone address may be any value, and the address field of PCIe TLP is DW-aligned, the lower 2 bits of the TLP address are always 0 after the conversion. The lower 2 bits of the Wishbone address correspond to First be and Last be according to the PCIe protocol requirements. The SEL_O field and address of Wishbone are converted into the Length in TLP. Note that the Length of PCIe TLP is in DW (double word) units. After its value is converted with SEL_O, it may need to be added by 1 or 2 when the address is not DW-aligned. The net data after Wishbone removes invalid data is placed in the Payload of TLP. The data or response returned by WishboneNon-posted is converted to Completion type, and the Requester id of Completion is equal to the Requested id of Non-Posted request. The Bus Number and Device Number of Completer id come from the Bus Number and Device Number registers customized by iEP. This register is used to capture the Bus Number and Device Number in the Config message when iEP receives the Config request and store them in this register; the Function Number of Completer id is equal to the Function Number of Requester id in the Non-Posted request message. The Length field of Completion corresponds to the STB signal of Wishbone, and the unit of Length is DW. Because the Non-Posted request sent by WishboneMaster has been unpacked as described above, the corresponding returned data will not exceed the Max Payload Size. Therefore, the Byte_Count (number of remaining bytes) field of the Completion message in this direction is always 0. The other fields of the Completion message are consistent with those of Non-Posted, or are taken according to the protocol.

[0059] It should be noted that for Non-Posted requests, the WB to TLP module needs to manage the lifecycle of all Non-Posted requests that return Completion normally or abnormally based on the request tag. When a Non-Posted request receives a Completion message, or does not return a Completion message when the timeout period specified by the PCIe protocol is greater than the timeout period, the lifecycle of the request ends.

[0060] Correspondingly, for Posted requests, since the maximum number of bytes transmitted per beat of the Wishbone bus is 64 bytes, which is less than the minimum value of the Max Payload Size of 128 bytes specified by the PCIe protocol, Posted requests can always be forwarded by the WB to TLP module or the WB to CPL module, and there is no need to disassemble the Wishbone system packet.

[0061] In another specific embodiment, when transmitting data through the Wishbone bus, performing an information comparison operation based on the register and performing a corresponding data forwarding operation according to the information comparison result may include: if the data to be sent is response data sent by the upstream port to respond to a bus request of the Wishbone bus, then performing an information comparison operation on the bus number corresponding to the data to be sent and the bus number of the register corresponding to the virtual port, so as to determine the target virtual port and the corresponding target Wishbone bus port corresponding to the data to be sent according to the corresponding information comparison result; if the data to be sent is request data for the upstream port to initiate a request to the Wishbone bus, then performing an information comparison operation on the address corresponding to the data to be sent and the address range of the register corresponding to the PCIe Endpoint, so as to determine the target PCIeEndpoint and the corresponding target Wishbone bus port corresponding to the data to be sent according to the corresponding information comparison result; forwarding the data to be sent to the corresponding target Wishbone bus port to complete the corresponding data forwarding operation. Specifically, as Figure 5 As shown in the figure, during the data transmission process, Wishbone Master removes different functional IP (Intellectual Property, which refers to the intellectual property components in the integrated circuit design, here refers to Figure 5SATA (Serial Advanced Technology Attachment, here refers to the hard disk) and USB (Universal Serial Bus, here refers to the USB flash drive) requests are implemented by dividing different address segments. For example, 0x100_0000_0000~0x200_0000_0000 is allocated to Wishbone bus port Port0 (SATA), 0x200_0000_0000~0x300_0000_0000 is allocated to Wishbone bus port Port1 (USB), and then CYC_O_0 in the Wishbone bus is used to indicate the read and write of Port0, and CYC_O_1 is used to indicate the read and write of Port1. When the request address given by iATU (internalAddressTranslateUnit) to the Wishbone Master bus falls within the range of 0x100_0000_0000~0x200_0000_0000, CYC_O_0 is set to valid, indicating that the device attached to Port0 is read and written; when the request address falls within the range of 0x200_0000_0000~0x300_0000_0000, CYC_O_1 is set to valid, indicating that the device attached to Port1 is read and written; when the request address does not fall within the address window of any port, the Default port directly replies with a Completion with data of all 1. Specifically, the Bar register of the iEP configuration space is sent to the Wishbone Master Port address judgment logic through a wire, and the request address is compared with the Bar address range (Bar base address + Bar size) of each iEP at the Wishbone Master bus, thereby determining which CYC_O is valid, so as to realize the forwarding of data to different ports. Correspondingly, Wishbone Slave has different Ports (corresponding to Figure 5The Completion message returned by the request sent by SATA and USB in the iDP configuration space is distinguished by different IDs. Specifically, the Second Bus Number register of the iDP configuration space is sent to the Wishbone Slave Port through a wire. If the Bus Number in the Completion message is equal to the Second Bus Number of a certain iDP, it means that the request is to access the iEP corresponding to the iDP. Therefore, after the Completion message is converted to Wishbone, it is forwarded to the Wishbone Slave Port corresponding to the iEP. Note that the system pre-sets which Wishbone Slave Port corresponds to the iEP. For example, Figure 5 iEP0 can be set to correspond to Wishbone Slave Port0. If the Bus Number in the Completione message is not equal to the Second BusNumber of any iDP, the Completion message is discarded. Each Non-Posted request sent by the Wishbone Slave port may return multiple corresponding Completion messages, so the CPL to WB module is required to collect and accumulate the Length of Completion messages with the same Requester ID and the same Tag. When the accumulated Completion Length (that is, the Payload length carried by the Completion) is equal to or greater than the length of the Non-Posted request, it means that all Completions are returned, and these Completion data need to be merged, and then disassembled into data adapted to the Wishbone bus and sent to the Wishbone bus.

[0062] In a specific embodiment, the data transmission based on the PCIe protocol may include: performing address conversion on the data stream of the data transmission process through the internal address conversion unit to achieve address isolation between the address domain corresponding to the uplink port and the address domain corresponding to the PCIe Endpoint. Specifically, address domain isolation can achieve complete isolation of the USP address and the iEP part Wishbone address, and work in different address domains. Figure 6As shown in the figure, in the downstream direction, the address segment received by USP is 0x1_0000_0000~0x3_0000_0000. After USP receives the operation of 0x1_0000_0000~0x3_0000_0000, it is filtered by Prefetchable Memory Base Register and Prefetchable Memory Limit Register, and the address remains unchanged after being output from the TL (transaction layer) of USP. After passing through the iATU1 (integration address translation units) in the USP system, the address is converted to the segment 0x100_0000_0000~0x300_0000_0000, and then according to the pre-defined rules of the USP architecture, the operations of the address segment 0x100_0000_0000~0x200_0000_0000 are forwarded to iEP0, and the operations of 0x200_0000_0000~0x300_0000_0000 are forwarded to iEP1. This achieves the isolation of the USP system address domain and the iEP address domain of the upstream data flow. Correspondingly, in the upstream direction, the address segment sent by iEP0 is 0x500_0000_0000~0x600_0000_0000, and the address segment sent by iEP1 is 0x600_0000_0000~0x700_0000_0000. After filtering by the Prefetchable Memory Base Register and PrefetchableMemory Limit Register of iDP0 and iDP1, the address remains unchanged after being output from the TL of iEP0 or iEP1. After passing through the system iATU2 and iATU3, the address is converted to 0x5_0000_0000~0x6_0000_0000 and 0x6_0000_0000~0x7_0000_0000 respectively, and then forwarded to the USP with a total address segment of 0x5_0000_0000~0x7_0000_0000. Realize the isolation of the USP system address domain and the iEP address domain of the downstream data flow.

[0063] It should be pointed out that the above example is a 64-bit address segment with an address range greater than 4GB. For a 32-bit address segment with an address range less than 4GB, the iDP configuration space registers Memory Base Register and Memory Limit Register are used accordingly. At this time, the iATU uses the same method to isolate the iEP address from the USP system address. Figure 7 As shown, inside Wishbone Master and Wishbone Slave ( Figure 7Wishbone Crossbar, a cross connection of the Y-shaped bus), sets the Rxatu (receiver address translation unit) window corresponding to the iEP Bar address for each functional IP (SATA / USB, etc.), so that the address after passing through the bar is only the offset, and its base address can be arbitrarily set by Rxatu to meet the base address requirements of different functional IPs. That is, the address finally received by the IP = the address output by iATU – Bar base address + Rxatu IP side address – Rxatu Bar side address (assuming it is 0). Figure 8 As shown in the figure, the address received by USB from Wishbone is USB_Address = 'h200_0070_0000 – 'h200_0000_0000 + 'h100_0000 – 'h0 = 'h170_0000.

[0064] It can be seen that the present application can access the configuration space of the customized ECAM through the uplink port downlink configuration request to realize the sending and receiving of PCIe configuration transactions and the completed transactions; expand the configuration space of i-ECAM, and then send the system function module that needs to perceive the iDP configuration space register to the relevant function module by means of register wire (Wire), and align the module function for control; the PCIe Endpoint is inside the chip, and can connect with the uplink port to send and receive data by hanging a virtual port; and the built-in PCIe Endpoint can have the ability to be enumerated by the standard PCIe enumeration software and the ability to process and route various TLP transactions by simulating the physical layer link building behavior; on this basis, add the port Port required by the functional IP corresponding to the iEP on the Wishbone bus to realize the expansion of the iEP. This reduces the hardware cost, and the built-in PCIe Endpoint has better latency performance, is easy to expand, is compatible with the PCIe standard protocol, and can improve the reliability and efficiency of transaction processing.

[0065] like Fig. 9 As shown, an integrated circuit expansion device is applied to an ASIC chip integrating multiple virtual ports and having multiple PCIeEndpoints built in, the configuration space of the virtual ports and the PCIeEndpoints are both located in the ECAM of the ASIC chip, and each of the PCIeEndpoints communicates with the upstream port by connecting to the corresponding virtual port; wherein the device comprises:

[0066] The first expansion module 11 is used to obtain a Config configuration transaction request for the ECAM through the uplink port, so as to access the configuration space of the virtual port and / or the PCIeEndpoint in the ECAM through the Config configuration transaction request, and return a response message for the Config configuration transaction request to the uplink port to complete the expansion operation of the configuration space;

[0067] The second expansion module 12 is used to simulate the physical layer link establishment behavior through the PCIe Endpoint so that the PCIe enumeration software recognizes the PCIe Endpoint as an Endpoint device, completes the expansion process of the integrated circuit, and realizes data transmission based on the PCIe protocol.

[0068] It can be seen that this application can access the configuration space of the customized ECAM through the uplink port downlink configuration request to realize the sending and receiving of PCIe configuration transactions and completed transactions; the PCIe Endpoint is inside the chip, and can connect to the uplink port to send and receive data by hanging a virtual port; and the built-in PCIe Endpoint can be enumerated by the standard PCIe enumeration software by simulating the physical layer link building behavior, as well as the ability to process and route various TLP transactions. This reduces the hardware cost, and the built-in PCIe Endpoint has better latency performance, is easy to expand, is compatible with the PCIe standard protocol, and can improve the reliability and efficiency of processing transactions.

[0069] In a specific embodiment, the first expansion module 11 may include:

[0070] A first conversion unit, configured to obtain a Config configuration transaction request for the ECAM through the uplink port, and convert the Config configuration transaction request into a local request through a first preset conversion interface;

[0071] A first response message generating unit, configured to access the configuration space of the corresponding virtual port and / or PCIe Endpoint in the ECAM using the local request to generate a corresponding local response message;

[0072] The second conversion unit is used to convert the local response message into a response message for the Config configuration transaction request through a second preset conversion interface, and return the response message to the uplink port to complete the expansion operation of the configuration space.

[0073] In a specific embodiment, the device may include:

[0074] A register connection module is used to connect the registers of the configuration space in the ECAM to the Wishbone bus by means of wiring, so as to perform information comparison operations based on the registers when transmitting data through the Wishbone bus, and perform corresponding data forwarding operations according to the information comparison results; the Wishbone bus includes a master line and a slave line.

[0075] In a specific embodiment, the second expansion module 12 may include:

[0076] A third conversion unit is used to obtain the data to be sent for the Wishbone bus through the upstream port, and convert the data to be sent into the Wishbone format through a third preset interface to obtain the converted data to be sent, so as to transmit the converted data to the Wishbone bus to complete the corresponding data transmission operation; wherein the data to be sent includes response data for responding to the bus request of the Wishbone bus and request data for initiating a request to the Wishbone bus.

[0077] In a specific embodiment, the register connection module may include:

[0078] a first information comparison unit, configured to, when the data to be sent is response data sent by the upstream port to respond to a bus request of the Wishbone bus, perform an information comparison operation on a bus number corresponding to the data to be sent and a bus number of a register corresponding to the virtual port, so as to determine a target virtual port corresponding to the data to be sent and a corresponding target Wishbone bus port according to a corresponding information comparison result;

[0079] a second information comparison unit, configured to perform an information comparison operation on an address corresponding to the data to be sent and an address range of a register corresponding to the PCIe Endpoint when the data to be sent is request data initiated by the upstream port to the Wishbone bus, so as to determine a target PCIe Endpoint corresponding to the data to be sent and a corresponding target Wishbone bus port according to a corresponding information comparison result;

[0080] The data forwarding unit is used to forward the data to be sent to the corresponding target Wishbone bus port to complete the corresponding data forwarding operation.

[0081] In a specific embodiment, the second expansion module 12 may include:

[0082] A fourth conversion unit is used to obtain the data to be uploaded for the upstream port through the Wishbone bus, and convert the data to be uploaded into a PCIe message format through a fourth preset interface to obtain the converted upload data, so as to transmit the converted upload data to the upstream port to complete the corresponding data transmission operation; wherein, the data to be uploaded includes response data for responding to the request data initiated by the upstream port and a bus request for initiating a request to the upstream port.

[0083] In a specific embodiment, the second expansion module 12 may include:

[0084] The address conversion submodule is used to perform address conversion on the data stream in the data transmission process through its internal address conversion unit to achieve address isolation between the address domain corresponding to the uplink port and the address domain corresponding to the PCIe Endpoint.

[0085] Furthermore, the present application also discloses an electronic device. Fig.10 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0086] Fig.10 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the integrated circuit expansion method disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0087] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0088] In addition, the memory 22, as a carrier for storing resources, can be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0089] The operating system 221 is used to manage and control the hardware devices and computer programs 222 on the electronic device 20, and can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the integrated circuit expansion method performed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0090] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the integrated circuit expansion method disclosed above. The specific steps of the method can refer to the corresponding contents disclosed in the above embodiments, and will not be repeated here.

[0091] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0092] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0093] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0094] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0095] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A method for expanding an integrated circuit, characterized in that: The invention is applied to an ASIC chip integrating multiple virtual ports and having multiple PCIeEndpoints built in, wherein the configuration spaces of the virtual ports and the PCIeEndpoints are both located in the ECAM of the ASIC chip, and each of the PCIeEndpoints communicates with an upstream port by connecting to a corresponding virtual port; wherein the method comprises: Obtaining a Config configuration transaction request for the ECAM through the uplink port, so as to access the configuration space of the virtual port and / or the PCIe Endpoint in the ECAM through the Config configuration transaction request, and returning a response message for the Config configuration transaction request to the uplink port, thereby completing the expansion operation of the configuration space; The PCIe Endpoint simulates the physical layer link establishment behavior so that the PCIe enumeration software recognizes the PCIe Endpoint as an Endpoint device, completing the expansion process of the integrated circuit, so as to realize data transmission based on the PCIe protocol; Among them, the registers of the configuration space in the ECAM are connected to the Wishbone bus by means of wiring, so that when data is transmitted through the Wishbone bus, information comparison operations are performed based on the registers, and corresponding data forwarding operations are performed according to the information comparison results; the Wishbone bus includes a master line and a slave line, and the registers are configuration registers corresponding to each of the PCIeEndpoints and each of the virtual ports that meet the requirements of the PCIe standard protocol.

2. The integrated circuit expansion method according to claim 1, characterized in that: The acquiring, through the uplink port, a Config configuration transaction request for the ECAM, so as to access the configuration space of the virtual port and / or the PCIe Endpoint in the ECAM through the Config configuration transaction request, and returning a response message for the Config configuration transaction request to the uplink port, thereby completing the configuration space expansion operation, includes: Acquire a Config configuration transaction request for the ECAM through the uplink port, and convert the Config configuration transaction request into a local request through a first preset conversion interface; Accessing the configuration space of the corresponding virtual port and / or PCIe Endpoint in the ECAM using the local request to generate a corresponding local response message; The local reply message is converted into a response message for the Config configuration transaction request through a second preset conversion interface, and the response message is returned to the uplink port to complete the expansion operation of the configuration space.

3. The integrated circuit expansion method according to claim 1, characterized in that: The data transmission based on the PCIe protocol includes: Acquire the data to be sent for the Wishbone bus through the uplink port, and convert the data to be sent into a Wishbone format through a third preset interface to obtain converted sent data, so as to transmit the converted sent data to the Wishbone bus to complete the corresponding data transmission operation; The data to be sent includes response data for responding to a bus request of the Wishbone bus and request data for initiating a request to the Wishbone bus.

4. The integrated circuit expansion method according to claim 3, characterized in that: The performing of information comparison operation based on the register when transmitting data through the Wishbone bus, and performing corresponding data forwarding operation according to the information comparison result, includes: If the data to be sent is response data sent by the upstream port to respond to a bus request of the Wishbone bus, an information comparison operation is performed on the bus number corresponding to the data to be sent and the bus number of the register corresponding to the virtual port, so as to determine the target virtual port corresponding to the data to be sent and the corresponding target Wishbone bus port according to the corresponding information comparison result; If the data to be sent is request data initiated by the upstream port to the Wishbone bus, an information comparison operation is performed on the address corresponding to the data to be sent and the address range of the register corresponding to the PCIe Endpoint, so as to determine the target PCIe Endpoint corresponding to the data to be sent and the corresponding target Wishbone bus port according to the corresponding information comparison result; The data to be sent is forwarded to the corresponding target Wishbone bus port to complete the corresponding data forwarding operation.

5. The integrated circuit expansion method according to claim 1, characterized in that: The data transmission based on the PCIe protocol includes: Acquire the data to be uploaded for the upstream port through the Wishbone bus, and convert the data to be uploaded into a PCIe message format through a fourth preset interface to obtain converted uploaded data, so as to transmit the converted uploaded data to the upstream port to complete the corresponding data transmission operation; The data to be uploaded includes response data for responding to request data initiated by the upstream port and a bus request for initiating a request to the upstream port.

6. The integrated circuit expansion method according to any one of claims 1 to 5, characterized in that: The data transmission based on the PCIe protocol includes: The address conversion is performed on the data stream of the data transmission process through the internal address conversion unit to achieve address isolation between the address domain corresponding to the uplink port and the address domain corresponding to the PCIe Endpoint.

7. An integrated circuit expansion device, characterized in that: An ASIC chip is applied to integrate multiple virtual ports and have multiple PCIeEndpoints built in, the configuration space of the virtual ports and the PCIeEndpoints are both located in the ECAM of the ASIC chip, and each PCIeEndpoint communicates with an upstream port by connecting to the corresponding virtual port; wherein the device comprises: A first expansion module is used to obtain a Config configuration transaction request for the ECAM through the uplink port, so as to access the configuration space of the virtual port and / or the PCIe Endpoint in the ECAM through the Config configuration transaction request, and return a response message for the Config configuration transaction request to the uplink port to complete the expansion operation of the configuration space; The second expansion module is used to simulate the physical layer link establishment behavior by the PCIe Endpoint so that the PCIe enumeration software recognizes the PCIe Endpoint as an Endpoint device, thereby completing the expansion process of the integrated circuit, so as to realize data transmission based on the PCIe protocol; Wherein, the device comprises: A register connection module is used to connect the registers of the configuration space in the ECAM to the Wishbone bus by means of wiring, so as to perform information comparison operations based on the registers when transmitting data through the Wishbone bus, and perform corresponding data forwarding operations according to the information comparison results; the Wishbone bus includes a master line and a slave line, and the registers are configuration registers corresponding to each of the PCIe Endpoints and each of the virtual ports that meet the requirements of the PCIe standard protocol.

8. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the integrated circuit expansion method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: Used to store a computer program, which, when executed by a processor, implements the integrated circuit expansion method according to any one of claims 1 to 6.

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