Dynamic component matching decoding circuit, decoding module and data conversion system

Abstract

The application provides a dynamic element matching decoding circuit, a decoding module and a data conversion system, wherein the dynamic element matching decoding circuit comprises a pseudo-random signal generating unit, a control signal generating unit and a decoding output unit; the pseudo-random signal generating unit is used for generating a pseudo-random signal; the control signal generating unit generates a control signal by performing logical operation on an input signal; the decoding output unit is connected with the pseudo-random signal generating unit and the control signal generating unit respectively, performs decoding output control based on a transmission gate, and realizes conversion of the input signal into an output signal with the pseudo-random signal. The application solves the problems of high power consumption and large transmission delay of the existing dynamic element matching decoding circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a dynamic element matching decoding circuit, a decoding module and a data conversion system. Background Art

[0002] In data conversion systems, dynamic element matching (DEM) technology is widely used in oversampled delta-sigma (Δ-Σ) analog-to-digital converters (ADCs), pipelined ADCs, and high-speed, high-precision DACs to effectively eliminate errors caused by component mismatches and prevent performance degradation. For example, in current-steering DACs, due to process variations and structural limitations, component mismatches inevitably occur during circuit design and manufacturing, leading to nonlinear distortion. DEM technology randomly disrupts the switching sequence of the current-steering DAC, transforming the resulting mismatch errors into pseudo-random noise uncorrelated with the input sequence rather than nonlinear distortion.

[0003] In traditional DEM decoding circuits, since the data path lacks a clock, the only delay between input and output is the propagation delay of the logic circuit. Power consumption and propagation delay are also important performance indicators for DEM decoding circuits. Especially for multi-stage DEM decoding circuits, power consumption and propagation delay increase exponentially. Therefore, how to effectively reduce the power consumption and propagation delay of DEM decoding circuits is a technical problem that those skilled in the art are eager to solve.

[0004] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a dynamic element matching decoding circuit, a decoding module and a data conversion system to solve the problems of high power consumption and large transmission delay in the existing DEM decoding circuit.

[0006] To achieve the above-mentioned and other related purposes, the present invention provides a dynamic element matching decoding circuit, comprising a pseudo-random signal generating unit, a control signal generating unit and a decoding output unit;

[0007] The pseudo-random signal generating unit is used to generate a pseudo-random signal;

[0008] The control signal generating unit generates a control signal by performing a logic operation on the input signal;

[0009] The decoding output unit is connected to the pseudo-random signal generating unit and the control signal generating unit respectively, and performs decoding output control based on a transmission gate to realize conversion of an input signal into an output signal with the pseudo-random signal.

[0010] Optionally, the pseudo-random signal generating unit includes a pseudo-random number generator, which generates the pseudo-random signal output based on a clock signal.

[0011] Optionally, the pseudo-random signal generating unit further includes a D flip-flop, an enable end receiving an enable signal, a clock end receiving the clock signal, a data end connected to the output end of the pseudo-random number generator, an in-phase output end serving as the first output end of the pseudo-random signal generating unit, and an inverting output end serving as the second output end of the pseudo-random signal generating unit.

[0012] Optionally, the control signal generating unit includes an XOR gate and a first inverter; wherein, the first input end of the XOR gate receives a first input signal, the second input end receives a second input signal, and the output end serves as the first output end of the control signal generating unit; the input end of the first inverter is connected to the output end of the XOR gate, and the output end serves as the second output end of the control signal generating unit.

[0013] Optionally, the decoding output unit includes a first transmission gate, a second transmission gate, a third transmission gate and a fourth transmission gate; wherein, the control ends of the first transmission gate and the second transmission gate are connected to the first output end of the control signal generating unit, the reverse control ends are connected to the second output end of the control signal generating unit, the input ends are respectively connected to the first output end and the second output end of the pseudo-random signal generating unit, and the output ends serve as the first output end and the second output end of the decoding output unit respectively; the control ends of the third transmission gate and the fourth transmission gate are connected to the second output end of the control signal generating unit, the reverse control ends are connected to the first output end of the control signal generating unit, the input ends receive the first input signal and the second input signal respectively, and the output ends are respectively connected to the output ends of the first transmission gate and the second transmission gate.

[0014] Optionally, the decoding output unit further includes a second inverter and a third inverter; wherein, the input end of the second inverter is connected to the output end of the first transmission gate, and the output end replaces the output end of the first transmission gate as the output end of the decoding output unit; the input end of the third inverter is connected to the output end of the second transmission gate, and the output end replaces the output end of the second transmission gate as the output end of the decoding output unit.

[0015] The present invention also provides a decoding module, comprising M decoding levels, wherein the i-th decoding level comprises 2 i -1The dynamic element matching decoding circuits as described above are each connected to the output of each dynamic element matching decoding circuit in the previous level. The input of each dynamic element matching decoding circuit in each decoding level is also connected to the corresponding data to be decoded, so as to convert the M data to be decoded into 2 M A thermometer code.

[0016] Optionally, M is a natural number greater than or equal to 3 and less than or equal to 5.

[0017] The present invention also provides a data conversion system, comprising at least one dynamic element matching decoding circuit as described above.

[0018] Optionally, the data conversion system includes a delta-sigma analog-to-digital converter system, a pipeline analog-to-digital converter system, or a current-steering digital-to-analog converter system.

[0019] As described above, the dynamic element matching decoding circuit, decoding module and data conversion system of the present invention realize decoding output control based on transmission gates through the design of pseudo-random signal generating units, control signal generating units and decoding output units, thereby utilizing the low power consumption and small delay characteristics of transmission gates to reduce the power consumption and transmission delay of the entire circuit, improve decoding efficiency, and increase data processing rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Shown is a structural diagram of a DEM decoding circuit.

[0021] Figure 2 Shown is a structural diagram of another DEM decoding circuit.

[0022] Figure 3 Shown is a structural schematic diagram of the DEM decoding circuit of the present invention.

[0023] Figure 4 Shown is a schematic structural diagram of the decoding module of the present invention.

[0024] Figure 5 Display as Figures 1 to 3 Schematic diagram of the path delay transient simulation results of different DEM decoding circuits shown.

[0025] Figure 6 Display as Figures 1 to 3 Schematic diagram of power consumption of different DEM decoding circuits shown.

[0026] Component number description

[0027] 100 decoding module

[0028] 110 Dynamic Component Matching Decoding Circuit

[0029] 111 Pseudo-random signal generation unit

[0030] 111a Pseudo-random number generator

[0031] 112 control signal generating unit

[0032] 113 Decoding Output Unit DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] See also Figures 1 to 6 It should be noted that the illustrations provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the form, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0035] Figure 1 A DEM decoding circuit is shown, including a pseudo-random number generator, an XOR gate, a first D flip-flop DFF1, a second D flip-flop DFF2, a first multiplexer MUX1, a second multiplexer MUX2 and a third multiplexer MUX3. The specific circuit connection is shown in FIG. Figure 1 When the two D flip-flops are enabled and pulled low, the DEM function of the above circuit is turned off. When the two D flip-flops are enabled and pulled high, the DEM function of the above circuit is turned on, thereby converting the input signal into an output signal with a pseudo-random signal.

[0036] Figure 2 Another DEM decoding circuit is shown, including a pseudo-random number generator, an XOR gate, a D flip-flop DFF, a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a fourth NAND gate NAND4 and a fifth NAND gate NAND5. The specific circuit connection is shown in FIG. Figure 2 When the D flip-flop enable is pulled low, the DEM function of the above circuit is turned off, and when the D flip-flop enable is pulled high, the DEM function of the above circuit is turned on, thereby converting the input signal into an output signal with a pseudo-random signal.

[0037] Figure 1In the circuit shown, since there is no clock in the data path, the only delay between input and output is the propagation delay of the logic circuit. In DEM decoding circuits, power consumption and propagation delay are also important performance indicators. Especially for multi-stage DEM decoding circuits, power consumption and propagation delay will increase exponentially. Figure 2 The circuit shown is simplified in structure and the redundant circuit is optimized, which not only reduces power consumption but also reduces the transmission delay on the logic link to a certain extent; however, Figure 2 The transmission delay of the circuit shown still has a lot of room for optimization.

[0038] Based on this, this embodiment provides a dynamic element matching (DEM) decoding circuit 110, including a pseudo-random signal generating unit 111, a control signal generating unit 112 and a decoding output unit 113. Figure 3 As shown; the improved DEM decoding circuit of this embodiment performs decoding output control based on the transmission gate, which is beneficial to reducing power consumption and transmission delay.

[0039] The pseudo-random signal generating unit 111 is configured to generate a pseudo-random signal PRN. In one embodiment, the pseudo-random signal generating unit 111 includes a pseudo-random number generator 111a and further includes a D flip-flop DFF. In the pseudo-random signal generating unit 111 of the above embodiment, the output of the pseudo-random signal PRN is controlled by an enable signal EN. For example, when the enable signal EN is valid, the pseudo-random signal PRN and its inverted signal PRNB are output.

[0040] The pseudo-random number generator 111a generates a pseudo-random signal PRN based on a clock signal CLK. In practical applications, the pseudo-random number generator 111a can be implemented using a known circuit structure, without limitation. The enable terminal of the D-type flip-flop DFF receives the enable signal EN, and the clock terminal of the D-type flip-flop DFF receives the clock signal CLK. The data terminal of the D-type flip-flop DFF is connected to the output terminal of the pseudo-random number generator 111a for connection to the pseudo-random signal PRN. The non-inverting output terminal of the D-type flip-flop DFF serves as the first output terminal of the pseudo-random signal generating unit 111 to output the pseudo-random signal PRN. The inverting output terminal of the D-type flip-flop DFF serves as the second output terminal of the pseudo-random signal generating unit 111 to output the inverted signal PRNB of the pseudo-random signal.

[0041] The control signal generating unit 112 generates the control signal CTL by performing a logic operation on the input signals (including the first input signal IN1 and the second input signal IN2). In one embodiment, the control signal generating unit 112 includes an exclusive-OR gate XOR and a first inverter INV1. By performing an exclusive-OR logic operation and an inverting logic operation on the first input signal IN1 and the second input signal IN2, the control signal CTL and its inverted signal CTLB are output.

[0042] Among them, the first input end of the exclusive OR gate XOR receives the first input signal IN1, the second input end of the exclusive OR gate XOR receives the second input signal IN2, and the output end of the exclusive OR gate XOR serves as the first output end of the control signal generating unit 112 to output the control signal CTL; the input end of the first inverter INV1 is connected to the output end of the exclusive OR gate XOR to connect to the control signal CTL, and the output end of the first inverter INV1 serves as the second output end of the control signal generating unit 112 to output the inverted signal CTLB of the control signal.

[0043] The decoding output unit 113 is connected to the pseudo-random signal generating unit 111 and the control signal generating unit 112 respectively, and performs decoding output control based on the transmission gate to convert the input signal into an output signal with a pseudo-random signal. In one embodiment, the decoding output unit 113 includes a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, and a fourth transmission gate TG4, wherein the first transmission gate TG1 and the second transmission gate TG2 are opened and closed at the same time, and the third transmission gate TG3 and the fourth transmission gate TG4 are opened and closed at the same time. When the first transmission gate TG1 and the second transmission gate TG2 are opened, the third transmission gate TG3 and the fourth transmission gate TG4 are closed, and when the first transmission gate TG1 and the second transmission gate TG2 are closed, the third transmission gate TG3 and the fourth transmission gate TG4 are opened. In addition, when the first transmission gate TG1 and the second transmission gate TG2 are opened, an output is generated based on the pseudo-random signal PRN and its inverted signal PRNB. When the third transmission gate TG3 and the fourth transmission gate TG4 are opened, an output is generated based on the first input signal IN1 and the second input signal IN2. In this way, the input signal is converted into an output signal (including the first output signal OUT1 and the second output signal OUT2) containing a pseudo-random signal.

[0044] Among them, the control end of the first transmission gate TG1 is connected to the first output end of the control signal generating unit 112 to connect to the control signal CTL, the inverting end of the first transmission gate TG1 is connected to the second output end of the control signal generating unit 112 to connect to the inverted signal CTLB of the control signal, the input end of the first transmission gate TG1 is connected to the first output end of the pseudo-random signal generating unit 111 to connect to the pseudo-random signal PRN, and the output end of the first transmission gate TG1 serves as the first output end of the decoding output unit 113 to output the first output signal OUT1; the control end of the second transmission gate TG2 is connected to the first output end of the control signal generating unit 112 to connect to the control signal CTL, the inverting end of the second transmission gate TG2 is connected to the second output end of the control signal generating unit 112 to connect to the inverted signal CTLB of the control signal, the input end of the second transmission gate TG2 is connected to the second output end of the pseudo-random signal generating unit 112 to connect to the inverted signal PRNB of the pseudo-random signal, and the second The output end of the transmission gate TG2 serves as the second output end of the decoding output unit 113 to output the second output signal OUT2; the control end of the third transmission gate TG3 is connected to the second output end of the control signal generating unit 112 to be connected to the inverted signal CTLB of the control signal, the inverted control end of the third transmission gate TG3 is connected to the first output end of the control signal generating unit 112 to be connected to the control signal CTL, the input end of the third transmission gate TG3 is connected to the first input signal IN1, and the output end of the third transmission gate TG3 is connected to the output end of the first transmission gate TG1; the control end of the fourth transmission gate TG4 is connected to the second output end of the control signal generating unit 112 to be connected to the inverted signal CTLB of the control signal, the inverted control end of the fourth transmission gate TG4 is connected to the first output end of the control signal generating unit 112 to be connected to the control signal CTL, the input end of the fourth transmission gate TG4 is connected to the second input signal IN2, and the output end of the fourth transmission gate TG4 is connected to the output end of the second transmission gate TG2.

[0045] Furthermore, the decoding output unit 113 further includes a second inverter INV2 and a third inverter INV3. The addition of the second inverter INV2 and the third inverter INV3 improves the driving capability of the first output signal OUT1 and the second output signal OUT2. The input of the second inverter INV2 is connected to the output of the first transmission gate TG1. The output of the second inverter INV2 replaces the output of the first transmission gate TG1 as the first output of the decoding output unit 113. In this case, the output of the first transmission gate TG1 no longer serves as the first output of the decoding output unit 113. The input of the third inverter INV3 is connected to the output of the second transmission gate TG2. The output of the third inverter INV3 replaces the output of the second transmission gate TG2 as the second output of the decoding output unit 113. In this case, the output of the second transmission gate TG2 no longer serves as the second output of the decoding output unit 113.

[0046] Accordingly, this embodiment further provides a decoding module 100, comprising M decoding levels, wherein the i-th decoding level comprises 2 i-1 The dynamic element matching decoding circuit 110 described above is configured such that M is a natural number greater than 1, i is equal to 1, ..., M; in one example, M is a natural number greater than or equal to 3 and less than or equal to 5. Taking M equal to 3 as an example, the decoding module 100 includes 3 decoding levels, wherein the first decoding level includes 2 1-1 = 1 dynamic element matching decoding circuit 110, the second decoding level includes 2 2-1 = 2 dynamic element matching decoding circuits 110, the third decoding level includes 2 3-1 = 4 dynamic element matching decoding circuits 110, such as Figure 4 As shown. It should be noted that, since the decoding module 100 generally includes two or more decoding levels, M is limited to a natural number greater than 1. Of course, M equal to 1 is also feasible. In fact, when M equals 1, the corresponding decoding module 100 structure is the same as the structure of the dynamic element matching decoding circuit 110 mentioned above, realizing the conversion of one to-be-decoded data into two thermometer codes.

[0047] For M decoding levels, the input end of each dynamic element matching decoding circuit 110 in the next level is connected to the output end of each dynamic element matching decoding circuit 110 in the previous level. The input end of each dynamic element matching decoding circuit 100 in each decoding level is also connected to the corresponding data to be decoded, so as to convert the M data to be decoded into 2 MThermometer code. Taking M equal to 3 as an example, the dynamic element matching decoding circuit 110 in the first decoding level is recorded as the first DEM circuit, the two dynamic element matching decoding circuits 110 in the second decoding level are recorded as the second DEM circuit and the third DEM circuit respectively, and the four dynamic element matching decoding circuits 110 in the third decoding level are recorded as the fourth DEM circuit, the fifth DEM circuit, the sixth DEM circuit and the seventh DEM circuit respectively; at this time, one input end of the first DEM circuit is connected to the first data to be decoded, the other input end of the first DEM circuit is connected to the preset data, and the two output ends of the first DEM circuit are connected to the second DEM circuit and the seventh DEM circuit respectively. The first input terminal of the three DEM circuits is connected to the second data to be decoded. The other input terminals of the second and third DEM circuits are each connected to the second data to be decoded. The two output terminals of the second DEM circuit are respectively connected to the input terminals of the fourth and fifth DEM circuits. The two output terminals of the third DEM circuit are respectively connected to the input terminals of the sixth and seventh DEM circuits. The other input terminals of the fourth, fifth, sixth, and seventh DEM circuits are each connected to the third data to be decoded. The two output terminals of the fourth, fifth, sixth, and seventh DEM circuits generate a total of eight thermometer code outputs. In actual applications, the first data to be decoded, the second data to be decoded, and the third data to be decoded are typically arranged from low-order data to high-order data, and the default data is usually 0.

[0048] Accordingly, this embodiment further provides a data conversion system comprising at least one dynamic element matching decoding circuit 110 as described above. Each dynamic element matching decoding circuit 110 can be configured as the structure shown in the decoding module 100 described above, but other structures are also possible and are not limited thereto. In one example, the data conversion system includes, but is not limited to, a delta-sigma analog-to-digital converter system, a pipelined analog-to-digital converter system, or a current-steering digital-to-analog converter system.

[0049] The following is a comparison of the performance of the DEM decoding circuit described in this embodiment. Figures 1 to 3 The DEM decoding circuits shown are made Figure 4 The decoding module shown is applied to the current steering type DAC system, where the current steering type DAC is a 12-bit DAC, the lower 9 bits are defined as binary decoding, and the upper 3 bits are defined as thermometer decoding (i.e., the data to be decoded, so the decoding module includes three decoding levels), the sampling rate is 200MHz, and the frequency of the input signal is 74.9MHz. The path delay of the DEM decoding circuit of each decoding module in the three systems is transiently simulated, and the results are shown in the figure below. Figure 5 As shown, Figure 3 The DEM decoding circuit shown is compared with Figure 1The DEM decoding circuit shown in the figure has a transmission delay of about 800ps. Figure 3 The DEM decoding circuit shown is compared with Figure 2 The DEM decoding circuit shown in the figure has a transmission delay of about 300ps. In addition, Figures 1 to 3 The power consumption of the three different DEM decoding circuits is shown as Figure 6 As shown. Figure 3 The DEM decoding circuit shown is compared with Figure 1 The DEM decoding circuit shown in the figure has great improvements in power consumption and transmission delay. Figure 3 The DEM decoding circuit shown is compared with Figure 2 The DEM decoding circuit shown in the figure has a significant improvement in transmission delay, which means that with almost the same power consumption, the sampling rate of the digital-to-analog converter can theoretically be increased from 200MHz to 500MHz, greatly improving the data processing rate.

[0050] In summary, the present invention's dynamic element matching decoding circuit, decoding module, and data conversion system, through the design of a pseudo-random signal generation unit, a control signal generation unit, and a decoding output unit, implements transmission gate-based decoding output control. This utilizes the transmission gate's low power consumption and minimal latency to reduce the overall circuit's power consumption and transmission delay, improving decoding efficiency and boosting data processing speed. Therefore, the present invention effectively overcomes the shortcomings of the prior art and possesses high industrial value.

[0051] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A dynamic element matching decoding circuit, characterized in that: It includes a pseudo-random signal generating unit, a control signal generating unit and a decoding output unit; The pseudo-random signal generating unit is used to generate a pseudo-random signal; The control signal generating unit generates a control signal by performing a logic operation on the input signal; The decoding output unit is connected to the pseudo-random signal generating unit and the control signal generating unit respectively, and performs decoding output control based on the transmission gate to realize converting the input signal into an output signal with the pseudo-random signal; The decoding output unit includes a first transmission gate, a second transmission gate, a third transmission gate, and a fourth transmission gate; the control ends of the first transmission gate and the second transmission gate are connected to the first output end of the control signal generating unit, the reverse control ends are connected to the second output end of the control signal generating unit, the input ends are respectively connected to the first output end and the second output end of the pseudo-random signal generating unit, and the output ends serve as the first output end and the second output end of the decoding output unit respectively; the control ends of the third transmission gate and the fourth transmission gate are connected to the second output end of the control signal generating unit, the reverse control ends are connected to the first output end of the control signal generating unit, the input ends receive the first input signal and the second input signal respectively, and the output ends are respectively connected to the output ends of the first transmission gate and the second transmission gate; The decoding output unit further includes a second inverter and a third inverter; the input end of the second inverter is connected to the output end of the first transmission gate, and the output end replaces the output end of the first transmission gate as the output end of the decoding output unit; the input end of the third inverter is connected to the output end of the second transmission gate, and the output end replaces the output end of the second transmission gate as the output end of the decoding output unit.

2. The dynamic element matching decoding circuit according to claim 1, characterized in that: The pseudo-random signal generating unit includes a pseudo-random number generator, which generates the pseudo-random signal output based on a clock signal.

3. The dynamic element matching decoding circuit according to claim 2, characterized in that: The pseudo-random signal generating unit also includes a D flip-flop, an enable end receiving an enable signal, a clock end receiving the clock signal, a data end connected to the output end of the pseudo-random number generator, an in-phase output end serving as a first output end of the pseudo-random signal generating unit, and an inverting output end serving as a second output end of the pseudo-random signal generating unit.

4. The dynamic element matching decoding circuit according to claim 1, characterized in that: The control signal generating unit includes an XOR gate and a first inverter; wherein, the first input end of the XOR gate receives a first input signal, the second input end receives a second input signal, and the output end serves as the first output end of the control signal generating unit; the input end of the first inverter is connected to the output end of the XOR gate, and the output end serves as the second output end of the control signal generating unit.

5. A decoding module, characterized in that: It includes M decoding levels, wherein the i-th decoding level includes 2 i-1 A dynamic element matching decoding circuit according to any one of claims 1 to 4, wherein M is a natural number greater than 1, i is equal to 1, ..., M, the input end of each dynamic element matching decoding circuit in the subsequent level is correspondingly connected to the output end of each dynamic element matching decoding circuit in the previous level, and the input end of each dynamic element matching decoding circuit in each decoding level is also connected to the corresponding data to be decoded, so as to convert the M data to be decoded into 2 M A thermometer code.

6. The decoding module according to claim 5, characterized in that M is a natural number greater than or equal to 3 and less than or equal to 5.

7. A data conversion system, characterized in that: The method comprises at least one dynamic element matching decoding circuit according to any one of claims 1 to 4.

8. The data conversion system according to claim 7, characterized in that: The data conversion system includes a delta-sigma analog-to-digital converter system, a pipeline analog-to-digital converter system, or a current-steering digital-to-analog converter system.

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